[ /Title (CD54H C30, CD74H C30, CD74H CT30) /Subject (High Speed CMOS Logic 8- CD54/74HC30, CD54/74HCT30 Data sheet acquired from Harris Semiconductor SCHS121D High Speed CMOS Logic 8-Input NAND Gate August 1997 - Revised September 2003 Features Description * Buffered Inputs The 'HC30 and 'HCT30 each contain an 8-input NAND gate in one package. They provide the system designer with the direct implementation of the positive logic 8-input NAND function. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family. * Typical Propagation Delay: 10ns at VCC = 5V, CL = 15pF, TA = 25oC * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times Ordering Information * Significant Power Reduction Compared to LSTTL Logic ICs PART NUMBER * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH Pinout CD54HC30, CD54HCT30 (CERDIP) CD74HC30 (PDIP, SOIC, SOP, TSSOP) CD74HCT30 (PDIP, SOIC) TOP VIEW A 1 14 VCC B 2 13 NC C 3 12 H D 4 11 G E 5 10 NC F 6 9 NC GND 7 8 Y TEMP. RANGE (oC) CD54HC30F3A -55 to 125 14 Ld CERDIP CD54HCT30F3A -55 to 125 14 Ld CERDIP CD74HC30E -55 to 125 14 Ld PDIP CD74HC30M -55 to 125 14 Ld SOIC CD74HC30MT -55 to 125 14 Ld SOIC CD74HC30M96 -55 to 125 14 Ld SOIC CD74HC30NSR -55 to 125 14 Ld SOP CD74HC30PW -55 to 125 14 Ld TSSOP CD74HC30PWR -55 to 125 14 Ld TSSOP CD74HC30PWT -55 to 125 14 Ld TSSOP CD74HCT30E -55 to 125 14 Ld PDIP CD74HCT30M -55 to 125 14 Ld SOIC CD74HCT30MT -55 to 125 14 Ld SOIC CD74HCT30M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) 2003, Texas Instruments Incorporated. PACKAGE 1 CD54/74HC30, CD54/74HCT30 Functional Diagram 1 A 2 B 3 C 4 D 5 E 6 F 11 G 12 H 8 Y Y = ABCDEFGH TRUTH TABLE INPUTS A B C D E F G H OUTPUT L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant Logic Symbol 1 A B C D E 2 3 4 8 Y 5 6 F G H 11 12 2 CD54/74HC30, CD54/74HCT30 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA Package Thermal Impedance, JA (see Note 1) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Onl