74LVX14 Low Voltage Hex Inverter with Schmitt Trigger Input Features General Description Input voltage level translation from 5V to 3V The LVX14 contains six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitterfree output signals. In addition, they have a greater noise margin than conventional inverters. Ideal for low power/low noise 3.3V applications Guaranteed simultaneous switching noise level and dynamic threshold performance The LVX14 has hysteresis between the positive-going and negative-going input thresholds (typically 1.0V) which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. Ordering Information Order Number Package Number Package Description 74LVX14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. (c)1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 www.fairchildsemi.com 74LVX14 -- Low Voltage Hex Inverter with Schmitt Trigger Input February 2008 74LVX14 -- Low Voltage Hex Inverter with Schmitt Trigger Input Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names Description In Inputs On Outputs (c)1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 Truth Table Input Output A O L H H L www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Rating Supply Voltage -0.5V to +7.0V IIK DC Input Diode Current, VI = -0.5V VI DC Input Voltage IOK DC Output Diode Current -20mA -0.5V to 7V VO = -0.5V -20mA VO = VCC + 0.5V +20mA VO DC Output Voltage -0.5V to VCC + 0.5V IO DC Output Source or Sink Current 25mA ICC or IGND DC VCC or Ground Current TSTG Storage Temperature P 50mA -65C to +150C Power Dissipation 180mW Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Rating Supply Voltage 2.0V to 3.6V VI Input Voltage 0V to 5.5V VO Output Voltage 0V to VCC TA Operating Temperature -40C to +85C Note: 1. Unused inputs must be held HIGH or LOW. They may not float. (c)1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 www.fairchildsemi.com 3 74LVX14 -- Low Voltage Hex Inverter with Schmitt Trigger Input Absolute Maximum Ratings TA = -40C to +85C TA = +25C Symbol Parameter VCC Conditions Min. Typ. Min. Vt+ Positive Threshold Vt- Negative Threshold 3.0 0.9 VH Hysteresis 3.0 0.3 VOH HIGH Level Output Voltage 2.0 VIN = VIL or VIH, IOH = -50A 1.9 2.0 1.9 3.0 VIN = VIL or VIH, IOH = -50A 2.9 3.0 2.9 VIN = VIL or VIH, IOH = -4mA 2.58 VOL 3.0 Max. LOW Level Output Voltage 2.2 Max. Units 2.2 V 1.2 V 0.9 1.2 0.3 V V 2.48 2.0 VIN = VIL or VIH, IOL = 50A 0.0 0.1 0.1 3.0 VIN = VIL or VIH, IOL = 50A 0.0 0.1 0.1 VIN = VIL or VIH, IOL = 4mA 0.36 0.44 V IIN Input Leakage Current 3.6 VIN = 5.5V or GND 0.1 1.0 A ICC Quiescent Supply Current 3.6 VIN = VCC or GND 2.0 20 A Noise Characteristics(2) TA = 25C Symbol Parameter VCC (V) CL (pF) Typ. Limit Units VOLP Quiet Output Maximum Dynamic VOL 3.3 50 0.3 0.5 V VOLV Quiet Output Minimum Dynamic VOL 3.3 50 -0.3 -0.5 V VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 50 2.0 V VILD Maximum LOW Level Dynamic Input Voltage 3.3 50 0.8 V Note: 2. Input tr = tf = 3ns (c)1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 www.fairchildsemi.com 4 74LVX14 -- Low Voltage Hex Inverter with Schmitt Trigger Input DC Electrical Characteristics TA = -40C to +85C TA = +25C Symbol tPLH, tPHL Parameter Propagation Delay Time VCC (V) CL (pF) 2.7 3.3 0.3 tOSLH, tOSHL Output to Output Skew(3) 2.7 Min. Typ. Max. Min. Max. Units 15 8.7 16.3 1.0 19.5 ns 50 11.2 19.8 1.0 23.0 15 6.8 10.6 1.0 12.5 50 9.3 14.1 1.0 16.0 50 3.3 1.5 1.5 1.5 1.5 ns Note: 3. Parameter guaranteed by design tOSLH = |tPLHm-tPLHn|, tOSHL = |tPHLm-tPHLn| Capacitance TA = -40C to +85C TA = +25C Symbol Parameter Min. Typ. Max. 10 CIN Input Capacitance 4 CPD Power Dissipation Capacitance(4) 21 Min. Max. 10 Units pF pF Note: 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. C PD x V CC x f IN x I CC Average operating current can be obtained by the eqation: ICC(opr.) = -------------------------------------------------------6 ( per, Gate ) (c)1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 www.fairchildsemi.com 5 74LVX14 -- Low Voltage Hex Inverter with Schmitt Trigger Input AC Electrical Characteristics 74LVX14 -- Low Voltage Hex Inverter with Schmitt Trigger Input Physical Dimensions 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45 0.25 R0.10 R0.10 8 0 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 www.fairchildsemi.com 6 74LVX14 -- Low Voltage Hex Inverter with Schmitt Trigger Input Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 www.fairchildsemi.com 7 0.65 0.43 TYP 1.65 6.10 0.45 12.00 TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 www.fairchildsemi.com 8 74LVX14 -- Low Voltage Hex Inverter with Schmitt Trigger Input Physical Dimensions (Continued) ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) EZSWITCHTM * TM PDP-SPMTM Power220(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) Programmable Active DroopTM QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM SMART STARTTM SPM(R) STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 FPSTM FRFET(R) Global Power ResourceSM Green FPSTM Green FPSTMe-SeriesTM GTOTM i-LoTM IntelliMAXTM ISOPLANARTM MegaBuckTM MICROCOUPLERTM MicroFETTM MicroPakTM MillerDriveTM Motion-SPMTM OPTOLOGIC(R) OPTOPLANAR(R) (R) Fairchild(R) Fairchild Semiconductor(R) FACT Quiet SeriesTM FACT(R) FAST(R) FastvCoreTM FlashWriter(R) * (R) SupreMOSTM SyncFETTM (R) The Power Franchise(R) TinyBoostTM TinyBuckTM TinyLogic(R) TINYOPTOTM TinyPowerTM TinyPWMTM TinyWireTM SerDesTM UHC(R) Ultra FRFETTM UniFETTM VCXTM * EZSWITCHTM and FlashWriter(R) are trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I33 (c)1993 Fairchild Semiconductor Corporation 74LVX14 Rev. 1.5.0 www.fairchildsemi.com 9 74LVX14 -- Low Voltage Hex Inverter with Schmitt Trigger Input TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.