74LVX14M_NL - Fairchild Semiconductor

74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input

74LVX14 Rev. 1.5.0

February 2008

74LVX14

Low Voltage Hex Inverter with Schmitt Trigger Input

Features

■

Input voltage level translation from 5V to 3V

■

Ideal for low power/low noise 3.3V applications

■

Guaranteed simultaneous switching noise level and

dynamic threshold performance

General Description

The LVX14 contains six inverter gates each with a

Schmitt trigger input. They are capable of transforming

slowly changing input signals into sharply defined, jitter-

free output signals. In addition, they have a greater noise

margin than conventional inverters.

The LVX14 has hysteresis between the positive-going

and negative-going input thresholds (typically 1.0V)

which is determined internally by transistor ratios and is

essentially insensitive to temperature and supply voltage

variations.

The inputs tolerate voltages up to 7V allowing the inter-

face of 5V systems to 3V systems.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order

Number

Package

Number Package Description

74LVX14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LVX14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVX14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LVX14 Rev. 1.5.0 2

74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input

Connection Diagram

Pin Description

Logic Symbol

IEEE/IEC

Truth Table

Pin Names Description

Inputs

Outputs

Input Output

74LVX14 Rev. 1.5.0 3

74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions

(1)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Note:

1. Unused inputs must be held HIGH or LOW. They may not float.

Symbol Parameter Rating

Supply Voltage –0.5V to +7.0V

DC Input Diode Current, V

–0.5V –20mA

DC Input Voltage –0.5V to 7V

DC Output Diode Current

–0.5V –20mA

+ 0.5V +20mA

DC Output Voltage –0.5V to V

+ 0.5V

DC Output Source or Sink Current ±25mA

or I

GND

DC V

or Ground Current ±50mA

STG

Storage Temperature –65°C to +150°C

PPower Dissipation 180mW

Symbol Parameter Rating

Supply Voltage 2.0V to 3.6V

Input Voltage 0V to 5.5V

Output Voltage 0V to V

Operating Temperature –40°C to +85°C

74LVX14 Rev. 1.5.0 4

74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input

DC Electrical Characteristics

Noise Characteristics

(2)

Note:

2. Input t

3ns

Symbol Parameter V

Conditions

+25°C

–40°C to

+85°C

UnitsMin. Typ. Max. Min. Max.

+Positive Threshold 3.0 2.2 2.2 V

–Negative Threshold 3.0 0.9 0.9 V

Hysteresis 3.0 0.3 1.2 0.3 1.2 V

HIGH Level Output

Voltage

2.0 V

or V

–50µA

1.9 2.0 1.9 V

3.0 V

or V

–50µA

2.9 3.0 2.9

or V

–4mA

2.58 2.48

LOW Level Output

Voltage

2.0 V

or V

50µA

0.0 0.1 0.1 V

3.0 V

or V

50µA

0.0 0.1 0.1

or V

4mA

0.36 0.44

Input Leakage

Current

3.6 V

5.5V or GND ±0.1 ±1.0 µA

Quiescent Supply

Current

3.6 V

or GND 2.0 20 µA

Symbol Parameter V

(V) C

(pF)

25°C

UnitsTyp. Limit

OLP

Quiet Output Maximum Dynamic V

3.3 50 0.3 0.5 V

OLV

Quiet Output Minimum Dynamic V

3.3 50 –0.3 –0.5 V

IHD

Minimum HIGH Level Dynamic Input Voltage 3.3 50 2.0 V

ILD

Maximum LOW Level Dynamic Input Voltage 3.3 50 0.8 V

74LVX14 Rev. 1.5.0 5

74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input

AC Electrical Characteristics

Note:

3. Parameter guaranteed by design t

OSLH

PLHm

–t

PLHn

|, t

OSHL

PHLm

–t

PHLn

Capacitance

Note:

4. C

is defined as the value of the internal equivalent capacitance which is calculated from the operating current

consumption without load.

Average operating current can be obtained by the eqation: I

CC(opr.)

Symbol Parameter V

CC (V) CL (pF)

TA = +25°C

TA = –40°C to

+85°C

UnitsMin. Typ. Max. Min. Max.

tPLH, tPHL Propagation Delay Time 2.7 15 8.7 16.3 1.0 19.5 ns

50 11.2 19.8 1.0 23.0

3.3 ± 0.3 15 6.8 10.6 1.0 12.5

50 9.3 14.1 1.0 16.0

tOSLH, tOSHL Output to Output Skew(3) 2.7 50 1.5 1.5 ns

3.3 1.5 1.5

Symbol Parameter

TA = +25°C

TA = –40°C to

+85°C

UnitsMin. Typ. Max. Min. Max.

CIN Input Capacitance 4 10 10 pF

CPD Power Dissipation Capacitance(4) 21 pF

CPD VCC fIN ICC

×××

6per Gate,()

---------------------------------------------------------

74LVX14 Rev. 1.5.0 6

74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input

Physical Dimensions

Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

LAND PATTERN RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD:

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

PIN ONE

INDICATOR

8°

0°

SEATING PLANE

DETAIL A

SCALE: 20:1

GAGE PLANE

0.25

X45°

0.10

BC A

14 B

SEE DETAIL A

5.60

0.65

1.70 1.27

8.75

8.50

7.62

6.00 4.00

3.80

(0.33)

1.27 0.51

0.35

1.75 MAX

1.50

1.25 0.25

0.10 0.25

0.19

(1.04)

0.90

0.50

0.36

R0.10

0.50

0.25

74LVX14 Rev. 1.5.0 7

74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input

Physical Dimensions (Continued)

Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LVX14 Rev. 1.5.0 8

74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input

Physical Dimensions (Continued)

Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

F. DRAWING FILE NAME: MTC14REV6

R0.09 min

12.00°TOP & BOTTO

0.43 TYP

1.00

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

R0.09min

E. LANDPATTERN STANDARD: SOP65P640X110-14M

0.65

6.10

1.65

0.45

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

B. DIMENSIONS ARE IN MILLIMETERS

74LVX14 Rev. 1.5.0 9

TRADEMARKS

Thefollowing includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global

subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

ACEx®

Build it Now™

CorePLUS™

CROSSVOLT™

CTL™

Current Transfer Logic™

EcoSPARK®

EZSWITCH™ *

™

Fairchild®

Fairchild Semiconductor®

FACT Quiet Series™

FACT®

FAST®

FastvCore™

FlashWriter®*

FPS™

FRFET®

Global Power ResourceSM

Green FPS™

Green FPS™e-Series™

GTO™

i-Lo™

IntelliMAX™

ISOPLANAR™

MegaBuck™

MICROCOUPLER™

MicroFET™

MicroPak™

MillerDrive™

Motion-SPM™

OPTOLOGIC®

OPTOPLANAR®

PDP-SPM™

Power220®

POWEREDGE®

Power-SPM™

PowerTrench®

Programmable Active Droop™

QFET®

QS™

QT Optoelectronics™

Quiet Series™

RapidConfigure™

SMART START™

SPM®

STEALTH™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SupreMOS™

SyncFET™®

The Power Franchise®

TinyBoost™

TinyBuck™

TinyLogic®

TINYOPTO™

TinyPower™

TinyPWM™

TinyWire™

µSerDes™

UHC®

Ultra FRFET™

UniFET™

VCX™

*EZSWITCH™ and FlashWriter®are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S

WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

2. A critical component in any component of a life support,

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Preliminary First Production

This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

No Identification Needed Full Production

This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

the design.

Obsolete Not In Production

This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I33

74LVX14 — Low Voltage Hex Inverter with Schmitt Trigger Input