©2009 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
FQD2N60C/FQU2N60C Rev. B3
FQD2N60C/FQU2N60C 600V N-Channe l MOSFET
FQD2N60C/FQU2N60C
600V N-Channel MOSFET
Features
1.9A, 600V, R
DS(on)
= 4.7 @V
GS
= 10 V
Low gate charge (typical 8.5 nC)
Low Crss (typical 4.3 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Description
These N-Channel enhancement mode power field effect transis-
tors are produced using Fairchild’s proprietary, planar stripe,
DMOS technology.
This advanced technology has been especially tailored to mini-
mize on-state resistance, provide superior switching perfor-
mance, and withstand high energy pulse in the avalanche and
commutation mode. These devices are well suited for high effi-
ciency switched mode power supplies, active power factor cor-
rection, electronic lamp ballasts based on half bridge topology.
Absolute Maximum Ratings
Thermal Charac t eris tics
* When mounted on the minimum pad size recommended (PCB Mount)
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S
D
G
I-PAK
FQU Series
D-PAK
FQD Series GSD
GS
D
Symbol Parameter FQD2N60C / FQU2N60C Units
V
DSS
Drain-Source Voltage 600 V
I
D
Drain Current - Continuous (T
C
= 25°C) 1.9 A
- Continuous (T
C
= 100°C) 1.14 A
I
DM
Drain Current - Pulsed
(Note 1)
7.6 A
V
GSS
Gate-Source Voltage ± 30 V
E
AS
Single Pulsed Avalanche Energy
(Note 2)
120 mJ
I
AR
Avalanche Current
(Note 1)
1.9 A
E
AR
Repetitive Avalanche Energy
(Note 1)
4.4 mJ
dv/dt Peak Diode Recovery dv/dt
(Note 3)
4.5 V/ns
P
D
Power Dissipation (T
A
= 25°C)* 2.5 W
Power Dissipation (T
C
= 25°C) 44 W
- Derate above 25°C 0.35 W/°C
T
J
, T
STG
Operating and Storage Temperature Range -55 to +150 °C
T
L
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
300 °C
Symbol Parameter Typ Max Units
R
θJC
Thermal Resistance, Junction-to-Case -- 2.87 °C/W
R
θJA
Thermal Resistance, Junction-to-Ambient* -- 50 °C/W
R
θJA
Thermal Resistance, Junction-to-Ambient -- 110 °C/W
RoHS Compliant
January 2009
QFET
®
2www.fairchildsemi.com
FQD2N60C/FQU2N60C Rev. B3
FQD2N60C/FQU2N60C 600V N-Channe l MOSFET
Package Marking and Ordering Information
Electrical Characteristics
T
C
= 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 56mH, I
AS
= 2A, V
DD
= 50V, R
G
= 25 Ω, Starting T
J
= 25°C
3. I
SD
2A, di/dt 200A/µs, V
DD
BV
DSS,
Starting T
J
= 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
Device Marking Device Package Reel Size Tape Width Quantity
FQD2N60C FQD2N60C D-PAK - -
FDU2N60C FDU2N60C I-PAK - -
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage V
GS
= 0 V, I
D
= 250 µA 600 -- -- V
BV
DSS
/
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250 µA, Referenced to 25°C -- 0.6 -- V/°C
I
DSS
Zero Gate Voltage Drain Current V
DS
= 600 V, V
GS
= 0 V -- -- 1 µA
V
DS
= 480 V, T
C
= 125°C -- -- 10 µA
I
GSSF
Gate-Body Leakage Current, Forward V
GS
= 30 V, V
DS
= 0 V -- -- 100 nA
I
GSSR
Gate-Body Leakage Current, Reverse V
GS
= -30 V, V
DS
= 0 V -- -- -100 nA
On Characteristics
V
GS(th)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 250 µA2.0--4.0V
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= 10 V, I
D
= 0.95 A -- 3.6 4.7
g
FS
Forward Transconductance V
DS
= 40 V, I
D
= 0.95 A
(Note 4)
-- 5.0 -- S
Dynamic Characteristics
C
iss
Input Capacitance V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
-- 180 235 pF
C
oss
Output Capacitance -- 20 25 pF
C
rss
Reverse Transfer Capacitance -- 4.3 5.6 pF
Switching Characteristics
t
d(on)
Turn-On Delay Time V
DD
= 300 V, I
D
= 2 A,
R
G
= 25
(Note 4, 5)
-- 9 28 ns
t
r
Turn-On Rise Time -- 25 60 ns
t
d(off)
Turn-Off Delay Time -- 24 58 ns
t
f
Turn-Off Fall Time -- 28 66 ns
Q
g
Total Gate Charge V
DS
= 480 V, I
D
= 2 A,
V
GS
= 10 V
(Note 4, 5)
-- 8.5 12 nC
Q
gs
Gate-Source Charge -- 1.3 -- nC
Q
gd
Gate-Drain Charge -- 4.1 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current -- -- 1.9 A
I
SM
Maximum Pulsed Drain-Source Diode Forward Current -- -- 7.6 A
V
SD
Drain-Source Diode Forward Voltage V
GS
= 0 V, I
S
= 1.9 A -- -- 1.4 V
t
rr
Reverse Recovery Time V
GS
= 0 V, I
S
= 2 A,
dI
F
/ dt = 100 A/µs
(Note 4)
-- 230 -- ns
Q
rr
Reverse Recovery Charge -- 1.0 -- µC
3www.fairchildsemi.com
FQD2N60C/FQU2N60C Rev. B3
FQD2N60C/FQU2N60C 600V N-Channe l MOSFET
Typical Perfo rmance Characte rist ics
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics
Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage
Drain Current and Gate Voltage Variation vs. Source Current
and Temperatue
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
10
-1
10
0
10
1
10
-2
10
-1
10
0
V
GS
Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
5.0 V
Bottom : 4.5 V
Notes :
1. 250µ s Pulse Test
2. T
C
= 25
I
D
, Drain Current [A]
V
DS
, Drain-Source Voltage [V]
246810
10
-1
10
0
10
1
150
o
C
25
o
C
-55
o
C
Notes :
1. VDS = 40V
2. 250µ s Pulse Test
I
D
, Drain Current [A]
V
GS
, Gate-Source Voltage [V]
012345
0
2
4
6
8
10
12
V
GS
= 20V
V
GS
= 10V
Note : T
J
= 25
R
DS(ON)
[],
Drain-Source On-Resistance
I
D
, Drain Current [A]
0.2 0.4 0.6 0.8 1.0 1.2 1.4
10
-1
10
0
150
Notes :
1. V
GS
= 0V
2. 25 s Pulse Test
25
I
DR
, Reverse Drain Current [A]
V
SD
, Source-Drain voltage [V]
10
-1
10
0
10
1
0
50
100
150
200
250
300
350
400
450
500
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
Notes ;
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
C
oss
C
iss
Capacitance [pF]
V
DS
, Drain-Source Voltage [V]
0246810
0
2
4
6
8
10
12
V
DS
= 300V
V
DS
= 120V
V
DS
= 480V
Note : I
D
= 2A
V
GS
, Gate-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
4
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FQD2N60C/FQU2N60C Rev. B3
FQD2N60C/FQU2N60C 600V N-Channe l MOSFET
Typical Perfo rmance Characte rist ics
(Continued)
Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation
vs. Temperature vs. Temperature
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 11. Typical Drain Current Slope Figure 12. Typical Drain-S ource Voltage
vs. Gate Resistance Slope vs. Gate Resistance
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
Notes :
1. V
GS
= 0 V
2. I
D
= 250 µ A
BV
DSS
, (Normalized)
Drain-Source Breakdown Voltage
T
J
, Junction Temperature [
o
C]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes :
1. V
GS
= 10 V
2. I
D
= 0.95 A
RDS(ON), (Normalized)
Drain-Source On-Resistance
T
J, Juncti on Temperature [o
C]
10
0
10
1
10
2
10
3
10
-2
10
-1
10
0
10
1
100 ms
DC
10 ms
1 ms
100
µ
s
Operation in This Area
is Limited by R
DS(on)
Notes :
1. T
C
= 25
o
C
2. T
J
= 150
o
C
3. Single Pulse
I
D
, Drain Current [A]
V
DS
, Drain-Source Voltage [V]
25 50 75 100 125 150
0.0
0.4
0.8
1.2
1.6
2.0
ID, Drain Current [A]
TC
, Case Temperature [ ]
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-1
10
0 Notes :
1. Z
θJC
(t) = 2.87 /W Max.
2. D uty Factor, D =t
1
/t
2
3. T
JM
- T
C
= P
DM
* Z
θJC
(t)
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
Z
θJC
(t), Thermal Response
t
1
, Square W ave Pulse Duration [sec]
t
1
P
DM
t
2
5
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FQD2N60C/FQU2N60C Rev. B3
FQD2N60C/FQU2N60C 600V N-Channe l MOSFET
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & W avefo rms
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50KΩ
200nF
12V
Same Type
as DUT
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50KΩ
200nF
12V
Same Type
as DUT
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
E
AS
=LI
AS2
----
2
1--------------------
BV
DSS
-V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
10V DUT
R
G
L
I
D
t
p
E
AS
=LI
AS2
----
2
1
E
AS
=LI
AS2
----
2
1
----
2
1--------------------
BV
DSS
-V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
10V DUT
R
G
LL
I
D
I
D
t
p
6
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FQD2N60C/FQU2N60C Rev. B3
FQD2N60C/FQU2N60C 600V N-Channe l MOSFET
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
dv/dt controlled by R
G
•I
SD
controlled by pulse period
V
DD
L
I
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
I
FM
, Body Diode Forward Current
Body Diode Reverse Current
I
RM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pulse Period
--------------------------
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
dv/dt controlled by R
G
•I
SD
controlled by pulse period
V
DD
LL
I
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
I
FM
, Body Diode Forward Current
Body Diode Reverse Current
I
RM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pulse Period
--------------------------
D = Gate Pulse Width
Gate Pulse Period
--------------------------
7
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FQD2N60C/FQU2N60C Rev. B3
FQD2N60C/FQU2N60C 600V N-Channe l MOSFET
Mechanical Dimensions
TO-252 (DPAK) (FS PKG Code 36)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
millimeters
Pa rt Weight per unit (gram): 0.33
8
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FQD2N60C/FQU2N60C Rev. B3
FQD2N60C/FQU2N60C 600V N-Channe l MOSFET
Mechanical Dimensions
Dimensions in Millimeters
I - PAK
Rev. I37
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effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
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CorePLUS™
CorePOWER™
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CTL™
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EcoSPARK®
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EZSWITCH™ *
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OPTOLOGIC®
OPTOPLANAR®
®
PDP SPM™
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QFET®
QS™
Quiet Series™
RapidConfigure™
Saving our world, 1mW /W /kW at a time™
SmartMax™
SMART START™
SPM®
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SuperFET™
SuperSOT™-3
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SuperSOT™-8
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®
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tm
®
tm
tm
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Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Preliminary First Production
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
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make changes at any time without notice to improve the design.
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9
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FQD2N60C/FQU2N60C Rev. B3
FQD2N60C/FQU2N60C 600V N-Channe l MOSFET