HB56U232BA/SBA Series
2,097,152-word × 32-bit High Density Dynamic RAM Module
ADE-203-721B (Z)
Rev. 2.0
May. 26, 1997
Description
The HB56U232BA/SBA is a 2M × 32 dynamic RAM module, mounted 4 pieces of 16-Mbit DRAM
(HM5117805) sealed in SOJ package. The HB56U232BA/SBA offers Extended Data Out (EDO) Page
Mode as a high speed access time. An outline of the HB56U232BA/SBA is 72-pin single in-line package.
Therefore, the HB56U232BA/SBA makes high density mounting possible without surface mount
technology. The HB56U232BA/SBA provides common data inputs and outputs. Decoupling capacitors
are mounted on the module board.
Features
• 72-pin single in-line package
Outline: 107.95 mm (Length) × 25.40 mm (Height) × 5.28 mm (Thickness)
Lead pitch: 1.27 mm
• Single 5 V (±5%) supply
• High speed
Access time: tRAC = 50/60/70ns (max)
• Low power dissipation
Active mode: 2.31/2.10/1.89 W (max)
Standby mode (TTL): 42 mW (max)
(CMOS): 3.15 mW (max) (L-version)
• EDO page mode capability
• Refresh period
2048 refresh cycles: 32 ms
128 ms (L-version)
• 3 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
• TTL compatible
HB56U232BA/SBA Series
2
Ordering Information
Type No. Access time Package Contact pad
HB56U232BA-5N
HB56U232BA-6N
HB56U232BA-7N
50 ns
60 ns
70 ns
72-pin SIP socket type Gold
HB56U232BA-5NL
HB56U232BA-6NL
HB56U232BA-7NL
50 ns
60 ns
70 ns
HB56U232SBA-5N
HB56U232SBA-6N
HB56U232SBA-7N
50 ns
60 ns
70 ns
72-pin SIP socket type Solder
HB56U232SBA-5NL
HB56U232SBA-6NL
HB56U232SBA-7NL
50 ns
60 ns
70 ns
HB56U232BA/SBA Series
3
Pin Arrangement
1Pin 36Pin 37Pin 72Pin
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1V
SS 19 A10 37 NC 55 DQ11
2 DQ0 20 DQ4 38 NC 56 DQ27
3 DQ16 21 DQ20 39 VSS 57 DQ12
4 DQ1 22 DQ5 40 CAS0 58 DQ28
5 DQ17 23 DQ21 41 CAS2 59 VCC
6 DQ2 24 DQ6 42 CAS3 60 DQ29
7 DQ18 25 DQ22 43 CAS1 61 DQ13
8 DQ3 26 DQ7 44 RAS0 62 DQ30
9 DQ19 27 DQ23 45 NC 63 DQ14
10 VCC 28 A7 46 NC 64 DQ31
11 NC 29 NC 47 WE 65 DQ15
12 A0 30 VCC 48 NC 66 NC
13 A1 31 A8 49 DQ8 67 PD1
14 A2 32 A9 50 DQ24 68 PD2
15 A3 33 NC 51 DQ9 69 PD3
16 A4 34 RAS2 52 DQ25 70 PD4
17 A5 35 NC 53 DQ10 71 NC
18 A6 36 NC 54 DQ26 72 VSS
HB56U232BA/SBA Series
4
Pin Description
Pin name Function
A0 to A10 Address inputs:
Row address: A0 to A10
Column address: A0 to A9
Refresh address: A0 to A10
DQ0 to DQ31 Data-in/Data-out
CAS0 to CAS3 Column address strobe
RAS0, RAS2 Row address strobe
WE Read/Write enable
VCC Power supply
VSS Ground
PD1 to PD4 Presence detect pin
NC No connection
Presence Detect Pin Arrangement
Function
Pin No. Pin name 50 ns 60 ns 70 ns
67 PD1 NC NC NC
68 PD2 NC NC NC
69 PD3 VSS NC VSS
70 PD4 VSS NC NC
HB56U232BA/SBA Series
5
Block Diagram
RAS0
CAS0
DQ0 to DQ7
V
CC
V
SS
WE
A0 to A10
D0 to D3
D0 to D3
D0 to D3
D0 to D3
I/O0 to I/O7
CAS RAS
OE
D0
CAS RAS
OE
D1
CAS1
0.22 µF × 9 pcs
* D0 to D3: HM5117805
8
DQ8 to DQ15 I/O0 to I/O7
8
RAS2
CAS2
DQ16 to DQ23 I/O0 to I/O7
CAS RAS
OE
D2
CAS RAS
OE
D3
CAS3
8
DQ24 to DQ31 I/O0 to I/O7
8
11
HB56U232BA/SBA Series
6
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to VSS VT–1.0 to +7.0 V
Supply voltage relative to VSS VCC –1.0 to +7.0 V
Short circuit output current Iout 50 mA
Power dissipation Pt 4 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Recommended DC Operating Conditions (Ta = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VSS 000 V
V
CC 4.75 5.0 5.25 V 1
Input high voltage VIH 2.4 — 5.5 V 1
Input low voltage VIL –1.0 — 0.8 V 1
Note: 1. All voltage referred to VSS.
HB56U232BA/SBA Series
7
DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 5%, VSS = 0 V)
50 ns 60 ns 70 ns
Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes
Operating current ICC1 — 440 — 400 — 360 mA tRC = min 1, 2
Standby current ICC2 — 8 — 8 — 8 mA TTL interface,
RAS, CAS = VIH,
Dout = High-Z
— 4 — 4 — 4 mA CMOS interface,
RAS, CAS ≥ V
C C – 0. 2 V,
Dout = High-Z
Standby current
(L-version) ICC2 — 0.6 — 0.6 — 0.6 mA CMOS interface,
RAS, CAS ≥ V
C C – 0. 2 V,
Dout = High-Z
RAS-only refresh
current ICC3 — 440 — 400 — 360 mA tRC = min 2
Standby current ICC5 —20—20—20mARAS = VIH, CAS = VIL,
Dout = enable 1
CAS-before-RAS
refresh current ICC6 — 440 — 400 — 360 mA tRC = min
EDO page mode
current ICC7 — 400 — 360 — 340 mA tHPC = min 1, 3
Battery backup current
(Standby with CBR
refresh) (L-version)
ICC10 — 2 — 2 — 2 mA CMOS interface,
Dout = High-Z,
CBR refresh:
tRC = 62.5 µs,
tRAS ≤ 0.3 µs
4
Input leakage current ILI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 5.5 V
Output leakage current ILO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 5.5 V,
Dout = disable
Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA
Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected, ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. CAS = L (≤ 0.2 V) while RAS = L (≤ 0.2 V).
HB56U232BA/SBA Series
8
Capacitance (Ta = 25°C, VCC = 5 V ± 5%)
Parameter Symbol Typ Max Unit Notes
Input capacitance (Address) CI1 —40pF1
Input capacitance (WE)C
I2 —48pF1
Input capacitance (RAS)C
I3 —29pF1
Input capacitance (CAS)C
I4 —22pF1
I/O capacitance (DQ) CI/O — 22 pF 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
HB56U232BA/SBA Series
9
AC Characteristics (Ta = 0 to 70˚C, VCC = 5 V ±5%, VSS = 0 V) *1, *2, *18
Test Conditions
• Input rise and fall times: 2 ns
• Input level: 0 V, 3.0V
• Input timing reference levels: 0.8 V, 2.4 V
• Output timing reference levels: 0.8 V, 2.0 V
• Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, and Refresh Cycles (Common parameters)
50 ns 60 ns 70 ns
Parameter Symbol Min Max Min Max Min Max Unit Notes
Random read or write cycle
time tRC 84 — 104 — 124 — ns
RAS precharge time tRP 30 — 40 — 50 — ns
CAS precharge time tCP 7 — 10 — 13 — ns
RAS pulse width tRAS 50 10000 60 10000 70 10000 ns
CAS pulse width tCAS 7 10000 10 10000 13 10000 ns
Row address setup time tASR 0—0—0—ns
Row address hold time tRAH 7 — 10 — 10 — ns
Column address setup time tASC 0—0—0—ns
Column address hold time tCAH 7 — 10 — 13 — ns
RAS to CAS delay time tRCD 11 37 14 45 14 52 ns 3
RAS to column address
delay time tRAD 9 2512301235ns4
RAS hold time tRSH 10 — 13 — 13 — ns
CAS hold time tCSH 35 — 40 — 45 — ns
CAS to RAS precharge time tCRP 5—5—5—ns
CAS delay time from Din tDZC 0—0—0—ns
Transition time (rise and fall) tT250250250ns5
Refresh period
(2,048 cycles) tREF —32—32—32ms
Refresh period
(2,048 cycles) (L-version) tREF — 128 — 128 — 128 ms
HB56U232BA/SBA Series
10
Read Cycle
50 ns 60 ns 70 ns
Parameter Symbol Min Max Min Max Min Max Unit Notes
Access time from RAS tRAC — 50 — 60 — 70 ns 6, 7
Access time from CAS tCAC — 13 — 15 — 18 ns 7, 8, 15
Access time from address tAA — 25 — 30 — 35 ns 7, 9, 15
Read command setup time tRCS 0—0—0—ns
Read command hold time to
CAS tRCH 0—0—0—ns10
Read command hold time
from RAS tRCHR 50 — 60 — 70 — ns
Read command hold time to
RAS tRRH 5—5—5—ns10
Column address to RAS
lead time tRAL 25 — 30 — 35 — ns
Column address to CAS
lead time tCAL 15 — 18 — 23 — ns
CAS to output in low-Z tCLZ 0—0—0—ns
Output data hold time tOH 3—3—3—ns19
Output buffer turn-off time tOFF — 13 — 15 — 15 ns 11, 19
CAS to Din delay time tCDD 13 — 15 — 18 — ns
Output data hold time from
RAS tOHR 3—3—3—ns19
Output buffer turn-off time to
RAS tOFR —13—15—15ns19
Output buffer turn-off to WE tWEZ —13—15—15ns
WE to Din delay time tWED 13 — 15 — 18 — ns
RAS to Din delay time tRDD 13 — 15 — 18 — ns
RAS to next CAS delay time tRNCD 50 — 60 — 70 — ns
HB56U232BA/SBA Series
11
Write Cycle
50 ns 60 ns 70 ns
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write command setup time tWCS 0—0—0—ns12
Write command hold time tWCH 7 — 10 — 13 — ns
Write command pulse width tWP 7 — 10 — 10 — ns
Data-in setup time tDS 0—0—0—ns13
Data-in hold time tDH 7 — 10 — 13 — ns 13
Refresh Cycle
50 ns 60 ns 70 ns
Parameter Symbol Min Max Min Max Min Max Unit Notes
CAS setup time
(CBR refresh cycle) tCSR 5—5—5—ns
CAS hold time
(CBR refresh cycle) tCHR 7 — 10 — 10 — ns
WE setup time
(CBR refresh cycle) tWRP 0—0—0—ns
WE hold time
(CBR refresh cycle) tWRH 7 — 10 — 10 — ns
RAS precharge to CAS hold
time tRPC 5—5—5—ns
EDO Page Mode Cycle
50 ns 60 ns 70 ns
Parameter Symbol Min Max Min Max Min Max Unit Notes
EDO page mode cycle time tHPC 20 — 25 — 30 — ns 16
EDO page mode RAS pulse
width tRASP — 100000 — 100000 — 100000 ns 14
Access time from CAS
precharge tCPA — 28 — 35 — 40 ns 7, 15
RAS hold time from CAS
precharge tCPRH 28 — 35 — 40 — ns
Output data hold time from
CAS low tDOH 3 — 3 — 3 — ns 7, 15
Read command hold time
from CAS precharge tRCHC 28 — 35 — 40 — ns
HB56U232BA/SBA Series
12
Notes: 1. AC measurements assume tT = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS
refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh
cycles are required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD ≥ tRCD (max) + tAA (max) - tCAC (max), then access time is controlled
exclusively by tCAC.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
6. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
7. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
8. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
9. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
10.Either tRCH or tRRH must be satisfied for a read cycles.
11.tOFF (max) defines the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
12.Early write cycle only (tWCS ≥ tWCS (min)).
13.These parameters are referred to CAS leading edge in early write cycles.
14.tRASP defines RAS pulse width in EDO page mode cycles.
15.Access time is determined by the longest among tAA, tCAC and tCPA.
16.tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles.
17.When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC / VSS line noise, which causes to degrade VIH min./ VIL max level.
18.All the VCC and VSS pins shall be supplied with the same voltages.
19.Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF.
20.XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
HB56U232BA/SBA Series
13
Timing Waveforms*20
Read Cycle
!
RAS
Address
WE
Dout
Din
tRC
tRAS tRP
tCSH tCRP
tRCD tRSH
tCAS
tT
tRAD tRAL
tCAL
t
ASC
tCAH
tASR
Row Column
t
RAH
tRCS tRCH
tRRH
tCDD
tDZC
High-Z
Dout
tRAC
tAA tCAC
tCLZ
tOH
tOFF
CAS
tRDD
tWED
tOFR
tOHR
tWEZ
tRCHR
HB56U232BA/SBA Series
14
Early Write Cycle
RAS
Address
WE
Din
Dout
tRC
*
tRAS tRP
tCRP
tCSH
tRCD tRSH
tCAS
tT
tASR tRAH tASC tCAH
ColumnRow
tWCS tWCH
tWP
tDS tDH
Din
tWCS WCS(min)
High-Z*
t
CAS
HB56U232BA/SBA Series
15
RAS-Only Refresh Cycle
!
RAS
Address
Dout High-Z
Row
tRC tRP
tRAS
tT
tCRP tRPC tCRP
tASR tRAH
tOFF
tOFR
CAS
HB56U232BA/SBA Series
16
CAS-Before-RAS Refresh Cycle
,
RAS
CAS
WE
Dout
Address
tRC tRP
tRAS
tRPC tCSR tCHR tRPC tCRP
tCP
tWRH
tWRP
tCP
tT
tOFF
tOFR
High-Z
tRP
HB56U232BA/SBA Series
17
Hidden Refresh Cycle
,
#*
Din
Dout
WE
Address
RAS
tRC tRC tRC tRP
tRAS
tRP
tRAS
tRP
tRAS
tT
tRCD
tRSH tCHR tCRP
tRAD tRAL
tCAH
tASC
tRAH
tASR
t
tCDD
tDZC
OFF
t
OH
t
CAC
t
AA
t
RAC
t
CLZ
t
Dout
ColumnRow
High-Z
tRCH
tRRH
CAS
tWED
tRDD
WEZ
t
OFR
t
OHR
t
RCS tWRH
tRRH tWRP
tWRH tWRP
HB56U232BA/SBA Series
18
EDO Page Mode Read Cycle
!"
Din
Dout
WE
Address
RAS
t
CP
t
CP
t
CP
t
T
t
RCH
t
RRH
t
DZC
t
CDD
t
RDD
High-Z
t
OFR
t
OFF
t
OH
t
OHR
t
CPA
t
AA
t
CAC
t
CAC
t
AA
t
RAC
t
AA
t
CAC
t
CPA
t
AA
t
CAC
t
t
RASP
t
RP
t
CAS
t
CAS
t
CAS
t
CAL
t
CSH
t
RNCD
t
HPC
t
HPC
CRP
t
t
ASR
t
RAH
Column 1 Column 2 Column 3
Column 4
t
t
CAH
t
ASC
t
CAH
t
CAH
t
ASC
t
CAH
t
ASC
t
WED
t
RAL
Row
Dout 2 Dout 4
Dout 1
t
CAS
t
RCS
tt
RCS
Dout 3
t
t
CPRH
t
HPC
t
WEZ
DOH
t
DOH
RCH
t
RCHR
t
CAL
t
CAL
t
CAL
t
RSH
t
RCHC
CPA
ASC
CAS
HB56U232BA/SBA Series
19
EDO Page Mode Early Write Cycle
*tWCS WCS(min)
RAS
Address
WE
Din
Dout
tRASP tRP
tTtCSH tHPC tRSH tCRP
tCAS
tCP
tCAS
tCP
tCAS
tRCD
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
ttWCS
t
tWCS
t
tWCS
tDH
tDS tDH
tDS tDH
tDS
Din 1 Din 2 Din N
High-Z*
t
Row Column 1 Column 2 Column N
CAS
WCH
WCHWCH
tWP
tWP
tWP
HB56U232BA/SBA Series
20
Physical Outline
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
72 1
1A
107.95
4.25
44.45
1.75
1.27 typ.
0.05 6.35
0.25
25.40
1.00
2.54 min.
0.10
R1.57
R0.062
6.35
0.25
0.08
2.03
0.25
R1.57
R0.062
101.19
3.98
2.54 min
0.10
0.041 ± 0.001
0.25 max
0.01
2-Ø 3.175
0.125
6.35 44.45
1.75
10.16
0.40
Deteil A
1.27 + 0.10
– 0.08
0.05 + 0.004
– 0.003
Front side
Back side
72
1.04 ± 0.03
Component area
Unit: mm
inch
5.28 max
0.208
,,
,,
,,
,,
,,
,,
,,
3.17 min
0.125
HB56U232BA/SBA Series
21
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
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Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: 415-589-8300
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Tel: 089-9 91 80-0
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Cop
y
ri
g
ht © Hitachi, Ltd., 1997. All ri
g
hts reserved. Printed in Japan.
HB56U232BA/SBA Series
22
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
1.0 Feb. 20, 1997 Initial issue S. Tsukui K. Tsuneda
2.0 May. 26, 1997 (referred to HM5117805 rev. 3.0)
Correct errors
