
XF652
Enhanced Clock Generator for 2 DIMM Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.3 5/6/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 3 of 7
POWER MANAGEMENT FUNCTION
The device clocks may be disabled using the PWR_DWN# pin in order to reduce power consumption. All clocks are
stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. When powered
down, the reference oscillator and VCOs are stopped. On low to high transitions of PWR_DWN#, external circuitry
should allow 2 mS for the VCOs to stabilize prior to assuming that the pulse widths are correct.
MAXIMUM RATINGS
Voltage Relative to VSS: -0.3V
Voltage Relative to VDD: 0.3V
Storage Temperature: -65ºC to + 150ºC
Ambient Temperature: -55ºC to +125ºC
Maximum Power Supply: 7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
SWITCHING CHARACTERISTICS
Characteristic Symbol Min Typ Max Units Conditions
Output Duty Cycle -45 50 55 %Measured at 1.5V
CPU to PCI Offset tOFF 1-4ns 15 pf Load Measured at 1.5V
Skew (CPU-CPU) tSKEW1- - 250 ps 15 pf Load Measured at 1.5V
Skew (CPu-SDRAM) tSKEW2- - 500 ps 15 pf Load Measured at 1.5V
Skew (PCI-PCI) tSKEW3- - 250 ps 15 pf Load Measured at 1.5V
∆Period Adjacent Cycles ∆P- - +250 ps -
Jitter Spectrum 20 dB
Bandwidth from Center BWJ500 KHz
VDD = VDD3 =3.3V ±5%, VDD2 = 2.375V to 2.9V, TA = 0ºC to +70ºC
note 1: Ring Back must not enter this range.