3 4 5 6 VDD2A VDD3A 7 VDD4A 2 VGG34A FUNCTIONAL BLOCK DIAGRAM Gain: 14.5 dB typical at 50 GHz to 70 GHz S11: 22 dB typical at 50 GHz to 70 GHz S22: 19 dB typical at 50 GHz to 70 GHz P1dB: 17 dBm typical at 50 GHz to 70 GHz PSAT: 21 dBm typical OIP3: 25 dBm typical at 70 GHz to 90 GHz Supply voltage: 3.5 V at 350 mA 50 matched input/output Die size: 2.5 mm x 3.32 mm x 0.05 mm VDD1A FEATURES VGG12A Data Sheet 50 GHz to 95 GHz, GaAs, pHEMT, MMIC, Wideband Power Amplifier ADPA7001CHIPS RFOUT 8 ADPA7001CHIPS APPLICATIONS 15 12 VDET VREF VDD4B VDD3B VGG34B 14 13 11 10 9 16895-001 16 VDD2B RFIN VGG12B 1 VDD1B Test instrumentation Military and space Telecommunications infrastructure Figure 1. GENERAL DESCRIPTION The ADPA7001CHIPS is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), balanced medium power amplifier, with an integrated temperature compensated on-chip power detector that operates from 50 GHz to 95 GHz. In the lower band of 50 GHz to 70 GHz, the ADPA7001CHIPS provides 14.5 dB (typical) of gain, 25.5 dBm output third-order intercept (OIP3), and 17 dBm of output power for 1 dB gain compression. Rev. B In the upper band of 70 GHz to 90 GHz, the ADPA7001CHIPS provides 14 dB (typical) of gain, 25 dBm output IP3, and 17.5 dBm of output power for 1 dB gain compression. The ADPA7001CHIPS requires 350 mA from a 3.5 V supply. The ADPA7001CHIPS amplifier inputs/outputs are internally matched to 50 , facilitating integration into multichip modules (MCMs). All data is taken with the chip connected via one 0.076 mm (3 mil) ribbon bond of 0.076 mm (3 mil) minimal length. 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Technical Support www.analog.com ADPA7001CHIPS Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Interface Schematics .....................................................................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Revision History ............................................................................... 2 Applications Information .............................................................. 14 Specifications..................................................................................... 3 50 GHz to 70 GHz Frequency Range ......................................... 3 Mounting and Bonding Techniques for Millimeterwave GaAs MMICs .............................................................................. 14 70 GHz to 90 GHz Frequency Range ......................................... 3 Typical Application Circuit ....................................................... 16 90 GHz to 95 GHz Frequency Range ......................................... 4 Assembly Diagram ..................................................................... 17 Absolute Maximum Ratings............................................................ 5 Outline Dimensions ....................................................................... 18 Thermal Resistance ...................................................................... 5 Ordering Guide .......................................................................... 18 ESD Caution .................................................................................. 5 REVISION HISTORY 10/2019--Rev. A to Rev. B Added Figure 19 and Figure 22; Renumbered Sequentially ....... 9 8/2018--Revision 0: Initial Version 3/2019--Rev. 0 to Rev. A Changes to Figure 44 ...................................................................... 16 Rev. B | Page 2 of 18 Data Sheet ADPA7001CHIPS SPECIFICATIONS 50 GHz TO 70 GHz FREQUENCY RANGE TDIE BOTTOM = 25C, VDD = VDD1A = VDD2A = VDD3A = VDD4A = 3.5 V and supply current (IDQ) = IDQ1A + IDQ2A + IDQ3A + IDQ4A = 350 mA, unless otherwise noted. Adjust VGG = VGG12A = VGG34A from -1.5 V to 0 V to achieve the desired IDQ. Typical VGG = -0.5 V for IDQ = 350 mA. Table 1. Parameter FREQUENCY RANGE GAIN Gain Variation over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept INPUT Input Third-Order Intercept SUPPLY Current Voltage Symbol Min 50 12.5 S11 S22 P1dB PSAT OIP3 15.5 IIP3 IDQ VDD 1.5 Typ 14.5 0.02 Unit GHz dB dB/C 22 19 dB dB 17 21 25.5 dBm dBm dBm 11.5 dBm POUT per tone = 0 dBm with 1 MHz tone spacing mA V Adjust VGG to achieve IDQ = 350 mA typical 350 3.5 Max 70 400 4.0 Test Conditions/Comments Output power (POUT) per tone = 0 dBm with 1 MHz tone spacing 70 GHz TO 90 GHz FREQUENCY RANGE TDIE BOTTOM = 25C, VDD = VDD1A = VDD2A = VDD3A = VDD4A = 3.5 V and IDQ = IDQ1A + IDQ2A + IDQ3A + IDQ4A = 350 mA, unless otherwise noted. Adjust VGG = VGG12A = VGG34A from -1.5 V to 0 V to achieve the desired IDQ. Typical VGG = -0.5 V for IDQ = 350 mA. Table 2. Parameter FREQUENCY RANGE GAIN Gain Variation over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept INPUT Input Third-Order Intercept SUPPLY Current Voltage Symbol Min 70 12 S11 S22 P1dB PSAT OIP3 16 IIP3 IDQ VDD 1.5 Typ 14 0.02 Unit GHz dB dB/C 18 13 dB dB 17.5 21 25 dBm dBm dBm POUT per tone = 0 dBm with 1 MHz tone spacing 11 dBm POUT per tone = 0 dBm with 1 MHz tone spacing mA V Adjust VGG to achieve IDQ = 350 mA typical 350 3.5 Max 90 400 4.0 Rev. B | Page 3 of 18 Test Conditions/Comments ADPA7001CHIPS Data Sheet 90 GHz TO 95 GHz FREQUENCY RANGE TDIE BOTTOM = 25C, VDD = VDD1A = VDD2A = VDD3A = VDD4A = 3.5 V, and IDQ = IDQ1A + IDQ2A + IDQ3A + IDQ4A = 350 mA, unless otherwise noted. Adjust VGG = VGG12A = VGG34A from -1.5 V to 0 V to achieve the desired IDQ. Typical VGG = -0.5 V for IDQ = 350 mA. Table 3. Parameter FREQUENCY RANGE GAIN Gain Variation over Temperature RETURN LOSS Input Output SUPPLY Current Voltage Symbol Min 90 S11 S22 IDQ VDD 1.5 Typ 15 0.02 Unit GHz dB dB/C 15 12 dB dB 350 3.5 Max 95 400 4.0 Rev. B | Page 4 of 18 mA V Test Conditions/Comments Adjust VGG to achieve IDQ = 350 mA typical Data Sheet ADPA7001CHIPS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Drain Bias Voltage (VDD) Gate Bias Voltage (VGG) Radio Frequency (RF) Input Power (RFIN) Continuous Power Dissipation (PDISS), at TDIE BOTTOM = 85C (Derate 26.95 mW/C Above 85C) Storage Temperature Range (Ambient) Operating Temperature Range (Die Bottom) ESD Sensitivity Human Body Model (HBM) Channel Temperature to Maintain 1 Million Hour Mean Time to Failure (MTTF) Nominal Channel Temperature at TDIE BOTTOM = 85C, VDD = 3.5 V Rating 4.5 V -2 V to 0 V dc 17 dBm 2.4 W Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JC is the junction-to-case thermal resistance. Table 5. Thermal Resistance -65C to +150C -55C to +85C Package Type C-16-2 ESD CAUTION Class 0 125 V 175C 130.4C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 5 of 18 JC 37.1 Unit C/W ADPA7001CHIPS Data Sheet 2 3 4 5 6 7 VGG12A VDD1A VDD2A VGG34A VDD3A VDD4A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFOUT 8 ADPA7001CHIPS VDD3B VDD4B 14 13 12 11 10 9 16895-002 VGG34B 15 VDET VDD2B 16 VREF VDD1B RFIN VGG12B 1 Figure 2. Pad Configuration Table 6. Pad Function Descriptions Pad No. 1 2 3, 4 8 9 Mnemonic RFIN VGG12A VDD1A, VDD2A VGG34A VDD3A, VDD4A RFOUT VDET 10 VREF 11, 12 VDD4B, VDD3B VGG34B 5 6, 7 13 16 VDD2B, VDD1B VGG12B Die Bottom GND 14, 15 Description RF Input. This pad is ac-coupled and matched to 50 . See Figure 3 for the interface schematic. Gate Control Pad for the First and Second Stage Amplifiers. See Figure 4 for the interface schematic. Drain Bias Voltage Pads for the First and Second Stage Amplifiers. External bypass capacitors of 100 pF, 0.1 F, and 4.7 F are required on these pads. Connect these pads to a 3.5 V supply. See Figure 5 for the interface schematic. Gate Control Pad for the Third and Fourth Stage Amplifiers. See Figure 4 for the interface schematic. Drain Bias Voltage Pads for the Third and Fourth Stage Amplifiers. External bypass capacitors of 100 pF, 0.1 F, and 4.7 F are required on these pads. Connect these pads to a 3.5 V supply. See Figure 5 for the interface schematic. RF Output. This pad is ac-coupled and matched to 50 . See Figure 9 for the interface schematic. DC Voltage Representing the RF Output Power. This pad is rectified by the diode that is biased through an external resistor. See Figure 9 for the interface schematic. DC Voltage of the Diode. This pad is biased through an external detector circuit used for temperature compensation of VDET. See Figure 10 for the interface schematic. Drain Bias Voltage Pads for the Fourth and Third Stage Alternative Bias Configuration. External bypass capacitors of 100 pF, 0.1 F, and 4.7 F are required. See Figure 7 for the interface schematic. Gate Control Pad for the Third and Fourth Stage Alternative Bias Configuration. Coupling capacitors are required. See Figure 8 for the interface schematic. Drain Bias Voltage Pads for the Second and First Stage Alternative Bias Configuration. External bypass capacitors of 100 pF, 0.1 F, and 4.7 F are required. See Figure 7 for the interface schematic. Gate Control Pad for the First and Second Stage Alternative Bias Configuration. Coupling capacitors are required. See Figure 8 for the interface schematic. Ground. Die bottom must be connected to RF/dc ground. See Figure 6 for the interface schematic. Rev. B | Page 6 of 18 Data Sheet ADPA7001CHIPS 16895-003 INTERFACE SCHEMATICS 16895-007 VDD1B TO VDD4B Figure 7. VDD1B to VDD4B Interface Schematic 16895-004 Figure 3. RFIN Interface Schematic VGG12A VGG34A 16895-008 RFIN VGG12B VGG34B Figure 8. VGG12B and VGG34B Interface Schematic Figure 4. VGG12A and VGG34A Interface Schematic RFOUT 16895-009 16895-005 VDD1A TO VDD4A VDET 16895-006 GND VREF 16895-010 Figure 9. RFOUT and VDET Interface Schematic Figure 5. VDD1A to VDD4A Interface Schematic Figure 10. VREF Interface Schematic Figure 6. GND Interface Schematic Rev. B | Page 7 of 18 ADPA7001CHIPS Data Sheet 20 22 15 20 10 18 16 S11 S21 S22 0 14 GAIN (dB) 5 -5 -10 12 10 8 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 6 -20 4 -25 2 -30 40 50 60 70 80 90 100 FREQUENCY (GHz) 0 45 66 77 85 95 FREQUENCY (GHz) Figure 14. Gain vs. Frequency for Various VDD Values Figure 11. Broadband Gain and Return Loss vs. Frequency 20 0 18 -5 INPUT RETURN LOSS (dB) 16 14 GAIN (dB) 55 16895-014 -15 16895-011 BROADBAND GAIN AND RETURN LOSS (dB) TYPICAL PERFORMANCE CHARACTERISTICS 12 10 8 +85C +25C -55C 6 4 +85C +25C -55C -10 -15 -20 -25 55 66 77 85 95 FREQUENCY (GHz) -30 45 16895-012 -5 INPUT RETURN LOSS (dB) 16 12 10 8 200mA 250mA 300mA 350mA 400mA 450mA 95 55 -10 200mA 250mA 300mA 350mA 400mA 450mA -15 -20 -25 66 77 85 FREQUENCY (GHz) 95 16895-013 GAIN (dB) 14 0 45 85 0 18 2 77 Figure 15. Input Return Loss vs. Frequency at Various Temperatures 20 4 66 FREQUENCY (GHz) Figure 12. Gain vs. Frequency for Various Temperatures 6 55 Figure 13. Gain vs. Frequency for Various IDQ Values -30 45 55 66 77 85 95 FREQUENCY (GHz) Figure 16. Input Return Loss vs. Frequency for Various IDQ Values Rev. B | Page 8 of 18 16895-016 0 45 16895-015 2 Data Sheet ADPA7001CHIPS 0 0 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V -10 -15 -20 -15 -20 -25 55 66 77 85 95 FREQUENCY (GHz) -30 45 16895-017 -30 45 55 66 77 85 95 FREQUENCY (GHz) Figure 17. Input Return Loss vs. Frequency for Various VDD Values Figure 20. Output Return Loss vs. Frequency for Various VDD Values 0 0 +85C +25C -55C -5 -10 -15 -20 -25 -10 -15 -20 200mA 250mA 300mA 350mA 400mA 450mA -25 66 77 85 95 FREQUENCY (GHz) -30 45 22 20 20 18 18 16 16 PSAT (dBm) 24 22 14 +85C +25C -55C 8 10 8 4 2 2 65 70 75 80 85 90 95 FREQUENCY (GHz) 100 16895-019 4 60 95 12 6 55 85 14 6 0 50 77 Figure 21. Output Return Loss vs. Frequency for Various IDQ Values 24 10 66 FREQUENCY (GHz) Figure 18. Output Return Loss vs. Frequency at Various Temperatures 12 55 Figure 19. P1dB vs. Frequency at Various Temperatures +85C +25C -55C 0 50 55 60 65 70 75 80 85 90 95 FREQUENCY (GHz) Figure 22. PSAT vs. Frequency at Various Temperatures Rev. B | Page 9 of 18 100 16895-022 55 16895-018 -30 45 16895-021 OUTPUT RETURN LOSS (dB) -5 OUTPUT RETURN LOSS (dB) -10 16895-020 -25 P1dB (dBm) 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V -5 OUTPUT RETURN LOSS (dB) INPUT RETURN LOSS (dB) -5 Data Sheet 24 24 22 22 20 20 18 18 16 16 PSAT (dBm) 14 12 10 200mA 250mA 300mA 350mA 400mA 450mA 8 6 4 14 12 10 6 4 2 60 65 70 75 80 85 90 FREQUENCY (GHz) 0 50 20 18 18 16 16 PSAT (dBm) 22 20 14 12 10 2 0 50 55 60 80 85 90 FREQUENCY (GHz) 0 50 55 14 14 12 12 10 10 IIP3 (dBm) 16 8 6 +85C +25C -55C 70 75 80 85 FREQUENCY (GHz) 90 16895-025 65 70 75 80 85 90 6 200mA 250mA 300mA 350mA 400mA 450mA 2 60 65 8 4 2 55 60 Figure 27. PSAT vs. Frequency for Various VDD Values 16 0 50 90 FREQUENCY (GHz) Figure 24. P1dB vs. Frequency for Various VDD Values 4 85 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 2 75 80 10 4 70 75 12 6 65 70 14 8 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 16895-024 P1dB (dBm) 24 22 4 65 Figure 26. PSAT vs. Frequency for Various IDQ Values 24 6 60 FREQUENCY (GHz) Figure 23. P1dB vs. Frequency for Various IDQ Values 8 55 16895-027 55 16895-023 0 50 16895-026 2 IIP3 (dBm) 200mA 250mA 300mA 350mA 400mA 450mA 8 Figure 25. IIP3 vs. Frequency at Various Temperatures 0 50 55 60 65 70 75 80 85 FREQUENCY (GHz) Figure 28. IIP3 vs. Frequency for Various IDQ Values Rev. B | Page 10 of 18 90 16895-028 P1dB (dBm) ADPA7001CHIPS Data Sheet ADPA7001CHIPS 16 29 14 27 25 23 8 6 21 19 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 17 4 15 0 50 1.5V 2.0V 2.5V 55 3.0V 3.5V 4.0V 60 65 13 70 75 80 85 90 FREQUENCY (GHz) 11 50 16895-029 2 55 65 70 75 80 85 90 FREQUENCY (GHz) Figure 29. IIP3 vs. Frequency for Various VDD Values Figure 32. OIP3 vs. Frequency for Various VDD Values 1.6 29 50GHz 55GHz 60GHz 65GHz 70GHz 75GHz 80GHz 85GHz 88GHz 27 1.5 25 1.4 PDISS (W) 23 OIP3 (dBm) 60 16895-032 10 OIP3 (dBm) IIP3 (dBm) 12 21 19 1.3 1.2 17 +85C +25C -55C 15 1.1 55 60 65 70 75 80 85 90 FREQUENCY (GHz) 1.0 -8 16895-030 -2 0 2 4 6 8 10 12 Figure 33. PDISS vs. Input Power at 85C for Various Frequencies 29 480 27 50GHz 55GHz 60GHz 65GHz 70GHz 75GHz 80GHz 85GHz 88GHz DRAIN SUPPLY CURRENT (mA) 460 25 23 21 19 17 200mA 250mA 300mA 350mA 400mA 450mA 15 13 55 60 440 420 400 380 360 65 70 75 80 85 FREQUENCY (GHz) Figure 31. OIP3 vs. Frequency for Various IDQ Values 90 340 -8 16895-031 OIP3 (dBm) -4 INPUT POWER AT 85C Figure 30. OIP3 vs. Frequency at Various Temperatures 11 50 -6 -6 -4 -2 0 2 4 6 RF INPUT POWER (dBm) 8 10 12 16895-034 11 50 16895-033 13 Figure 34. Drain Supply Current vs. RF Input Power for Various Frequencies Rev. B | Page 11 of 18 ADPA7001CHIPS Data Sheet 0 0 +85C +25C -55C -0.04 -20 -30 -40 -50 -60 55 66 77 85 95 FREQUENCY (GHz) -0.12 -0.20 -6 -4 -2 0 2 4 6 8 10 12 RF INPUT POWER (dBm) Figure 37. Gate Supply Current vs. RF Input Power Figure 35. Reverse Isolation vs. Frequency at Various Temperatures 1 700 +85C +25C -55C 650 600 DRAIN SUPPLY CURRENT (mA) VREF - VDET (V) 50GHz 55GHz 60GHz 65GHz 70GHz 75GHz 80GHz 85GHz 88GHz -0.16 -0.24 -8 16895-035 -70 45 -0.08 16895-037 GATE SUPPLY CURRENT (mA) REVERSE ISOLATION (dB) -10 0.1 0.01 550 500 450 400 350 300 250 200 150 100 50 Figure 36. Detector Voltage (VREF - VDET) vs. Output Power for Various Temperatures at 70 GHz Rev. B | Page 12 of 18 GATE SUPPLY VOLTAGE (V) Figure 38. Drain Supply Current vs. Gate Supply Voltage -0.2 16895-038 -0.3 -0.4 -50 -0.5 20 -0.6 18 -0.7 16 -0.8 14 -0.9 OUTPUT POWER (dBm) 12 -1.0 10 -1.1 8 -1.2 6 -1.3 4 -1.4 2 -1.5 0 -1.6 -2 -1.7 -4 -1.8 -6 16895-036 0 0.001 -8 Data Sheet ADPA7001CHIPS THEORY OF OPERATION The architecture of the ADPA7001CHIPS medium power amplifier is shown in Figure 39. The ADPA7001CHIPS uses four cascaded, four-stage amplifiers operating in quadrature between six 90 hybrids. The input signal is divided evenly into two. Then, each signal is again divided into two, and each of these paths is amplified through four independent gain stages. Then, the amplified signals are combined at the output. This balanced amplifier approach forms an amplifier with a combined gain of 14 dB and a PSAT value of 21 dBm. A portion of the RF output signal is directionally coupled to a diode for detection of the RF output power. When the diode is dc biased, it rectifies the RF power and makes it available for measurement as a dc voltage at VDET. To allow temperature compensation of VDET, an identical and symmetrically located circuit, minus the coupled RF power, is available via VREF. Taking the difference of VREF - VDET provides a temperature compensated signal that is proportional to the RF output. (see Figure 36). The 90 hybrids ensure that the input and output return losses are greater than or equal to 15 dB and 12 dB, respectively. See the application circuits shown in Figure 43 and Figure 44 for further details on biasing the various blocks. FOUR STAGE BALANCED AMPLIFIER 90 COUPLER 90 COUPLER 90 COUPLER 90 COUPLER RFOUT FOUR STAGE BALANCED AMPLIFIER 90 COUPLER 90 COUPLER DIRECTIONAL COUPLER VREF VDET Figure 39. ADPA7001CHIPS Architecture Rev. B | Page 13 of 18 16895-039 RFIN ADPA7001CHIPS Data Sheet APPLICATIONS INFORMATION The ADPA7001CHIPS is a GaAs, pHEMT, MMIC power amplifier. Capacitive bypassing is required for VDD1A through VDD4A and VDD1B through VDD4B (see Figure 43). VGG12A is the gate bias pad for the first and second gain stages. VGG34A is the gate bias pad for the third and fourth gain stages. Apply a gate bias voltage to VGG12A and VGG34A, and use capacitive bypassing as shown in Figure 43. All measurements for this device were taken using the typical application circuit (see Figure 43) and configured as shown in the assembly diagram (Figure 45). Table 7. Power Selection Table1, 2 IDQ (mA) 200 250 300 350 400 450 1 2 The following is the recommended bias sequence during power-up: Gain (dB) 10 11.5 13 14 15 16 P1dB (dBm) 11 13.5 15.5 16.5 17.5 18 OIP3 (dBm) 22 23 24 25 26 27 PDISS (mW) 700 875 1050 1225 1400 1575 VGG (V) -0.64 -0.59 -0.54 -0.48 -0.44 -0.39 Data taken at the following nominal bias conditions: VDD = 3.5 V, T = 25C. Adjust VGG12A and VGG34A from -1.5 V to 0 V to achieve the desired drain current. The following is the recommended bias sequence during power-down: The VDD = 3.5 V and IDD = 350 mA bias conditions are recommended to optimize overall performance. Unless otherwise noted, the data shown was taken using the recommended bias conditions. Operation of the ADPA7001CHIPS at different bias conditions may provide performance that differs from what is shown in Table 1 and Table 2. Biasing the ADPA7001CHIPS for higher drain current typically results in higher P1dB, output IP3, and gain at the expense of increased power consumption (see Table 7). 1. 2. MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS 1. 2. 3. 4. 5. 3. 4. Connect GND to RF/dc ground. Set the gate bias voltage to -1.5 V. Set all the drain bias voltages, VDD = 3.5 V. Increase the gate bias voltage to achieve a quiescent current, IDQ = 350 mA. Apply the RF signal. Turn off the RF signal. Decrease the gate bias voltage to -1.5 V to achieve IDQ = 0 mA (approximately). Decrease all of the drain bias voltages to 0 V. Increase the gate bias voltage to 0 V. VDD1A VDD2A VDD1B VDD2B VDD3A VDD3B Attach the die directly to the ground plane with conductive epoxy (see the Handling Precautions section, the Mounting section, and the Wire Bonding section). VDD4A VDD4B RFIN RFOUT Microstrip, 50 transmission lines on 0.127 mm (5 mil) thick alumina, thin film substrates are recommended for bringing the radio frequency to and from the chip. Raise the die 0.075 mm (3 mil) to ensure that the surface of the die is coplanar with the surface of the substrate. Place microstrip substrates as close to the die as possible to minimize ribbon bond length. Typical die to substrate spacing is 0.076 mm to 0.152 mm (3 mil to 6 mil). To ensure wideband matching, a 15 fF capacitive stub is recommended on the PCB board before the ribbon bond. VGG12A VGG12B 16895-045 VGG34A VGG34B MATCHING STUB/BOND PAD SHUNT CAPACITANCE = 15fF Figure 40. Simplified Block Diagram Simplified bias pad connections to dedicated gain stages and dependence and independence among pads are shown in Figure 40. RFIN 50 TRANSMISSION LINE 3mil GOLD RIBBON 3mil GAP MMIC Figure 41. High Frequency Input Wideband Matching Rev. B | Page 14 of 18 16895-040 PCB BOARD Data Sheet ADPA7001CHIPS MATCHING STUB/BOND PAD SHUNT CAPACITANCE = 15fF RFOUT 3mil GOLD RIBBON 50 TRANSMISSION LINE PCB BOARD MMIC Mounting 16895-041 3mil GAP Figure 42. High Frequency Output Wideband Matching Place microstrip substrates as close to the die as possible to minimize bond wire length. Typical die to substrate spacing is 0.076 mm to 0.152 mm (3 mil to 6 mil). Handling Precautions To avoid permanent damage, follow these storage, cleanliness, static sensitivity, transient, and general handling precautions: Place all bare die in either waffle or gel-based ESD protective containers and then seal the die in an ESD protective bag for shipment. After the sealed ESD protective bag is opened, store all die in a dry nitrogen environment. Handle the chips in a clean environment. Do not attempt to clean the chip using liquid cleaning systems. Follow ESD precautions to protect against ESD strikes. While bias is applied, suppress instrument and bias supply transients. Use shielded signal and bias cables to minimize inductive pickup. Handle the chip along the edges with a vacuum collet or with a sharp pair of tweezers. The surface of the chip have fragile air bridges and must not be touched with vacuum collet, tweezers, or fingers. Before epoxy die is attached, apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip after it is placed into position. Cure the epoxy per the schedule of the manufacturer. Wire Bonding RF bonds made with 0.003 in. x 0.0005 in. gold ribbon are recommended for the RF ports. These bonds must be thermosonically bonded with a force of 40 g to 60 g. DC bonds of 0.001 in. (0.025 mm) diameter, thermosonically bonded, are recommended. Create ball bonds with a force of 40 g to 50 g and wedge bonds with a force of 18 g to 22 g. Create all bonds with a nominal stage temperature of 150C. Apply a minimum amount of ultrasonic energy to achieve reliable bonds. Keep all bonds as short as possible, less than 12 mil (0.31 mm). Alternatively, short (3 mil) RF bonds made with two 1 mil wires can be used. Rev. B | Page 15 of 18 ADPA7001CHIPS Data Sheet TYPICAL APPLICATION CIRCUIT The drain and gate voltages can be applied to either the north or the south side of the circuit. NO DC BIAS APPLIED NC 100pF 100pF 100pF + 4.7F 0.01F 100pF 100pF NC 4.7F 0.01F 100pF + 2 3 4 5 6 7 RFIN 1 RFOUT 8 9 10 11 +5V 12 13 VDET 14 100k 100k 10k +5V 10k 15 16 VREF VOUT = VREF - VDET 100pF 4.7F 0.01F 100pF 10k + VDD1B TO VDD4B 10k -5V 100pF100pF100pF + 4.7F 0.01F 100pF SUGGESTED CIRCUIT 16895-043 VGG12B TO VGG34B Figure 43. Application Circuit VDD1A TO VDD4A VGG12A TO VGG34A 100pF 100pF 100pF + 4.7F 0.01F 100pF 100pF 4.7F 0.01F 100pF + 2 3 4 5 6 7 RFIN 1 RFOUT 8 9 10 11 +5V 12 13 100k VDET 14 100k 10k +5V 10k 15 16 VREF NC VOUT = VREF - VDET 100pF 4.7F 0.01F 100pF 10k + 10k + 4.7F 0.01F 100pF -5V 100pF100pF 100pF SUGGESTED CIRCUIT NO DC BIAS APPLIED Figure 44. Alternate Application Circuit Rev. B | Page 16 of 18 16895-144 NC Data Sheet ADPA7001CHIPS 16895-044 ASSEMBLY DIAGRAM Figure 45. Assembly Diagram Rev. B | Page 17 of 18 ADPA7001CHIPS Data Sheet OUTLINE DIMENSIONS 2.500 0.208 0.087 2 5 4 3 0.05 0.149 0.076 x 0.076 6 7 0.144 3.320 0.048 x 0.083 8 2.170 0.048 x 0.083 2.045 1 1.408 1.920 1.283 1.158 0.461 15 14 13 12 11 10 9 TOP VIEW (CIRCUIT SIDE) 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.120 0.15 0.15 0.15 0.15 0.15 *AIR BRIDGE AREA *This die utilizes fragile air bridges. Any pickup tools used must not contact this area. SIDE VIEW 07-30-2018-A 16 0.072 Figure 46. 16-Pad Bare Die [CHIP] (C-16-2) Dimensions shown in millimeters ORDERING GUIDE Model ADPA7001CHIPS ADPA7001CHIPS-SX Temperature Range -55C to +85C -55C to +85C Package Description 16-Pad Bare Die [CHIP] 16-Pad Bare Die [CHIP] (c)2018-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16895-0-10/19(B) Rev. B | Page 18 of 18 Package Option C-16-2 C-16-2