IRFP450 - Intersil Corporation

4-353

File Number

2331.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

IRFP450

14A, 500V, 0.400 Ohm, N-Channel

Power MOSFET

This N-Channel enhancement mode silicon gate power ﬁeld

effect transistor is an advanced power MOSFET designed,

tested, and guaranteed to withstand a speciﬁed level of

energy in the breakdown avalanche mode of operation. All of

these power MOSFETs are designed for applications such

as switching regulators, switching convertors, motor drivers,

relay drivers, and drivers for high power bipolar switching

transistors requiring high speed and low gate drive power.

These types can be operated directly from integrated

circuits.

Formerly developmental type TA17435.

Features

• 14A, 500V

•r

DS(ON) = 0.400Ω

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

JEDEC STYLE TO-247

Ordering Information

PART NUMBER PACKAGE BRAND

IRFP450 TO-247 IRFP450

NOTE: When ordering, use the entire part number. G

SOURCE

DRAIN

GATE

DRAIN

(TAB)

Data Sheet July 1999

4-354

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Speciﬁed

IRFP450 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 500 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 500 V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID14

8.8 A

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 56 A

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

GS ±20 V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD180 W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.44 W/oC

Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 860 mJ

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T

STG -55 to 150 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. TJ = 25oC to 125oC.

Electrical Speciﬁcations TC = 25oC, Unless Otherwise Speciﬁed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 500 - - V

Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V

Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA

VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA

On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 14 - - A

Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA

On Resistance (Note 2) rDS(ON) ID = 7.9A, VGS = 10V (Figures 8, 9) - 0.3 0.4 Ω

Forward Transconductance (Note 2) gfs VDS ≥ 50V, ID = 7.9A (Figure 12) 9.3 13.8 - S

Turn-On Delay Time td(ON) VDD =250V, ID≈14A, VGS = 10V, RGS = 6.1Ω,

RL = 17.4Ω MOSFET Switching Times are

Essentially Independent of Operating Temperature

-1627ns

Rise Time tr-4566ns

Turn-Off Delay Time td(OFF) - 68 100 ns

Fall Time tf-4160ns

Total Gate Charge

(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID≈ 14A, VDS = 0.8 x Rated BVDSS

IG(REF) = 1.5mA (Figure 14) Gate Charge is

Essentially Independent of OperatingTemperature

- 82 130 nC

Gate to Source Charge Qgs -12-nC

Gate to Drain “Miller” Charge Qgd -42-nC

Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 2000 - pF

Output Capacitance COSS - 400 - pF

Reverse Transfer Capacitance CRSS - 100 - pF

Internal Drain Inductance LDMeasured from the Contact

Screw on Header Closer to

Source and Gate Pins to

Center of Die

Modified MOSFET

Symbol Showing the

Internal Device

Inductances

- 5.0 - nH

Internal Source Inductance LSMeasured from the Source

Lead, 6.0mm (0.25in) from

Header to Source Bonding

Pad

- 12.5 - nH

Thermal Resistance, Junction to Case RθJC - - 0.70 oC/W

Thermal Resistance, Junction to Ambient RθJA Free Air Operation - - 30 oC/W

IRFP450

4-355

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current ISD Modified MOSFET Symbol

Showing the Integral

Reverse P-N Junction

Rectifier

- - 14 A

Pulse Source to Drain Current (Note 3) ISDM - - 56 A

Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 14A, VGS = 0V (Figure 13) - - 1.4 V

Reverse Recovery Time trr TJ = 150oC, ISD = 13A, dISD/dt = 100A/µs - 1300 - ns

Reverse Recovery Charge QRR TJ = 150oC, ISD = 13A, dISD/dt = 100A/µs - 7.4 - µC

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD = 50V, starting TJ= 25oC, L = 7.9mH, RG= 25Ω, peak IAS = 14A.

Typical Performance Curves

Unless Otherwise Speciﬁed

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

0 50 100 150

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

0.2

0.4

0.6

0.8

1.0

1.2

050 100

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

150

25 75 125

0.1

10-3

10-5 10-4 10-3 10-2 0.1 1 10

ZθJC, THERMAL IMPEDANCE

t1, RECTANGULAR PULSE DURATION (s)

SINGLE PULSE

PDM

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC + TC

0.1

0.02

0.2

0.5

0.01

0.05

10-2

IRFP450

4-356

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

NOTE: Heating effect of 2µs is minimal.

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves

Unless Otherwise Speciﬁed (Continued)

110

102103

VDS, DRAIN TO SOURCE VOLTAGE (V)

103

102

0.1

ID, DRAIN CURRENT (A)

SINGLE PULSE

TJ = MAX RATED

BY rDS(ON)

AREA IS LIMITED

OPERATION IN THIS

10µs

100µs

1ms

10ms

ID, DRAIN CURRENT (A)

0 50 100 150 200

250

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

VGS = 10V

VGS = 6.0V

VGS = 4.5V

VGS = 4.0V

VGS = 5.5V

VGS = 5.0V

DUTY CYCLE = 0.5% MAX

0369 15

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 10V

VGS = 4.5V

VGS = 5.5V

VGS = 6.0V

VGS = 5.0V

VGS = 4.0V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

102

0.1

10-2

0246810

VGS, GATE TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT(A)

TJ = 150oCTJ = 25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDS ≥ 50V

0.3

0.6

10 20 30 40

rDS(ON), ON-STATE RESISTANCE (S)

ID, DRAIN CURRENT (A)50

0.7

0.4

0.5

0.8

VGS = 20V

VGS = 10V

60 70

0.9

10 PULSE DURATION = 2µs

DUTY CYCLE = 0.5% MAX

rDS(ON), NORMALIZED DRAIN TO SOURCE

3.0

1.8

1.2

0.6

0-40 0 40

TJ, JUNCTION TEMPERATURE (oC)

120

2.4

80 160

ON RESISTANCE

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = 10V, ID = 7.9A

IRFP450

4-357

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves

Unless Otherwise Speciﬁed (Continued)

rDS(ON), NORMALIZED DRAIN TO SOURCE

1.25

1.05

0.95

0.85

0.75 -40 0 40

TJ, JUNCTION TEMPERATURE (oC)

120

1.15

ID = 250µA

160

BREAKDOWN VOLTAGE

VDS, DRAIN TO SOURCE VOLTAGE (V)

C, CAPACITANCE (pF)

10000

8000

6000

4000

2000

012 5102 5

102

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

VGS = 0V, f = 1MHz

CISS

COSS

CRSS

0048121620

ID, DRAIN CURRENT (A)

gfs, TRANSCONDUCTANCE (S)

TJ = 150oC

TJ = 25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDS ≥ 50V

0 0.5 1.0 1.5 2.0 2.5

VSD, SOURCE TO DRAIN VOLTAGE (V)

102

0.1

ISD, SOURCE TO DRAIN CURRENT (A)

= 150

TJ = 25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

0 25 50 75 100 125

ID = 14A

Qg, GATE CHARGE (nC)

VGS, GATE TO SOURCE (V)

VDS = 250V

VDS = 400V

VDS = 100V

IRFP450

4-358

Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS

DUT

-VDD

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

0.3µF

12V

BATTERY 50kΩ

VDS

DUT

IG(REF)

(ISOLATED

VDS

0.2µF

CURRENT

REGULATOR

ID CURRENT

SAMPLING

IG CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR

SAME TYPE

AS DUT Qg(TOT)

Qgd

Qgs

VDS

VGS

VDD

IG(REF)

IRFP450

4-359

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

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from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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IRFP450