2001-2013 Microchip Technology Inc. DS35007C-page 1
PIC16F84A
High Performance RISC CPU Features:
• Only 35 single word instructions to learn
• All instructions single-cycle except for program
branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 1024 words of program memory
• 68 bytes of Data RAM
• 64 bytes of Data EEPROM
• 14-bit wide instruction words
• 8-bit wide data bytes
• 15 Special Function Hardware registers
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Four interrupt sources:
- External RB0/INT pin
- TMR0 timer overflow
- PORTB<7:4> interrupt-on-change
- Data EEPROM write complete
Peripheral Feat ures:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 25 mA source max. per pin
• TMR0: 8-bit timer/counter with 8-bit
progra mmable presca le r
S pecial Microcontroller Feat ures:
• 10,000 erase/write cycles Enhanced FLASH
Program memory typica l
• 10,000,0 00 typ ic al erase/wri te cy cles EEPROM
Data memory t ypical
• EEPROM Data Retention > 40 years
• In-Circuit Serial Programming™ (ICSP™) - via
two pins
• Power-on Res et (POR), Power-up T imer (PWRT),
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip RC
Oscillator for reliable operation
• Code protection
• Power saving SLEEP mode
• Selectable osc illator options
Pin Diagrams
CMOS Enhanced FLASH/EEPROM
Technology:
• Low power, high speed technology
• Fully static design
• Wide operating voltage range:
- Commercial: 2.0V to 5.5V
- Industrial: 2.0V to 5.5V
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
-15 A typical @ 2V, 32 kHz
- < 0.5 A typic al st andby current @ 2V
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
RA2
RA3
RA4/T0CKI
MCLR
VSS
RB0/INT
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PDIP, SOIC
PIC16F84A
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
RA2
RA3
RA4/T0CKI
MCLR
VSS
RB0/INT
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
SSOP
PIC16F84A
10 11
VSS
VDD
18-pin Enhanced FLASH/EEPROM 8-Bit Micr ocontroller
PIC16F84A
DS35007C-page 2 2001-2013 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 3
2.0 Memory O rganization................................................................................................................................................................... 5
3.0 Data EEP R OM Memo ry.......... ................................ ................................... ................................................................................ 13
4.0 I/O Ports...................................... ........................................ .................................... ................................................................... 15
5.0 Timer0 Module ........................................................................................................................................................................... 19
6.0 Speci a l Features of th e CPU.............................. ............................ ............................... ............................................................. 21
7.0 Instruction Set Summary............................................................................................................................................................ 35
8.0 Development Suppor t. ................................................................................................................................................................ 43
9.0 Electrical Characteristics............................................................................................................................................................ 47
10.0 DC/AC Characteristic Graphs .................................................................................................................................................... 59
11.0 Packagin g In fo rmation..... ....................... ........................... ................................ ............... .......................................................... 69
Appendix A: Revision History .............................................................................................................................................................. 77
Appendix B: Conversion Considerations.................... ......... .. .... .. .... .. ......... .. .... .. .... ....... .... .. .... .. ........................................................... 78
Appendix C: Migration from Baseline to
Mid-range Devices80
INDEX.................................................................................................................................................................................................. 81
The Micro chip Web Site... ........................................ .................................... ........................................................................................ 85
Customer Change Notification Service ................................................................................................................................................ 85
Customer Support.................................................. ................. ...... ................. ........ .............................................................................. 85
Reader Response................................................................................................................................................................................ 86
PIC16F84A Product Identification System........................................................................................................................................... 87
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2001-2013 Microchip Technology Inc. DS35007C-page 3
PIC16F84A
1.0 DEVICE OVERVIEW
This do cu me nt co nta i ns dev ic e spec if i c in for m at ion fo r
the operation of the PIC16F84A device. Additional
information may be found in the PIC® Mid-Range Ref-
erence M anual, (DS33 023), which ma y be downloade d
from the Microchip website. The Reference Manual
should be considered a complementary document to
this dat a shee t, and is hig hly recom mended re ading for
a better understanding of the device architecture and
operation of the peripheral modules.
The PIC 16 F84 A be lo ngs to the mid-range fa mi ly o f th e
PIC® microcontroller devices. A block diagram of the
device is shown in Figure 1-1.
The program memory contains 1K words, which trans-
lates to 1024 instructions, since each 14-bit program
memory word is the same width as each device instruc-
tion. The data memory (RAM) contains 68 bytes. Data
EEPROM is 64 bytes.
There are also 13 I/O pins that are user-configured on
a pin-to-pin bas is. Some pins are multiplexed with other
device functions. These functions include:
• External inte rrup t
• Change on PORTB interrupt
• Timer0 clock input
Table 1-1 details the pinout of the device with descrip-
tions and details for each pin.
FIGURE 1-1: PIC16F84 A BLOCK DIAGRAM
FLASH
Program
Memory
Program Counter
13
Program
Bus
Instruction Register
8 Level S tack
(13-bit)
Direct Addr
8
Instruction
Decode &
Control
Timing
Generation
OSC2/CLKOUT
OSC1/CLKIN
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VDD, VSS
W reg
ALU
MUX I/O Por ts
TMR0
STATUS reg
FSR reg
Indirect
Addr
RA3:RA0
RB7:RB1
RA4/T0CKI
EEADR
EEPROM
Data Memory
64 x 8
EEDATA
Addr Mux
RAM Addr
RAM
File Registers
EEPROM D ata M emory
Data Bus
5
7
7
RB0/INT
14
8
8
1K x 14 68 x 8
PIC16F84A
DS35007C-page 4 2001-2013 Microchip Technology Inc.
TABLE 1-1: PIC16F84A PINOUT DESCRIPTION
Pin Name PDIP
No. SOIC
No. SSOP
No. I/O/P
Type Buffer
Type Description
OSC1/CLKIN 16 16 18 I ST/CMOS(3) Oscillator crystal input/external clock sour ce input.
OSC2/CLKOUT 15 15 19 O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. In RC mode,
OSC2 pin outputs CLKOUT, which has 1/4 the
frequency of OSC1 and denotes the instruction
cycle rate.
MCLR 4 4 4 I/P ST Master Clear (Reset) input/programming voltage
input. Thi s pin is an active l ow RESET to the device.
PORTA is a bi-directional I/O port.
RA0 17 17 19 I/O TTL
RA1 18 18 20 I/O TTL
RA2 1 1 1 I/O TTL
RA3 2 2 2 I/O TTL
RA4/T0CKI 3 3 3 I/O ST Can also be se lec ted to be the clo ck in put t o the
TMR0 timer/counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on
all inputs.
RB0/INT 6 6 7 I/O TTL/ST(1) RB0 /INT can also be selected as an ex ternal
interrupt pin.
RB1 7 7 8 I/O TTL
RB2 8 8 9 I/O TTL
RB3 9 9 10 I/O TTL
RB4 10 10 11 I/O TTL Interrupt-on-change pin.
RB5 11 11 12 I/O TTL Interrupt-on-change pin.
RB6 12 12 13 I/O TTL/ST(2) Interrupt-on-change pin.
Serial program mi ng cloc k.
RB7 13 13 14 I/O TTL/ST(2) Interrupt-on-change pin.
Serial program mi ng dat a.
VSS 5 5 5,6 P — Ground reference for logic and I/O pins.
VDD 14 14 15,16 P — Positive supply for logic and I/O pins.
Legend: I= input O = Output I/O = Input/Output P = Power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigge r input when configured as the externa l interrupt.
2: This buffer is a Sc hmitt Trigger input when used in S erial Programming mo de.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2001-2013 Microchip Technology Inc. DS35007C-page 5
PIC16F84A
2.0 MEMORY ORGANIZATION
There are two memory blocks in the PIC16F84A.
These are the program memory and the data memory.
Each block has its own bus, so that access to each
block can occur during the same oscillator cycle.
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into th e data m em ory, but is i ndi rec tly m ap ped . T hat is,
an indir ect addres s pointer s peci fies th e addre ss of th e
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 3.0.
Addit ional informat ion on devi ce memory may be found
in the PIC® Mid-Range Reference M anual, (DS33 023).
2.1 Program Memory Organization
The P IC16FXX has a 13-bit p rogram c ounter capable
of addressing an 8K x 14 program memory space. For
the PIC16F84A, the first 1K x 14 (0000h-03FFh) are
physic ally im plemented (Fi gure 2-1). Acce ssing a l oca-
tion above the physically implemented address will
cause a wraparound. For example, for locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h,
the instruction will be the same.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK - PIC16F84A
PC<12:0>
Stack Level 1
Stack Level 8
RESET Vector
Peripheral Interrupt Vector
User Memory
Space
CALL, RETURN
RETFIE, RETLW 13
0000h
0004h
1FFFh
3FFh
PIC16F84A
DS35007C-page 6 2001-2013 Microchip Technology Inc.
2.2 Data Memory Organization
The dat a mem ory is p artiti oned into two areas . The firs t
is the Special F unctio n Regis ters (SFR) a rea , while th e
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device.
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general
purpose RAM. The banked areas of the SFR are fo r the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These c ont rol b it s are loc ated in th e STATUS Regi ste r.
Figure 2-2 shows the data memory map organization.
Instructions MOVWF and MOVF can move values from
the W register to any location in the register file (“F”),
and vice-versa.
The entire data memory can be accessed either
directly us in g the abso lute addres s of each registe r fil e
or indirectly through the File Select Register (FSR)
(Section 2.5). Indirect addressing uses the present
value of the RP0 b it for access into th e banked areas of
data memory.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (ST ATUS<5>). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers, implemented as static RAM.
2.2.1 GENERAL PURPOSE REGISTER
FILE
Each General Purpose Register (GPR) is 8-bits wide
and is a cc essed ei ther directl y o r indirectl y th rou gh th e
FSR (Sectio n 2.5).
The GPR addresses in Bank 1 are mapped to
address es in B ank 0. As an ex am ple , add res si ng l oc a-
tion 0Ch or 8Ch will access the same GPR.
FIGURE 2-2: REGISTER FILE MAP -
PIC16F84A
File Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
FFh
Bank 0 Bank 1
Indirect addr.(1) Indirect addr .(1)
TMR0 OPTION_REG
PCL
STATUS
FSR
PORTA
PORTB
EEDATA
EEADR
PCLATH
INTCON
68
General
Purpose
Registers
(SRAM)
PCL
STATUS
FSR
TRISA
TRISB
EECON1
EECON2(1)
PCLATH
INTCON
Mapped
in Bank 0
Unimplemented data memory location, read as '0'.
File Address
Note 1: Not a physical regist er.
CFh
D0h
4Fh
50h
(accesses)
——
2001-2013 Microchip Technology Inc. DS35007C-page 7
PIC16F84A
2.3 Special Function Registers
The Special Function Registers (Figure 2-2 and
Table 2-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
The spec ial function regi sters can be clas sified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
describ ed in the se ction for that speci fic feature .
TABLE 2-1: SPECIAL FUNCTION REGISTER FILE SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-on
RESET
Details
on pa ge
Bank 0
00h INDF Uses contents of FSR to address Data Memory (not a physical register) ---- ---- 11
01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 20
02h PCL Low Order 8 bits of the Program Counter (PC) 0000 0000 11
03h STATUS(2) IRP RP1 RP0 TO PD ZDCC
0001 1xxx 8
04h FSR Indirect Data Memory Address Pointer 0 xxxx xxxx 11
05h PORTA(4) — — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx 16
06h PORTB(5) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx 18
07h —Unimplemented location, read as '0' — —
08h EEDATA EEPROM Data Register xxxx xxxx 13,14
09h EEADR EEP ROM Address Register xxxx xxxx 13,14
0Ah PCLATH — — — Write Buffer for upper 5 bits of the PC(1) ---0 0000 11
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 10
Bank 1
80h INDF Uses Contents of FSR to address Data Memory (not a physical register) ---- ---- 11
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 9
82h PCL Low order 8 bits of Program Counter (PC) 0000 0000 11
83h STATUS (2) IRP RP1 RP0 TO PD ZDCC
0001 1xxx 8
84h FSR Indirect data memory address pointer 0 xxxx xxxx 11
85h TRISA — — — PORTA Data Direction Register ---1 1111 16
86h TRISB PORTB Data Direction Register 1111 1111 18
87h —Unimplemented location, read as '0' — —
88h EECON1 — — — EEIF WRERR WREN WR RD ---0 x000 13
89h EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 14
0Ah PCLATH — — — Write buffer for upper 5 bits of the PC(1) ---0 0000 11
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 10
Legend: x = unknown, u = unchanged. - = unimplemented, read as '0', q = value depends on condition
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> are never trans-
ferred to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR Reset.
3: Other (non power-up) RESET S include: external RESET through MCLR and the Wat chdog Timer Reset.
4: On any device RESET, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
PIC16F84A
DS35007C-page 8 2001-2013 Microchip Technology Inc.
2.3.1 STATUS REGIS TER
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bit for
data memory.
As with any register, the STATUS register can be the
destina tion for any instruction. If the ST A TUS register is
the destination for an instruction that affects the Z, DC
or C bits, then the write to these three bits is disabled.
These b its are set o r c lea red ac co rdin g to device logic .
Furthermore, the TO and PD bits are not writable.
Therefore , the resul t of an ins truc ti on w i th t he STATUS
register as dest ina tio n ma y b e different than inte nde d.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS reg ister (Table 7- 2),
because these instructions do not affect any status bit.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16F84A and
should be progra mmed as cleared . Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
3: When the STATUS register is the
destination for an instruction that affects
the Z, DC or C bit s, then the writ e to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7-6 Unimplemented: Maintain as ‘0’
bit 5 RP0: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction , or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF inst ructio ns) (for borrow , the p olarit y
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is
reversed)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: A subtraction is executed by adding the tw o’s complement of the second operand.
For rotate (RRF, RLF) instruc tio ns, this bit is l oad ed w ith ei the r th e high or low ord er
bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001-2013 Microchip Technology Inc. DS35007C-page 9
PIC16F84A
2.3.2 OPTION REGISTER
The OPTION register is a readable and writable
register whi ch con t ains various cont rol bi ts to c onfigu re
the TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION REGISTER (ADDRESS 81h)
Note: When the prescaler is assigned to
the WDT (PSA = '1'), TMR0 has a 1:1
prescaler assignment.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (C LKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16F84A
DS35007C-page 10 2001-2013 Microchip Technology Inc.
2.3.3 INTCON REGISTER
The INTCON register is a readable and writable
register that contains the various enable bits for all
interrupt sources.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
Note: Interru pt fl ag bits are set when an in terrupt
conditi on occ urs , re gardless of the st ate of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interr upts
bit 6 EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE Write Complete interrupts
0 = Disables the EE Write Complete interrupt
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TM R0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register h as overflowed (must be cleared in software)
0 = TMR0 register d id not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external inte rrupt occurred (must be cleared in softwar e )
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001-2013 Microchip Technology Inc. DS35007C-page 11
PIC16F84A
2.4 PCL and PCLATH
The pr ogra m cou nter (PC) specifies th e a ddre ss of th e
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. If the pro-
gram counter (PC) is modified or a conditional test is
true, the instruction requires two cycles. The second
cycle is execu ted as a NOP. All u pdates to the PC H reg-
ister go through the PCLATH register.
2.4.1 STACK
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from thi s branch in program executi on.
Mid-range devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writ able. The PC i s PUSHed on to the st ack
when a CALL instruction is executed or an interrupt
causes a bran ch . The st ac k i s PO Ped in the ev en t of a
RETURN, RETLW or a RETFIE instruction execution.
PCLAT H is no t mo di fie d wh en t he s tac k i s P US Hed o r
POPed.
Aft er the st ack has been PU SHed eigh t times , the nin th
push ov erwrit es the v alue tha t was stor ed fro m the first
push. The tenth p us h ov erw ri tes the second push (an d
so on).
2.5 Indirect Addressing; INDF and
FSR Registers
The INDF register is no t a physica l register . Addr essing
INDF actu ally ad dresse s the regi ster w hose ad dress i s
cont ained in the FSR reg ister (FSR is a pointer). This is
indirect addressing.
EXAMPLE 2-1: INDIR ECT ADDRESS ING
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
An effective 9-bit address is obtained by concatenating
the 8-bit FSR reg ister and the IRP bi t (ST A TU S<7>), as
shown in Figure 2-3. However, IRP is not used in the
PIC16F84A.
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of th e IND F r egi ste r will return the v al ue
of 10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah.
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
PIC16F84A
DS35007C-page 12 2001-2013 Microchip Technology Inc.
FIGURE 2-3: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1 RP0 6 From Opcode 0IRP7
(FSR) 0
Indirect Addressing
Bank Select Location Select Bank Select Location Select
00 01 80h
FFh
00h
0Bh
0Ch
7Fh
Bank 0 Bank 1
Note 1: For memory map detail, see Figure 2-2.
2: Maintain as clear for upward compatibility with future products.
3: Not implemented.
4Fh
50h
Data
Memory(1)
(3) (3)
(2) (2)
Addresses
map back to
Bank 0
2001-2013 Microchip Technology Inc. DS35007C-page 13
PIC16F84A
3.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (ful l VDD range). This me mo ry
is not d irectly mapp ed in the register file spa ce. Instea d
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
• EECON1
• EECON2 (not a physically implemented register)
• EEDATA
• EEADR
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC16F84A devices have 64 bytes of
data EEPROM with an address range from 0h to 3Fh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the n ew data (erase be fore write). The EEPROM
data memory is rated for high erase/wri te cycles. The
write time is controlled by an on-chip timer. The write-
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
When the device is code protected, the CPU may
continu e to rea d and wr ite th e data EEPROM memory.
The device programmer can no longer access
this memory.
Additional information on the Data EEPROM is avail-
able in the PIC® Mid-Range Reference Manual
(DS33023).
REGISTER 3-1: EECON1 REGISTER (ADDRESS 88h)
U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
— — — EEIF WRERR WREN WR RD
bit 7 bit 0
bit 7-5 Unimplemented: Read as '0 '
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prem at urel y term ina ted
(any MCLR Reset or any WDT Reset during normal operation)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1 WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F84A
DS35007C-page 14 2001-2013 Microchip Technology Inc.
3.1 Reading the EEPROM Data
Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
nex t cycle, in the EEDATA register; therefore, it can be
read in the next instructi on. EEDATA will hold this v alue
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 3-1: DATA EEPROM READ
3.2 Writing to the EEPROM Data
Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 3-2: DATA EEPROM WRITE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental writes
to data EEPROM due to errant (unexpected) code exe-
cution (i.e., lost programs). The user should keep the
WREN bit clear at all times, except when updating
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit wil l not af fect this wr ite cycle. T he WR bit wil l
be inhib ited from bei ng s et unless the W R EN bit is se t.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
3.3 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 3-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the spe cif ic ati on lim it .
Generally, the EEPROM write failure will be a bi t which
was written as a '0', but reads back as a '1' (due to
leakage off the bit).
EXAMPL E 3-3: WRITE VER IF Y
TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
BCF STATUS, RP0 ; Bank 0
MOVLW CONFIG_ADDR ;
MOVWF EEADR ; Address to read
BSF STATUS, RP0 ; Bank 1
BSF EECON1, RD ; EE Read
BCF STATUS, RP0 ; Bank 0
MOVF EEDATA, W ; W = EEDATA
BSF STATUS, RP0 ; Bank 1
BCF INTCON, GIE ; Disable INTs.
BSF EECON1, WREN ; Enable Write
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1,WR ; Set WR bit
; begin write
BSF INTCON, GIE ; Enable INTs.
Required
Sequence
BCF STATUS,RP0 ; Bank 0
: ; Any code
: ; can go here
MOVF EEDATA,W ; Must be in Bank 0
BSF STATUS,RP0 ; Bank 1
READ
BSF EECON1, RD ; YES, Read the
; value written
BCF STATUS, RP0 ; Bank 0
;
; Is the value written
; (in W reg) and
; read (in EEDATA)
; the same?
;
SUBWF EEDATA, W ;
BTFSS STATUS, Z ; Is difference 0?
GOTO WRITE_ERR ; NO, Write error
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n
Power-on
Reset
Value on
all other
RESETS
08h EEDATA EEPROM Data Register xxxx xxxx uuuu uuuu
09h EEADR EEPROM Address Register xxxx xxxx uuuu uuuu
88h EECON1 — — — EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM Control Register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition.
Shaded cells are not used by data EEPROM.
2001-2013 Microchip Technology Inc. DS35007C-page 15
PIC16F84A
4.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Addit ion al inf orm atio n o n I/O ports may be found i n the
PIC® Mid-Range Reference Manual (DS33023).
4.1 PORTA and TRISA Registers
PORTA is a 5-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA b it (= 1) will make the correspondin g PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the correspon ding POR TA pin an out put (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, where as wri tin g to i t wi ll write to th e port latch. All
write operations are read-modify-write operations.
Therefore , a write to a port implies that the port pins are
read. This value is modi fied and then writt en to the port
data l atc h.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schm itt Trigger inp ut and an open d rain o utput.
All other RA port pins have TTL input levels and full
CMOS output drivers.
EXAMPLE 4-1: INITIALIZING PORTA
FIGURE 4-1: BLOCK DIAGRAM OF
PINS RA3:RA0
FIGURE 4-2: BLOCK DIAGRAM OF PIN
RA4
Note: On a Pow er-on Re set, t hese pins ar e con-
figured as inputs and read as '0'.
BCF STATUS, RP0 ;
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x0F ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA4 as output
; TRISA<7:5> are always
; read as '0'.
Data
Bus
Q
D
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD Po rt
TTL
Input
Buffer
VSS
VDD
I/O pin
Note: I/O pins have protection diodes to VDD and VSS.
Data
Bus
WR
Port
WR
TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
N
VSS
RA4 pin
TMR0 Clock Input
QD
Q
CK
QD
Q
CK
EN
QD
EN
Note: I/O pins have protection diodes to VDD and VSS.
PIC16F84A
DS35007C-page 16 2001-2013 Microchip Technology Inc.
TABLE 4-1: PORTA FUNCTIONS
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit0 Buffer Type Function
RA0 bit0 TTL Input/output
RA1 bit1 TTL Input/output
RA2 bit2 TTL Input/output
RA3 bit3 TTL Input/output
RA4/T0CKI bit4 ST Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Add r e s s Nam e Bit 7 Bit 6 B it 5 Bit 4 B it 3 Bit 2 B i t 1 B it 0 Va lue on
Power-on
Reset
V alue on all
other
RESETS
05h PORTA ——— RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
85h TRISA ——— TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are unimplemented, read as '0'.
2001-2013 Microchip Technology Inc. DS35007C-page 17
PIC16F84A
4.2 PORTB and TRISB Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the co rresponding POR TB pin an output (i.e., put
the contents of the output latch on the selected pin).
EXAMPLE 4-2: INITIALIZING PORTB
Each of th e POR TB pins has a we ak inte rnal pul l-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configu red as an outpu t. The pull- ups are disab led on a
Power-on Reset.
Four of POR TB’s pi ns, RB7:RB4, hav e an interrupt-o n-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
inter rupt in the fol lowi ng man ne r :
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used f or the int errup t-on - ch ang e
feature. Polling of PORTB is not recommended while
usin g the interrupt-on-change feature.
FIGURE 4-3: BLOCK DIAGRAM OF
PINS RB7:RB4
FIGURE 4-4: BLOCK DIAGRAM OF
PINS RB3:RB0
BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
RBPU(1)
Data Latch
From other
P
VDD
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
Weak
Pull-up
RD Port
Latch
TTL
Input
Buffer
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
I/O pin(2)
RBPU(1)
I/O pin(2)
Data Latch P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
RB0/INT
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protec tion to VDD and VSS.
PIC16F84A
DS35007C-page 18 2001-2013 Microchip Technology Inc.
TABLE 4-3: PORTB FUNCTIONS
TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit Buffer Type I/O Consistency Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input.
Internal software programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with int errup t-on -ch ang e).
Internal software programmable weak pull-up.
RB5 bit5 TTL Input/output pin (with int errup t-on -ch ang e).
Internal software programmable weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with int errup t-on -ch ange).
Internal software programmable weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with int errup t-on -ch ange).
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
Address Name B it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-on
Reset
Value on
all other
RESETS
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
0Bh,8Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
2001-2013 Microchip Technology Inc. DS35007C-page 19
PIC16F84A
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt-on-overflow from FFh to 00h
Figure 5-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PIC® Mid-Range Reference Manual (DS33023).
5.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule wi ll i ncr em en t ev ery instruction c y cle (with ou t pre s-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When an external cl ock input i s used for T ime r0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). A lso, there is a delay in the actu al
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is avai lab le i n the PIC ® Mid-Range Re ference Manual ,
(DS33023).
5.2 Prescaler
An 8- bit counter i s availabl e as a pre scaler for th e T imer0
module, or as a postscaler for the Watchdog Timer,
respectively (Figure 5-2). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet. Note that there is only one prescaler available
which is mutually exclusively shared between the Timer0
module and the Watchdog Timer. Thus, a prescaler
assignment for the Timer0 module means that there is no
prescaler for the W atchdog Timer , and vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignme nt and prescale ratio.
Clearing b it PSA will assign t he prescaler to the T imer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the W atchdog
Timer (WDT). When the prescaler is assigned to the
WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 regi ster (e.g., CLRF 1, MOVWF 1,
BSF 1,etc.) will clear the presca ler. When ass igned to
WDT, a CLRWDT instruction will clear the prescaler
along with the WDT.
FIGURE 5-1: TIMER0 BLOCK DIAGRAM
Note: Writing to TMR0 when the prescaler is
assigned to Ti mer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).
RA4/T0CKI
T0SE
0
1
1
0
pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0
PSOUT
(2 Cycle Delay)
PSOUT Data Bus
8
PSA
PS2, PS1, PS0 Set Int errupt
Flag bit T0IF
on Overflow
3
PIC16F84A
DS35007C-page 20 2001-2013 Microchip Technology Inc.
5.2.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on the fly” during program
execution).
5.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in softw are by the T imer0 mo dule Interrupt Ser-
vice Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut-off during SLEEP.
FIGURE 5-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Note: To avoid an unintended device RESET, a
specific instruc tion sequence (shown in the
PIC® Mid-Range Reference Manual,
DS33023) must be executed when chang-
ing the prescaler assignment from Timer0
to the WDT. This sequence must be fol-
lowed even if the WDT is disabled.
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (= FOSC/4)
SYNC
2
Cycles TMR0 reg
8-bit Prescaler
8 - to - 1 MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS , T 0SE, PSA, PS2: PS0 are (O PT IO N _REG< 5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set Fl a g b i t T0IF
on Overflow
8
PSA
T0CS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Val ue on all
other
RESETS
01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
0Bh,8Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
2001-2013 Microchip Technology Inc. DS35007C-page 21
PIC16F84A
6.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other
process ors are spec ial circuit s to deal with the needs of
real time applications. The PIC16F84A has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These features are:
• OSC Selection
• RESET
- Power-on Re set (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming™ (ICSP™)
The PIC16F84A has a Watchdog Timer which can be
shut-off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers th at of fe r necessa ry delay s on po wer-up. O ne is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which pro-
vides a fixed delay of 72 ms (nominal) on power-up
only. This design keeps the device in RESET while the
power sup ply s tabi lize s. With these two time rs on-c hip,
most applications need no external RESET circuitry.
SLEEP mode offers a very low current power-down
mode. The user can wake-up from SLEEP through
external RESET, Watchdog Tim er Time-out or through
an interrupt. Several oscillator options are provided to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select the various options.
Additional information on special features is available
in the PIC® Mid-Range Reference Manual (DS33023).
6.1 Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped in
program memory location 2007h.
Address 2007h is beyond the user program memory
space and it belongs to the special test/configuration
memory space (2000h - 3FFFh). This space can only
be accessed during programming.
REGISTER 6-1: PIC16F84A CONFIGURATION WORD
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u
CP CP CP CP CP CP CP CP CP CP PWRTE WDTE F0SC1 F0SC0
bit13 bit0
bit 13-4 CP: Code Protection bit
1 = Code protection disabled
0 = All program memory is code prote ct ed
bit 3 PWRTE: Power-up Timer Enable bit
1 = Power-up Timer is disabled
0 = Power-up Timer is enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
PIC16F84A
DS35007C-page 22 2001-2013 Microchip Technology Inc.
6.2 Oscillator Configurations
6.2.1 OSCILLATOR TYPES
The PIC16F84A can be operated in four different
oscillator modes. The user can program two
configu ration bit s (FOSC1 and F OSC0) to select one of
these four modes:
• LP Low Power Crystal
• XT Crystal/Resonator
• HS High Speed Crystal/Resonator
• RC Resistor/Capacitor
6.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP, or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 6-1).
FIGURE 6-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
The PIC16F84A oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT, LP, or HS modes, the
device can have an external clock source to drive the
OSC1/CLKIN pin (Figure 6-2).
FIGURE 6-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
T ABLE 6-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Note 1: See Table 6-1 for reco mmended v alues
of C1 and C2.
2: A series resistor (RS) may be required
for AT strip cut crystals.
C1(1)
C2(1)
XTALOSC2
OSC1
RF(3)
SLEEP
To
Logic
PIC16FXX
RS(2)
Internal
Ranges Tested:
Mode Freq OSC1/C1 OSC2/C2
XT 455 kHz
2.0 MHz
4.0 MHz
47 - 100 pF
15 - 33 pF
15 - 33 pF
47 - 100 pF
15 - 33 pF
15 - 33 pF
HS 8.0 MHz
10.0 MHz 15 - 33 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF
Note: Recommended values of C1 and C2 are
identical to the ranges tested in this table.
Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for the
appropriate values of external compo-
nents.
Note: When using resonators with frequencies
above 3 .5 MHz, the use of HS mode rather
than XT m ode, is recommend ed. HS m ode
may be used at any VDD for which the
controller is rated.
OSC1
OSC2
Open
Clock from
Ext. System PIC16FXX
2001-2013 Microchip Technology Inc. DS35007C-page 23
PIC16F84A
TABLE 6-2: CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR 6.2.3 RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cos t sav in gs . The RC osc il lator
frequency is a function of the supply voltage, the
resistor (REXT) values, capacitor (CEXT) values, and
the operati ng tempe ratur e. In additi on to this , the oscil-
lator frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead fram e c apacitance be twee n package
types also affects the oscillation frequency, especially
for low CEXT values. The user needs to take into
account variation, due to tolerance of the external
R and C components. Figure 6-3 shows how an R/C
combination is connected to the PIC16F84A.
FIGURE 6-3: RC OSCILLATOR MODE
Mode Freq OSC1/C1 OSC2/C2
LP 32 kHz
200 kHz 68 - 100 pF
15 - 33 pF 68 - 100 pF
15 - 33 pF
XT 100 kHz
2 MHz
4 MHz
100 - 150 pF
15 - 33 pF
15 - 33 pF
100 - 150 pF
15 - 33 pF
15 - 33 pF
HS 4 MHz
20 MHz 15 - 33 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF
Note: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time. These values are for design
guidance only. Rs may be required in HS
mode, as wel l as XT mode , to av oid ove r-
driving crystals with low drive level specifi-
cation. Since each crystal has its own
charact eristics , the user should c onsult th e
crystal manufacturer for appropriate
values of external components.
For VDD > 4.5V, C1 = C2 30 pF i s reco m-
mended.
OSC2/CLKOUT
CEXT
REXT
PIC16FXX
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 5 k REXT 100 k
CEXT > 20pF
PIC16F84A
DS35007C-page 24 2001-2013 Microchip Technology Inc.
6.3 RESET
The PIC16F84A differentiates between various kinds
of RESET:
• Pow er-on Reset (POR)
•MCLR
during normal operation
•MCLR during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
Figure 6-4 shows a simplified block diagram of the
On-Chip RESET Circuit. The MCLR Reset path has a
noise filter to ignore small pulses. The electrical speci-
fications state the pulse width requirements for the
MCLR pin.
Some re gisters are not af fected in any RE SET co ndition ;
their s ta tu s is un know n on a PO R and unch ange d in a ny
other RESET. Most other registers are reset to a “RESET
state” on POR, MCLR or WDT Reset durin g normal oper-
ation and on MCLR during SLEEP. They are not af fecte d
by a WDT Reset during SLEEP, since this RESET is
viewed as the resumption of normal operation.
Table 6-3 gives a description of RESET conditions for
the program counter (PC) and the STATUS register.
Table 6-4 gives a full description of RESET st ates for all
registers.
The TO and PD bits are set or cleared differently in dif-
ferent RESET situations (Section 6.7). These bits are
used in software to determine the nature of the RESET.
FIGURE 6-4: SIMPLIFI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
TABLE 6-3: RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
S
RQ
External Reset
MCLR
VDD
OSC1/
WDT
Module
VDD Rise
Detect
OST/PWRT
On-Chip
RC Osc(1)
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
Enable PWRT
SLEEP
CLKIN
Note 1: This is a separate oscillator f rom the RC os c illator of the CLKIN pin.
2: See Table 6-5.
See Table 6-5
Condition Program Counter STATUS Register
Power-on Reset 000h 0001 1xxx
MCLR during normal operat ion 000h 000u uuuu
MCLR during SLEEP 000h 0001 0uuu
WDT Reset (during normal operation) 000h 0000 1uuu
WDT Wake-up PC + 1 uuu0 0uuu
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu
Legend: u = unchanged, x = unknown
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
2001-2013 Microchip Technology Inc. DS35007C-page 25
PIC16F84A
TABLE 6-4: RESET CONDITIONS FOR ALL REGISTERS
Register Address Power-on Reset
MCLR during:
– normal operation
– SLEEP
WDT Reset during
normal operation
W ake -up fro m SLEEP:
– through interrupt
– through WDT Time-out
W—xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h ---- ---- ---- ---- ---- ----
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h 0000 0000 0000 0000 PC + 1(2)
STATUS 03h 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(4) 05h ---x xxxx ---u uuuu ---u uuuu
PORTB(5) 06h xxxx xxxx uuuu uuuu uuuu uuuu
EEDATA 08h xxxx xxxx uuuu uuuu uuuu uuuu
EEADR 09h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh 0000 000x 0000 000u uuuu uuuu(1)
INDF 80h ---- ---- ---- ---- ---- ----
OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu
PCL 82h 0000 0000 0000 0000 PC + 1(2)
STATUS 83h 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 84h xxxx xxxx uuuu uuuu uuuu uuuu
TRISA 85h ---1 1111 ---1 1111 ---u uuuu
TRISB 86h 1111 1111 1111 1111 uuuu uuuu
EECON1 88h ---0 x000 ---0 q000 ---0 uuuu
EECON2 89h ---- ---- ---- ---- ---- ----
PCLATH 8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 8Bh 0000 000x 0000 000u uuuu uuuu(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: Table 6-3 lists the RESET value for each specific condition.
4: On any device RESET, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
PIC16F84A
DS35007C-page 26 2001-2013 Microchip Technology Inc.
6.4 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for VDD
must be met for this to operate properly. See Electrical
Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met.
For additional information, refer to Application Note
AN607, "Power-up Trouble S hooting."
The POR circuit does not produce an internal RESET
when VDD declines.
6.5 Power-up Timer (PWRT)
The Power-up Timer (PWRT) provides a fixed 72 ms
nominal time-out (TPWRT) from POR (Figures 6-6
through 6-9). The Power-up Timer operates on an
internal RC oscillator. The chip is kept in RESET as
long as the PWRT is active. The PWRT delay allows
the VDD to rise to an acceptable level (possible excep-
tion shown in Figure 6-9).
A configuration bit, PWRTE, can enable/disable the
PWRT. See Register 6-1 for the operation of the
PWRTE bit for a particu lar devi ce .
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
6.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 6-6, Figure 6-7, Figure 6-8
and Figure 6-9). This ensures the crystal oscillator or
resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case
(Figure 6-9), an external Power-on Reset circuit may
be necessary (Figure 6-5).
FIGURE 6-5: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Note 1: External Power-on Reset circuit is required
only if VDD power-up rate is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 A). A larger voltage drop will
degrade VIH level on the MCLR pin.
3: R1 = 100 to 1 k will limit any current flow-
ing into MCLR from external capacitor C, in
the event of a MCLR pin breakdown due to
ESD or EOS.
C
R1
R
D
VDD
MCLR
PIC16FXX
VDD
2001-2013 Microchip Technology Inc. DS35007C-page 27
PIC16F84A
FIGURE 6-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 6-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 6-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OS T TI M E-OU T
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
TPWRT
TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PIC16F84A
DS35007C-page 28 2001-2013 Microchip Technology Inc.
FIGURE 6-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD):
SLOW VDD RISE TIME
6.7 Time-out Sequence and
Power-down Status Bits (TO/PD)
On power-up (Figures 6-6 through 6-9), the time-out
sequence is as follows:
1. PWRT time-out is invoked after a POR has
expired.
2. Then, the OST is activated.
The tot a l time -ou t wil l vary bas ed on os ci llator configu-
ration and PWRTE configuration bit status. For exam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all.
TABLE 6-5: TIME-OUT IN VARIOUS
SITUATIONS
Since the time-outs occur from the PO R pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high, execution will begin immediately
(Figure 6-6). This is useful for testing purposes or to
synchronize more than one PIC16F84A device when
operating in parallel.
Table 6-6 shows the significance of the TO and PD bits.
Table 6-3 lists the RESET conditions for some special
registers, while Table 6-4 lists the RESET conditions
for all the registers.
TABLE 6-6: STATUS BITS AND THEIR
SIGNIFICANCE
VDD
MCLR
V1
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before V DD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
INTERNAL POR
TPWRT
TOST
PWRT TIME-OUT
OST TIME-O UT
INTERNAL RESET
Oscillator
Configuration
Power-up Wa ke-up
from
SLEEP
PWRT
Enabled PWRT
Disabled
XT, HS, LP 72 ms +
1024TOSC 1024TOSC 1024TOSC
RC 72 ms — —
TO PD Condition
11
Power-on Reset
0x
Illegal, TO is set on POR
x0
Illegal, PD is set on POR
01
WDT Reset (duri ng normal operation)
00
WDT Wake-up
11
MCLR during normal operation
10
MCLR during SLEEP or interrupt
wake-up from SLEEP
2001-2013 Microchip Technology Inc. DS35007C-page 29
PIC16F84A
6.8 Interrupts
The PIC16F84A has 4 sources of int err upt:
• External interrupt RB0/INT pin
• TMR0 ove rflo w interrupt
• PORTB change interrupts (pins RB7:RB4)
• Data EEPROM write complete interrupt
The interrupt control register (INTCON) records
indivi dual int errup t reques ts in flag bit s. It als o cont ain s
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
re-enable s inte rrup t s.
The RB0/INT pin interrupt, the RB port change in terrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pu sh ed onto th e s tack a nd the PC is lo ade d
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles. The
exact latency depends when the interrupt event occurs.
The latency is the same for both one and two cycle
instructions. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
FIGURE 6-10: INTERRUPT LOGIC
6.8.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the Interrupt Service
Routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 6.11) o nly if the INTE bit was s et prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
6.8.2 TMR0 INTERRUPT
An overflow (FFh 00h) in TMR0 will set flag bit T0IF
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 5.0).
6.8.3 PORTB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 4.2).
6.8.4 DATA EEPROM INTERRUPT
At the completion of a data EEPROM write cycle, flag
bit EEIF (EEC ON1<4>) will be s et. The interrup t can be
enabled/disabled by setting/clearing enable bit EEIE
(INTCON<6>) (Section 3.0).
Note: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
RBIF
RBIE
T0IF
T0IE
INTF
INTE
GIE
EEIE
Wake-up
(If in SLEEP mode)
Interrupt to CPU
EEIF
Note: For a change on the I/O pin to be
recognized, the pulse width must be at
least TCY wide.
PIC16F84A
DS35007C-page 30 2001-2013 Microchip Technology Inc.
6.9 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users wi sh to sa ve key r e gist e r
values during an interrupt (e.g., W register and
STATU S regist er). This is implemented in software.
The code in Example 6-1 stores and restores the
STATUS and W register’s values. The user defined
registers, W_TEMP and STATUS_TEMP are the tem-
porary storage locations for the W and STATUS
registers values.
Example 6-1 does the following:
a) Stores the W register.
b) Stores the STATUS register in STATUS_TEMP.
c) Executes the Interrupt Service Routine code.
d) Restores the STATUS (and bank select bit)
register.
e) Restores the W register.
EXAMPLE 6-1: SAVING STATUS AND W REGISTERS IN RAM
6.10 Watchdog Timer (WDT)
The Watchdog Timer is a free running On-Chip RC
Oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscil lat or of the O SC1/C LKI N pin. Tha t means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation, a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT wake-up causes the device to wake-up
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit
WDTE as a '0' (Section 6.1).
6.10.1 WDT PERIOD
The WDT ha s a nominal tim e-out period of 18 ms, (wi th
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be as si gne d to th e WD T un der soft w are c ont rol b y
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out and generating a device
RESETcondition.
The TO bit in the STATUS register will be cleared upon
a WDT time-ou t.
PUSH MOVWF W_TEMP ; Copy W to TEMP register,
SWAPF STATUS, W ; Swap status to be saved into W
MOVWF STATUS_TEMP ; Save status to STATUS_TEMP register
ISR : :
:; Interrupt Service Routine
: ; should configure Bank as required
:;
POP SWAPF STATUS_TEMP,W ; Swap nibbles in STATUS_TEMP register
; and place result into W
MOVWF STATUS ; Move W into STATUS register
; (sets bank to original state)
SWAPF W_TEMP, F ; Swap nibbles in W_TEMP and place result in W_TEMP
SWAPF W_TEMP, W ; Swap nibbles in W_TEMP and place result into W
2001-2013 Microchip Technology Inc. DS35007C-page 31
PIC16F84A
6.10.2 WDT PROGRAMMING
CONSIDERATIONS
It should also be taken into account that under worst
case cond itions (VDD = Min., Temperature = Max., Max.
WDT Pr e sca ler ), it may ta ke sev e ral se co nds b ef or e a
WDT time-out occurs.
FIGURE 6-11: WATC HDOG TIMER BLOCK DIAGRAM
TABLE 6-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
From TMR0 Clock Source
(Figure 5-2)
To TMR0 (Figure 5-2)
Postscaler
WDT Timer
M
U
X
PSA
8 - to -1 MUX
PSA
WDT
Time-out
1
0
0
1
WDT
Enable Bit
PS2:PS0
•
•
8
MUX
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
Power-on
Reset
V alue on all
other
RESETS
2007h Config. bits (2) (2) (2) (2) PWRTE(1) WDTE FOSC1 FOSC0 (2)
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown. Shaded cells are not used by the WDT.
Note 1: S ee Register 6-1 for operation of the PWRTE bit.
2: See Register 6-1 and Section 6.12 for operation of the code and data protection bits.
PIC16F84A
DS35007C-page 32 2001-2013 Microchip Technology Inc.
6.11 Power-down Mode (SLEEP)
A device may be powered down (SLEEP) and later
powered up (wake-up from SLEEP).
6.11.1 SLEEP
The Power-down mode is entered by executing the
SLEEP instruction.
If enabled, the Watchdog Timer is cleared (but keeps
running) , the PD bit (STA TUS<3>) is cleared, the TO bit
(STATUS<4>) is set, and the oscillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEP instruction was executed (driving high, low,
or hi-impedance).
For the lowest current consumption in SLEEP mode,
place al l I/O pin s a t eith er VDD or VSS, with no externa l
circuitry drawing current from the I/O pins, and disable
external clocks. I/O pins that are hi-impedance inputs
should be pu lled high or lo w exte rna lly to a vo id s witc h-
ing curre nts cau sed by floatin g input s. The T0CK I input
should also be at VDD or VSS. The contribution from
on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
6.11.2 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. WDT wake-up (if WDT was enabled).
3. Interrupt from RB0/INT pin, RB port change, or
data EEPROM write complete.
Peripherals cannot generate interrupts during SLEEP,
since no on-chip Q clocks are present.
The first event (MCLR Reset) will cause a device
RESET. The two latte r ev en ts are c ons id ered a co nti n-
uation of program execution. The TO and PD bits can
be used to determine the cause of a device RESET.
The PD bit, whic h is set on pow er-u p, is clear ed wh en
SLEEP is invoked. The TO bit is cleared if a WDT
time-out occurred (and caused wake-up).
While th e SLEEP instructio n is being e xecuted, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up thro ugh an interrup t eve nt, the corres pon din g
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the inst ruction af ter the SLEEP ins truction. If the GIE b it
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
FIGURE 6-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS, or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will contin ue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
2001-2013 Microchip Technology Inc. DS35007C-page 33
PIC16F84A
6.11.3 WA KE -UP USIN G INTERR UPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llowin g wil l occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction w il l com -
plete as a NOP. Therefore, the WDT and WDT
pos tsc aler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device will imme-
diately wake -up from SLEE P. The SLEEP
instruc t io n will be com pl etel y ex ec ute d befo re the
wake-up. Therefore, the WDT and WDT
pos tsc aler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
6.12 Program Verification/Code
Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
6.13 ID Locations
Four memo ry locations (2000h - 2004h) are designate d
as ID locations to store checksum or other code
identification numbers. These locations are not
accessible during normal execution but are readable
and writable only during program/verify. Only the
four Least Signific an t bits of ID location are us abl e.
6.14 In-Circuit Serial Programming
PIC16F84A microcontrollers can be serially
progra mmed w hile in t he end appl icati on ci rcu it. Th is i s
simply done with two lines for clock and dat a, and three
other lines for power, ground, and the programming
voltage. Customers can manufacture boards with
unprogrammed devices, and then program the
microcontroller just before shipping the product,
allowing the most recent firmware or custom firmware
to be programmed.
For complete details of Serial Programming, please
refer to the In-Circuit Serial Programming™ (ICSP™)
Guide, (DS302 77).
PIC16F84A
DS35007C-page 34 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS35007C-page 35
PIC16F84A
7.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word, divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 7-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 7-1
shows the opcode field descriptions.
For byte-oriented i nst ruc tions, 'f' rep res ents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W reg ister . If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator whic h sel ec ts the nu mber of the bit a ffected
by the oper ation, w hile 'f' represen ts the address of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 7-1: OPCODE FIELD
DESCRIPTIONS
The instruction set is highly orthogonal and is grouped
into three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In thi s cas e, t he ex ec u ti o n tak es tw o in s tru ct i o n cy cles
with the second cycle executed as a NOP. One in struc-
tion cycle consists of four oscillator periods. Thus, for
an osc illator frequency of 4 M Hz, th e normal i nstructio n
executi on ti me is 1 s. If a condit ional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 s.
Table 7-2 lists the instructions recognized by the
MPASM™ Assembler.
Figure 7-1 shows the general formats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 7-1: GENERAL FORMAT FOR
INSTRUCTIONS
A description of each instruction is available in the PIC®
Mid-Range Reference Manual (DS33023).
Field Description
fRegister file address ( 0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon't care location (= 0 or 1)
The assembler will generate code with x = 0.
It is the recom mende d form of use for comp at-
ibility with all Microchip software tools.
dDestinat ion select; d = 0: store resul t in W,
d = 1: store result in file register f.
Default is d = 1
PC Program Counter
TO Ti me-out bit
PD Power-down bit
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instr uctions.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT # ) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal )
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16F84A
DS35007C-page 36 2001-2013 Microchip Technology Inc.
TABLE 7-2: PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcod e Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1 (2)
1
1 (2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move litera l to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latc h is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Addit ional info rmation on the mid-ran ge instruc tion set i s available in the PIC® M id-Rang e MCU Family Ref-
erence Manual (DS33023).
2001-2013 Microchip Technology Inc. DS35007C-page 37
PIC16F84A
7.1 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [label] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are ad ded to the eight-bi t literal 'k'
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [label] ADDWF f,d
Operands: 0 f 127
d
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Desc ription: Ad d the content s of the W register
with register 'f '. If 'd' is 0, the result
is stored in the W register. If 'd' is
1, the result is stored back in
register 'f'.
ANDLW AND Literal with W
Syntax: [label] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal
'k'. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [label] ANDWF f,d
Operands: 0 f 127
d
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W regist er. If 'd' is 1, the re sult
is stored back in register 'f'.
BCF Bit Clear f
Syntax: [label] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Af fe cte d: None
Description: Bit 'b' in regi ster 'f' is cleared.
BSF Bit Set f
Syntax: [label] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Af fe cte d: None
Description: Bit 'b' in register 'f' is set.
BTFSS Bit Test f, Skip if Set
Syntax: [label] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Af fe cte d: None
Descr ipti on : If bit 'b' in regi st er ' f' is '0', the nex t
instructi on is ex ecuted.
If bit 'b' is '1', then the next instruc-
tion is discarded and a NOP is exe-
cuted instead, making this a 2TCY
instruction.
PIC16F84A
DS35007C-page 38 2001-2013 Microchip Technology Inc.
BTFSC Bit Test, Skip if Clear
Syntax: [label] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit 'b' in register 'f' is '1', the next
instruction is executed.
If bit 'b' in register 'f' is '0', the next
instruction is discarded, and a NOP
is exec ute d ins te ad, m ak in g thi s a
2TCY instruction.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate a ddress is loade d into P C bit s
<10:0>. The upper bits of the PC
are load ed from PCLA TH. CALL is
a two-cycle instruction.
CLRF Clear f
Syntax: [label] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Desc ript ion : The content s of register 'f' are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Tim er
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Af fe cte d: TO, PD
Description: CLRWDT instruction resets the
W atchdog T imer . It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Af fe cte d: Z
Description: The contents of register 'f' are
complemented. If 'd' is 0, the
result is stored in W. If 'd' is 1, the
result is stored back in register 'f'.
DECF Decrement f
Syntax: [label] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Af fe cte d: Z
Description: Decrement register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
2001-2013 Microchip Technology Inc. DS35007C-page 39
PIC16F84A
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register 'f' are
decremented. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is placed back in
register 'f'.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOP is executed instead,
making it a 2TCY instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The e le ven -bi t im me dia t e v al ue i s
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two-
cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register 'f' are
incremented. If 'd' is 0, the result
is placed in the W regis ter. If 'd' is
1, the result is placed back in
register 'f'.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
Status Af fe cte d: None
Description: The contents of register 'f' are
incremen ted. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in
register 'f'.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOP is e xecuted i nstead, making
it a 2TCY instruction.
IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
Status Af fe cte d: Z
Descr iption: The c ontents of the W regis ter are
OR’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destination)
Status Af fe cte d: Z
Description: Inclusive OR the W register with
register 'f'. If 'd' is 0, the result is
placed in the W re gis ter. If 'd' is 1,
the result is placed back in
register 'f'.
PIC16F84A
DS35007C-page 40 2001-2013 Microchip Technology Inc.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination )
Status Affected: Z
Description: The contents of register f are
moved t o a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The eight-bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)
Status Affected: None
Description: Move data from W register to
register 'f'.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Af fe cte d: None
RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Af fe cte d: None
Description: The W register is loaded with the
eight-bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Af fe cte d: None
Description: Return from subroutine. The stack
is POPed an d t he top of the s t ack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
2001-2013 Microchip Technology Inc. DS35007C-page 41
PIC16F84A
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0, the
result is placed in the W regis ter.
If 'd' is 1, the result is stored back
in register 'f'.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Desc ript ion : The contents of register 'f' are
rotat ed one bit to the r ight throug h
the C arry Flag. If 'd' is 0 , the result
is placed in the W register. If 'd' is
1, the result is placed back in
register 'f'.
SLEEP
Syntax: [ label ]SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected: TO, PD
Desc ription: The power-down st atus bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleare d.
The processor is put into SLEEP
mode w ith the osci lla tor stopp ed.
Register fC
Register fC
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Operation: k - (W) W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal 'k'. The result is
placed in the W register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from regi ster 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in registe r 'f'.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Af fe cte d: None
Description: The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the resu lt is pl aced in
register 'f'.
PIC16F84A
DS35007C-page 42 2001-2013 Microchip Technology Inc.
XORLW Exclusive OR Literal with W
Syntax: [label] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight-bit lit-
eral 'k'. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [label] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
Status Af fe cte d: Z
Description: Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
2001-2013 Microchip Technology Inc. DS35007C-page 43
8.0 DEVELOP MENT SUPPO R T
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Progra mmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonst ration/Development Boards,
Evaluation Kits, and Starter Kits
8.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The M PLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circui t Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Exten si ve on-l in e help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-tou ch compile o r assemble , and downl oad to
emulator and simulator tools (automatically
updates all project information)
• Debug us ing :
- Source f iles (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
DS35007C-page 44 2001-2013 Microchip Technology Inc.
8.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
8.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontroll ers and the dsPIC fam ily of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
process or , and one-s tep driver , and can run on multipl e
platforms.
8.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
sour ce fil es
• Directives that allow complete control over the
assembly process
8.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLA B C18 C Compiler. It can link relocatabl e objects
from precompiled libraries, using directives from a
linker script.
The MPLIB O bject Li brarian manage s the cre ation an d
modification of library files of precompiled code. When
a rout in e from a l ibra ry is c al led fro m a source f ile , only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deleti on and extraction
8.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the asse mbler to pro duce i ts o bje ct file . The ass embl er
generates relocatable object files that can then be
archived or lin ked with other relocatable object fi les and
arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB IDE compatibility
2001-2013 Microchip Technology Inc. DS35007C-page 45
8.7 MPLAB SIM Sof tware Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and i nternal regi sters.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
developm ent tool .
8.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated D evelopment Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgrad able through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
8.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
device s. It debugs and programs PIC® Flas h microco n-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nect ed to t he des ign e nginee r's PC using a hig h-spee d
USB 2.0 i nte rfac e a nd is co nnected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 support s all
MPLAB ICD 2 headers.
8.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most af fordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller , hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
DS35007C-page 46 2001-2013 Microchip Technology Inc.
8.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The P ICkit™ 2 Develo pment Program mer/Debu gger i s
a low-cost development tool with an easy to use inter-
face fo r programmin g and debu gging Micr ochip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC3 2 fam il ies o f 8 - bi t, 1 6-b it, an d 3 2-b it
microcontrollers, and many Microchip Serial EEPROM
produ cts . With Mic rochip ’s power ful MPL AB Integrate d
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file reg ist ers can be ex amin ed and m odifie d.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller , hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
8.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64 ) for me nus an d err or messag es an d a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is in cluded
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer can rea d, verify an d program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPL AB PM3 has high-spe ed comm unications and
optimized algorithms for quick programming of large
memory devices and inc orporates an MMC card for file
storage and data applications.
8.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototypi ng areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The board s suppo rt a variety of features, includ ing LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory .
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2001-2013 Microchip Technology Inc. DS35007C-page 47
PIC16F84A
9.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-55C to +125C
Storage temperature.............................................................................................................................. -65C to +150C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) .........................................-0.3V to (VDD + 0.3V)
Volta ge on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5V
Volta ge on MCLR with respect to VSS(1).......................................................................................................-0.3 to +14V
Voltage on RA4 with respect to VSS ........................................................................................................... -0.3 to +8.5V
Total power dissipation(2) .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into V DD pin..............................................................................................................................100 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output cl amp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin....................................................................................................25 mA
Maximum current sunk byPORTA..........................................................................................................................80 mA
Maximum current sourced by PORTA.....................................................................................................................50 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB ..................................................................................................................100 mA
Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a se ries resi sto r of 50 -100 s ho uld be us ed w hen ap ply in g a “lo w ” le vel to the MCLR pi n rather tha n
pulling this pin directly to VSS.
2: Power di ssip atio n is ca lcula ted as follow s: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x I OL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those ind icated in the ope ration listi ngs of this spe cificati on is not implied. Exposure to ma ximum ratin g conditio ns for
extended periods may affect device reliability.
PIC16F84A
DS35007C-page 48 2001-2013 Microchip Technology Inc.
FIGURE 9-1: PIC16F84 A-20 VOLTAGE-FREQUENCY GRAPH
FIGURE 9-2: PIC16LF84A-04 VO L TAGE-
FREQUENCY GRAPH FIGURE 9-3: PIC16F84A-04 VOLTAGE-
FREQUENCY GRAPH
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
20 MHz
5.0V
3.5V
3.0V
2.5V
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
5.0V
3.5V
3.0V
2.5V
FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz
4 MHz 10 MHz
Note 1: VDDAPPMIN is the minimum voltage of the
PIC® device in the application.
2: FMAX has a maximum frequency of 10 MHz.
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
5.0V
3.5V
3.0V
2.5V
4 MHz
2001-2013 Microchip Technology Inc. DS35007C-page 49
PIC16F84A
9.1 DC Characteristics
PIC16LF84A-04
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0C TA +70C (commercial)
-40C TA +85C (industrial)
-40C TA +125C (extended)
PIC16F84A-04
(Commercial, Industrial, Extended)
PIC16F84A-20
(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0C TA +70C (commercial)
-40C TA +85C (industrial)
-40C TA +125C (extended)
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
VDD Supply Voltage
D001 16LF84A 2.0 — 5.5 V XT, RC, and LP osc configuration
D001
D001A 16F84A 4.0
4.5 —
—5.5
5.5 V
VXT, RC and LP osc configuration
HS osc configuration
D002 VDR RAM Data Retention
Voltage (Note 1) 1.5 — — V Device in SLEEP mode
D003 VPOR VDD Start Voltage to ensure
internal Power-on Reset
signal
— Vss — V See sectio n on Power- on Reset for deta ils
D004 SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05 — — V/ms
IDD Supply Curr ent (Note 2)
D010 16LF84A — 1 4 mA RC and XT osc configuration (Note 4)
FOSC = 2.0 MHz, VDD = 5.5V
D010
D010A
D013
16F84A —
—
—
1.8
3
10
4.5
10
20
mA
mA
mA
RC and XT osc configuration (Note 4)
FOSC = 4.0 MHz, VDD = 5.5V
RC and XT osc configuration (Note 4)
FOSC = 4.0 MHz, VDD = 5.5V
(During FLASH prog ram ming)
HS osc configuration (PIC16F84A-20)
FOSC = 20 MHz, VDD = 5.5V
D014 16LF84A — 15 45 A LP osc conf iguration
FOSC = 32 kHz, VDD = 2.0V , WDT disabled
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These pa rameters are for design guidance
only and are not tested .
NR Not rated for operation.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD,
T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula IR = VDD/2REXT (mA) with REXT in kOhm.
5: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD measurement.
PIC16F84A
DS35007C-page 50 2001-2013 Microchip Technology Inc.
IPD Power-down Current (Note 3)
D020 16LF84A
D020 16F84A-20
16F84A-04
D021A 16LF84A — 0.4 1.0 AVDD = 2.0V, WDT disabled, industrial
D021A 16F84A-20
16F84A-04 —
—1.5
1.0 3.5
3.0 A
AVDD = 4.5V, WDT disabled, industrial
VDD = 4.0V, WDT disabled, industrial
D021B 16F84A-20
16F84A-04 —
—1.5
1.0 5.5
5.0 A
AVDD = 4.5V, WDT disabled, extended
VDD = 4.0V, WDT disabled, extended
D022 IWDT
Module Differential Current
(Note 5)
Watchdog Timer —
—
—
—
—
.20
3.5
3.5
4.8
4.8
16
20
28
25
30
A
A
A
A
A
VDD = 2.0V, Industrial, Commercial
VDD = 4.0V, Commercial
VDD = 4.0V, Industrial, Extended
VDD = 4.5V, Commercial
VDD = 4.5V, Industrial, Extended
9.1 DC Characteristics (Continued)
PIC16LF84A-04
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0C TA +70C (commercial)
-40C TA +85C (industrial)
-40C TA +125C (extended)
PIC16F84A-04
(Commercial, Industrial, Extended)
PIC16F84A-20
(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0C TA +70C (commercial)
-40C TA +85C (industrial)
-40C TA +125C (extended)
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These pa rameters are for design guidance
only and are not tested .
NR Not rated for operation.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD,
T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula IR = VDD/2REXT (mA) with REXT in kOhm.
5: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD measurement.
2001-2013 Microchip Technology Inc. DS35007C-page 51
PIC16F84A
9.2 DC Characteristics: PIC16F84A-04 (Commercial, Industri al)
PIC16F84A-20 (Commercial, Industrial)
PIC16LF84A-04 (Commercial, Industrial)
DC Character ist ics
All Pins Except Power Supply Pins
Standard Operating Conditions (unless otherwise stated)
Operati ng tem per ature 0C TA +70C (commercial)
-40C TA +85C (industrial)
Operating voltage VDD range as described in DC specifications
(Section 9.1)
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
VIL Input Low Voltage
I/O ports:
D030 with TTL buf fer VSS —0.8 V4.5V VDD 5.5V (Note 4)
D030A VSS —0.16VDD V Entire rang e (Note 4)
D031 with Schmitt Trigger buffer VSS —0.2VDD V Entire range
D032 MCLR, RA 4/T0 CKI VSS —0.2VDD V
D033 OS C1 (XT, HS and LP modes) VSS —0.3VDD V(Note 1)
D034 OSC1 (RC mode) VSS —0.1VDD V
VIH Input Hi gh Voltage
I/O ports: —
D040
D040A with TTL buffer 2.0
0.25VDD+0.8 —
—VDD
VDD V
V4.5V VDD 5.5V (Note 4)
Entire range (Note 4)
D041 with Schmitt Trigger buffer 0.8 VDD —VDD Entire range
D042 MCLR, 0.8 VDD —VDD V
D042A RA4/T0CKI 0.8 VDD —8.5 V
D043 OS C1 (XT, HS and LP modes) 0.8 VDD —VDD V(Note 1)
D043A OSC1 (RC mode) 0.9 VDD VDD V
D050 VHYS Hysteresis of Schmitt Trigger
Inputs —0.1—V
D070 IPURB PORTB Weak Pull-up Current 50 250 400 AVDD = 5.0V, VPIN = VSS
IIL Input Leakage Current
(Notes 2, 3)
D060 I / O ports — — 1AVss VPIN VDD,
Pin at hi-impedance
D061 MCLR, RA 4/T0 CKI — — 5AVss VPIN VDD
D063 OSC1 — — 5AVss VPIN VDD, XT, HS
and LP osc configuration
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: In RC oscillato r co nfig ura tion , the OSC1 pin is a Sch mi tt Trigger input . Do not dri ve the PIC 1 6F8 4A with an
external clock while the device is in RC mode, or chip damage may result.
2: The leakage current on the MCL R pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as coming out of the pin.
4: The user may choose the better of the two specs.
PIC16F84A
DS35007C-page 52 2001-2013 Microchip Technology Inc.
VOL Output Low Voltage
D080 I /O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V
D083 OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD = 4.5V,
(RC mode only)
VOH Output High Voltage
D090 I / O ports (Note 3) VDD-0.7 — — V IOH = -3.0 mA , VDD = 4.5V
D092 OSC2/CLKOUT (Note 3) VDD-0.7 — — V IOH = -1.3 mA, VDD = 4.5V
(RC mode only)
VOD Open Drain High Voltag e
D150 RA4 pin — — 8.5 V
Capacitive Loa ding Specs on
Output Pins
D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes
when external clock is used
to drive OSC1
D101 CIO All I/O pi ns an d OSC2
(RC mode) ——50pF
Data EEPROM Memory
D120 EDEndurance 1M 10M — E/W 25C at 5V
D121 VDRW VDD for read/write VMIN —5.5 VVMIN = Minimum operating
voltage
D122 TDEW Erase/Write cycle time — 4 8 ms
Program FLASH Memory
D130 EPEndurance 1000 10K — E/W
D131 VPR VDD for read VMIN —5.5 VVMIN = Minimum operating
voltage
D132 VPEW VDD for erase/write 4.5 — 5.5 V
D133 TPEW Erase/Write cycle time — 4 8 ms
9.2 DC Characteristics: PIC16F84A-04 (Commercial, Industri al)
PIC16F84A-20 (Commercial, Industrial)
PIC16LF84A-04 (Commercial, Industrial) (Continued)
DC Character ist ics
All Pins Except Power Supply Pins
Standard Operating Conditions (unless otherwise stated)
Operati ng tem per ature 0C TA +70C (commercial)
-40C TA +85C (industrial)
Operating voltage VDD range as described in DC specifications
(Section 9.1)
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: In RC oscillato r co nfig ura tion , the OSC1 pin is a Sch mi tt Trigger input . Do not dri ve the PIC 1 6F8 4A with an
external clock while the device is in RC mode, or chip damage may result.
2: The leakage current on the MCL R pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as coming out of the pin.
4: The user may choose the better of the two specs.
2001-2013 Microchip Technology Inc. DS35007C-page 53
PIC16F84A
9.3 AC (Timing) Characteristi cs
9.3.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS
2. TppS
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp 2to os, oscOSC1
ck CLKOUT ost oscillator start-up timer
cy cycle time pwrt power-up timer
io I/O port rbt RBx pins
inp INT pin t0 T0CKI
mp MCLR wdt watchdog timer
Uppe rcase letters and their meanings:
SF Fall P Period
HHigh RRise
I Invalid (high impedance) V Valid
L Low Z High Impedance
PIC16F84A
DS35007C-page 54 2001-2013 Microchip Technology Inc.
9.3.2 TIMING CONDITIONS
The temperature and voltages specified in Table 9-1
apply to all timing specifications unless otherwise
noted. All timings are measure d between high an d low
measurement points as indicated in Figure 9-4.
Figure 9-5 specifies the load conditions for the timing
specifications.
TABLE 9-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
FIGURE 9-4: PARAME TER MEA SUREMENT INFORMATION
FIGURE 9-5: LOAD CONDITIONS
AC CHARACTERISTICS
S tandard Operating Conditions (unless otherw is e stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C fo r industrial
Operating voltage VDD range as described in DC specifications (Section 9.1)
0.9 VDD (High)
0.1 VDD (Low)
0.8 VDD RC
0.3 VDD XTAL
OSC1 Measurement Points I/O Port Measurement Points
0.15 VDD RC
0.7 VDD XTAL (High)
(Low)
Load Condition 1 Load Condition 2
Pin
RL
CL
VSS
VDD/2
VSS
CL
Pin
RL = 464
CL = 50 pF for all pi ns ex cept OS C2
15 pF for OSC2 output
2001-2013 Microchip Technology Inc. DS35007C-page 55
PIC16F84A
9.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 9-6: EXTER NAL CLOCK TIMING
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
13344
2
TABLE 9-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param No. Sym Characteristic Min Typ† Max Units Conditions
FOSC External CLKIN Frequency(1) DC — 2 MHz XT, RC osc (-04, LF)
DC — 4 MHz XT, RC osc (-04)
DC — 20 MHz HS osc (-20)
DC — 200 kHz LP osc (-04, LF)
Oscillator Frequency(1) DC — 2 MHz RC osc (-04, LF)
DC — 4 MHz RC osc (-04)
0.1 — 2 MHz XT osc (-04, LF)
0.1 — 4 MHz XT osc (-04)
1.0 — 20 MHz HS osc ( -20)
DC — 200 kHz LP osc (-04, LF)
1T
OSC External CLKIN Period(1) 500 — — ns XT, RC osc (-04, LF)
250 — — ns XT, RC osc (-04)
50 — — ns HS osc (-20)
5.0 — — s LP osc (-04, LF)
Oscillator Period(1) 500 — — ns RC osc (-04, LF)
250 — — ns RC osc (-04)
500 — 10,000 ns XT osc (-04, LF)
250 — 10,000 ns XT osc (-04)
50 — 1,000 ns HS osc (-20)
5.0 — — s LP osc (-04, LF)
2T
CY Instruction Cycle Time(1) 0.2 4/FOSC DC s
3 TosL,
TosH Clock in (OSC1) High or Low
Time 60 — — ns XT osc (-04, LF)
50 — — ns XT osc (-04)
2.0 — — s LP osc (-04, LF)
17.5 — — ns HS osc (-20)
4TosR,
TosF Clock in (OSC1) Rise or Fall
Time 25 — — ns XT osc (-04)
50 — — ns LP osc (-04, LF)
7.5 — — ns HS osc (-20)
† Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: In stru ction cycle period (TCY) equals four times the input oscillator time-base period. All specified values
are based on charac teri za tion data for that partic ula r oscillator type unde r standard ope rating condi tions
with the dev ic e exe cu tin g code. Exceed ing t hes e sp ec ifi ed li mi ts may res ul t in an un stable oscilla tor opera-
tion and/or higher than expected current consumption. All devices are tested to operate at "Min." values
with an external clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
PIC16F84A
DS35007C-page 56 2001-2013 Microchip Technology Inc.
FIGURE 9-7: CLKOUT AND I/O TIMING
TABLE 9-3: CLKOUT AND I/O TIMING REQUIREMENTS
OSC1
CLKOUT
I/O Pin
(Input)
I/O Pin
(Output)
Q4 Q1 Q2 Q3
10
13
14
17
20, 21
22
23
19 18
15
11
12
16
old value new value
Note: All tests must be done with specified capacitive loads (Figure 9-5) 50 pF on I/O pins and CLKOUT.
Param
No. Sym Characteristic Min Typ† Max Units Conditions
10 TosH2ckL OSC1 to CLKOUT Standard — 15 30 ns (Note 1)
10A Extended (LF) — 15 120 ns (Note 1)
11 TosH2ckH OSC1 to CLKOUT Standard — 15 30 ns (Note 1)
11A Extended (LF) — 15 120 ns (Note 1)
12 TckR CLKOUT rise time Standard — 15 30 ns (Note 1)
12A Extended (LF) — 15 100 ns (Note 1)
13 TckF CLKOUT fall time Standard — 15 30 ns (Note 1)
13A Extended (LF) — 15 100 ns (Note 1)
14 TckL2ioV CLKOUT to Port out valid — — 0.5TCY +20 ns (Note 1)
15 TioV2ckH Port in valid before
CLKOUT Standard 0.30TCY + 30 — — ns (Note 1)
Extended (LF) 0.30TCY + 80 — — ns (Note 1)
16 TckH2ioI Por t in hold after CLKOUT 0——ns(Note 1)
17 TosH2ioV OSC1 (Q1 cycle) to
Port out valid Standard — — 125 ns
Extended (LF) — — 250 ns
18 TosH2ioI OSC1 (Q2 cycle) to Port
input invalid (I/O in hold time) Standard 10 — — ns
Extended (LF) 10 — — ns
19 TioV2osH Port input valid to OSC1
(I/O in setup time) Standard -75 — — ns
Extended (LF) -175 — — ns
20 TioR Port output rise time Standard — 10 35 ns
20A Extended (LF) — 10 70 ns
21 TioF Port output fall time Standard — 10 35 ns
21A Extended (LF) — 10 70 ns
22 TINP INT pin high
or low time Standard 20 — — ns
22A Extended (LF) 55 — — ns
23 TRBP RB7:RB4 change INT
high or low time Standard TOSC§— — ns
23A Extended (LF) TOSC§— — ns
† Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
§ By design.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2001-2013 Microchip Technology Inc. DS35007C-page 57
PIC16F84A
FIGURE 9-8: RESET , WATC HDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
TABLE 9-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER REQUIREMENTS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 — — sVDD = 5.0V
31 TWDT Watchdog Timer Time-out
Period (No Prescaler) 71833msV
DD = 5.0V
32 TOST Oscillati on Start-up Timer
Period 1024TOSC ms TOSC = OSC1 period
33 TPWRT Power-up Timer Period 28 72 132 ms VDD = 5.0V
34 TIOZ I/O hi-impedance from MCLR
Low or RESET ——100ns
† Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested .
PIC16F84A
DS35007C-page 58 2001-2013 Microchip Technology Inc.
FIGURE 9-9: TIMER0 CLOCK TIMINGS
TABLE 9-5: TIMER0 CLOCK REQUIREMENTS
RA4/T0CKI
40 41
42
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
40 Tt0H T0CKI High Pulse
Width No Pr escal er 0.5TCY + 20 — — ns
With Prescaler 50
30 —
——
—ns
ns 2.0V VDD 3.0V
3.0V VDD 6.0V
41 Tt0L T0CKI Low Pulse
Width No Pr escal er 0.5TCY + 20 — — ns
With Prescaler 50
20 —
——
—ns
ns 2.0V VDD 3.0V
3.0V VDD 6.0V
42 Tt0P T0CKI Period TCY + 40
N— — ns N = prescale value
(2, 4, ..., 256)
† Data in "Typ" colum n is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
2001-2013 Microchip Technology Inc. DS35007C-page 59
PIC16F84A
10.0 DC/AC CHARACTERISTIC GRAPHS
The graphs provided in this section are for design guidance and are not tested.
In som e grap hs , th e data presented are outside spec ified op erating range (i.e ., out sid e speci fied VDD ran ge) . Th is i s
for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. ‘Typical’ represents the mean of the distribution at 25C. ‘Max’ or ‘Min’ represents
(mean + 3) or (mean - 3), respectively, where is a standard deviation over the whole temperature range.
PIC16F84A
DS35007C-page 60 © 2001-2013 Microchip Technology Inc.
FIGURE 10-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE, 25°C)
FIGURE 10-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE, -40° TO +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4 6 8 10 12 14 16 18 20
FOSC (MHz)
IDD (mA)
2.5 V
3.0 V
3.5 V
4.0 V
4.5 V
5.0 V
5.5 V
2.0 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
4 6 8 10 12 14 16 18 20
FOSC (MHz)
IDD (mA)
2.5 V
3.0 V
3.5 V
4.0 V
4.5 V
5.0 V
5.5 V
2.0 V
2001-2013 Microchip Technology Inc. DS35007C-page 61
PIC16F84A
FIGURE 10-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE, 25°C)
FIGURE 10-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE, -40° TO +125°C)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (MHz)
IDD (mA)
2.0 V
2.5 V
3.0 V
3.5 V
4.0 V
4.5 V
5.0 V
5.5 V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (MHz)
IDD (mA)
2.0 V
2.5 V
3.0 V
3.5 V
4.0 V
4.5 V
5.0 V
5.5 V
PIC16F84A
DS35007C-page 62 © 2001-2013 Microchip Technology Inc.
FIGURE 10-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE, 25°C)
FIGURE 10-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE, -40° TO +125°C)
0
10
20
30
40
50
60
70
80
25 50 75 100 125 150 175 200
FOSC (kHz)
IDD (µA)
5.0 V
5.5 V
4.0 V
3.5 V
4.5 V
3.0 V
2.5 V
2.0 V
0
50
100
150
200
250
25 50 75 100 125 150 175 200
FOSC (kHz)
IDD (µA)
5.0 V
5.5 V
4.0 V
3.5 V
4.5 V
3.0 V
2.5 V
2.0 V
2001-2013 Microchip Technology Inc. DS35007C-page 63
PIC16F84A
FIGURE 10-7: AVERAGE FOSC vs. VDD FOR R (RC MODE, C = 22 pF, 25C)
FIGURE 10-8: AVERAGE FOSC vs. VDD FOR R (RC MODE, C = 100 pF, 25C)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq ( M Hz)
5.1 k
3.3 k
10 k
100 k
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2.02.53.03.54.04.55.05.5
VDD (V)
Freq (KHz)
100 k
10 k
5.1 k
3.3 k
PIC16F84A
DS35007C-page 64 © 2001-2013 Microchip Technology Inc.
FIGURE 10-9: AVERAGE FOSC vs. VDD FOR R (RC MODE, C = 300 pF, 25C)
FIGURE 10-10 : IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
0
100
200
300
400
500
600
700
800
900
2.02.53.03.54.04.55.05.5
VDD (V)
Freq (KHz)
3.3 k
5.1 k
10 k
100 k
0.0
0.1
1.0
10.0
2.02.53.03.54.04.55.05.5
VDD (V)
IPD (µA)
Max
Typ
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2001-2013 Microchip Technology Inc. DS35007C-page 65
PIC16F84A
FIGURE 10-11: IPD vs. VDD (WDT MODE)
FIGURE 10-12: TYPICAL, MINIMUM, AND MAXIMUM WDT PERIOD vs. VDD OVER TEMP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (µA)
Max
Typ
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0
10
20
30
40
50
60
2.02.53.03.54.04.55.05.5
VDD (V)
WDT Period (ms)
Ma
x
Min
Typ
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F84A
DS35007C-page 66 © 2001-2013 Microchip Technology Inc.
FIGURE 10-13: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C)
FIGURE 10-14: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0
IOH (mA)
VOH (V)
Ma
Typ
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25
IOH (mA)
VOH (V)
Max
Typ
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2001-2013 Microchip Technology Inc. DS35007C-page 67
PIC16F84A
FIGURE 10-15: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C)
FIGURE 10-16: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25
IOL (mA)
VOL (V)
Max
Typ
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0
IOL (mA)
VOL (V)
Max
Typ
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F84A
DS35007C-page 68 © 2001-2013 Microchip Technology Inc.
FIGURE 10-17: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO +125C)
FIGURE 10-18: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VTH
VTH
VTH
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VIH Max VIH Typ
VIH Min
VIL Max VIL Typ
VIL Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2001-2013 Microchip Technology Inc. DS35007C-page 69
PIC16F84A
11.0 PACKAGING INFORMATION
11.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanum eri c trac eab ili ty code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the ful l Micr ochip part nu mber ca nnot be m arked on one line , it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
18-Lead PDIP (300 mil) Example
18-Lead SOIC (7.50 mm) Example
20-Lead SSOP (5.30 mm) Example
PIC16F84A-04I/P
0110017
PIC16F84A-04
/SO
0110017
PIC16F84A-
20/SS
0110017
3
e
3
e
3
e
PIC16F84A
DS35007C-page 70 2001-2013 Microchip Technology Inc.
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PIC16F84A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16F84A
DS35007C-page 72 2001-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS35007C-page 73
PIC16F84A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16F84A
DS35007C-page 74 2001-2013 Microchip Technology Inc.
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2001-2013 Microchip Technology Inc. DS35007C-page 75
PIC16F84A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16F84A
DS35007C-page 76 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS35007C-page 77
PIC16F84A
APPENDIX A: REVISION HISTORY
Version Date Revision Description
A 9/1998 This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the PIC16 F8X Dat a Sheet, DS30430.
B 05/2001 Added DC and AC Characteristics Graphs and Tables to Section 10.
C 11/2011 Updated the “Packaging Information” section.
PIC16F84A
DS35007C-page 78 2001-2013 Microchip Technology Inc.
APPENDIX B: CONVERSION CONSIDERATIONS
Considerations for converting from one PIC16X8X
dev i ce to another are listed in Table 1.
TABLE 1: CONVERSION CONSIDERATIONS - PIC16C84, PIC16F83/F84, PIC16CR83/CR84,
PIC16F84A
Difference PIC16C84 PIC16F83/F84 PIC16CR83/
CR84 PIC16F84A
Program Memo ry Size 1K x 14 512 x 14 / 1K x 14 512 x 14 / 1K x 14 1K x 14
Data Memory Size 36 x 8 36 x 8 / 68 x 8 36 x 8 / 68 x 8 68 x 8
Voltage Range 2.0V - 6.0V
(-40C to +85C) 2.0V - 6.0V
(-40C to +85C) 2.0V - 6.0V
(-40C to +85C) 2.0V - 5.5V
(-40C to +125C)
Maximum O perating Fre-
quency 10 MHz 10 MHz 10 MHz 20 MHz
Supply Current (IDD).
See parameter # D014 in
the electrical specs for
more detail.
IDD (typ) = 60 A
IDD (max) = 400 A
(LP osc, FOSC = 32 kHz,
VDD = 2.0V,
WDT disabled)
IDD (typ ) = 15 A
IDD (m ax) = 45 A
(LP osc, FOSC = 32 kHz,
VDD = 2.0V,
WDT disabled)
IDD (typ) = 15 A
IDD (max) = 45 A
(LP osc, FOSC = 32 kHz,
VDD = 2.0V,
WDT disabled)
IDD (typ ) = 15 A
IDD (max) = 45 A
(LP osc, FOSC = 32 kHz,
VDD = 2.0V,
WDT disabled)
Power-down Current
(IPD). See parameters #
D020, D021, and D021A
in the electrical specs for
more detail.
IPD (typ) = 26 A
IPD (max) = 100 A
(VDD = 2.0V,
WDT disabled, industrial)
IPD (typ) = 0.4 A
IPD (max) = 9 A
(VDD = 2.0V,
WDT disabled, industrial)
IPD (typ) = 0.4 A
IPD (max) = 6 A
(VDD = 2.0V,
WDT disabled, industrial)
IPD (typ) = 0.4 A
IPD (max) = 1 A
(VDD = 2.0V,
WDT disabled, industrial)
Input Low Voltage (VIL).
See parameters # D032
and D034 in the electrical
specs for more detail.
VIL (max) = 0.2VDD
(OSC1, RC mode) VIL (max) = 0.1VDD
(OSC1, RC mode) VIL (max) = 0.1VDD
(OSC1, RC mode) VIL (max) = 0.1VDD
(OSC1, RC mode)
Input High Voltage (VIH).
See parameter # D040 in
the electrical specs for
more detail.
VIH (min) = 0.36VDD
(I/O Po rts with TTL,
4.5V VDD 5. 5V)
VIH (min) = 2.4V
(I/O Ports with TTL,
4.5V VDD 5.5V)
VIH (min) = 2.4V
(I/O Ports with TTL,
4.5V VDD 5.5V)
VIH (min) = 2.4V
(I/O Ports with T TL,
4.5V VDD 5.5V)
Data EEPRO M Memory
Erase/Write cycle time
(TDEW). See p arameter #
D122 in the electrical
specs for more detail.
TDEW (typ) = 10 ms
TDEW (max) = 20 ms TDEW (typ) = 10 ms
TDEW (max) = 20 ms TDEW (typ) = 10 ms
TDEW (max) = 20 ms TDEW (typ) = 4 ms
TDEW (max) = 8 ms
Port Output Rise/Fall
time (TioR, TioF). See
parameters #20, 20A,
21, and 21A in the elec-
trical specs for more
detail.
TioR, TioF (max) = 25 ns
(C84)
TioR, TioF (max) = 60 ns
(LC84)
Ti oR, Ti oF (max) = 35 ns
(C84)
Ti oR, Ti oF (max) = 70 ns
(LC84)
T ioR, T ioF (max) = 35 ns
(C84)
T ioR, T ioF (max) = 70 ns
(LC84)
Ti oR, Ti oF (max) = 35 ns
(C84)
Ti oR, Ti oF (max) = 70 ns
(LC84)
MCLR on-chip filter. See
parameter #30 in the
electrical specs for more
detail.
No Yes Yes Yes
PORTA and crystal oscil-
lator values less than
500 kHz
For crystal oscillator con-
figurations operating
below 500 kHz, the device
may generate a spurious
internal Q-clock when
PORTA<0> switches
state.
N/A N/A N/A
RB0/INT p i n TTL TTL/ST*
(*Schmitt Trigger) TTL/ST*
(*Schmitt Trigger) TTL/ST*
(*Schmitt T rigger)
2001-2013 Microchip Technology Inc. DS35007C-page 79
PIC16F84A
EEADR<7:6> and IDD It is recommended that
the EEADR<7:6> bits be
cleared. When either of
these bits is set, the maxi-
mum IDD for the device is
higher than when both are
cleared.
N/A N/A N/A
The polarity of the
PWRTE bit PWRTE PWRTE PWRTE PWRTE
Recommended value of
REXT for RC oscillator
circuits
REXT = 3k - 100kREXT = 5k - 100kREXT = 5k - 100kREXT = 3k - 100k
GIE bit unintentional
enable If an interrupt occurs while
the Global Interrupt
Enable (GIE) bit is being
cleared, the GIE bit may
unintentionally be re-
enabled by the user’s
Interrupt Service Routine
(the RETFIE instructio n).
N/A N/A N/A
Packages PDIP, SOIC PDIP, SOIC PDIP, SOIC PDIP, SOIC, SSOP
Open Drain High
Voltage (VOD)14V 12V 12V 8.5V
TABLE 1: CONVERSION CONSIDERATIONS - PIC16C84, PIC16F83/F84, PIC16CR83/CR84,
PIC16F84A (CONTINUED)
Difference PIC16C84 PIC16F83/F84 PIC16CR83/
CR84 PIC16F84A
PIC16F84A
DS35007C-page 80 2001-2013 Microchip Technology Inc.
APPENDIX C: MIGRATION FROM
BASELINE TO
MID-RANGE DEVICE S
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a mid-range device (i.e.,
PIC16CXXX).
The following is the list of feature improvements over
the PIC16C5X microcontroller family:
1. Instruction word length is increased to 14-bits.
This allows larger page sizes, both in program
memory (2K now as opposed to 512K before)
and the register file (128 bytes now versus
32 bytes before).
2. A PC latch register (PCLATH) is added to han-
dle progra m memory p aging. PA2, P A1 and PA0
bits are removed from the STATUS register and
plac ed in the OPTION regis ter.
3. Data memory paging is redefined slightly. The
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW. Two
instructions, TRIS and OPTION, are being
phased out, although they are kept for
compatibility with PIC16C5X.
5. OPTION and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to eight-deep.
8. RESET vector is changed to 0000h.
9. RESET of all registers is revisited. Five dif ferent
RESET (and wake-up) types are recognized.
Registers are reset differently.
10. Wake-up from SLEEP through interrupt is
added.
11. Two separate timers, the Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT), are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt-on-
change features.
13. T0CKI pin is also a port pin (RA4/T0CKI).
14. FSR is a full 8-bit register.
15. "In system programmin g" is made possible. The
user can program PIC16CXX de vices using only
five pins: VDD, VSS, VPP, RB6 (clock) and RB7
(data in/out).
To convert code written for PIC16C5X to PIC16F84A,
the user should take the following steps:
1. Remove any program memory page select
operatio ns (P A2, PA 1, P A0 bits ) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefi ne data variables for reall oc ati on.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change RESET vector to 0000h.
2001-2013 Microchip Technology Inc. DS35007C-page 81
PIC16F84A
INDEX
A
Absolute Maximum Ratings................................................47
AC (Timing) Characteristics................................................53
Archit e cture, Block Diagram .................. ....................... ........3
Assembler
MPASM Assembler.....................................................44
B
Banking, Data Memory .........................................................6
Block Diagrams
Crystal/Ceramic Resonator Operation........................22
External Clock Input Operation...................................22
External Power-on Reset Circuit.................................26
Inter rupt Logic............... .................................... ..........29
On-chip Reset.............................................................24
PIC16F84A ...................................................................3
PORTA
RA3:RA0 Pin s.................... .............. ...................15
RA4 Pins.............................................................15
PORTB
RB3:RB0 Pin s.................... .............. ...................17
RB7:RB4 Pin s.................... .............. ...................17
RC Oscillator Mode.....................................................23
Timer0.........................................................................19
Timer0/WDT Prescaler ...............................................20
Watchdog Timer (WDT)..............................................31
C
C (Carry ) bi t ... ........................... ................................ ............8
C Compilers
MPLAB C18... ....................... .................................... ..44
CLKIN Pin.............................................................................4
CLKOUT Pin.........................................................................4
Code Examples
Clearing RAM Using Indirect Addressing ....................11
Data EEPOM Write Ve rify.................... .......................14
Indirect Addressing.....................................................11
Initializing PORTA.......................................................15
Initializing PORTB.......................................................17
Reading Data EEPROM .............................................14
Savin g STATUS and W Regist e rs in RAM .................30
Writing to Data EEPROM............................................14
Code Protection ........................................................... 21, 33
Configuration Bits................................................................21
Configuration Word.............................................................21
Conversi o n Co n sideratio n s.................... ................... ..........78
Customer Change Notification Service...............................85
Custome r Notificatio n Se rvice...................... ................... ....85
Customer Support............................................................. ..85
D
Data EEPROM Mem o ry.................. ............................ ........13
Associ a te d Re g i sters.... ........................... ...................14
EEADR Register..............................................7, 13, 25
EECON1 Registe r....... .......... ............... ............7, 13, 25
EECON2 Registe r....... .......... ............... ............7, 13, 25
EEDATA Register............................................ 7, 13, 25
Write Complete Enable (EEIE Bit)..............................29
Write Complete Flag (EEIF Bit)...................................29
Data EEPROM Write Co mple te......... .............. ...................29
Data Memor y .......................... ........................... ...................6
Bank Select (RP0 Bit)...................................................6
Banking.........................................................................6
DC bit....................................................................................8
DC Ch a r a cteri s t i c s. .. ...... ............. .......... ......... .......... .....49, 51
Development Support......................................................... 43
Device Overview................................................................... 3
E
EECON1 Register
EEIF Bit ...................................................................... 29
Elect r i ca l C h a ra c t e r i stics ... ...... ..... ...... .......... ..... .......... ...... . 4 7
Load Conditions.......................................................... 54
Paramete r Measurement Information....... .................. 54
PIC16F84A-04 Voltage-Frequency Graph ................. 48
PIC16F84A-20 Voltage-Frequency Graph ................. 48
PIC16LF84A-04 Voltage-Frequency Graph ............... 48
Temperature and Voltage Specifications - AC ........... 54
Endurance ............................................................................ 1
Errata.................................................................................... 2
Extern a l C l o ck In put (R A4/T0C KI ) . See Timer0
External Interrupt Input (RB0/INT). See Interrupt Sources
Exter n al Po w e r-on R e se t C i r cu i t ..... ...... ...... .. ..... ...... .......... . 26
F
Firm w a r e Instructi o n s ...... ......... .......... .......... ......... ............. 35
I
I/O Ports ...... ................................................ ....................... 15
ID Locations..................................................................21, 33
In-C i rc u i t Serial Pr o grammin g (IC SP)... ...... .. ..... ...... .....21, 33
INDF Register....................................................................... 7
Indir ect Add res si n g...... .. .......... ..... .......... ......... .......... ......... 11
FSR Register.............................................. 6, 7, 11, 25
IND F R e g i ster...... ...... ......... .............. ......... ......7, 11, 25
Instruction Format............................................................... 35
Instruction Set..................................................................... 35
ADDLW....................................................................... 37
ADDWF ...................................................................... 37
ANDLW....................................................................... 37
ANDWF ...................................................................... 37
BCF ............................................................................ 37
BSF............................................................................. 37
BTFSC........................................................................ 38
BTFSS........................................................................ 37
CALL........................................................................... 38
CLRF.......................................................................... 38
CLRW......................................................................... 38
CLRWDT.................................................................... 38
COMF......................................................................... 38
DECF.......................................................................... 38
DECFSZ..................................................................... 39
GOTO......................................................................... 39
INCF........................................................................... 39
INCFSZ....................................................................... 39
IORLW........................................................................ 39
IORWF........................................................................ 39
MOVF......................................................................... 40
MOVLW...................................................................... 40
MOVWF...................................................................... 40
NOP............................................................................ 40
RETFIE....................................................................... 40
RETLW....................................................................... 40
RETURN..................................................................... 40
RLF............................................................................. 41
RRF............................................................................ 41
SLEEP........................................................................ 41
SUBLW....................................................................... 41
PIC16F84A
DS35007C-page 82 2001-2013 Microchip Technology Inc.
SUBWF.......................................................................41
SWAPF .......................................................................41
XORLW.......................................................................42
XORWF.......................................................................42
Summary Ta b l e...... ................................ .....................36
INT Interrupt (RB0/INT) .......................................................29
INTCON Register.................................7, 10, 18, 20, 25, 29
EEIE Bi t.............................................. .........................29
GIE Bi t...... ............................... ............................. 10, 29
INTE Bit............................... ................................. 10, 29
INTF Bit............................... ............................... ..10, 29
PEIE Bi t.............................................. .........................10
RBIE Bit ...............................................................10, 29
RBIF Bit..................................... .....................10, 17, 29
T0IE Bit...... ....................... ............................... .... 10, 29
T0IF Bit ......................... .................................10, 20, 29
Inter net Addr e ss...................... ........................................ ....85
Inter rupt Sou r ces........................... ...............................21, 29
Block Diag ram............... ........................... ...................29
Data EEPROM Write Co mplete......... .............. .... 29, 32
Interrupt-on-Change (RB7:RB4) ...............4, 17, 29, 32
RB0/INT Pin, External...............................4, 18, 29, 32
TMR0 Overflow....................................................20, 29
Inter rupts, Co n te xt Savin g Duri n g......... ............................ ..30
Interrupts, Enable Bits
Data EEPROM Write Complete Enable (EEIE Bit) .....29
Global Interrupt Enable (GIE Bit) ................................10
Interrupt-on-Change (RB7: RB4) Enable (RB IE Bit)....10
Peripheral Interrupt Enable (PEIE Bit) ........................10
RB0/INT Enable (INTE Bit) .........................................10
TMR0 Overflow Enable (T0IE Bit)...............................10
Inter rupts, Fla g Bits..................... ........................... .............29
Data EEPROM Write Co mplete Flag (EEIF Bit)..........29
Interrupt-on-Change (RB7: RB4) F lag (RBIF Bit) ........10
RB0/INT Flag (INTF Bit)..............................................10
TMR0 Overflow Flag (T0IF Bit)....... ........................ ....10
IRP bit..... ........................................ .................................... ..8
M
Master Clear (MCLR)
MCLR Pin............................ ........................................ ..4
MCLR Reset, Normal Operation........ .......... ...............24
MCLR Reset, SLEEP...... ............................... ......24, 32
Memory Organization............................................................5
Data EEPROM Mem o ry.................. ............................13
Data Memor y .......................... ........................... ...........6
Program Memory ..........................................................5
Microc h i p In ternet Web Site............................. ...................85
Migration from Baseline to Mid-Range Devices..................80
MPLAB ASM30 Assembler, Linker, Librarian .....................44
MPLAB Integrated Development Environment Software ....43
MPLAB PM3 Device Programmer.......................................46
MPLAB REA L IC E In -Circuit Emula tor Syst e m...................45
MPLINK Object Linker/MPLIB Object Librar ia n ....... ...........44
O
OPCODE Fiel d Descri p tions... .......... ............... ...................35
OPTION Register..................................................................9
INTEDG Bi t...... ................... ............................... ...........9
PS2:PS0 Bits ................................................................9
PSA Bit..........................................................................9
RBPU Bit........ ............................... ................................9
T0CS Bit........................................................................9
T0SE Bit........................................................................9
OPTION_R EG Re g i ster.... ....................... .........7, 18, 20, 25
INTEDG Bit........ ..................................................... .... 29
PS2:PS0 Bits.............................................................. 19
PSA Bit ... .. ...... ..... ...... .. ...... ...... ..... ...... ...... ..... ...... ...... . 19
OSC1 Pin.............................................................................. 4
OSC2 Pin.............................................................................. 4
Oscillato r Configurat ion ....................... .........................21, 22
Block Diag ram ................ ....................... ...............22, 23
Capacitor Selection for Ceramic Resonators.............. 22
Capacitor Selection for Crystal Oscillator................... 23
Crystal Oscillator/Ceramic R esonators....................... 22
HS.........................................................................22, 28
LP .........................................................................22, 28
Oscillat or Ty pes................ ........... .......... ...... ............... 22
RC .................................................................22, 23, 28
XT.........................................................................22, 28
P
Packagi n g Informa tio n............................... ......................... 69
Marking....................................................................... 69
PD bit.................................................................................... 8
Pinout Descriptions................. .. .... ......... .... .... .. .... ......... .... ....4
Pointer, FSR....................................................................... 11
POR. See Power-on Reset
PORTA ...........................................................................4, 15
Associated Registers.................................................. 16
Functions.................................................................... 16
Initializing.................................................................... 15
PORTA Register.......................................7, 15, 16, 25
RA3:RA0 Block Diagra m........ ........................ ............ 15
RA4 Block Diagram....................................................15
RA4/T0CKI Pin......... .............. ............... ..........4, 15, 19
TRISA Register ...................................7, 15, 16, 20, 25
PORTB ...........................................................................4, 17
Associated Registers.................................................. 18
Functions.................................................................... 18
Initializing.................................................................... 17
PORTB Register.......................................7, 17, 18, 25
Pull-up Enable Bit (RBPU Bit)....................................... 9
RB0/INT Edge Select (INTEDG Bit) ............................. 9
RB0/INT Pin, External......................................4, 18, 29
RB3:RB0 Block Diagra m........ ........................ ............ 17
RB7:RB4 Block Diagra m........ ........................ ............ 17
RB7:RB4 Interrupt-on-Change ........................4, 17, 29
RB7:RB4 Interrupt-on-Change Enable (RBIE Bit )...... 10
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit).....10, 17
TRISB Register .........................................7, 17, 18, 25
Postscaler, WDT
Assignment (PSA Bit)................................................... 9
Rate Select (PS2:PS0 Bits).......................................... 9
Postscaler. See Prescaler
Power-down (PD ) Bit. See Power-on Reset (POR)
Power-down Mode. See SLEEP
Power-on Reset (POR)..........................................21, 24, 26
Oscillator Start-up Timer (OST)............. ...... .........21, 26
PD Bit ... ...... ......... ...... ...... ...... ..... ........8, 24, 28, 32, 33
Power-up Ti mer (P WRT )......... ..... ...... .......... ..... ...21, 26
Time-out Sequence ................................... ............. .... 28
Time-out Sequence on Power-up.............. ...........27, 28
TO Bit ..........................................8, 24, 28, 30, 32, 33
Prescaler............................................................................. 19
Assignment (PSA Bit) ................................................. 19
Block Diag ram ........................ ................... ................. 20
Rate Select (PS2:PS0 Bits)........................................19
Swit ch i n g Pre scal e r A ss i g nmen t .. .. .. ...... ......... .. ...... ... 20
2001-2013 Microchip Technology Inc. DS35007C-page 83
PIC16F84A
Prescaler, Timer0
Assignment (PS A Bit) .................... ...............................9
Rate Select (PS2:PS0 Bits) ..........................................9
Program Counter ................................................................11
PCL Register.................................................... 7, 11, 25
PCLATH Register ................... ................... ......7, 11, 25
Reset Conditions................... ................... ...................24
Program Memory ..................................................................5
General Purpose Registers...........................................6
Inter rupt Vector................... ................................... 5, 29
RESET Vec tor.......................................... .....................5
Special Function Registers...................................... 6, 7
Programming, Device Instructions......................................35
R
RAM. See Data Memory
Reader Response...............................................................86
Register File....... ................... ....................... ....................... ..6
Register File Map................ ....................... ....................... ....6
Registers
Configuration Word.....................................................21
EECON1 (EEPROM Contro l)..... .............. ...................13
INTCON......................................................................10
OPTION........................................................................9
STATUS........................................................................8
Reset............................................................................ 21, 24
Block Diag ram............. ....................... .................. 24, 26
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for All Registers..............................25
Reset Conditions for Program Counter.......................24
Reset Conditions for STATUS Register......................24
WDT Reset. See Watchdog Timer (WDT)
Revision History..................................................................77
RP1:RP0 (Bank Select) bits............ ................... ...................8
S
Saving W Register and STATUS in RAM . ..........................30
SLEEP ............................................................21, 24, 29, 32
Softwa re Simulator ( MP L AB SIM)...................... .................45
Speci a l Features of th e CPU ................. ....................... ......21
Special Function Registers .............................................. 6, 7
Speed, Operating................ .. .... .. .... ....... .. .... .. ...1, 22, 23, 55
Stack...................................................................................11
STATUS Regi ster .................................... ...........7, 8, 25, 30
C Bit.................................... ............................ ..............8
DC Bit............................................................................8
PD Bit................................................. 8, 24, 28, 32, 33
Reset Conditions................... ................... ...................24
RP0 Bit..........................................................................6
TO Bit...........................................8, 24, 28, 30, 32, 33
Z Bit...............................................................................8
T
Time-o ut (TO) Bit. See Power-on Reset (POR)
Timer0.................................................................................19
Associ a te d Re gister s............................... ...................20
Block Diag ram......... ........................... ....................... ..19
Clock Source Edge Select (T0SE Bit)...........................9
Cloc k So u rce Se l e ct (T0C S Bit)...... .. .......... ..... ...... ...... .9
Overflow Enable (T0IE Bit) .................................. 10, 29
Overflow Flag (T0 IF Bit)............. ....................10, 20, 29
Overflow Inte rr u p t ..... ............................... ............ 20, 29
Prescaler. See Prescaler
RA4/T0CKI Pin, External Clock ..................................19
TMR0 Register.................................................7, 20, 25
Timing Conditions............................................................... 54
Timing Diagrams
CLKOUT and I/O. ....................................................... 56
Diagrams and Specifications...................................... 55
CLKOUT and I/O Requirements......................... 56
External Clock Requirements............................. 55
RESET, Watchdog Timer, Oscillator
Start-up Timer and Power-up
Timer Requirements................................... 57
Timer0 Clock Requirements............................... 58
External Clock ............................................................ 55
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer................................. 57
Time-out Sequence on Power-up.........................27, 28
Timer0 Clock .............................................................. 58
Wake-up From Sleep Through Interrupt..................... 32
Timing Parameter Symbology ............................................ 53
TO bit.................................................................................... 8
W
W Register..... ....................... ............................ ............25, 30
Wake-up from SLEEP...............................21, 26, 28, 29, 32
Interrupts ..............................................................32, 33
MCLR Reset....... ................... ....................... .............. 32
WDT Reset............... ....................... ....................... .... 32
Watchdog Timer (WDT)................................................21, 30
Block Diag ram................ ................... ......................... 31
Postscaler. See Prescaler
Programming Considerations..................................... 31
RC Oscillator .............................................................. 30
Time-out Peri o d.............. ............................................ 30
WDT Reset, Normal Operation................................... 24
WDT Reset, SLEEP .............................................24, 32
WWW Address ............. .................................................... .. 85
WWW, On-Line Support....................................................... 2
Z
Z (Zero) bit......... ................................ ............................... .... 8
PIC16F84A
DS35007C-page 84 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS35007C-page 85
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4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2001-2013 Microchip Technology Inc. DS35007C-page87
PIC16F84A
PIC16F84 A PRODUCT IDENTIFICATION SYSTE M
To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office.
Device PIC16F84A(1), PIC16F84AT(2)
PIC16LF84A(1), PIC16LF84AT(2)
Frequency Range 04 = 4 MHz
20 = 20 MHz
Temperature
Range - = 0°C to +70°C
I = -40°C to +85°C
Package P = PDIP
SO = SOIC (Gull Wing, 300 mil body)
SS = SSOP
Pattern QTP, SQTP, ROM Code (factory specified) or
Special Requirements . Blank for OTP and
Windowed devices.
Examples:
a) PIC16F84A -04/P 301 = Commercial
temp., PDIP package, 4 MHz, normal VDD
limits, QTP pattern #301.
b) PIC16LF84A - 04I/SO = Industrial temp.,
SOIC package, 200 k Hz, Extended VDD
limits.
c) PIC16F84A - 20I/P = Industrial temp.,
PDIP package, 20 MHz, normal VDD limits.
Note 1: F = Standard VDD range
LF = Extended VDD range
2: T = in tape and reel - SOIC and
SSOP packages only.
PART NO. -XX X/XX XXX
PatternPackageTemperature
Range
Frequency
Range
Device
PIC16F84A
DS35007C-page 88 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS35007C-page 89
Information contained in this publication regarding device
applications and the like is p rovided only for your c onvenien ce
and may be supe rseded by updates. It is y our res ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC 32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology I nc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM ,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In-Cir c u it Se r i a l
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Tec hnology Germ any II GmbH & C o. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2001-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769409
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that i ts family of products is one of t he most secure families of its kind on the market today, when used in t he
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS35007C-page 90 2001-2013 Microchip Technology Inc.
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11/29/12
