ABS System IC 1 Overview 1.1 Features * * * * * * * * * TLE 6210 TLE 6211 5 V, 800 mA linear regulator Undervoltage/overvoltage reset Undervoltage and overvoltage logout Digital watchdog supervision for 2 Microcontrollers (motor) relay driver (valve) relay driver Inverted or non inverted lamp relay driver Enable output Overtemperature and overcurrent protection P-DSO-20-10, -12, -16 Type Ordering code Package/Shipment TLE 6210 C on request Bare dice TLE 6210 G on request P-DSO-20-12, Tape and Reel TLE 6211 G on request P-DSO-20-12, Tape and Reel 1.2 Functional Description The TLE 6210 and TLE 6211 are integrated circuit consisting of a 5 V voltage regulator with 800 mA current capability, different relay driver outputs and supervision logic. The supervision logic watches the input voltage and the regulator output voltage both for over-voltage and under-voltage. In addition two window watchdogs supervise the correct operation of 2 independent watchdog signals, e.g. from two Microcontrollers. The TLE 6210 and TLE 6211 are designed especially for the severe conditions of ABS/ ASR applications in an automotive environment. V1.2 Data Sheet 1 2002-08 TLE 6210 TLE 6211 Overview 1.3 Block Diagram UST UZP Linear Regulator USTS USTS under- and overvoltage reset detection Reset detection UZP UVLO and OVLO detection RES1 RES2 MR SupervisionLogic EN PGND VR PGND WD1 Window watchdog SILA WD 2 PGND NSILA SIA PGND MRA Oscillator Clock supervision UCP Charge Pump PGND GND TLE6210-block AD 20.09.01 Figure 1 Block Diagram V1.2 Data Sheet 2 2002-08 TLE 6210 TLE 6211 Pin / Pad Configuration 2 Figure 2 Pin / Pad Configuration 20 11 1 10 Pin Configuration P-DSO-20-12 UZP UCP RES1 EN RES2 Layout VR SILA NSILA GNDP GNDP GND Figure 3 UST USTS GND WD1 MRA WD2 SIA MR Chip-Layout V1.2 Data Sheet 3 2002-08 TLE 6210 TLE 6211 Pin / Pad Configuration Pin / Pad Definitions and Functions Pin Number TLE 6210 G TLE 6211G Symbol / Pad Name 1 1 GND Power GND connection 2 2 N.C. Not Connected 3 3 UZP Supply Voltage; reverse protection diode is required 4 4 UCP Charge Pump Capacitor pin; An external capacitor is the energy storage for the charge pump 5 5 RES1 Reset Output 1; open collector output with integrated pull-up resistor. A high indicates normal operation; function identical to RES2 6 6 EN Enable Output; open collector; low indicates an error condition 7 7 RES2 Reset Output 2; open collector output with integrated pull-up resistor. A high indicates normal operation; function identical to RES1 8 8 VR Valve Relay Output; open drain output 9 - SILA Lamp Output; open drain output; For TLE 6210 CW only - 9 NSILA Inverted Lamp Output; open drain output; For TLE 6211 CW only 10 10 GND Power Ground connection 11 11 GND Power Ground connection 12 12 MR Motor Relay Output; open drain output 13 13 SIA Lamp Control Signal Input; controls SILA/NSILA; a logic high switches SILA off and NSILA on 14 14 WD2 Watchdog Input 2 15 15 MRA Motor Relay Control Input; A logic High switches MR on 16 16 WD1 Watchdog Input 1 17 17 GND Logic Ground 18 18 Sense input for UST supervision 19 19 USTS UST 20 20 GND Ground Connection GND The lead frame connects the pins 1, 10, 11 and 20 to the backside metallization. Backside metallization V1.2 Data Sheet Function 5 V Linear Regulator Output 4 2002-08 TLE 6210 TLE 6211 Electrical Characteristics 3 Electrical Characteristics 3.1 Absolute Maximum Ratings -40 C Tj 150 C # M1 Parameter Supply Voltage Symbol Limit Values Unit Conditions UZP dUZP/dt M2 Supply Voltage variation M3 Output voltage at VR, MR UVR, UMR M4 Output voltage at SILA M5 Output voltage at NSILA M6 Output voltage at RES1, RES2 M7 Output voltage at EN M8 Input Voltage at WD1, WD2, MRA, SIA M9 Voltage UCP M10 Storage Temperature M11 Junction Temperature V1.2 Data Sheet USILA UNSILA URES1 URES2 UEN UWD1, UWD2 UMRA, USIA UCP Tstg Tj 5 min. max. 0 20 V - 0 26.5 V 0 < tp 5 min.; -40 C 80 C 0 35 V 0 < tp 200 ms; f < 0.067 Hz; n 360 cycles 0 35 V 0 < tp 50 ms; 0 < fp 1 Hz; n 36000 cycles -1.5 - V tp = 2 s - |10| V/ms - - 60 V VR, MR-DMOS off - 42 V SILA-DMOS off - 42 V NSILA-DMOS off -0.5 7 V - -0.5 7 V - -0.5 7 V - -0.5 20 V - -55 150 C - -40 150 175 C C continuos short term (< 50 h over lifetime) 2002-08 TLE 6210 TLE 6211 Electrical Characteristics 3.1 # Absolute Maximum Ratings (cont'd) -40 C Tj 150 C Parameter Symbol Limit Values Unit Conditions min. M12 ESD max. according to EIA/JESD 22-A 114B - 4000 - M13 Life Time tb V UZP, MR, EN, 2000 - V VR, SILA, all other pins 10000 - h ambient temperature range: -40C 2% -20C 10% 25C 24% 60C 34% 80C 24% 100C 5% >120C 1% Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V1.2 Data Sheet 6 2002-08 TLE 6210 TLE 6211 Electrical Characteristics 3.2 Functional Range # Parameter SymLimit Values bol min. typ. max. Unit Conditions F1 Supply voltage UZP 4.5 14.0 18 V - - - 26.5 V - - 4.5 V t < 5 min. UST 0.3 V; Reset = Low; Enable = Low; VR and MR off F2 Input capacitor CUZP 0.33 3.3 - mF TU = 20 C UN = 63 V Typ. = MKT -40 - 125 C P-DSO-20-12 -40 - - - 150 175 C C life time short time1) Thermal resistance Rthja junction-ambient - 40 - K/W P-DSO-20-12 minimum footprint Thermal resistance Rthjc junction-case - - 2.4 K/W P-DSO-20-12 F3 F4 Case Temperature F5 F6 1) Junction Temperature TC Tj Parameter may deviate in the temperature range Tj = 150 C ... 175 C Total operation time max. 50 h for temperature range Tj > 150 C Within the functional range the device works according to the functional description. However parameters may exceed the values given in the Characteristics. V1.2 Data Sheet 7 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4 Block Description and Electrical Characteristics 4.1 General Characteristics 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter SymLimit Values Unit Conditions bol min. typ. max. 4.1.1 Power consumption IUZP regulator - 7 15 mA UZP = 16 V, IUST = 800 mA, VR on, SILA on, EN, RES1, RES2 = High 4.1.2 Overtemperature Tab protection threshold 4.2 150 - - C Tj > Tab Oscillator A 16 kHz oscillator is used as time base for the 1 kHz clock. An independent clock supervision circuit supervises the oscillator. If the oscillator clock is missing the error flag is set. Characteristics Internal Oscillator 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Limit Values Unit Conditions Symbol min. typ. max. 16 - 17.6 18.4 kHz UZP 6 V kHZ 4.7 V UZP < 6 V tCLUE - 120 - ms error if tLow or tHigh > tCLUE tCLK 1 1.1 ms Period 4.2.1 Frequency fOSZ 4.2.2 Clock supervision 4.2.3 Logic time base V1.2 Data Sheet 14.4 13.6 0.9 8 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.3 Charge Pump The integrated charge pump requires an external capacitor at pin UCP. The charge pump voltage is typically 15 V. It is internally used for the voltage regulator only. It is only intended for internal function and may not be used for any external loads. The output voltage is short circuit protected against the supply voltage. Characteristics Charge Pump 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter 4.3.1 Power up time SymLimit Values Unit Conditions bol min. typ. max. tCP - 10 - ms UZP = 6 V; CCP = 68 nF; Load capacitor to U = 0.9 UCPmax 4.3.2 Charge pump voltage UCP 4.3.3 Frequency V1.2 Data Sheet fCP - 15 22 V 1.4 3.2 - MHz - 9 Regulator on 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.4 Voltage Regulator The 5 V low drop linear regulator can supply up to 800 mA current. The regulator requires an output capacitor. The linear regulator is equipped with overcurrent protection and its own overtemperature protection. The linear element consists of 2 anti-serial DMOS transistors. In case of low input supply voltage this avoids discharging of the output capacitor. The output voltage UST is supervised for over- and undervoltage. UST output has to be connected externally to the sense input USTS. If over- or undervoltage condition is detected the Reset outputs RES1 and RES2 are logical low. For a detailed description of the reset logic please see Chapter 4.9. Characteristics Voltage Regulator 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # 4.4.1 Parameter Nominal output voltage Symbol Limit Values min. typ. Unit max. UZP = 14 V; IST = 400 mA; Output capacitor as defined in 4.4.11; UST 4.4.2 UST load current IST 4.4.3 Line variation DUST Conditions 4.95 5.00 4.925 5.00 5.05 V 5.075 V on wafer level Tj = 25 C P-DSO-20-12 - - 800 mA - - - |50| mV Tj = 25 C; 6.0 V UZP 18 V; IST = 600 mA; capacitor as defined in 4.4.11; dUZ/dt < 1 V/ms V1.2 Data Sheet 10 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics Characteristics Voltage Regulator (cont'd) 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # 4.4.4 Parameter Load variation Symbol Limit Values min. typ. max. DUST - - |50| Unit Conditions mV Tj = 25 C; UZP = 14 V; 0 mA IST 800 mA; capacitor as defined in 4.4.11; dIST/dt 1 mA/ms 4.4.5 Temperature variation DUST - |50| |100| mV UZP = 14 V; IST = ISTmax; -40 C Tj 150 C; capacitor as defined in 4.4.11; for die mounted in a hybrid: dTU/dt 10 K/s for P-DSO-20-12: dTG/dt 5 K/min. 4.4.6 Long time drift DUST - 4.4.7 Overall output UST voltage tolerance 4.4.8 Power Supply ripple rejection 4.4.9 Series Resistor - |50| mV UZP UZPmax.; 0 mA IST ISTmax.; -40 C Tj 150 C; tb = 10000 h, see conditions M13. 4.75 5.00 5.25 V all parameters from 4.4.1 to 4.4.6 DUSTss - - |25| mV 0 Hz fUST 10 kHz; capacitor as defined in 4.4.11; 7 V UZP 24 V RDSon - - - - 1.7 2.7 W W Tj = 25 C Tj = 150 C UCP > 15 V; UZP = 6 V; IST = 800 mA 4.4.10 Maximum output IK current (output shorted) 0.8 - 1.6 A UCP > 15 V; UST = 0 V; 4.5 V UZP 18 V 4.4.11 Load capacitor at CUST output UST 3.3 - 150 mF TU = 20 C; UN = 25 V; Type ETQW Roederstein - 4 - W f = 100 kHz; TU = 20 C 4.4.12 UST off voltage USTRest - - 400 mV IST = 0 mA 4.4.13 Clamping voltage UZST - 7 V Z V1.2 Data Sheet 5.5 clamping voltage at I = 100 mA 11 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.5 Enable-Output EN The open collector enable output EN informs the system about any error condition. Any error except a detected supply under-voltage will set the EN output Low. Of cause for long under-voltage at the supply line, soon the UST output capacitor will be discharged and this will cause UST under-voltage and therefore EN Low. The time depends on the load and the output capacitor. The EN is an open collector output. It is short circuit protected to UST. After power up when the first watchdog edges at WD1 a WD2 are detected the Enable output is switched into High state. Characteristics EN Output 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol Limit Values min. typ. max. Unit Conditions IL 10 mA IL 1 mA UEN = 5 V 4.5.1 Output Low voltage UL - - - - 0.4 0.2 V V 4.5.2 Reverse current IR - - 5 mA V1.2 Data Sheet 12 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics Power Driver The TLE 6210/TLE 6211 includes 3 open drain outputs for loads up to 0.5 A: The two drivers VR and MR are intended for (valve and motor) relays, while the SILA/NSILA output is designed for a lamp. In the TLE 6210 GW the SILA output is available. The output goes low if the supply voltage UZP is no longer available - the DMOS is switched on automatically. In the TLE 6211 GW the NSILA has the inverted polarity related to SILA. In bare dice both outputs SILA and NSILA can be used. . 4.6 Valve Relay Output VR The valve relay output VR is switched On after the power up reset and valid watchdog signals. The driver has an open drain configuration and can supply up to 500 mA. The output is protected against overtemperature and overcurrent. The output is short circuit protected to UZ. The output stage is equipped with its own overtemperature protection. In case of overvoltage at the supply UZP the output is switched off. However the output is not protected against overvoltages caused by switching inductive loads. Therefore externally a free wheeling diode is required as shown in the application diagram. The valve relay output VR is controlled by the internal supervision logic. If any watchdog errors or supply over-voltage is detected or the 5 V regulator is out of range, the VR is switched off (please see also Table 1 on Page 19 and Table 2 on Page 28). Characteristics Relay Driver Output VR 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol min. typ. max. 4.6.1 Saturation Voltage UDS - - 1.2 V 4.6.2 On state resistance RDSon - - 2.4 W 4.6.3 Overload detection current IK 500 - - mA - 4.6.4 Output leakage current IR - - - - 0.5 2 mA mA UA 16 V 16 V < UA 60 V 4.6.5 Overtemperature shutdown threshold TK 150 - - C - V1.2 Data Sheet Limit Values 13 Unit Conditions Rlast 35 W; IL 0.5 A; 6 V UZP 16 V Tj = 150 C; IL = 0.5 A; UZP = 6 V 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.7 Motor Relay Driver The motor relay driver MR is controlled by the MRA input signal and the internal control logic. A logic High at the MRA input switches the MR low side switch on, a logic Low signal switches it off. However the supervision logic overrules the MRA input condition. Please see also Table 1 on Page 19 and Table 2 on Page 28. The output is an open collector output and can sink up to 500 mA. It is protected against overtemperature and overcurrent and short circuit prove to UZ. Even the output is switched off by the supervision logic at UZP overvoltage externally a free wheeling diode is required to protect the output against switching off inductive loads. Characteristics Relay Driver Output MR 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol min. typ. max. 4.7.1 Saturation Voltage UDS - - 1.2 V 4.7.2 On state resistance RDSon - - 2.4 W 4.7.3 Overload detection current IK 500 - - mA - 4.7.4 Output leakage current IR - - - - 0.5 2 mA mA UA 16 V 16 V < UA 60 V 4.7.5 Overtemperature shutdown threshold TK 150 - - C - V1.2 Data Sheet Limit Values 14 Unit Conditions Rlast 35 W; IL 0.5 A; 6 V UZP 16 V Tj = 150 C; IL = 0.5 A; UZP = 6 V 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.7.1 Control Input MRA The logic inputs MRA expect TTL-type signals from a m-controller with 5 V I/Os. An integrated pull-up resistor ensures that an open input is read High. Characteristics Control Inputs MRA 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter SymLimit Values Unit Conditions bol min. typ. max. 4.7.6 Internal pull-up resistor to UST RWD 4.7.7 UL Input voltage High UH 4.7.8 Input voltage Low 10 20 40 kW 0 V UE UST + 0.3 V -0.3 - 1.0 V - 2.0 - UST V - UE = UST UST < UE UST + 1 V + 1.0 4.7.9 Input current V1.2 Data Sheet IH - - |5| mA - - 1.0 mA 15 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.8 Error Lamp Output SILA and Lamp Relay Output NSILA The SILA output is a 300 mA open collector output. It is available in the TLE 6210 G. SILA is a self-on output: It is switched on if the supply voltage is missing. The TLE 6211 G is equipped with the logically inverted NSILA output. NSILA is a 30 mA open collector output. It is intended to drive the lamp relay. In the dice version TLE 6211 C both outputs can be used. Both SILA and NSILA are intended to control a warning lamp. The output is controlled by the internal supervision logic and control signal at the SIA pin. A logic High at the SIA input switches SILA off and NSILA on. The supervision logic will switch on SILA if a watchdog timing violation is detected or the output voltage UST is out of range. Table 1 on Page 19 and Table 2 on Page 28 give an overview on the different errors. The SILA output is equipped with its own overtemperature protection. Characteristics Lamp Driver Output SILA 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter 4.8.1 Saturation voltage SymLimit Values Unit Conditions bol min. typ. max. 2.5 2.5 V - - - I = 300 mA; UZP 6 V I = 300 mA; UZP = 0 V USILA - 4.8.2 Overload detection current IK 300 - - mA - 4.8.3 Output leakage current IR - - - - 0.1 4 mA mA 1 - 4.7 V 150 - - C USILA 16 V 16 V < USILA < 42 V USILA 2.5 V; I = 300 mA UZP 6 V 4.8.4 Threshold voltage for UZP automatic ON 4.8.5 Overtemperature shutdown threshold V1.2 Data Sheet TK 16 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics Characteristics Lamp-Relay Driver Output NSILA 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol Limit Values min. 4.8.6 On state resistance RDSon - Unit Conditions typ. max. - 33 W Tj = 150 C; I = 30 mA; UZP 7 V 4.8.7 Overload detection current IK 30 - - mA - 4.8.8 Output leakage current IR - - 10 mA UNSILA 42 V 4.8.1 Control Input SIA The logic inputs SIA expect TTL-type signals from a m-controller with 5 V I/Os. An integrated pull-up resistor ensures that an open input is read High. Characteristics Control Inputs SIA 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Limit Values Unit Conditions Symbol min. typ. max. 4.8.9 Internal pull-up resistor to UST RWD UL 4.8.11 Input voltage High UH 4.8.10 Input voltage Low 10 20 40 kW 0 V UE UST + 0.3 V -0.3 - 1.0 V - 2.0 - UST V - UE = UST UST < UE UST + 1 V + 1.0 4.8.12 Input current V1.2 Data Sheet IH - - |5| mA - - 1.0 mA 17 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics Supervision The TLE 6210 and TLE 6211 are equipped with a complex supervision logic. The input voltage and the regulator output voltage is supervised. In addition two m-controller are supervised by independent watchdog circuits. 4.9 Overvoltage and Undervoltage Both the supply voltage UZP and the output voltage UST are supervised for over- and undervoltage. In case any undervoltage or overvoltage condition at UST or UZP is detected, the reset outputs RES1 and RES2 are switched to low state. RES1 and RES2 are not controlled by the watchdog logic. To supervise the output voltage UST an independent bandgap from the reference bandgap is used. The reset outputs RES1 and RES2 are together controlled by the UST reset logic and the supply undervoltage lockout (UVLO) and overvoltage lockout (OVLO). A logic High at the RES1 and RES2 indicates normal operation. The outputs are open collector type outputs with integrated pull-up resistors to UST. Even when the UST voltage drops, the reset outputs RES1 and RES2 remain low (< 0.4 V). Both undervoltage and overvoltage detection of UST and UZP use a voltage hysteresis to avoid any reset toggling. Undervoltage and Overvoltage Detection UST The UST output voltage has to be externally connected to the USTS sense input. To be able to detect also wrong output voltages causes by a malfunction of the related bandgap reference for supervision an independent bandgap is used. As soon as any reset condition is detected the RES1 and RES2 go low. 4.9.1 Undervoltage Lockout (UVLO) and Overvoltage Lockout (OVLO) The supply voltage UZP is supervised as well. If the voltage rises above the upper threshold value of 19.5 V reset is asserted. When an undervoltage occurs, after some time the output voltage will drop below the reset threshold and a reset is asserted. The undervoltage lockout is only valid during power up. Both the OVLO and the UVLO threshold use a hysteresis to avoid reset glitches. In addition the OVLO is digitally filtered. Overvoltage below 2 to 3 clock cycles (equals typical 2 s or 3 s) are neglected to avoid resetting the system when any inductive load is switched off. V1.2 Data Sheet 18 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics When the undervoltage condition at UST or UZP is no longer detected a reset reaction time of typical 52 ms (52 clock cycles) is started. After this time the reset signal is set high. Table 1 Truth Table Overvoltage and Undervoltage Supervision The table assumes that no other error is detected, especially no watchdog failure and no clock failure. Supply voltage Regulator SILA Voltage UZP UST ok ok ok NSILA MR VR EN RES 1 Regulator RES 2 = SIA = not SIA = not MRA L Z H ON undervoltage L Z Z Z L L ON normal overvoltage L Z Z Z L H ON undervoltage undervoltage L Z Z Z Z* L OFF undervoltage ok = SIA = not SIA not MRA L H H ON overvoltage x =L Z Z* L OFF Z Z Z: high impedance * In the application the voltage is undefined as regulator is off V1.2 Data Sheet 19 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.9.2 Under- and Overvoltage Reset Behavior UZP 12V 5.3V t UST 5V 4.6V t 52ms RES1 5V t RES2 5V t Figure 4 Characteristics Supervision of UZP, UST 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol Limit Values min. typ. max. Unit Conditions UZP-Undervoltage 4.9.1 UZP undervoltage UZPU threshold 5.2 5.3 5.4 V UST off 4.9.2 UZP undervoltage UH 20 - 50 mV UZPU(ON) = UZPU(OFF) + UH1) hysteresis UZP-Overvoltage 4.9.3 UZP overvoltage UZUE 18.75 19.5 threshold V1.2 Data Sheet 20 20.25 V Outputs NSILA, VR, MR, UST off 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics Characteristics Supervision of UZP, UST (cont'd) 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter 4.9.4 UZP overvoltage Symbol Limit Values Unit Conditions UH = UZUE(on) - UZUE(off) UZP overvoltage min. typ. max. UH 0.5 - 1.0 V ton 2 1.8 - - 3 3.4 tCLK threshold ms toff 2 1.8 - - 3 3.4 tCLK UZP < overvoltage ms threshold hysteresis 4.9.5 UZP overvoltage filter UST-Undervoltage 4.9.6 UST undervoltage USTU threshold 4.5 4.6 4.7 V RES1, RES2 = low 4.9.7 UST undervoltage UH hysteresis 20 - 50 mV USTU(on) = USTU(off) + UH1) USTUE 5.3 5.4 5.5 V Error flag is set UH 20 - 50 mV ISTS 0.94 1.5 2.2 mA USTUE(ON) = USTUE (off) - UH1) USTS = 6 V tRH - 52 46.35 52 UST-Overvoltage 4.9.8 UST overvoltage threshold 4.9.9 UST overvoltage hysteresis 4.9.10 USTS input current Reset timing 4.9.11 Reset delay time 1) - tCLK 58.85 ms UZP 5.4 V UST 4.75 V Hysteresis guaranteed by design. V1.2 Data Sheet 21 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.10 Reset Outputs RES1, RES2 The two reset outputs RES1 and RES2 are open collector outputs with integrated pullup resistor of typical 10 kW to UST. Both outputs are protected against short circuits to UST. Characteristics RES1 and RES2 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter SymLimit Values Unit Conditions bol min. typ. max. 4.10.1 Output low voltage UL - - - - 0.4 0.4 V V 4.10.2 Output high voltage UH UST - UST V IL = 0.8 mA; UST = 1.8 V IL = 2 mA; UST = 4.5 V 1.8 V UST 4.5 V RL 10 MW 4.10.3 Internal pull-up resistor to UST RRES 5 10 20 kW 0 V UA UST + 0.3 V V1.2 Data Sheet - 0.1 22 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.11 Watchdog To supervise the operation of 2 m-processors watchdog logic for two input signals is integrated. The logic expects at each WD1 and WD2 rectangular signals with 10 ms high and 10 ms low time. Deviations from the expected time are counted as errors and influence the output signals. A digital filter suppresses noise or pulses below 3 clock cycles (typ. 3 ms). The detection ciruit is described in Figure 12. After power up and 1or 2 valid watchdog edges the WD logic enables the output Drivers. 1 WD1 2 10ms 1 0 1 WD2 EN 0 1 0 3* tCLK after the 2nd WD-edge (falling edge) wd-start-up-with Low AD 04/02 Figure 5 Enable output EN after correct watchdog signals at WD1 and WD2 are present; WD1 and WD2 start with logic Low 10ms 1 WD1 2 1 0 1 WD2 EN 0 1 0 3 * tCLK after 1st. WD edge wd-start-up-with High AD 04/02 Figure 6 Enable output EN after correct watchdog signals at WD1 and WD2 are present; WD1 and WD2 start with logic High V1.2 Data Sheet 23 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics The logic expects the time between two clock edges between 3 and 15 clock-cycles. If this window is not met, the outputs VR, MR and NSILA are switched off, SILA is switched on and the enable output goes low. An internal counter ( seeFigure 12) includes a 4 bit counter. Each time the value 15 is reached a dominant counter reset signal is generated at the output "=15". This pulse is generated continuously at t = (15+3) T1 + n * (16*T1) after the last valid watchdog pulse was detected. When internal resets and watchdog edges occur at the same time, the internal reset is dominant. 10ms t > 16 *tCLK 1 WD1 0 1 WD2 0 1 EN 0 Delay (3* tCLK) 15* tCLK + Delay = 15* tCLK + 3* tCLK wd-controls-en-2 AD 04/02 Figure 7 Missing watchdog signals cause EN low V1.2 Data Sheet 24 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 10ms t < 15 *tCLK 1 WD1 0 1 WD2 0 15*tCLK Delay (3* tCLK) 1 EN 0 Delay (3* tCLK) 15*tCLK + Delay = 15*tCLK + 3* tCLK wd-controls-en AD 03/02 Figure 8 Missing watchdog signals cause EN low 10ms WD Signal not detected 1 WD1 0 1 WD2 0 1 EN 0 (15+3) * tCLK 1 Counter Reset 0 16* tCLK Figure 9 wd-missing AD 03/02 Timing diagram - any watchdog signal missing causes a High signal at the output "=15" (Counter reset). This signal sets back the logic V1.2 Data Sheet 25 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics Any watchdog high or low time above 15 ms influences the enable (EN) and the VR output.If the time after the last watchdog edge exceeds 120 clock cycles - typical 120 ms- an error flag is set. This flag can only be removed by powering down the IC. 10ms 1 WD1 0 1 WD2 0 1 EN 0 (15+3) * tCLK Counter reset 1 0 16 * tCLK 1 set error flag 0 112 * tCLK + Delay = 112 * tCLK+ 3 * tCLK ) set-error-flag AD 03/02 Figure 10 Missing watchdog signals for more than 120 * tCLK (typ. 120ms) sets the failure register An integrated pull-up resistor to UST in the WD1 and WD2 inputs ensures to detect a permanent logic High in case the input is open. V1.2 Data Sheet 26 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics Characteristics WD1, WD2 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter SymLimit Values Unit bol min. typ. max. Conditions 10 20 40 kW 0 V UE UST + 0.3 V 4.11.2 Input voltage Low UL -0.3 - 1.0 V - 4.11.3 Input voltage High UH 2.0 - UST V - UE = UST UST < UE UST + 1 V 4.11.1 Internal pullup resistor to UST RWD + 1.0 IH 4.11.4 Input current - - |5| mA - - 1.0 mA Characteristics Watchdog 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Limit Values Symbol min. typ. max. Unit Conditions 1 - 2 tCLK Number of valid Watchdog input clock edges tpulse - 4.11.6 Closed window time 3 - tCLK The distance between clock edges is at least tpulse 4.11.5 Release tON reaction time 2.25 3 1.8 3 4.11.7 Open tVR window time 4.11.8 Error flag detection V1.2 Data Sheet tFSP equals: periodically pulse 3.3 3.3 ms ms - tCLK if the edge distance Dt > tVR, VR is switched off 13.5 15 17.6 ms - 120 - 108 120 132 tCLK if Dt > tFSP, the error flag is set. equals ms - 15 27 equals 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 4.11.1 Watchdog Logic Table 2 and Figure 11 show the watchdog logic. figure 12 shows the logic implementation Watchdog WD1, Clock WD2 Time between Edges SILA ok ok < 3 * tCLK VR EN RES1/2 Error Flag = SIA = not SIA = not MRA L Z H L ok L Z Z Z L H L > 15 * tCLK ok L Z Z Z L H L > 120 * tCLK ok L Z Z Z L H H H H ok Table 2 NSILA MR error L Z Z Z L Watchdog and Clock Supervision Truth Table The table assumes that no other error is detected, especially no undervoltage or overvoltage at the supply and regulator output. Z: High impedance V1.2 Data Sheet 28 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics t1 t2 t3 t4 t5 WD1 t WD2 t EN t VR t MR t SILA t NSILA t Figure 11 Watchdog Violation Reaction t1: t2: No watchdog signals at WD1 or WD2 t3: Watchdog open window time exceeded: but below 120 *tCLK (typ. 120 ms). Error Flag is not set. t4: t5: Watchdog time too short (below closed window time) Normal operation. EN is going high after the first watchdog edges at WD1 and WD2 are detected. Normal operation V1.2 Data Sheet 29 2002-08 TLE 6210 TLE 6211 Block Description and Electrical Characteristics 1 CLK 6 BIT SHIFT REGISTER WD Q0 Q1 Q2 Q3 Q4 Q5 & 1 RESQ & 1 wd-detect AD06/02 Figure 12 Logic Diagram: Detection of Watchdog Edges. The watchog signal is clocked through the shiftregister. The output condition of the edge detection circuit above is true for register state 111000 and 000111. 3 clks after the rising edge or falling edge of WDx the logic below will get a pulse of 1 clk length. overvoltage at UST (active H) CLK J WD1 Counter Q CLK C 120 Set Error register C CLK & 1 K 15 1 1 R 1 =15 sets VR high ohmic; ENQ on CLK WD2 J Q C CLK "1" K Q D 1 Q D C C Q R Q R 1 TLE6210-wd-logic AD 04/02 Undervoltage reset (low active) Figure 13 Block Diagram Watchdog Logic V1.2 Data Sheet 30 2002-08 TLE 6210 TLE 6211 Application Diagram 5 Application Diagram TLE6210/1 UST U Bat UZP UST 5V Linear Regulator USTS U USTS under- and overvoltage reset detection Reset detection UZP UVLO and OVLO detection U Bat Bat RES1 MR to Microcontroller RES2 to Microcontroller EN to Microcontroller SupervisionLogic PGND VR U Bat U PGND Bat WD1 from Microcontroller Window watchdog SILA WD 2 from Microcontroller PGND NSILA SIA from Microcontroller PGND MRA Oscillator Clock supervision UCP Charge Pump PGND from Microcontroller CCP 68nF GND GND Power GND Figure 14 TLE6210-app-diagram AD 11.7.02 Logic GND Application Diagram V1.2 Data Sheet 31 2002-08 TLE 6210 TLE 6211 Package Outlines 6 Package Outlines +0.07 -0.02 5 3 0.25 Heatslug (Mold) 0.95 0.15 0.25 M A 20x 14.2 0.3 20 11 11 1 10 10 0.25 B 20 5.9 0.1 (Metal) 0.4 +0.13 6.3 0.1 3.2 0.1 (Metal) 1.27 15.74 0.1 (Heatslug) B 2.8 1.3 1.2 -0.3 11 0.15 1) 3.5 MAX. 0 +0.1 3.25 0.1 P-DSO-20-12 (Plastic Dual Small Outline Package) Index Marking 1 x 45 15.9 0.15 1) (Mold) 1 Heatslug (Metal) A Does not include plastic or metal protrusion of 0.15 max. per side GPS05791 1) 13.7 -0.2 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device V1.2 Data Sheet 32 Dimensions in mm 2002-08 TLE 6210 TLE 6211 Revision History Version Date Major Changes V0.0 2002-08 Advanced Information Data Sheet TLE 6210, TLE 6211 Device is a replacement of the TLE 5200/TLE 5201 with the following deviations form the specification from 1998-01-21. Devices are only available in the P-DSO-20-12 package or as bare dice The data sheet structure was changed and some chapters where moved. Parameter reference numbers are changed now: TLE 5200/01 TLE 6210/11 * Control input SIA 1.x 4.8.x * Control input MRA 1.x 4.7.x * Enable 2.x 4.5.x * Reset outputs 3.x 4.10.x * SILA/NSILA 4.x 4.8.x * VR 5.x 4.6.x * MR 5.x 4.7.x * Voltage supervision 6.x 4.9.x * Oscillator 7.x 4.2.x * Watchdog 8.x 4.11.x * Charge Pump 9.x 4.3.x * 5 V Regulator 10.x 4.4.x * General information 10.x 4.1.x Absolute Maximum Ratings: Digital I/Os (reference M6, M7, M8) changed to -0.5 to 7 V V0.1 2001-11 Update truth table V0.2 2002-04 increase error flag detection time tFSP from 112 clock cycles to 120 clock cycles (parameter 4.11.8) Add of logic block diagram (figure 12) and watchdog timing diagrams (figure 5 to 10) V1.2 Data Sheet 33 2002-08 TLE 6210 TLE 6211 Revision History Version Date Major Changes V1.0 2002-07 Data sheet Remove pad / chip information from the datasheet ESD value SILA, MR, VR,UZP 4kV Update typ. value 4.3.3 Extend and correct block description at chapters 4.4; 4.6; 4.7; 4.8 Table 1: SILA function at overtemperature changed Table 2: timings as a function of tCLK Figure 11, t3: corect timing Chapter 4.11: Extend description; add figure 12: Detection of watchdog edges Appplciation diagram: replace free wheeling zener diodes at MR and VR relay by normal diodes. V1.1 2002-07 change device suffixes: bare dice: TLE621x C packaged: TLE621x G V1.2 2002-08 Table 1 and text chapter 4.8: correct NSILA at overvoltage Change long term drift 4.4.6 to 10000h Add a more detailed description to figure 12. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing. V1.2 Data Sheet 34 2002-08 TLE 6210 TLE 6211 Edition 2002-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2002. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. V1.2 Data Sheet 35 2002-08