TLE6211G - Infineon Technologies

V1.2 Data Sheet 1 2002-08

ABS System IC

TLE 6210

TLE 6211

-DSO-20-10, -12, -16

1Overview

1.1 Features

• 5 V, 800 mA linear regulator

• Undervoltage/overvoltage reset

• Undervoltage and overvoltage logout

• Digital watchdog supervision for 2 Microcontrollers

• (motor) relay driver

• (valve) relay driver

• Inverted or non inverted lamp relay driver

• Enable output

• Overtemperature and overcurrent protection

1.2 Functional Description

The TLE 6210 and TL E 6211 are in tegrated circui t con sis ting of a 5 V vo ltag e regu lato r

with 800 mA c urrent capabi lity, differen t relay driver ou tputs and su pervision lo gic. The

supervision logic watches the input voltage and the regulator output voltage both for

over-voltage and under-voltage. In addition two window watchdogs supervise the correct

operation of 2 independent watchdog signals, e.g. from two Microcontrollers.

The TLE 6210 and TLE 6211 are designe d espe cia lly for the severe con diti ons of ABS/

ASR applications in an automotive environment.

Type Ordering code Package/Shipment

TLE 6210 C on request Bare dice

TLE 6210 G on request P-DSO-20-12, Tape and

Reel

TLE 6211 G on request P-DSO-20-12, Tape and

Reel

TLE 6210

TLE 6211

Overview

V1.2 Data Sheet 2 2002-08

1.3 Block Diagram

Figure 1 Block Diagram

Linear Regulator

Reset detection

UZP UVLO

and OVLO

detection

USTS

under- and

overvoltage

reset

detection

TLE6210-block

AD 20.09.01

UST

USTS

UZP

GND

RES1

RES2

PGND

Window

watchdog

SIA

MRA

WD1

WD 2

Oscillator

Clock

super-

vision

Charge

Pump

UCP

SupervisionLogic

PGND

SILA

PGND

NSILA

PGND

TLE 6210

TLE 6211

Pin / Pad Configuration

V1.2 Data Sheet 3 2002-08

2 Pin / Pad Configuration

Figure 2 Pin Configuration P-DSO-20-12

Figure 3 Chip-Layout

110

1120

Layout

NSILA

GNDP

SILA

GNDP

GND

RES2

RES1

UCP

UZP

SIA

WD2

MRA

WD1

GND

USTS

UST

TLE 6210

TLE 6211

Pin / Pad Configuration

V1.2 Data Sheet 4 2002-08

Pin / Pad Definitions and Functions

Pin Number Symbol

Pad Name

Function

TLE 6210 G TLE 6211G

11GNDPower GN D connection

22N.C.Not Connected

33UZP Supply Voltage; reverse protection diode is

required

44UCP Charge Pump Capacitor pin; An external

capacitor is the energy storage for the charge

pump

55RES1Reset Output 1; open collector output with

integrated pull-up res istor. A high indicates normal

operation; function identical to RES2

66ENEnable Output; open collector; low indicates an

error condition

77RES2Reset Output 2; open collector output with

integrated pull-up res istor. A high indicates normal

operation; function identical to RES1

88VRValve Relay Output; open drain output

9–SILALamp Output; open drain output;

For TLE 6210 CW only

–9NSILAInverted Lamp Output; open drain output;

For TLE 6211 CW only

10 10 GND Power Ground connection

11 11 GND Power Ground connection

12 12 MR Motor Relay Output; open drain output

13 13 SIA Lamp Control Signal Input; controls SILA/NSILA;

a logic high switches SILA off and NSILA on

14 14 WD2 Watchdog Input 2

15 15 MRA Motor Relay Control Input;

A logic High switches MR on

16 16 WD1 Watchdog Input 1

17 17 GND Logic Ground

18 18 USTS Sense input for UST supervision

19 19 UST 5 V Linear Regulator Output

20 20 GND Ground Connection

Backside metallization GND The lead frame connects the pins 1, 10, 11 and 20

to the backside metallization.

TLE 6210

TLE 6211

Electrical Characteristics

V1.2 Data Sheet 5 2002-08

3 Electrical Characteristics

3.1 Absolute Maximum Ratings

-40 °C £ Tj £ 150 °C

# Parameter Symbol Limit Values Unit Conditions

min. max.

M1 Supply Voltage UZP 020V–

026.5V

0 < tp £ 5 min.;

-40 °C £ 80 °C

035V0 < tp £ 200 ms;

f < 0.067 Hz;

n £ 360 cycles

035V0 < tp £ 50 ms;

0 < fp £ 1 Hz;

n £ 36000 cycles

-1.5 – V tp = 2 s

M2 Supply Voltage variation dUZP/dt–|10|V/ms–

M3 Output voltage at VR, MR UVR, UMR – 60 V VR, MR-DMOS off

M4 Output voltage at SILA USILA – 42 V SILA-DMOS off

M5 Output voltage at NSILA UNSILA – 42 V NSILA-DMOS off

M6 Output voltage at

RES1, RES2 URES1

URES2

-0.5 7 V –

M7 Output voltage at EN UEN -0.5 7 V –

M8 Input Voltage at

WD1, WD2, MRA, SIA UWD1, UWD2

UMRA, USIA

-0.5 7 V –

M9 Voltage UCP UCP -0.5 20 V –

M10 Storage Temperature Tstg -55 150 °C–

M11 Junction Temperature Tj-40 150

175 °C

°C

continuos

short term (< 50 h

ov er li feti me)

TLE 6210

TLE 6211

Electrical Characteristics

V1.2 Data Sheet 6 2002-08

Note: Stresses above the ones listed here may cause permanent damage to the

device. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

M12 ESD –

±4000

±2000

–

according to

EIA/JESD 22-A

114B

UZP, MR, EN,

VR, SILA,

all other pins

M13 Life Time tb10000 – h ambient

temperature

range:

-40°C 2%

-20°C 10%

25°C 24%

60°C 34%

80°C 24%

100°C 5%

>120°C 1%

3.1 Absolute Maximum Ratings (cont’d)

-40 °C £ Tj £ 150 °C

# Parameter Symbol Limit Values Unit Conditions

min. max.

TLE 6210

TLE 6211

Electrical Characteristics

V1.2 Data Sheet 7 2002-08

Within the functional range the device works according to the functional description.

However parameters may exceed the values given in the Characteristics.

3.2 Functional Range

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

F1 Supply voltage UZP 4.5 14.0 18 V –

– – 26.5 V t < 5 min.

––4.5V

UST £ 0.3 V;

Reset = Low;

Enable = Low;

VR and MR off

F2 Input

capacitor CUZP 0.33 3.3 – mFTU = 20 °C

UN = 63 V

Typ. = MKT

F4 Case Temperature TC-40 – 125 °CP-DSO-20-12

Junction

Temperature Tj-40

––

–150

175 °C

°C

life time

short time1)

F5 Thermal resistance

junction-ambient Rthja – 40 – K/W P-DSO-20-12

minimum footprint

F6 Thermal resistance

junction-case Rthjc – – 2.4 K/W P-DSO-20-12

1) Param et er m ay deviate in the tem perature range Tj = 150 °C … 175 °C

Total operation time m ax . 50 h for temperature range Tj > 150 °C

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 8 2002-08

4 Block Description and Electrical Characteristics

4.1 General

4.2 Oscillator

A 16 kHz oscillator is used as time base for the 1 kHz clock. An independent clock

supervision circuit supervises the oscillator. If the oscillator clock is missing the error flag

is set.

Characteristics

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not o therw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.1.1 Power consumption

regulator IUZP –715mAUZP = 16 V,

IUST = 800 mA,

VR on, SILA on,

EN, RES1, RES2 = High

4.1.2 Overtemperature

protecti on thres hold Tab 150 – – °CTj > Tab

Characteristics Internal Oscillator

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not o therw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.2.1 Frequency fOSZ 14.4

13.6 16

–17.6

18.4 kHz

kHZ UZP ³ 6 V

4.7 V £ UZP < 6 V

4.2.2 Clock supervision tCLUE – 120 – ms error if

tLow or tHigh > tCLUE

4.2.3 Logic time base tCLK 0.9 1 1.1 ms Period

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 9 2002-08

4.3 Charge Pump

The integrated charge pump requires an external capacitor at pin UCP. The charge pump

voltage is typically 15 V. It is internally used for the voltage regulator only. It is only

intended for internal function and may not be used for any external loads. The output

voltage is short circuit protected against the supply voltage.

Characteristics Charge Pump

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not o therw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.3.1 Power up time tCP –10– msUZP = 6 V; CCP = 68 nF;

Load capacitor to

U=0.9´UCPmax

4.3.2 Charge pump voltage UCP – 15 22 V Regulator on

4.3.3 Frequency fCP 1.4 3.2 – MHz –

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 10 2002-08

4.4 Voltage Regulator

The 5 V low drop linear regulator can supply up to 800 mA current. The regulator

requires an output capacitor. The linear regulator is equipped with overcurrent protection

and its own overtemperature protection. The linear element consists of 2 anti-serial

DMOS transistors. In case of low input supply voltage this avoids discharging of the

output capacitor.

The output voltage UST is su perv ise d fo r ov er- an d undervol tage . UST ou tput has to be

connected externally to the sense input USTS. If over- or undervoltage condition is

detected the Re set outputs RES1 and RES2 are logical low. For a detailed des cription

of the reset logic please see Chapter 4.9.

Characteristics Voltage Regulator

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not o therw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.4.1 Nominal output

voltage UST

4.95

4.925 5.00

5.00 5.05

5.075 V

UZP = 14 V; IST = 400 mA;

Output capacitor as defined in

4.4.11;

on wafer level Tj = 25 °C

P-DSO-20-12

4.4.2 UST load current IST – – 800 mA –

4.4.3 Line variation DUST ––|50|mV Tj = 25 °C; 6.0 V £ UZP £ 18 V;

IST = 600 mA; capacitor as

defined in 4.4.11;

dUZ/dt < 1 V/ms

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 11 2002-08

4.4.4 Load variation DUST ––|50|mV Tj = 25 °C; UZP = 14 V;

0 mA £ IST £ 800 mA;

capacitor as defined in 4.4.11;

dIST/dt £ 1 mA/ms

4.4.5 Temperature

variation DUST –|50||100|mV UZP = 14 V; IST =ISTmax;

-40 °C £ Tj £ 150 °C;

capacitor as defined in 4.4.11;

for die mounted in a hybrid:

dTU/dt £ 10 K/s

for P-DSO-20-12:

dTG/dt £ 5 K/min.

4.4.6 Long time drift DUST

––|50|mV

UZP £ UZPmax.;

0 mA £ IST £ ISTmax.;

-40 °C £ Tj £ 150 °C;

tb = 10000 h, see conditions

M13.

4.4.7 Overall output

voltage tolerance UST 4.75 5.00 5.25 V all parameters from 4.4.1 to

4.4.6

4.4.8 Power Supply

ripple rejection DUSTss ––|25|mV 0 Hz £ fUST £ 10 kHz;

capacitor as defined in 4.4.11;

7 V £ UZP £ 24 V

4.4.9 Series Resistor RDSon –

––

–1.7

2.7 W

Tj = 25 °C

Tj = 150 °C

UCP > 15 V; UZP = 6 V;

IST = 800 mA

4.4.10 Maximum output

current (output

shorted)

IK0.8 – 1.6 A UCP > 15 V; UST = 0 V;

4.5 V £ UZP £ 18 V

4.4.11 Load capacitor at

output UST

CUST 3.3 – 150 mFTU = 20 °C; UN = 25 V;

Type ETQW Roederstein

Z –4–Wf = 100 kHz; TU = 20 °C

4.4.12 UST off voltage USTRest – – 400 mV IST = 0 mA

4.4.13 Clamping

voltage UZST 5.5 – 7 V clamping voltage at

I = 100 mA

Characteristics Voltage Regulator (cont’d)

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 12 2002-08

4.5 Enable-Output EN

The open collector enable output EN informs the system about any error condition. Any

error except a detected supply under-voltage will set the EN output Low. Of cause for

long under-vol tage at the su pply line, soo n the UST output capa citor w ill b e dis charged

and this will cause UST und er-voltag e and the refore EN Low. The time dep ends on the

load and the output capacitor. The EN is an open collector output. It is short circuit

protected to UST.

After power up when the first watchdog edge s at WD1 a WD2 are detected the Enable

output is switched into High state.

Characteristics EN Output

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Symbol Limit Values Unit Conditions

min. typ. max.

4.5.1 Output Low voltage UL–

––

–0.4

0.2 V

VIL £ 10 mA

IL £ 1 mA

4.5.2 Reverse curren t IR––5mAUEN = 5 V

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 13 2002-08

Power Driver

The TLE 6210/TLE 6211 includes 3 open drain outputs for loads up to 0.5 A: The two

drivers VR and MR are intended for (valve and motor) relays, while the SILA/NSILA

output is designed for a lamp.

In the TLE 6210 GW the SILA output is available. The output goes low if the supply

voltage UZP is no longer available – the DMOS is switched on automatically. In the

TLE 6211 GW the NSILA has the inverted polarity related to SILA. In bare dice both

outputs SILA and NSILA can be used.

4.6 Valve Relay Output VR

The valve relay output VR is switched On af ter the power up reset and valid w atchdog

signals. Th e driver has an ope n drain configurati on and can supp ly up to 500 mA. The

output is protected again st overtemperatu re a nd overcurren t. Th e o utpu t i s s hort circuit

protected to UZ. The output sta ge is equipped with its ow n overtem perature pro tection.

In case of overvoltage at th e s upply UZP the out put is s w itch ed o ff. Howev er th e ou tput

is not protected against overvoltages caused by switching inductive loads. Therefore

externally a free wheeling diode is required as shown in the application diagram.

The valve relay output VR is controlled by the internal supervision logic. If any watchdog

errors or supply over-volt age is detected or th e 5 V regulator is out of range , the VR is

switched off (please see also Table 1 on Page 19 and Table 2 on Page 28).

Characteristics Relay Driver Output VR

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.6.1 Saturation Voltage UDS ––1.2VRlast ³ 35 W; IL £ 0.5 A;

6 V £ UZP £ 16 V

4.6.2 On state resistance RDSon ––2.4WTj = 150 °C; IL = 0.5 A;

UZP = 6 V

4.6.3 Overload detection

current IK500 – – mA –

4.6.4 Output leak age

current IR–

––

–0.5

2mA

mA UA £ 16 V

16 V < UA £ 60 V

4.6.5 Overtemperature

shutdown thres hol d TK150 – – °C–

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 14 2002-08

4.7 Motor Relay Driver

The motor relay driver MR is controlled by the MRA input signal and the internal control

logic. A logic High at the MRA input switches the MR low side switch on, a logic Low

signal s w itch es it off. Howeve r t he supervision logic o verru les t he MRA input condition.

Please see also Table 1 on Page 19 and Table 2 on Page 28.

The output is an open collector output and can sink up to 500 mA. It is protected against

overtemperature and overcurrent and short circuit prove to UZ. Even the output is

switched off by the supervision logic at UZP overvoltage externally a free wheeling diode

is required to protect the output against switching off inductive loads.

Characteristics Relay Driver Output MR

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.7.1 Saturation Voltage UDS ––1.2VRlast ³ 35 W; IL £ 0.5 A;

6 V £ UZP £ 16 V

4.7.2 On state resistance RDSon ––2.4WTj = 150 °C; IL = 0.5 A;

UZP = 6 V

4.7.3 Overload detection

current IK500 – – mA –

4.7.4 Output leak age

current IR–

––

–0.5

2mA

mA UA £ 16 V

16 V < UA £ 60 V

4.7.5 Overtemperature

shutdown thres hol d TK150 – – °C–

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 15 2002-08

4.7.1 Control Input MRA

The logic inputs MRA expect TTL-type signals from a m-controller with 5 V I/Os. An

integrated pull-up resistor ensures that an open input is read High.

Characteristics Control Inputs MRA

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.7.6 Internal pull-up

resistor to UST

RWD 10 20 40 kW0 V £ UE £ UST + 0.3 V

4.7.7 Input vol tage Low UL-0.3 – 1.0 V –

4.7.8 Input vol tage High UH2.0 – UST

+ 1.0 V–

4.7.9 Input current IH––|5|mAUE = UST

––1.0mAUST < UE £ UST + 1 V

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 16 2002-08

4.8 Error Lamp Output SILA and Lamp Relay Output NSILA

The SILA output is a 300 mA open collector output. It is available in the TLE 6210 G.

SILA is a self-on output: It is switched on if the supply voltage is missing. The

TLE 6211 G is equipped with the logically inverted NSILA output. NSILA is a 30 mA open

collector output. It is intended to drive the lamp relay. In the dice version TLE 6211 C

both outputs can be used.

Both SILA and NSILA are intended to control a warning lamp . The output is controlled

by the internal supervision logic and control signal at the SIA pin.

A logic High at the SIA input switches SILA off and NSILA on.

The supervision logic will switch on SILA if a watchdog timing violation is detected or the

output voltage UST is out of range. Table 1 on Page 19 and Table 2 on Page 28 give an

overview on the different errors.

The SILA output is equipped with its own overtemperature protection.

Characteristics Lamp Driver Output SILA

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise spec ified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.8.1 Saturation voltage USILA –

––

–2.5

2.5 VI = 300 mA; UZP ³ 6 V

I = 300 mA; UZP = 0 V

4.8.2 Overload detection

current IK300––mA–

4.8.3 Output leakage

current IR–

––

–0.1

4mA

mA USILA £ 16 V

16 V < USILA < 42 V

4.8.4 Threshold voltage for

automatic ON UZP 1–4.7VUSILA £ 2.5 V;

I = 300 mA

4.8.5 Overtemperature

shutdown threshold TK150 – – °CUZP ³ 6 V

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 17 2002-08

4.8.1 Control Input SIA

The logic inputs SIA expect TTL-type signals from a m-controller with 5 V I/Os. An

integrated pull-up resistor ensures that an open input is read High.

Characteristics Lamp-Relay Driver Output NSILA

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.8.6 On state resistance RDSon ––33WTj = 150 °C; I = 30 mA;

UZP ³ 7 V

4.8.7 Overload detection

current IK30––mA–

4.8.8 Output leakage

current IR––10mAUNSILA £ 42 V

Characteristics Control Inputs SIA

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.8.9 Internal pull-up

resistor to UST

RWD 10 20 40 kW0 V £ UE £ UST + 0.3 V

4.8.10 Input volt age Low UL-0.3 – 1.0 V –

4.8.11 Input voltage High UH2.0 – UST

+ 1.0 V–

4.8.12 I nput c u rrent IH––|5|mAUE = UST

––1.0mAUST < UE £ UST + 1 V

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 18 2002-08

Supervision

The TLE 6210 and TL E 6211 are equipp ed with a c omplex supervis ion logi c. The input

voltage and the regulator output voltage is supervised. In addition two m-controller are

supervised by independent watchdog circuits.

4.9 O vervoltage an d Undervolt age

Both the supply voltage UZP and the output voltage UST are supervised for over- and

undervoltage.

In case any undervoltag e or overvolta ge conditio n at UST or UZP is detected, the reset

outputs RES1 a nd RES2 are switched t o low st ate. RES1 and R ES2 are not co ntrolled

by the watchdog logic.

To supervise the output voltage UST an independent bandgap from the reference

bandgap is used.

The reset outputs RES1 and RES2 are together controlled by the UST reset logic and

the supply undervoltage lockout (UVLO) and overvoltage lockout (OVLO).

A logic H igh at the RES1 a nd RES2 indic ates normal operat ion. The ou tputs are open

collector type outputs with integrated pull-up resistors to UST. Even when the UST

voltage drops, the reset outputs RES1 and RES2 remain low (< 0.4 V).

Both undervoltag e and overvoltage dete ction of UST and UZP use a vo ltage hys teresis

to avoid any reset toggling.

Undervoltage and Overvoltage Detection UST

The UST output voltage has to be externally connected to the USTS sense input.

To be able to detect als o wrong output vo ltages cause s by a malfuncti on of the related

bandgap reference for supervision an independent bandgap is used.

As soon as any reset condition is detected the RES1 and RES2 go low.

4.9.1 Undervoltage Lockout (UVLO) and Overvoltage Lockout (OVLO)

The supply voltage UZP is supervised as well. If the voltage rises above the upper

threshold value of 19.5 V reset is asserted. When an undervoltage occurs, after some

time the ou tput vol tage will drop bel ow the rese t thre shold and a res et is a sserted. The

undervoltage lockout is only valid during power up.

Both the OVLO and the UVLO threshold use a hysteresis to avoid reset glitches. In

addition the OVLO is digitally filtered. Overvoltage below 2 to 3 clock cycles (equals

typical 2 µs or 3 µs) are neglected to avoid resetting the system when any inductive load

is switched off.

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 19 2002-08

When the unde rvoltage condition at UST or UZP is no longer detected a reset reaction

time of typical 52 ms (52 clock cycles) is started. After this time the reset signal is set

high.

Z: high impedance

* In the application the voltage is undefined as regulator is off

Table 1 Truth Table Overvoltage and Undervoltage Supervision

The table assumes that no other error is detected, especially no watchdog failure and no

clock failure.

Supply

voltage

UZP

Regulator

Voltage

UST

SILA NSILA MR VR EN RES 1

RES 2 Regulator

ok ok = SIA = not SIA = not

MRA LZHON

ok under-

voltage LZ ZZLL ON

normal over-

voltage LZ ZZLHON

under-

voltage under-

voltage LZ ZZZ*L OFF

under-

voltage ok = SIA = not SIA not

MRA LHHON

over-

voltage x = LZ ZZZ*L OFF

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 20 2002-08

4.9.2 Under- and Overvoltage Reset Behavi or

Figure 4

Characteristics Supervision of UZP, UST

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Symbol Limit Values Unit Conditions

min. typ. max.

UZP-Undervoltage

4.9.1 UZP undervoltage

threshold UZPU 5.2 5.3 5.4 V UST off

4.9.2 UZP undervoltage

hysteresis UH20 – 50 mV UZPU(ON) =

UZPU(OFF) + UH1)

UZP-Overvoltage

4.9.3 UZP overvolt age

threshold UZUE 18.75 19.5 20.25 V Outputs NSILA,

VR, MR, UST off

UZP

12V

5.3V

UST

4.6V

ES1

ES2

52ms

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 21 2002-08

4.9.4 UZP overvolt age

hysteresis UH0.5 – 1.0 V UH =

UZUE(on) - UZUE(off)

4.9.5 UZP overvolt age

filter ton 2

1.8 –

–3

3.4 ´ tCLK

ms UZP ³ overvoltage

threshold

toff 2

1.8 –

–3

3.4 ´ tCLK

ms UZP < overvoltage

threshold

UST-Undervoltage

4.9.6 UST undervoltage

threshold USTU 4.5 4.6 4.7 V RES1, RES2 = low

4.9.7 UST undervoltage

hysteresis UH20 – 50 mV USTU(on) =

USTU(off) + UH1)

UST-Overvoltage

4.9.8 UST over vol tage

threshold USTUE 5.3 5.4 5.5 V Error flag is set

4.9.9 UST overvoltage

hysteresis UH20 – 50 mV USTUE(ON) =

USTUE (off) - UH1)

4.9.10 USTS input

current ISTS 0.94 1.5 2.2 mA USTS = 6 V

Reset timing

4.9.11 Reset delay time tRH –

46.35 52

52 –

58.85 ´ tCLK

ms UZP ³ 5.4 V

UST ³ 4.75 V

1) Hyste res is guaranteed by des ign.

Characteristics Supervision of UZP, UST (cont’d)

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Symbol Limit Values Unit Conditions

min. typ. max.

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 22 2002-08

4.10 Reset Outputs RES1, RES2

The two reset outputs RES1 and RES2 are open col lector outputs with integrat ed pull-

up resistor of typical 10 kW to UST. Both outputs are protected against sho rt circuits to

UST.

Characteristics RES1 and RES2

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.10.1 Output low

voltage UL–

––

–0.4

0.4 V

VIL = 0.8 mA; UST = 1.8 V

IL = 2 mA; UST = 4.5 V

1.8 V £ UST £ 4.5 V

4.10.2 Output high

voltage UHUST

- 0.1 –UST VRL ³ 10 MW

4.10.3 Internal pull-up

resistor to UST

RRES 51020kW0 V £ UA £ UST + 0.3 V

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 23 2002-08

4.11 Watchdog

To supervise the operation of 2 m-processors watchdog logic for two input signals is

integrated. The logic expects at each WD1 and WD2 rectangular signals with 10 ms high

and 10 ms low time. Deviations from the expected time are counted as errors and

influence the output signals.

A digital filter suppresses noise or pulses below 3 clock cycles (typ. 3 ms).

The detection ciruit is described in Figure 12.

After power up and 1or 2 valid watchdog edges the WD logic enables the output Drivers.

Figure 5 Enable output EN after correct watchdog signals at WD1 and WD2

are present; WD1 and WD2 start with logic Low

Figure 6 Enable output EN after correct watchdog signals at WD1 and WD2

are present; WD1 and WD2 start with logic High

WD1

WD2

10ms

3* t

CLK

after the 2nd WD-edge (falling edge)

wd-start-up-with Low

AD 04/02

WD1

WD2

3 * t

CLK

after 1st. WD edge

10ms

wd-start-up-with High

AD 04/02

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 24 2002-08

The logic e xpects the time betw een two cl ock edges between 3 and 15 cl ock-cycle s. If

this window is not met, the outputs VR, MR and NSILA are switched off, SILA is switched

on and the enable output goes low.

An internal counter ( seeFigure 12) includes a 4 bit counter. Each time the value 15 is

reached a dominant counter reset signal is generated at the output "=15". This pulse is

generated continuously at

t = (15+3) T1 + n * (16*T1)

after the last valid watchdog pulse was detected.

When internal resets and wa tchdog edges occur at the same time, the inte rnal reset is

dominant.

Figure 7 Missing watchdog signals cause EN low

15* t

CLK

+ Delay =

15* t

CLK

+ 3* t

CLK

10ms

WD1

WD2

Delay (3* t

CLK

)

t > 16 *t

CLK

wd-controls-en-2

AD 04/02

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 25 2002-08

Figure 8 Missing watchdog signals cause EN low

Figure 9 Timing diagram - any watchdog signal missing causes a High signal

at the output "=15" (Counter reset). This signal sets back the logic

15*t

CLK

+ Delay

= 15*t

CLK

+ 3* t

CLK

WD1

WD2

Delay (3* t

CLK

)

t < 15 *t

CLK

Delay (3* t

CLK

)

15*t

CLK

wd-controls-en

AD 03/02

10ms

WD1

WD2

WD Signal not detected

(15+3) * t

CLK

Counter Reset

16* t

CLK

wd-missing

AD 03/02

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 26 2002-08

Any watchdog high or low time above 15 ms influences the enable (EN) and the VR

output.If the time after the last watchdog edge exceeds 120 clock cycles - typical

120 ms- an error flag is set. This flag can only be removed by powering down the IC.

Figure 10 Missing watchdog signals for more than 120 * tCLK (typ. 120ms) sets

the failure register

An integrated pull-up resistor to UST in the WD1 and WD2 inputs ensures to detect a

permanent logic High in case the input is open.

10ms

WD1

WD2

(15+3) * t

CLK

112 * t

CLK

+ Delay = 112 * t

CLK

+ 3 * t

CLK

)

Counter reset

16 * t

CLK

set error flag

set-error-flag

AD 03/02

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 27 2002-08

Characteristics WD1, WD2

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.11.1 Internal pullup

resistor to UST

RWD 10 20 40 kW0 V £ UE £ UST + 0.3 V

4.11.2 Input voltage Low UL-0.3 – 1.0 V –

4.11.3 Input voltage High UH2.0 – UST

+ 1.0 V–

4.11.4 Input current IH––|5|mAUE = UST

––1.0mAUST < UE £ UST + 1 V

Characteristics Watchdog

6 V £ UZP £ 18 V, -40 °C £ Tj £ +150 °C, if not otherw ise specified

# Parameter Sym-

bol Limit Values Unit Conditions

min. typ. max.

4.11.5 Release

reaction time tON 1– 2 ´ tCLK Number of valid Watchdog

input clock edges

4.11.6 Closed

window time tpulse –

2.25

1.8

–

3.3

´ tCLK

The distance between

clock edges is at least tpulse

equals:

periodically

pulse

4.11.7 Open

window time tVR –

13.5

–

17.6

´ tCLK

if the edge distance

Dt > tVR, VR is sw itc hed off

equals

4.11.8 Error flag

detection tFSP –

108

120

–

132

´ tCLK

if Dt > tFSP, the error flag is

set.

equals

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 28 2002-08

4.11.1 Watchdog Log ic

Table 2 and Figure 11 show the watchdog logic. figure 12 shows the logic

implementation

Z: High impedance

Watchdog WD1,

WD2

Time between

Edges

Clock SILA NSILA MR VR EN RES1/2 Error

Flag

ok ok = SIA = not SIA = not

MRA LZH L

< 3 * tCLK ok L Z Z Z L H L

> 15 * tCLK ok L Z Z Z L H L

> 120 * tCLK ok L Z Z Z L H H

ok error L Z Z Z L H H

Table 2 Watchdog and Clock Supervision Truth Table

The table assumes that no other error is detected, especially no undervoltage or

overvoltage at the supply and regulator output.

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 29 2002-08

Figure 11 Watchdog Violation Reaction

t1: No watchdog signals at WD1 or WD2

t2: Normal operation. EN is going high after the first watchdog edges at WD1 and WD2

are detected.

t3: Watchdog open window time exceeded: but below 120 *tCLK (typ. 120 ms).

Error Flag is not set.

t4: Watchdog time too short (below closed window time)

t5: Normal operation

WD1

WD2

SILA

t 1 t 2 t 3 t 4 t 5

TLE 6210

TLE 6211

Block Description and Electrical Characteristics

V1.2 Data Sheet 30 2002-08

Figure 12 Logi c Diagram: Detection of Watchdog Edges.

The watchog signal is clocked through the shiftregister. The output condition of the edge

detection circuit above is true for register state 111000 and 000111. 3 clks after the rising

edge or falling edge of WDx the logic below will get a pulse of 1 clk length.

Figure 13 Block Diagram Watchdog Logic

6 BIT

SHIFT

RESQ

CLK

wd-detect

AD06/02

CLK

WD1

WD2

CLK

Counter

overvoltage at UST

(active H)

Set Error register

1 sets VR high ohmic;

ENQ on

120

=15

“ 1 “

Undervoltage

reset (low active)

³15

CLK

TLE6210-wd-logic

AD 04/02

TLE 6210

TLE 6211

Application Diagram

V1.2 Data Sheet 31 2002-08

5 Application Diagram

Figure 14 Application Diagram

Linear Regulator

Reset detection

UZP UVLO

and OVLO

detection

USTS

under- and

overvoltage

reset

detection

TLE6210-app-diagram

AD 11.7.02

UST

USTS

UZP

GND

RES1

RES2

PGND

Window

watchdog

SIA

MRA

WD1

WD 2

Oscillator

Clock

super-

vision

Charge

Pump

UCP

SupervisionLogic

GND

68nF

Logic

GND

Power

GND

Bat

UST

from Microcontroller

Microcontroller

PGND

SILA

PGND

NSILA

PGND

Bat

TLE6210/1

TLE 6210

TLE 6211

Package Outlines

V1.2 Data Sheet 32 2002-08

6 Package Outlines

Heatslug

110110

ndex Marking

Does not include plastic or metal protrusion of 0.15 max. per side

1 x 45˚

(Mold)

15.9

±0.15

-0.2

(Metal)

13.7

+0.1

+0.13

0.4

20 11

0.25

1.27

1.2

-0.3

(Heatslug)

15.74

±0.1

(Metal)

0.25

Heatslug

(Mold)

20x

3.2

14.2

±0.3

±0.1

0.95

3.25

3.5 MAX.

0.1

1.3

±0.1

-0.02

+0.07

6.3

0.25

±0.15

2.8

(Metal)

5.9

±0.1

±0.15

5˚

±3˚

P-DSO-20-12

(Plastic Dual Small Outline Package)

GPS05791

orts of Packing

ackage outlines for tubes, trays etc. are contained in our

ata Book “Package Information”. Dimensions in mm

MD = Surface Mounted Device

TLE 6210

TLE 6211

Revision History

V1.2 Data Sheet 33 2002-08

Version Date Major Changes

V0.0 2002-08 Advanced Information Data Sheet TLE 6210, TLE 6211

Device is a replacement of the TLE 5200/TLE 5201 with the

following deviations form the specification from 1998-01-21.

Devices are only available in the P-DSO-20-12 package or as bare

dice

The data sheet structure was changed and some chapters where

moved. Parameter reference numbers are changed now:

TLE 5200/01 TLE 6210/11

• Control input SIA 1.x 4.8.x

• Control input MRA 1.x 4.7.x

• Enable 2.x 4.5.x

• Reset outputs 3.x 4.10.x

• SILA/NSILA 4.x 4.8.x

• VR 5.x 4.6.x

• MR 5.x 4.7.x

• Voltage supervision 6.x 4.9.x

• Oscillator 7.x 4.2.x

• Watchdog 8.x 4.11.x

• Charge Pump 9.x 4.3.x

• 5 V Regula tor 10.x 4.4.x

• General information 10.x 4.1.x

Absolute Maximum Ratings:

Digital I/Os (reference M6, M7, M8) changed to -0.5 to 7 V

V0.1 2001-11 U pd ate truth tabl e

V0.2 2002-04 increase error flag detection time tFSP from 112 clock cycles to 120

clock cycles (parameter 4.11.8)

Add of logic block diagram (figure 12) and watchdog timing

diagrams (figure 5 to 10)

TLE 6210

TLE 6211

Revision History

V1.2 Data Sheet 34 2002-08

Integrated protection functions are designed to prevent IC destruction under fault

conditions described in the data sheet. Fault conditions are considered as “outside”

normal operati ng range . Protectio n functi ons are n ot designed for contin uous rep etit ive

operation.

Characteristics show the deviation of parameter at the given supply voltage and junction

temperature. Typical values show the typical parameters expected from manufacturing.

V1.0 2002-07 Data sheet

Remove pad / chip information from the datasheet

ESD value SILA, MR, VR,UZP 4kV

Update typ. value 4.3.3

Extend and correct block description at chapters 4.4; 4.6; 4.7; 4.8

Table 1: SILA function at overtemperature changed

Table 2: timings as a function of tCLK

Figure 11, t3: corect timing

Chapter 4.11: Extend description; add figure 12: Detection of

watchdog edges

Appplciation diagram: replace free wheeling zener diodes at MR

and VR relay by normal diodes.

V1.1 2002-07 change device suffixes:

bare dic e: TLE621x C

packaged: TLE621x G

V1.2 2002-08 Table 1 and text chapter 4.8: correct NSILA at overvoltage

Change long term drift 4.4.6 to 10000h

Add a more detailed description to figure 12.

Version Date Major Changes

Edition 2002-08

Published by Infineon Technologies AG,

St.-Marti n -Str asse 53,

D-81541 München, Germany

All Rights R eserved.

Attentio n pl ease!

The informat ion herein is given to descr ibe certain c om ponents and sh all not be considered as warranted

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infr ingement, reg arding

circuits, descriptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For furth er infor m at ion on technology, deliver y te rms and c onditions and prices plea s e co nt ac t your neares t

Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.

Warnings

Due to technic al requirement s co mp onents may contain dange rous substan ce s. For information on the types in

question please contac t your neares t Infi neon Technolo gies Of f i ce.

Infineon Technologies Components may only be used in life-support devices or systems with the e xpress written

approval of Infineon Technologies, if a f ailure of such components can reasonably be expected to cause the failure

of that l i fe-support devi ce o r system, or to a ffect the sa fety or ef fectiveness of that d evice or system. Life support

devices or systems are intended to be implante d in the human body, or to support and/or main ta in and susta i n

and/or protect human life . If they fail, it is reasonable to assume that the health of the user or other persons ma y

be endangered.

TLE 6210

TLE 6211

V1.2 Data Sheet 35 2002-08