G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Features : Description : The GLT4160N04 is a high-performance CMOS dynamic random access memory containing 16,777,216 bits organized in a x4 configuration. The GLT4160N04 offers page cycle access with Extended Data Output. The GLT4160N04 has 11 row- and 11 column-addresses, and accepts 2048-cycle refresh in 32 ms. The GLT4160N04 provides EDO PAGE MODE operation which allows for fast data access within a row-address defined boundary, up to 2048 x 4 bits with cycle times as short as 45ns. 4,194,304 words by 4 bits organization. Fast access time and cycle time Low power dissipation. Read-Modify-Write, RAS -Only Refresh, CAS -Before- RAS Refresh, Hidden Refresh. 2,048 refresh cycles per 32ms. Available in 300 mil 26(24) SOJ and TSOPII. 2.0V0.2V Vcc Power Supply voltage. All inputs and Outputs are LVTTL compatible. Extended Data-Out (EDO) Page access cycle. Self-refresh Capability.(S-Version). HIGH PERFORMANCE 100 Max. RAS Access Time, (tRAC) 100 ns Max. Column Address Access Time, (tAA) 50 ns Min. Extended Data Out Page Mode Cycle Time, (tPC) 45 ns Min. Read/Write Cycle Time, (tRC) 190 ns Max. CAS Access Time (tCAC) 25 ns G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 -1- G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Pin Configuration : GLT4160N04 300mil 26(24) TSOPII GLT4160N04 300mil 26(24) SOJ Vcc DQ0 DQ1 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 VSS DQ3 DQ2 CAS OE A9 Vcc DQ0 DQ1 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 VSS DQ3 DQ2 CAS OE A9 A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 Pin Descriptions: Name A0 - A10 Function RAS Address Inputs Row Address Strobe CAS Column Address Strobe WE Write Enable OE Output Enable DQ0 - DQ3 VCC VSS NC Data Inputs / Outputs +2V Power Supply Ground No Connection G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 -2- A6 A5 A4 VSS G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Absolute Maximum Ratings* Capacitance* TA=25C, VCC=2V0.2V, VSS=0V Operating Temperature, TA (ambient) Symbol Parameter .................................................0C to +70C CIN1 Address Input For Extended Temperature.................-20C to 85C CIN2 RAS, CAS, WE, OE Storage Temperature(plastic)............-55C to +150C Voltage Relative to VSS........................-0.5V to + 3.5V COUT Data Input/Output Short Circuit Output Current...............................20mA Power Dissipation...............................................1.0W *Note: Operation above Absolute Maximum Ratings can aversely affect device reliability. Max. Unit 5 pF 7 pF 7 pF *Note: Capacitance is sampled and not 100% tested Electrical Specifications l l All voltages are referenced to GND. After power up, wait more than 200s and then, execute eight CAS -before- RAS or RAS -only refresh cycles as dummy cycles to initialize internal circuit. Block Diagram : WE CAS 4 DATA-IN BUFFER DATA-OUT BUFFER NO.2 CLOCK GENERATOR DQ0 DQ1 4 DQ2 DQ3 4 OE RAS COLUMNADDRESS BUFFER(11) COLUMN DECODER 11 2048 REFRESH CONTROLLER REFRESH COUNTER 11 ROW ADDRESS BUFFERS(11) NO.1 CLOCK GENERATOR 4 SENSE AMPLIFIERS I/O GATING 2048 11 ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11 2048 2048 x 1024 x 4 MEMORY ARRAY VDD VSS G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 -3- G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Truth Table: Function ADDRESS tR tC DATA-IN/OUT DQ1-DQ4 RAS CAS WE OE Standby H HX X X X X High-Z READ L L H L ROW COL Data-Out EARLY WRITE L L L X ROW COL Data-In READ WRITE L L HL LH ROW COL Data-Out,Data-In EDO-PAGE-MODE 1st Cycle L HL H L ROW COL Data-Out READ 2nd cycle L HL H L n/a COL Data-Out EDO-PAGE-MODE 1st Cycle L HL L X ROW COL Data-In EARLY-WRITE 2nd cycle L HL L X n/a COL Data-In EDO-PAGE-MODE 1st Cycle L HL HL LH ROW COL Data-Out,Data-In READ-WRITE 2nd cycle L HL HL LH n/a COL Data-Out,Data-In L H X X ROW n/a High-Z LHL L H L ROW COL Data-Out WRITE LHL L L X ROW COL Data-In RAS -ONLY REFRESH HIDDEN REFRESH READ CBR REFRESH HL L H X X X High-Z SELF REFRESH HL L H X X X High-Z G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 -4- G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) DC and Operating Characteristics (1-2) TA = 0C to 70C, -20C to 85C VCC=2V0.2V, VSS=0V, unless otherwise specified. Sym. ILI ILO ICC1 ICC2 ICC3 Parameter Test Conditions Input Leakage Current (any input pin) 0V VIN VCC+0.3V (All other pins not under test=0V) 0V Vout VCC Output is disabled (Hiz) tRC = tRC (min.) Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE Standby Current, (TTL) Refresh Current, RAS -Only ICC4 Operating Current, EDO Page Mode ICC5 Refresh Current, ICC6 CAS Before RAS Standby Current, (CMOS) Access Time Min. -5 Typ Max. +5 A -5 tRAC = 100ns +5 Self refresh Current VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A 40 1,2 mA RAS , CAS at VIH other inputs VSS 1 RAS cycling, CAS at VIH tRC = tRC (min.) RAS at VIL, CAS address cycling:tPC=tPC(min.) RAS , CAS address cycling: tRC=tRC (min.) tRAC = 100ns mA 40 2 mA tRAC = 100ns 40 1,2 mA tRAC = 100ns RAS VCC-0.2V, 40 mA 1 200 A 1 200 A +0.6 VCC+0.2 0.6 V V V V CAS VCC-0.2V, All other inputs VSS ICC7 Unit Notes RAS = CAS =0.2V, WE = OE = A0~A10=VCC0.2V or 0.2V DQ0~DQ3=VCC-0.2V,0.2V or Open -0.2 1.6 IOL = 2mA IOH = -2mA 1.6 3 4 Notes: 1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and EDO Fast Page Mode. 3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -0.9V for a period not to exceed 10ns. All AC parameters are measured with VIL(min.)VSS and VIH(max.)VCC. 4. Specified VIH(max.) is steady state operation . During transitions VIH(max.) may overshoot to VCC+0.9V for a period not to exceed 10ns. All AC parameters are measured with VIL(min.) VSS and VIH(max.) VCC . G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 -5- G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) AC Characteristics TA = 0C to 70C , -20C to 85C VCC = 2 V 0.2V, VIH/VIL = 1.7/0.4 V, VOH/VOL = 1.4/0.6V An initial pause of 200 s and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up. 100 Parameter Symbol Min. Read or Write Cycle Time Max. Unit Notes tRC 190 ns tRWC 245 ns RAS Precharge Time tRP 80 ns RAS Pulse Width tRAS 100 Access Time from RAS Read Modify Write Cycle Time Access Time from CAS Access Time from Column Address 10k ns tRAC 100 ns 1,2,3 tCAC 25 ns 1,5,10 tAA 50 ns 1,5,6 CAS to Output Low-Z tCLZ 5 CAS to Output High-Z tCEZ 5 RAS Hold Time tRSH 25 ns CAS Hold Time tCSH 100 ns CAS Pulse Width tCAS 25 10k ns RAS to CAS Delay Time tRCD 25 75 ns RAS to Column Address Delay Time tRAD 20 50 ns tCRP 10 ns tASR 0 ns Row Address Hold Time tRAH 15 ns Column Address Set-Up Time tASC 0 ns Column Address Hold Time tCAH 20 ns Column Address to RAS Lead Time tRAL 50 ns CAS to RAS Precharge Time Row Address Set-Up Time ns 25 ns 7 Column Address Hold Time Referenced to RAS Read Command Set-Up Time tAR 75 ns tRCS 0 ns Read Command Hold Time Referenced to CAS tRCH 0 ns 4 Read Command Hold Time Referenced to RAS Write Command Set-Up Time tRRH 0 ns 4 tWCS 0 ns 8,9 Write Command Hold Time tWCH 20 ns Write Command Pulse Width tWP 20 ns Write Command to RAS Lead Time tRWL 25 ns Write Command to CAS Lead Time tCWL 25 ns G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 -6- G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) AC Characteristics 100 Parameter Symbol Min. Max. Unit Notes Data Set-Up Time tDS 0 ns Data Hold Time tDH 20 ns Data Hold Time Referenced to RAS tDHR 75 ns RAS to WE Delay Time tRWD 135 ns CAS to WE Delay Time tCWD 60 ns Column Address to WE Delay Time tAWD 80 ns CAS Precharge to WE Delay tCPWD 85 ns RAS to CAS Precharge Time tRPC 5 ns tCPT 30 ns CAS precharge time ( CAS Before RAS counter test cycle) tCPA Access Time from CAS Precharge EDO Page Mode Cycle Time 55 ns tPC 45 ns tPRWC 120 ns CAS Precharge Time (EDO Page Mode) tCP 10 ns RAS Pulse Width (EDO Page Mode Only) tRASP 100 tRHCP 60 EDO Page Mode Read-Modify-Write Cycle Time RAS Hold Time from CAS precharge 100k ns ns Access Time from OE tOEA 25 OE to Data Delay Time tOED 25 ns OE to Output Low-Z tOLZ 3 ns OE to Output High-Z tOEZ 3 WE to Data Delay tWED 25 ns OE Command Hold Time tOEH 25 ns Data Output Hold after CAS low tDOH 5 ns RAS to Output High-Z tREZ 3 25 ns WE to Output High-Z tWEZ 3 25 ns OE to CAS Hold Time tOCH 5 ns CAS Hold Time to OE tCHO 5 ns OE Precharge Time tOEP 5 ns WE Puts width (EDO mixed read write cycle) tWPE 5 ns CAS Set-Up Time for CAS -before- RAS Cycle tCSR 5 ns 25 ns ns G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 -7- 8 G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) 100 Parameter Symbol Min. CAS Hold Time for CAS -before- RAS Cycle WE to RAS precharge time ( CAS Before Max. Unit Notes tCHR 20 ns tWRP 10 ns tWRH 10 ns tT 2 RAS refresh ) WE to RAS hold time ( CAS Before RAS refresh ) Transition Time 50 ns Refresh Period (2,048 cycles) tREF 32 ms Refresh Period (S-Version) tREFS 128 ms RAS Pulse Width ( CAS Before RAS Self refresh ) RAS precharge Time ( CAS Before RAS Self refresh ) CAS Hold Time ( CAS Before RAS Self refresh ) tRASS 100 s tRPS 180 ns tCHS -50 ns G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 -8- G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) TEST MODE CYCLE 100 Parameter Symbol Min. Random read or write cycle time Max. Unit Notes tRC 195 ns Read-modify-write cycle time tRWC 250 ns Access time from RAS tRAC 90 ns 1,2,3,7 tCAC 30 ns 1,3,7 tAA 55 ns 1,2,7 Access time from CAS Access time from column address RAS pulse width tRAS 105 10k ns CAS pulse width tCAS 30 10k ns RAS hold time tRSH 30 ns CAS hold time tCSH 105 ns Column address to RAS lead time tRAL 55 ns CAS to WE delay time tCWD 65 ns 8 tRWD 140 ns 8 tAWD 85 ns 8 CAS Precharge to WE delay time EDO Page Mode cycle time tCPWD 89 ns 8 tPC 50 ns EDO page mode read-modify-write cycle time tPRWC 125 ns RAS Pulse width (EDO page cycle) tRASP 105 Access time form CAS precharge RAS to WE delay time Column address to WE delay time 100k ns tCPA 60 ns OE access time tOEA 30 ns OE to data delay tOED 30 ns OE command hold time Write command set-up time (Test mode in) tOEH 30 ns tWTS 10 ns Write command hold time (Test mode in) tWTH 10 ns G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 -9- 1 G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Notes: 1. Measure with a load equivalent to one TTL input and 100 pF. 2. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tCAC dominant. 3. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), access time will be controlled by tAA. 4. Either tRRH or tRCH must be satisfied for a Read Cycle. 5. Access time is determined by the longest of tAA, tCAC and tCPA. 6. Assumes that tRAD tRAD (max.). 7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 9. tWCS (min.) must be satisfied in an Early Write Cycle. 10. tDS and tDH are referenced to the latter occurrence of CA S or W E . 11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns. G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 10 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Read Cycle tRC tRAS tRP VIH- RAS VIL- tCSH tCRP tRCD tCRP tRSH VIH- CAS tCAS VIL- tRAD tASR Address VIHVIL- tRAL tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tAR tRCH tRRH tRCS VIH- WE VIL- tCEZ tAA tOEZ VIH- OE tOEA VIL- tCAC tCLZ tRAC DQ VOHDATA-OUT VOLDon't Care Early Write Cycle NOTE : DOUT = OPEN tRC tRP tRAS VIH- RAS VIL- tCSH tCRP CAS tRCD tRSH VIH- tCRP tCAS VIL- VIH- Address VIL- tASR tRAH tRAD tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tAR VIH- tWCS WE tWCR tWCH tWP VIL- VIH- OE VIL- tDHR tDS tDH VIH- DQ VIL- DATA - IN Don't Care G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 11 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) OE Controlled Write Cycle NOTE : DOUT = OPEN tRC RAS tRP tRAS VIHVIL- tCSH tCRP CAS tRCD tCRP tRSH VIH- tCAS VIL- VIH- Address VIL- tRAL tCAH tRAD tASC tASR tRAH ROW ADDRESS COLUMN ADDRESS tCWL tRWL tRCS VIH- WE tWP VIL- VIH- OE tOEH tOED VIL- tDS tDH VIH- DQ DATA - IN VIL- Don't Care Read - Modify - Write Cycle tRC RAS VIHVIL- tCRP CAS tRP tRAS tRCD tCRP tRSH VIH- tCAS VILtCSH tRAD tASR tCAH tASC Address VIHVIL- tRAH ROW ADDR. COLUMN ADDRESS tAWD tRWL tCWL tCWD WE OE VIHtWP VIL- VIH- tOEA VILtCLZ tAA DQ VI/OHVI/OL- tRAC tCAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don't Care G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 12 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) EDO Page Mode Read Cycle NOTE : DOUT = OPEN tRASP tRP VIH- tRHCP RAS VIL- tCSH tCRP tRCD tPC tCAS VIH- tCAS CAS VIL- VIHVIL- tPC tCP tCAS tCAS tCAH tASC tCAH tRAD tRAH tASC tCSR Address tPC tCP tCP tCAH tCAH tASC COLUMN ADDRESS ROW ADDR. tASC COLUMN ADDRESS COL. ADDR. COL. ADDR. tRRH tRCS tRCH VIH- WE tCAC tAA tAA VIL- tCPA tCPA tCHO tOEP tOCH tCAC tOEA VIH- tCPA tCAC tAA tOEA OE VIL- tCAC tRAC tOLZ VOH- DQ tCLZ VOL- tOEP tOEZ tDOH tOEZ VALID DATA-OUT VALID VALID DATA-OUT DATA-OUT EDO Page Mode Early Write Cycle tOEZ VALID DATA-OUT VALID DATA-OUT Don't Care NOTE : DOUT = OPEN tRASP tRP tRHCP VIH- RAS VIL- tPC tCRP tRCD tCAS tCP tPC tCAS tCP tRSH tCAS VIH- CAS VIL- tRAD tRAH tASC tASR Address VIHVIL- ROW ADDR. COLUMN ADDRESS tWCS VIH- WE tCSH tCAH tASC tCAH COLUMN ADDRESS tWCH tWCS tWP tWP tWCH tCAH tASC COLUMN ADDRESS tWCS tWCH tWP VIL- VIH- OE VIL- tDS VIH- DQ VIL- tDH VALID DATA-IN tDS VALID DATA-IN tDS tDS tDS VALID DATA-IN Don't Care G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 13 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) EDO Page Mode Read - Modify - Write Cycle NOTE : DOUT = OPEN tRASP RAS VIH- tRP tCSH VIL- tRCD tCAS tRSH tCAS tCP tCRP VIH- CAS VIL- tASR VIH- Address VIL- tRAD tRAH tASC ROW ADDR. tPRWC tRAL tCAH tCAH tASC COL. ADDR. COL. ADDR. tRWL tCWL tCWL tRCS VIH- WE tCWD tWP tCWD VIL- tWP tAWD tAWD tCPWD tOEH tRWD OE VIH- tOEA tOEA tDH VIL- tCAC tAA tCAC tAA tOED tOEZtDS tRAC tDH tOED tOEZ tDS VI/OH- DQ VI/OL- tCLZ tCLZ VALID DATA-IN VALID DATA-OUT VALID DATA-IN VALID DATA-OUT Don't Care EDO Page Read And Write Mixed Ccycle tRP tRASP RAS CAS VIHVIL- VIHVIL- tASR ADDRESS VIHVIL- WE VIHVIL- OE VIHVIL- tHPC tRAH tASC tCAS tRCS tASC COL. ADDR VI/OH- tASC tCAH COLUMN ADDRESS tRCH tRCS tHPC tCP tCAS tCAH tASC COLUMN ADDRESS tCAH COLUMN ADDRESS tRCH tRCH tWCS tWCH tWPE DQ0~DQ3 VI/OL- tCP tCAS tCAH ROW ADDR tHPC tCP tCLZ tCPA tOEA tCAC tWEZ tAA tRAC VALID DATA-OUT tWED tWEZ VALID DATA-OUT tDH tDS VALID DATA-IN tAA tREZ VALID DATA-OUT Don't Care G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 14 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) CAS - Before - RAS Refresh Cycle tRC tRC tRP tRAS tRAS tRP VIH- RAS VIL- tCSR tCHR tRPC tCSR tCHR tRPC tCRP VIH- CAS VIL- tWRH tWRP tWRP tWRH VIH- WE VIL- Remark Address, OE : Don't care DQ : Hi - Z RAS -Only Refresh Cycle tRC tRC tRP tRAS tRAS tRP VIH- RAS VIL- tCRP tRPC tCRP VIH- CAS VIL- tRAH tASR VIH- Address tASR ROW ADDRESS VIL- tRAH ROW ADDRESS Remark Address, WE, OE : Don't care DQ : Hi - Z Hidden Refresh Cycle ( Read ) tRC tRC tRP tRAS RAS tRAS tRP VIHVIL- tCRP tRCD tRSH tCHR VIH- CAS VIL- tRAD tASR Address VIHVIL- tRAL tCAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCS tRRH tWRP tWRH VIH- WE tAA VIL- tOEA VIH- OE VIL- tCAC tRAC tWEZ tOEZ tCLZ tCEZ tREZ VIH- DQ OPEN DATA-OUT VIL- Don't Care G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 15 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Hidden Refresh Cycle ( Write ) NOTE : DOUT = OPEN tRC tRP tRAS RAS tRAS tRP VIHVIL- tRCD tCRP tRSH tCHR VIH- CAS VIL- tRAD tASC Address VIHVIL- tCAH ROW ADDRESS tRSH tASC tCAH COLUMN ADDRESS tWCS VIH- WE tWCH tWRP tWRH tWP VIL- VIH- OE VIL- tDS DQ tDH VIHDATA-IN VIL- Don't Care G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 16 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) CAS-Before RAS Refresh Counter Test Cycle tRP tRAS VIHRAS VIL- tCSR tRSH tCAS tCPT tCHR VIHCAS VIL- tRAL tASC Address VIH- COLUMN ADDRESS VIL- Read Cycle tCAH tWRP tWRH tAA tCAC tRCS tRRH tRCH VIH- WE VIL- tOEA VIH- OE VIL- tOEZ tCLZ VOHDQ VOL- Write Cycle tCEZ VALID DATA-OUT tWRP tWRH tRWL tCWL tWCS tWCH tWP VIH- WE VIL- VIH- OE VIL- tDS VIHDQ VIL- OPEN VALID DATA-IN Read-Modify-Write VIH- WE VIL- tDH tRCS tAWD tCWD tCWL tRWL tWP tWRP tWRH tCAC tAA tOEA VIH- OE VIL- tOED tCLZ tOEZ tDH tDS VI/OH- DQ VI/OL- VALID VALID DATA-OUT DATA-IN G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 17 - Don't Care G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Test Mode In Cycle tRC tRP RAS VIHVIL- tRP tRAS tRPC tRPC tCP tCSR CAS VIHVIL- WE VIHVIL- tWTS tCHR tWTH tCEZ OPEN VI/OHDQ V I/OL- Don't Care Test Mode By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the x 16-bit organization during test mode. Don't care about the input levels of the CAS input A0, A1 . (1) Setting the mode Executing the test mode cycle (WE , CAS before RAS refresh cycle ) sets the test mode. (2) Write / read operation When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell. Next, when the data is read from the output pin at the same address, the cell be checked. Output = "1" Normal write (all memory cells) Output = "0" Abnormal write (3) Refresh Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal counter. (4) Mode Cancellation The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle. G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 18 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) CAS-Before-RAS Self Refresh Cycle tRP RAS VIHVIL- tRPC tRPC tCP CAS tRPS tRASS tCHS tCSR VIHVIL- tCEZ DQ OPEN VI/OHVI/OL- tWRP WE tWRH VIHVILDon't Care NOTE : OE , Address = Don't Care G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 19 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Ordering Information Part Number SPEED POWER FEATURE TEMPERATURE GLT4160N04-100J3 GLT4160N04E-100J3 GLT4160N04P-100J3 GLT4160N04-100TC GLT4160N04E-100TC GLT4160N04P-100TC 100ns 100ns 100ns 100ns 100ns 100ns Normal Normal Normal Normal Normal Normal EDO EDO EDO EDO EDO EDO Commercial Extended Commercial Commercial Extended Commercial PACKAGE SOJ 300mil 26(24)L SOJ 300mil 26(24)L SOJ 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L TSOPII 300mil 26(24)L Parts Numbers (Top Mark) Definition : GLT 4 160 N 04 4 : DRAM 5 : Synchronous DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM 9 : SGRAM -SRAM CONFIG. 064 : 8K 256 : 256K 512 : 512K 100 : 1M 200 : 2M 400 : 4M 04 08 16 32 : : : : x04 x08 x16 x32 -DRAM 10 : 1M(C/EDO) 11 : 1M(C/FPM) 12 : 1M(H/EDO) 13 : 1M(H/FPM) 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) 160 : 16M(EDO) 161 : 16M(FPM) 640 : 64M(EDO) 641 : 64M(FPM) P - 100 TC SPEED -SRAM 12 : 12ns 15 : 15ns 20 : 20ns 55 : 55ns 70 : 70ns 85 : 85ns 120 : 120ns -DRAM VOLTAGE Blank : 5V L : 3.3V M : 2.5V N : 2.0V -SDRAM POWER 40 : 4M 160 : 16M 320 : 32M,4Bank 640 : 64M Blank : Standard L : Low Power LL : Low Low Power SL : Super Low Power 25 : 25ns 28 : 28ns 30 : 30ns 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns 70 : 70ns 80 : 80ns 100 : 100ns SDRAM : 5 : 5ns/200 MHZ 5.5 : 5.5ns/183 MHZ 6 : 6ns/166 MHZ 7 : 7ns/143 MHZ 8 : 8ns/125 MHZ 10 : 10ns/100 MHZ PACKAGE T : PDIP(300mil) TS : TSOP(Type I) ST : sTSOP(Type I) TC : TSOPll (40/44) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP FG : 48Pin BGA 9x12 FH : 48Pin BGA 8x10 FI : 48Pin BGA 6x8 FJ : 60Ball VFBGA Temperature Range E : Extended Temperature I : Industrial Temperature Blank : Commercial Temperature P : Pb - free part G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 20 - G -LINK GLT4160N04 4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr 2003 (Rev. 1.2) Package Information 300mil 24/26 Lead Thin Small Outline Package SOJ 300mil 24/26 Lead Thin Small Outline Package (TSOP) TYPE II G-Link Technology Corporation,Taiwan Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-26599658 - 21 -