G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 1 -
Features : Description :
∗ 4,194,304 words by 4 bits organization.
∗ Fast access time and cycle time
∗ Low power dissipation.
∗ Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden Refresh.
∗ 2,048 refresh cycles per 32ms.
∗ Available in 300 mil 26(24) SOJ and TSOPII.
∗ 2.0V±0.2V Vcc Power Supply voltage.
∗ All inputs and Outputs are LVTTL
compatible.
∗ Extended Data-Out (EDO) Page access
cycle.
∗ Self-refresh Capability.(S-Version).
The GLT4160N04 is a high-performance
CMOS dynamic random access memory
containing 16,777,216 bits organized in a x4
configuration. The GLT4160N04 offers page
cycle access with Extended Data Output.
The GLT4160N04 has 11 row- and 11
column-addresses, and accepts 2048-cycle
refresh in 32 ms.
The GLT4160N04 provides EDO PAGE
MODE operation which allows for fast data
access within a row-address defined
boundary, up to 2048 x 4 bits with cycle
times as short as 45ns.
HIGH PERFORMANCE 100
Max.
RAS
Access Time, (tRAC)100 ns
Max. Column Address Access Time, (tAA)50 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC)45 ns
Min. Read/Write Cycle Time, (tRC)190 ns
Max.
CAS
Access Time (tCAC)25 ns
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 2 -
Pin Configuration :
Vcc
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
16
15
14
26
25
24
23
A9
A8
A7
A6
OE
CAS
VSS
DQ3
DQ1
WE
RAS
NC
VCC
DQ2
A5
A4
VSS
A10
Vcc
DQ0
A10
A0
A1
A2
A3
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
16
15
14
26
25
24
23
A9
A8
A7
A6
OE
CAS
VSS
DQ3
DQ1
WE
RAS
NC
VCC
DQ2
A5
A4
VSS
Pin Descriptions:
Name Function
A0 - A10 Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
DQ0 - DQ3Data Inputs / Outputs
VCC +2V Power Supply
VSS Ground
NC No Connection
GLT4160N04
300mil 26(24) TSOPII
GLT4160N04
300mil 26(24) SOJ
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 3 -
Absolute Maximum Ratings* Capacitance*
TA=25°C, VCC=2V±0.2V, VSS=0V
Operating Temperature, TA (ambient)
.............................................….0°C to
+70°C
For Extended Temperature……………..-20°C to 85°C
Storage Temperature(plastic)............-55°C to +150°C
Voltage Relative to V
SS
........................-0.5V to + 3.5V
Short Circuit Output Current...............................20mA
Power Dissipation...............................................1.0W
Symbol
CIN1
CIN2
COUT
Parameter
Address Input
RAS, CAS, WE, OE
Data Input/Output
Max.
5
7
7
Unit
pF
pF
pF
*Note: Operation above Absolute Maximum Ratings can
aversely affect device reliability. *Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l All voltages are referenced to GND.
l After power up, wait more than 200µs and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
NO.2 CLOCK
GENERATOR
COLUMN-
ADDRESS
BUFFER(11)
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFERS(11)
NO.1 CLOCK
GENERATOR
11
11
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
RAS
11
11 COLUMN
DECODER
DATA-OUT
BUFFER
DATA-IN
BUFFER
SENSE AMPLIFIERS
I/O GATING
2048 x 1024 x 4
MEMORY
ARRAY
2048
2048
4
4
4
4
WE
CAS DQ
0
DQ
1
DQ
2
DQ
3
OE
V
DD
V
SS
ROW DECODER
2048
A
0
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 4 -
Truth Table:
Function
RAS
CAS
WE
OE
ADDRESS DATA-IN/OUT
tRtCDQ1-DQ4
Standby HH→XX X X X High-Z
READ L L HLROW COL Data-Out
EARLY WRITE L L L XROW COL Data-In
READ WRITE L L H→L L→HROW COL Data-Out,Data-In
EDO-PAGE-MODE 1st Cycle LH→LHLROW COL Data-Out
READ 2nd cycle LH→LHLn/a COL Data-Out
EDO-PAGE-MODE 1st Cycle LH→LLXROW COL Data-In
EARLY-WRITE 2nd cycle LH→LLXn/a COL Data-In
EDO-PAGE-MODE 1st Cycle LH→LH→L L→HROW COL Data-Out,Data-In
READ-WRITE 2nd cycle LH→LH→L L→Hn/a COL Data-Out,Data-In
RAS
-ONLY REFRESH LHX X ROW n/a High-Z
HIDDEN REFRESH READ L→H→LLHLROW COL Data-Out
WRITE L→H→LL L XROW COL Data-In
CBR REFRESH H→LLHX X X High-Z
SELF REFRESH H→LLHX X X High-Z
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 5 -
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, -20°C to 85°C VCC=2V±0.2V, VSS=0V, unless otherwise specified.
Sym. Parameter Test Conditions Access
Time Min. Typ Max. Unit Notes
ILI Input Leakage Current
(any input pin) 0V ≤ VIN ≤ VCC+0.3V
(All other pins not under
test=0V)
-5 +5 µA
ILO Output Leakage Current
(for High-Z State) 0V ≤ Vout ≤ VCC
Output is disabled (Hiz) -5 +5 µA
ICC1 Operating Current,
Random READ/WRITE tRC = tRC (min.) tRAC = 100ns 40 mA 1,2
ICC2 Standby Current, (TTL)
RAS
,
CAS
at VIH
other inputs ≥VSS 1mA
ICC3 Refresh Current,
RAS
-Only
RAS
cycling,
CAS
at VIH
tRC = tRC (min.)
tRAC = 100ns 40 mA 2
ICC4 Operating Current,
EDO Page Mode
RAS
at VIL,
CAS
address
cycling:tPC=tPC(min.)
tRAC = 100ns 40 mA 1,2
ICC5 Refresh Current,
CAS
Before
RAS
RAS
,
CAS
address
cycling: tRC=tRC (min.)
tRAC = 100ns 40 mA 1
ICC6 Standby Current, (CMOS)
RAS
≥VCC-0.2V,
CAS
≥VCC-0.2V,
All other inputs VSS
200 µA1
ICC7 Self refresh Current
RAS
=
CAS
=0.2V,
WE = OE = A0~A10=VCC-
0.2V or 0.2V
DQ0~DQ3=VCC-0.2V,0.2V
or Open
200 µA
VIL Input Low Voltage -0.2 +0.6 V3
VIH Input High Voltage 1.6 VCC+0.2 V4
VOL Output Low Voltage IOL = 2mA 0.6 V
VOH Output High Voltage IOH = -2mA 1.6 V
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output
open.
2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one
transition per address cycle in random Read/Write and EDO Fast Page Mode.
3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to –0.9V for a period not to
exceed 10ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
4. Specified VIH(max.) is steady state operation . During transitions VIH(max.) may overshoot to VCC+0.9V for a period not
to exceed 10ns. All AC parameters are measured with VIL(min.) ≥ VSS and VIH(max.) ≤ VCC .
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 6 -
AC Characteristics
TA = 0°C to 70°C , -20°C to 85°C VCC = 2 V ± 0.2V, VIH/VIL = 1.7/0.4 V, VOH/VOL = 1.4/0.6V
An initial pause of 200 µs and 8
CAS
-before-
RAS
or
RAS
-only refresh cycles are required after power-up.
100
Parameter Symbol Min. Max. Unit Notes
Read or Write Cycle Time tRC 190 ns
Read Modify Write Cycle Time tRWC 245 ns
RAS
Precharge Time tRP 80 ns
RAS
Pulse Width tRAS 100 10k ns
Access Time from
RAS
tRAC 100 ns 1,2,3
Access Time from
CAS
tCAC 25 ns 1,5,10
Access Time from Column Address tAA 50 ns 1,5,6
CAS
to Output Low-Z tCLZ 5ns
CAS
to Output High-Z tCEZ5 25 ns
RAS
Hold Time tRSH 25 ns
CAS
Hold Time tCSH 100 ns
CAS
Pulse Width tCAS 25 10k ns
RAS
to
CAS
Delay Time tRCD 25 75 ns
RAS
to Column Address Delay Time tRAD 20 50 ns 7
CAS
to
RAS
Precharge Time tCRP 10 ns
Row Address Set-Up Time tASR 0ns
Row Address Hold Time tRAH 15 ns
Column Address Set-Up Time tASC 0ns
Column Address Hold Time tCAH 20 ns
Column Address to
RAS
Lead Time tRAL 50 ns
Column Address Hold Time Referenced to
RAS
tAR 75 ns
Read Command Set-Up Time tRCS 0ns
Read Command Hold Time Referenced to
CAS
tRCH 0ns 4
Read Command Hold Time Referenced to
RAS
tRRH 0ns 4
Write Command Set-Up Time tWCS 0ns 8,9
Write Command Hold Time tWCH 20 ns
Write Command Pulse Width tWP 20 ns
Write Command to
RAS
Lead Time tRWL 25 ns
Write Command to
CAS
Lead Time tCWL 25 ns
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 7 -
AC Characteristics 100
Parameter Symbol Min. Max. Unit Notes
Data Set-Up Time tDS 0ns
Data Hold Time tDH 20 ns
Data Hold Time Referenced to
RAS
tDHR 75 ns
RAS
to
WE
Delay Time tRWD 135 ns
CAS
to
WE
Delay Time tCWD 60 ns
Column Address to
WE
Delay Time tAWD 80 ns
CAS
Precharge to
WE
Delay tCPWD 85 ns
RAS
to
CAS
Precharge Time tRPC 5ns
CAS
precharge time (
CAS
Before
RAS
counter test cycle)
tCPT 30 ns
Access Time from
CAS
Precharge tCPA 55 ns
EDO Page Mode Cycle Time tPC 45 ns
EDO Page Mode Read-Modify-Write Cycle Time tPRWC 120 ns
CAS
Precharge Time (EDO Page Mode) tCP 10 ns
RAS
Pulse Width (EDO Page Mode Only) tRASP 100 100k ns
RAS
Hold Time from
CAS
precharge tRHCP 60 ns
Access Time from
OE
tOEA 25 ns 8
OE
to Data Delay Time tOED 25 ns
OE
to Output Low-Z tOLZ 3ns
OE
to Output High-Z tOEZ 3 25 ns
WE
to Data Delay tWED 25 ns
OE
Command Hold Time tOEH 25 ns
Data Output Hold after
CAS
low tDOH 5ns
RAS
to Output High-Z tREZ 3 25 ns
WE
to Output High-Z tWEZ 3 25 ns
OE
to
CAS
Hold Time tOCH 5ns
CAS
Hold Time to
OE
tCHO 5ns
OE
Precharge Time tOEP 5ns
WE
Puts width (EDO mixed read write cycle) tWPE 5ns
CAS
Set-Up Time for
CAS
-before-
RAS
Cycle tCSR 5ns
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 8 -
100
Parameter Symbol Min. Max. Unit Notes
CAS
Hold Time for
CAS
-before-
RAS
Cycle tCHR 20 ns
WE
to
RAS
precharge time (
CAS
Before
RAS
refresh )
tWRP 10 ns
WE
to
RAS
hold time (
CAS
Before
RAS
refresh )
tWRH 10 ns
Transition Time tT2 50 ns
Refresh Period (2,048 cycles) tREF 32 ms
Refresh Period (S-Version) tREFS 128 ms
RAS
Pulse Width (
CAS
Before
RAS
Self
refresh )
tRASS 100 µs
RAS
precharge Time (
CAS
Before
RAS
Self
refresh )
tRPS 180 ns
CAS
Hold Time (
CAS
Before
RAS
Self
refresh )
tCHS -50 ns
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 9 -
TEST MODE CYCLE 100
Parameter Symbol Min. Max. Unit Notes
Random read or write cycle time tRC 195 ns
Read-modify-write cycle time tRWC 250 ns
Access time from
RAS
tRAC 90 ns 1,2,3,7
Access time from
CAS
tCAC 30 ns 1,3,7
Access time from column address tAA 55 ns 1,2,7
RAS
pulse width tRAS 105 10k ns
CAS
pulse width tCAS 30 10k ns
RAS
hold time tRSH 30 ns
CAS
hold time tCSH 105 ns
Column address to
RAS
lead time tRAL 55 ns
CAS
to WE delay time tCWD 65 ns 8
RAS
to WE delay time tRWD 140 ns 8
Column address to WE delay time tAWD 85 ns 8
CAS
Precharge to WE delay time tCPWD 89 ns 8
EDO Page Mode cycle time tPC 50 ns
EDO page mode read-modify-write cycle time tPRWC 125 ns
RAS
Pulse width (EDO page cycle) tRASP 105 100k ns
Access time form
CAS
precharge tCPA 60 ns 1
OE
access time tOEA 30 ns
OE
to data delay tOED 30 ns
OE
command hold time tOEH 30 ns
Write command set-up time (Test mode in) tWTS 10 ns
Write command hold time (Test mode in) tWTH 10 ns
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 10 -
Notes:
1. Measure with a load equivalent to one TTL input and 100 pF.
2. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tCAC
dominant.
3. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), access time will be
controlled by tAA.
4. Either tRRH or tRCH must be satisfied for a Read Cycle.
5. Access time is determined by the longest of tAA, tCAC and tCPA.
6. Assumes that tRAD ≥ tRAD (max.).
7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.)
is specified as a reference point only. If tRAD is greater than the specified tRAD (max.)
limit, the access time is controlled by tCAA and tCAC.
8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
9. tWCS (min.) must be satisfied in an Early Write Cycle.
10. tDS and tDH are referenced to the latter occurrence of
CAS
or
WE
.
11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns.
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 11 -
Read Cycle
ROW
ADDRESS COLUMN
ADDRESS
DATA-OUT
tRC
tRAS tRP
tCRP
tCSH
tRCD tRSH
tCAS
tCRP
tASR tRAH
tRAD tASC tCAH
tRAL
tRCH
tRRH
tAR
tRCS
tAA
tOEA
tCEZ
tOEZ
tCAC
tCLZ
tRAC
Don't Care
VIH-
VIL-
RAS
VIH-
VIL-
CAS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VOH-
VOL-
DQ
Early Write Cycle NOTE : DOUT = OPEN
tRP
tRC
tCRP
tCSH
tCRP tRCD tRSH
tCAS
tASR
tRAH
tRAD
tASC tCAH tRAL
tCWL
tRWL
tWCR
tWCH
tWP
tWCS
tAR
tDS tDH
tDHR
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
VIH-
VIL-
RAS
VIH-
VIL-
CAS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VIH-
VIL-
DQ
Don't Care
tRAS
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 12 -
OE Controlled Write Cycle NOTE : DOUT = OPEN
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
OED
t
OEH
t
DH
Read - Modify - Write Cycle
t
RP
t
RC
t
CRP
t
CRP
t
RCD
t
RSH
VALID
DATA-OUT
COLUMN
ADDRESS
ROW
ADDR.
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Don't Care
t
RAS
VALID
DATA-IN
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
CSH
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
RAC
t
DH
t
DS
t
OED
t
OEZ
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 13 -
EDO Page Mode Read Cycle NOTE : DOUT = OPEN
tRASP tRP
tCRP tRCD tCAS
tCSH
tCP
tCAS tCAS tCAS
tCP tCP
tPC tPC tPC
tCSR tRAH
tRAD
tASC
tASC tASC tASC
tCAH tCAH tCAH tCAH
tRCS tRCH tRRH
tOEA tOEA
tCAC
tCPA
tAA
tOCH
tCPA
tAA
tCAC
tOEP
tCHO
tAA
tCAC
tCPA
tCLZ
tOLZ
tRAC
tCAC tDOH tOEZ
tOEP tOEZ tOEZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT VALID
DATA-OUT
VIH-
VIL-
RAS
VIH-
VIL-
CAS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
DQVOH-
VOL-
ROW
ADDR. COLUMN
ADDRESS COLUMN
ADDRESS COL.
ADDR. COL.
ADDR.
Don't Care
tRHCP
EDO Page Mode Early Write Cycle NOTE : DOUT = OPEN
tRASP tRP
tCRP tRCD tCAS
VIH-
VIL-
RAS
VIH-
VIL-
CAS
tCAS
tCAS
tCP tCP
tPC tPC
tRSH
tASR
tRAD
tRAH
tASC tCAH
tCSH
tASC tASC
tCAH tCAH
tWCS
tWP
tWCH tWCS tWCStWCH tWCH
tWP tWP
tDS tDS tDStDH tDS tDS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
DQ VIH-
VIL-
ROW
ADDR. COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don't Care
tRHCP
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 14 -
EDO Page Mode Read - Modify - Write Cycle NOTE : DOUT = OPEN
t
RASP
t
RP
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
Don't Care
t
CSH
t
RCD
t
CAS
t
CP
t
CAS
t
RSH
t
CRP
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
PRWC
t
RCS
t
WP
t
CWL
t
WP
t
CWL
t
RWL
t
CWD
t
AWD
t
RWD
t
OEA
t
CWD
t
AWD
t
CPWD
t
OEA
t
OEH
t
RAC
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
CLZ
t
CLZ
VALID
DATA-OUT VALID
DATA-IN VALID
DATA-OUT VALID
DATA-IN
ROW
ADDR. COL.
ADDR. COL.
ADDR.
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
EDO Page Read And Write Mixed Ccycle
t
RASP
t
RP
t
CAS
t
HPC
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
ASR
t
HPC
t
HPC
t
RAH
t
ASC
t
CAH
t
ASC
t
ASC
t
ASC
t
CAH
t
CAH
t
CAH
t
RCS
t
RCH
t
RCS
t
RCH
t
RCH
t
WCS
t
WCH
t
WPE
t
CPA
t
CLZ
t
WED
t
WEZ
t
RAC
t
AA
t
CAC
t
OEA
t
WEZ
t
DS
t
DH
t
AA
t
REZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT VALID
DATA-IN
ROW
ADDR COL.
ADDR COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
I/OH-
V
I/OL-
RAS
CAS
ADDRESS
WE
OE
DQ
0
~DQ
3
Don't Care
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 15 -
CAS
- Before -
RAS
Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
CSR
t
CSR
t
CHR
t
CHR
t
RPC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
t
WRH
t
WRP
V
IH-
V
IL-
WE
t
WRP
t
WRH
Remark Address, OE : Don’t care DQ : Hi - Z
RAS
-Only Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
t
CRP
t
ASR
t
ASR
t
RAH
t
RAH
ROW
ADDRESS ROW
ADDRESS
Address
V
IH-
V
IL-
Remark Address, WE, OE : Don’t care DQ : Hi - Z
Hidden Refresh Cycle ( Read )
tRP
tCRP tRCD
VIH-
VIL-
RAS
VIH-
VIL-
CAS
tRAC
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
DQ VIH-
VIL-
ROW
ADDRESS
Don't Care
tRP
tCAC
tRCS
tASC tCAHtASR tCAH
tRAD tRAL
tRSH tCHR
t
RC
tRAS tRAS
COLUMN
ADDRESS
t
RC
tWRH
tAA
tOEA
tCLZ tREZ
tCEZ
tWEZ
tOEZ
DATA-OUT
OPEN
tWRPtRRH
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 16 -
Hidden Refresh Cycle ( Write ) NOTE : DOUT = OPEN
tRP
tCRP tRCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
tDS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
tRP
tDH
tWP
tWCH
tWCS
tASC tCAHtASC tCAH
tRAD tRSH
tRSH tCHR
tRC
tRAS tRAS
COLUMN
ADDRESS
DATA-IN
tWRP tWRH
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 17 -
CAS-Before RAS Refresh Counter Test Cycle
tCAS
tCPT
VIH-
VIL-
RAS
VIH-
VIL-
CAS
t
RP
tRAS
tCSR tCHR tRSH
tRAL
tASC
tAA
tCAC
tRCS tRRH tRCH
tWRP tWRH
tWRHtWRP
tOEA
tCEZ
tOEZ
tCLZ
tRWL
tCWL
tWCH
tWCS
tWP
tDS tDH
tRCS tAWD
tCWD tRWL
tCWL
tWP
tDH
tDS
tOED
tOEZ
tCLZ
tCAC
tAA
tOEA
OPEN
COLUMN
ADDRESS
VALID DATA-OUT
VALID DATA-IN
Don't Care
VALID
DATA-IN
VALID
DATA-OUT
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VOH-
VOL-
DQ
VIH-
VIL-
WE
VIH-
VIL-
OE
VIH-
VIL-
DQ
VIH-
VIL-
WE
VIH-
VIL-
OE
VI/OH-
VI/OL-
DQ
Read Cycle
Write Cycle
Read-Modify-Write
tCAH
tWRP tWRH
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 18 -
Test Mode In Cycle
tRP
t
RC
tRAS
tRP
tRPC
tCP tCSR tCHR
tWTS tWTH
tCEZ OPEN
tRPC
Don't Care
VIH-
VIL-
VIH-
VIL-
VIH-
VIL-
VI/OH-
VI/OL-
RAS
CAS
WE
DQ
Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the x
16-bit organization during test mode. Don’t care about the input levels of the CAS input A0, A1 .
(1) Setting the mode
Executing the test mode cycle (WE , CAS before RAS refresh cycle ) sets the test mode.
(2) Write / read operation
When either a “0” or a “1” is written to the input pin in test mode, this data is written to 16 bits of memory
cell.
Next, when the data is read from the output pin at the same address, the cell be checked.
Output = “1” Normal write (all memory cells)
Output = “0” Abnormal write
(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS
refresh cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS
refresh’s internal counter.
(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh
cycle.
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 19 -
CAS-Before-RAS Self Refresh Cycle
t
RPS
t
RASS
t
RP
tRPC
tCP tCSR
tCEZ
OPEN
tRPC
Don't Care
VIH-
VIL-
VIH-
VIL-
VI/OH-
VI/OL-
RAS
CAS
DQ
tCHS
tWRP tWRH
VIH-
VIL-
WE
NOTE : OE , Address = Don’t Care
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 20 -
Ordering Information
Part Number
SPEED
POWER
FEATURE
TEMPERATURE
PACKAGE
GLT4160N04-100J3
100ns
Normal
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160N04E-100J3
100ns
Normal
EDO
Extended
SOJ 300mil 26(24)L
GLT4160N04P-100J3
100ns
Normal
EDO
Commercial
SOJ 300mil 26(24)L
GLT4160N04-100TC
100ns
Normal
EDO
Commercial
TSOPII 300mil 26(24)L
GLT4160N04E-100TC
100ns
Normal
EDO
Extended
TSOPII 300mil 26(24)L
GLT4160N04P-100TC
100ns
Normal
EDO
Commercial
TSOPII 300mil 26(24)L
Parts Numbers (Top Mark) Definition :
GLT 4 160 N 04 P - 100 TC
4 : DRAM
5 : Synchronous
DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
9 : SGRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
200 : 2M
400 : 4M
-DRAM
10 : 1M(C/EDO)
11 : 1M(C/FPM)
12 : 1M(H/EDO)
13 : 1M(H/FPM)
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
160 : 16M(EDO)
161 : 16M(FPM)
640 : 64M(EDO)
641 : 64M(FPM)
-SDRAM
40 : 4M
160 : 16M
320 : 32M,4Bank
640 : 64M
VOLTAGE
Blank : 5V
L : 3.3V
M : 2.5V
N : 2.0V
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
55 : 55ns
70 : 70ns
85 : 85ns
120 : 120ns
-DRAM
25 : 25ns
28 : 28ns
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
70 : 70ns
80 : 80ns
100 : 100ns
SDRAM :
5 : 5ns/200 MHZ
5.5 : 5.5ns/183 MHZ
6 : 6ns/166 MHZ
7 : 7ns/143 MHZ
8 : 8ns/125 MHZ
10 : 10ns/100 MHZ
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
ST : sTSOP(Type I)
TC : TSOPll (40/44)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
FG : 48Pin BGA 9x12
FH : 48Pin BGA 8x10
FI : 48Pin BGA 6x8
FJ : 60Ball VFBGA
POWER
Blank : Standard
L : Low Power
LL : Low Low Power
SL : Super Low Power
Temperature Range
E : Extended Temperature
I : Industrial Temperature
Blank : Commercial Temperature
P : Pb – free part
G-LINK GLT4160N04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Apr 2003 (Rev. 1.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-26599658
- 21 -
Package Information
300mil 24/26 Lead Thin Small Outline Package SOJ
300mil 24/26 Lead Thin Small Outline Package (TSOP) TYPE II
