w3 Ze Yon Microtech MS8E128 SEMICONDUCTORS -70/90/120 1,048,576 bit High Speed CMOS E* PROM Module Features ~ . Package Details Very fast read access times - 70/90/120ns (Dimensions in inches) User selectable path width - 8, 16, 24 or 32 bits Pin 1 , Ident Automatic page write operation \ ponere = 0.010 Square Fast write cycle times : 3ms (F Version) Low power dissipation : 3mA Standby (L Version) * Hardware and Software data protection DATA Polling for end of write detection * Endurance : 10 cycles (E Version) Data retention : 10 years * Single 5V power supply Full military temperature range * On-board decoupling capacitors * TTL compatible Inputs and Outputs __ Ao - Ar4 __ WE; WE 2 Es WE 4 | i] | | OE | 0.10 o st 6 4 oo @ 0.10) oo 6 oo 0 +t, Oo 0 oOo 0 6 \7 N77 rT oo oo 90 o 0 0 oo 60 1.00 oo fo o Oo 0 zs 32K X 8 Re 32K X 8 ane 32K X8 AE 32K X 8 00 0 o 6 68 CE CEs | SRAM 32] SRAM CEs | SRAM CE 4 | SRAM oo 6 an oo 6 oo 06 0.16 Oo 0 6 - or ~ Oo 0 90 t oo MM] > -o t ! 7 | Do - D7 De - Dis Die - Das Daa - Dat 0.42 J) General Description The MS8 Memory Module Family offers an increase in packing density in excess of 2:1 over standard Dual-In-Line parts of similar capacity. The MS8E128 is a very high-performance Electrically Erasable and Programmable Read Only Memory Module and employs four high-speed, low-power 32K x 8 CMOS monolithic E*PROM devices to offer access times to 70ns. When deselected the standby current is less than 20mA. The module operates from a single +5V power supply and all inputs and outputs are both CMOS and TTL compatible. For flexibility the chip enable (CE) of each monolithic device may be individually accessed permitting user definable configurations (x8, x16, x24 or x32).MS8E128 Microtech - 70 /90/120 SEMICONDUCTORS General Description Cont. The module substrate is manufactured using multi-layer co-fired alumina and has 66 pins arranged in 6 rows of 11. When mounted on a board the module is particularly rugged and the central channel in its array of pins (see package details) facilitates thermal management by use of a heat ladder or by forced air cooling. The pins are so configured as to permit simplified pcb designs and the provision of on-board decoupling capacitors further decreases the additional components required on the users board. The MS8E128 is accessed like a Static RAM for the read or write cycle without the need for external components. Each of the monolithic devices on the module contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64 bytes of information are internally latched, freeing the addresses and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of D7, D15, D23 or D31 as appropriate. Once the end of a write cycle has been detected a new access for read or write can begin. The E2PROM devices used feature internal error correction for extended endurance and improved data retention characteristics. A optional software data protection mechanism is available to guard against inadvertent writes. The monolithic devices also include an extra 64 bytes of EPROM each for device identification or tracking. Module Operation A feature of the MS8E128 is the ability to individually access the chip enables (CE1, CE2, CE3 and CEa4) and also the write enables (WE1, WE2, WE3 and WEa) of its constituent devices corresponding to data lines Do-7, Dg-15, D16-23 and D24-31. This flexibility permits the user to define the configuration of the memory according to the system requirements. Read: The MS8E128 is accessed like a Static RAM. When a chip enable (CEn) and the output enable (OE) are low and the corresponding write enable (WEp) is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs of an individual device are put in the high state wnenever CEn or OE is high. This dual line control gives designers flexibility in preventing bus contention. Write: A low pulse on WEn or CEn with the corresponding CEn or WEn low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CEn or WEn, whichever occurs last. The data is latched by the rising edge of CEn or WEn. Once a byte write has started it will automatically time itself to completion. Tamia Ponds 9Microtech MS8E128 SEMICONDUCTORS - 70 /90/120 Module Operation Cont. Page Write Mode : The page write operation of the module allows one to 64 bytes of data to be loaded into each of its constituent devices and then simultaneously written during the internal programming period. After the first data byte has been loaded into a device successive bytes may be loaded in the same manner. Each new byte to be written must have its high to low transition on WEn (or CEn within 150us of the low to high transition of WEn (or CEn) of the preceding byte. If a high to low transition is not detected within this time period, the load period will end and the programming period will start. Ag to A14 specify the page address. The page address must be valid during each high to low transition of WEn (or CEn). Ao to As are used to specify which bytes within the page are to be written. The bytes may be written in any order and may be changed within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. Data Polling: The MS8E128 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D7, D15, D23 or D31. Once the write cycle has been completed, true data is valid on the corresponding outputs and the next cycle may begin. DATA Polling may begin at any time during the write cycle. Toggle Bit: In addition to DATA Polling the MS8E128 provides another method for determining the end of a write cycle. During a write operation, successive attempts to read data from a device will result in Dg, D14, D22 or D30 toggling between one and zero. Once the write cycle has completed, Dg, D14, D22 or D3o will stop toggling, and valid data will be read. Examining the toggle bit may begin at any time during the write cycle. Hardware Data Protection : Hardware features protect against inadvertent writes to the MS8E128 in the following ways : (a) Vcc sense - If Vcc is below 3.8V (typical) the write function is inhibited. (b) Voc power on delay - once Vcc has reached 3.8V the device will automatically time out 5ms (typical) before allowing a write. (c) Write inhibit - holding any one of OE low, CEn high or WEp high inhibits write cycles. (d) Noise filter - pulses of less than 15ns (typical) on the WEn or CEn inputs will not initiate a write cycle. Software Data Protection: A software controlled data protection feature is available on the MS8E128. Once the software protection is enabled a software algorithm must be issued to each device before a write may be performed. The software protection feature may be enabled or disabled by the user; when dispatched from Microtech Semiconductors, the software data protection feature is disabled, unless otherwise specified. To enable the software data protection, a series of write commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three write commands must begin each write cycle in order for the writes to occur. All software write commands must obey the page write timing specifications. Once set, theMS8E128 Microtech -70/ 90/120 SEMICONDUCTORS Module Operation Cont. Software Data Protection Cont. software protection feature remains active unless its disable command is issued. Power transitions will not reset the software protection feature, but the software feature will guard against inadvertent writes during power transitions. Device Identification : Each of the four devices used to implement the MS8E128 offers an extra 64 bytes of E?PROM memory to the user for device identification. By raising Ag to 12+0.5V and using address locations 7FCOH to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. Absolute Maximum Ratings (1,2) ) Min Max Unit Vcc Supply Voltage -0.6 +6.25 Vv VIN Any Input or Din/out Voltage -0.6 +6.25 Vv Vout Any Output Voltage -0.6 Voc+0.6 V VOE/Ag OE and Ag Voltage -.06 413.5 V Ptot Power Dissipation 1.8 Ww Tstg Storage Temperature -65 +150 C Tamb Operating Temperature -55 +125 C Note: 1. Stresses greater than those listed may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltage values referenced to Vss (GND) NN Y/ Operating Conditions ) ) Min Max Unit Voc Supply Voltage 4.5 5.5 V Tamb Operating Temperature Ambient -55 +125 C ViL Input Low Voltage (Logic 0!) - 0.8 Vv ViH Input High Voltage (Logic 1) 2.0 - Vv tAce Address Access Time (Option -70) - 70 ns tace Address Access Time (Option -90) - 90 ns tacc Address Access Time (Option -120) - 120 ns Notes 1. All voltages referenced to Vss (GND). NS ZSMicrotech SEMICONDUCTORS MS8E128 - 70 / 90/120 cr ~ Mode Selection Mode OE CE WE Outputs Standby/Write Inhibit X(1) VIH x High Z Read Vit Vit VIH Dout Write) VIH VIL ViL DIN Write Inhibit Xx X VIH Write Inhibit VIL x X Output Disable VIH x x High Z Chip Erase VH) Vi ViL High Z Notes: 1, X= Vir or Vin. 2. Refer to A.C. Programming Waveforms. L 3. VH=12.0V +0.5V. / > DC Electrical Characteristics" 2) Test Conditions Min Max Unit Vit Input Low Voltage 0.8 Vv (Logic 0) VIH Input High Voltage 2.0 Vv (Logic 1) lu Input Load Current OV s Vin s Voc 1V 10 pA ILo Output Leakage Current OVs Vout < Vcc 10 pA VoL Output Low Voltage lo. = 6.0 mA 0.45 Vv Vou Output High Voltage 10H = -4.0 MA 2.4 Vv Icc Power Supply Current : f = 5MHz; lout = OMA 320 mA Operating (4) isB1 Power Supply Current : __ ~~ MS8ER8L 12 mA Standby (TTL) 2.0Vs CE s Voc +1V MS8E 128 240 mA IsB2 Power Supply Current: -3.0V < CE <Vcc + 1V s/b CMOS MS8E128L 1200 mA Notes: 1. All limits over specified temperature and voltage range (unless otherwise specified). 2. All voltages referenced to Vss (GND) NN / AC Test Conditions Output Load Equivalent +5V I Input pulse levels Vss to 3.0V 1.8KQ Input rise and fall times <5ns Dout Input timing reference levels 1.5V > 100pF Output reference levels 1.5V 1.3K | Output load See Figure MS8E128 Microtech -70/90/120 SEMICONDUCTORS ( > AC Electrical Characteristics - Read Cycle) -70 -90 -120 Min Max Min Max Min Max Units taa Address Access Time 70 90 120 ns {CE Chip Enable Access Time") 70 90 120 ns toe Output Enable Access Time) 0 35 0 40 0 50 ns tor Chip Disable or Quiput Disabie to 35 0 40 0 50 ns Output in High Z toH Output Hold from Output Disable, Chip Disable or Address Change 0 0) ns (Whichever occurs first) Notes __ 1. CE may be delayed up to tacc - tce after the address transition without impact on tacc. 2. OE may be delayed up to tce - toe after the falling edge of CE without impact on tce or by tACC - toe after an address change without impact on tacc. 3. tor is specified from OE or CE whichever occurs first. 4, This parameter is not 100% tested. we / Read Cycle ADDRESS ADDRESS VALID x CE PON {ce toe OE . \ --tpF taa +toH OUTPUT HIGH Z OUTPUT VALID _ppMicrotech SEMICONDUCTORS MS8E128 -70/90/120 . sas . >) (ac Electrical Characteristics - Write Cycle Min Max Units tas Address Set-up Time 0 ns toes Output Enable Set-up Time 0 ns taAH Address Hold Time 50 ns tcs Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns twe Write SPulse Width (WE or CE) 100 ns tos Data Set-up Time 50 ns toH Data Hold Time 0 ns toEH Out put Enable Hold Time 0 ns tov _ Time to Data Valid NR") MS8E128 10 ms two Write Cycle Time MS8E128F 3 ms Note: _ a 1. NR = No Restriction. yy Write Cycle No. 1 (Write Enable Controlled) OE toes_. +t ; \ OEH ADDRESS tas tay 7 etcH | CE | 1 \ tes -- WE twe ~tov |-tos -| |__toH _. DATA IN Write Cycle No. 2 (Chip Enable Controlled) OF toes woh ADDRESS tas | | tAaH t ICH >| oO -tcs _, CE ; > UNDEFINED tov +|-tos | |.toH __. DATA IN PNrents 7 TaowsssMS8E128 Microtech -70/90/120 SEMICONDUCTORS ( AC Electrical Characteristics - Page Mode Write Cycle Min Type Max Units MS8E128 5 10 ms twC -Write Cycle Time MS8E128F 2 3.0 ms tas Address Set-up 0 ns taH Address Hold Time 50 ns tps Data Set-up Time 50 ns tDH Data Hold Time 0 ns twe Write Pulse Width 100 ns tatc Byte Load Cycle Time 150 us tweH Write Pulse Width High 50 ns Notes: - A6 through A 14 must specify the page address during each high to low transition of WE (or CE) OE must be high only when WE and CE are both low. NS JY Write Cycle - Page Mode SE fo OE SE VY SNS NY 7 A a vtwee tac Yo A f _tDH y a A0-A5 SM a tps+ (fo DATA x x L a (\y . ee . >) AC Electrical Characteristics - Chip Erase Min Max Units ts Chip Enable, Output Enable, Setup Time 5 us tM Chap Enable, Output Enable Hold Time 5 us tw Write Enable Pulse Width 10 ms VH High Voltage 11.5 12.5 Vv NS / Erase Cycl ms rase Cycle se OE / Vin ViH WE Nv << twMicrotech SEMICONDUCTORS MS8E128 - 70/90/ 120 Software Data Protection Enable Algorithm (1) LOAD DATA AA TO ADDRESS 5555 l LOAD DATA 55 TO ADDRESS 2AAA | LOAD DATA AO TO ADDRESS 5555 l LOAD DATA XX TO ANY ADDRESS 4 I LOAD LAST BYTE TO LAST ADDRESS WRITES ENABLED ) ENTER DATA PROTECT STATE Software Data Protection Disable Algorithm LOAD DATA AA TO ADDRESS 5555 l LOAD DATA 55 TO ADDRESS 2AAA | LOAD DATA 80 TO ADDRESS 5555 | LOAD DATA AA TO ADDRESS 5555 | LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 \ Notes: TO 1. Data Format: |/O7 - |/O0 (Hex); ADDRESS 5555 EXIT DATA @) Address Format: A14 -AO (Hex). l PROTECT STATE 2. Write Protect state will be activated LOAD DATA XX at end of write even if no other data TO is loaded. ANY ADDRESS ) 3. Write Protect state will be deactivated | at end of write period even if no other LOAD LAST BYTE data is loaded TO 4. 1 to 64 bytes of data are loaded. LAST ADDRESS Ne J Write Cycle - Software Protected. OE i CE TONY EN L/h twp tWPH tBLc WE AL IN tAH > AQ - AS XBYTE ADDRESS , 555 2AAA 5555 A6 - A14 Y TE ADDRESS _ tos, DATA AA 55 Ao < BYTE 0 BYTE 62 BYTE 63 |twe| Notes: A6 through A14 must specify the page address during each high to low transition of WE (or CE) after the software code has been entered. OE must be high only when WE and CE are both low.MS8E128 Microtech -70/90/ 120 SEMICONDUCTORS ( pin Functions Pint eos sos oo$o aaa oo 0 oo 0 coo OP ee ooo View goo eo0o$d ooo aoo ooo oa0o oo860 eo 0 oo0d Pin Pin Pin Pin Pin Pin No No No No No No 1 08 12 WE2 23 15 34 D24 45 Vee 56 D31 2 pg 13 CE2 24 Dt14 35 025 46 CE4 57 D30 3 D10 14 Vss 25 Di3 36 D26 47. WE4 58 029 4 Aig 15 O11 26 Di2 37 AG 48 027 59 D28 5 A14 16 At0 27 OE 38 AT 49 AS 60 AO 6 NC 17. AN 28 NC 39 NC 50 Ad 61 Ad 7 NC 18 A12 29 WET 40 AS 51 AS 62 A2 8 NC 19 Voc 30 07 41 AQ 52 WE3 63 023 9 DO 20 CEI 31 D6 42 DI6 53 CES 64 D22 10 D1 21. NC 32 D5 43 DI7 54 Vss 65 D021 141. D2 22 D3 33 D4 44 D18 55 ~DI9 66 020 Tamron Ne mse 16Microtech MS8E128 SEMICONDUCTORS -70/90/120 AC Electrical Characteristics - Data Polling (1) ) Min Max Units toH Data Hold Time 0 ns toEH Output Enable Hold Time 0 ns toe Output Enable to Output Delay 100 ns tWR_ Write Recovery Time 0 ns Note: ~ 1. These parameters are 100% tested. J Data Polling Waveforms WE _- L f b> CE NN NOS _ -toeH OE / NIN ON toH__, WR, 07 =| [te HIGH Z / AO - A14 An An An An An (AC Electrical Characteristics - Toggle Bit (1) ) Min Max Units toH Data Hold Time 10 ns toEH Output Enable Hold Time 10 ns toe Output Enable to Output Delay 100 ns toEHP Output Enable High Pulse 150 ns twrR Write Recovery Time 0 ns Note: a 1. These parameters are 100% tested. J Toggle Bit Waveforms WE CF IN LN LN OE _toeH, po TES 4 VV YO tox} | toe. twa 1/06 oe HR lp Notes: Le __ __ 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of |/O6 will vary. 3. Any address location may be used but the address should not vary. 11 Tamim PRendtMS8E128 - 70 / 90/120 Microtech SEMICONDUCTORS MS8E128 Module Flow ASSEMBLE MS8S128 EXTERNAL VISUAL INSPECTION BS9450 1.2.10.2.2 | HIGH TEMPERATURE STORAGE BS9400 1.2.6.3 150C For 24 Hours RAPID CHANGE OF TEMPERATURE BS9400 1.2.6.13 10 CYCLES -68C TO +150C | PRE BURN-IN ELECTRICAL TESTS | BURN-IN SCREEN BS9400 1.2.9.2 160 Hours min at 125C FINAL ELECTRICAL TESTS, AC,DC & Functional at 25C | FINAL ELECTRICAL TESTS, AC,DC & Functional at Tmin/Tmax | SAMPLE MECHANICAL TESTS rn Ordering Information MS8 E 128 LEF BSS2 - 70 PROM Selectable word-width module L Low Power Consumption (Blank = Standard Power) 128k Bytes E total capacity High Endurance: 100K Write Cycle (Blank = 10K Write Cycles) F Fast Write: 3ns Write Time (Blank= 10ns Write Time) Vo Released to BS9400 (Blank = Screened in accordance with MS8 Module Flow above.) Speed - 70ns - 90ns - 120nsMicrotech Semiconductors reserves the right to make changes in its product without notice in order to improve design or performance characteristics. While the information presented in this datasheet is believed to be accurate, no liability is assumed for any data contained within. Microtech Semiconductors 1992 \3 Microtech SEMICONDUCTORS Mill Lane, Alton, HantsGU34 20G Telephone: +44(0)420 89191 Facsimile: +44(0)420 87259 24 hr Answerphone: +44(0)420 543202 Telex: 858456 A Division of Rood Technology UK Ltd. FRANCE - Sales Office Zac de Courtaboeuf 10, Avenue du Qubec, Batement E8 LP517 91946 Les Ulis France Telephone: +33 (1)69.86.19.20 Telefax: +33 (1)69.86.18.74 A Division of Rood Technology S.A.R.L. GERMANY - Sales Office WeserstraBe 20 W-4290 Bocholt Germany Telephone: +49 (0)2871 12133 Telefax: +49 (0)2871 184042 A Division of Rood Technology GmbH Oz...