
IP1000M
Product Brief
Gigabit Ethernet NIC Single Chip
Features
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PCI & DMA Features
PCI Specification Revision 2.3 compliant
32-bit, 33/66MHz bus master capability
Efficient DMA operation maximizes PCI
band-width utilization
1 Terabyte (40 bit) address space
Scatter, gather transmit/receive DMA
Transmit "interrupt-less" mode of operation
Receive frame priority interrupts
Receive interrupt coalescing
FIFO Features
No external memory required
Receive FIFO flow control thresholds
Configurable TX/RX FIFO
MAC Features
IEEE 802.3z, 802.3x compliant
IEEE 802.1p, 802.1Q compliant
1000Mbps, 100Mbps, 10Mbps triple speed,
half/full duplex operation
Transmit and receive back to back frames
at full wire speed
Half duplex carrier extension and packet
bursting
Asymmetric/symmetric flow control
VLAN tag insertion/removal
VLAN tagged frame filtering
IPV4, TCP, UDP checksum
calculation/verification
802.3 MIB statistic register sets
64-bit hash table for multicast frame filtering
Up to 10K Jumbo frame support for transmit
and receive
Phsical Layer Features
Fully integrated IEEE 802.3ab compliant
1000BASE-T, 100BASE-TX and
10BASE-T port
DSP receiver includes feed-forward
equalizer, decision feedback equalizer,
echo canceller, crosstalk canceller, and
baseline wander correction
802.3ab compliant Auto-Negotiation for
automatic speed, duplex, and master/slave
configuration
Automatic MDI/MDI-X crossover function
and polarity correction
Automatic pair skew adjustment
PHY management registers
Smart Cable Analyzer (SCA™)
Smart speed downshift
APS(Auto Power Saving)
a. Power Saving with Link status
detecting
b. Keep only MAC alive through
software setting
Power Management, EEPROM and Package
WakeOnLAN support
ACPI Revision 1.0 compliant
1.8/3.3V CMOS with 5V tolerant I/O
EEPROM 24C02 support
128-pin LQFP package
General Description
The IP1000M is a truly 10/100/1000Mbps Gigabit
Ethernet NIC single chip which it incorporates a
32-bit PCI interface with bus master support. It is
manufactured using standard digital CMOS
process and contains all the active circuitry
required to implement the physical layer functions
to transmit and receive data on standard CAT5
unshielded twisted pair cable.
The IP1000M is designed for use in a variety of
applications including workstation NICs, and other
systems utilizing a PCI bus.
The IP1000M includes a 32-bit PCI bus interface,
IEEE 802.3 compliant MAC, transmit and receive
FIFO buffers, IEEE 802.3 compliant 10BASE-T,
and 100BASE-TX PHY, IEEE 802.3z compliant
1000 BASE-T PHY, serial EEPROM interface and
LED drivers.
The IP1000M supports features for use in “Green
PCs” or systems where control over system power
consumption is desired. The IP1000M supports
several power down states, and the ability to issue
a system “wake event” via reception of unique,
user defined Ethernet frames. In addition, the
IP1000M can assert a wake event in response to
changes in the Ethernet link status.
Confidential. 1/2 Jul. 18, 2003
Copyright © 2003, IC Plus Corp. IP1000M-PB-R01