5962-8753501XA - Aeroflex Incorporated

REVISIONS

LTR DESCRIPTION DATE (YR-MO-DA) APPROVED

DAdded device type 03. Figure 1; Made corrections to the height

dimensions for case outlines Y and Z. Added Figure 2; Terminal

connections table. Redrew entire document. -sld.

00-01-31 Raymond Monnin

The original first page of this drawing has been replaced

REV

SHEET

REV DDDDD

SHEET 15 16 17 18 19

REV STATUS REV DDDDDDDDDDDDDD

OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

PMIC N/A PREPARED BY

Donald R. Osborne

STANDARD MICROCIRCUIT

DRAWING CHECKED BY

D. A. Dicenzo

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

APPROVED BY

N. A. Hauck MICROCIRCUIT, HYBRID, LINEAR, DUAL

REDUNDANT, REMOTE TERMINAL UNIT

(RTU)

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE

87-08-06

AMSC N/A REVISION LEVEL

DSIZE

ACAGE CODE

67268 5962-87535

SHEET 1 OF 19

DSCC FORM 2233

APR 97 5962-E280-99

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

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1. SCOPE

1.1 Scope. This drawing describes device requirements for class H hybrid microcircuits to be processed in accordance with MIL-

PRF-38534.

1.2 PIN. The PIN shall be as shown in the following example:

5962-87535 01 X X

   

Drawing number Device Case Lead

type outline finish

(see 1.2.1) (see 1.2.2) (see 1.2.3)

1.2.1 Device type(s). The device type(s) identify the circuit function as follows:

Device type Generic number Circuit function

01 BUS-65112 Dual redundant remote terminal (RTU)

02 2452 Dual redundant remote terminal (RTU)

03 CT2512 Dual redundant remote terminal (RTU)

1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style

XSee figure 1 78 Hybrid package

YSee figure 1 82 Flat package

ZSee figure 1 82 Flat package

1.2.3 Lead finish. The lead finish shall be as specified in MIL-PRF-38534.

1.3 Absolute maximum ratings. 1/

Logic Supply voltage (VL)................................................................. 5.5 V dc

Positive supply voltage (VCC)............................................................ 18.0 V dc

Negative supply voltage (VEE)........................................................... -18.0 V dc

Storage temperature range .............................................................. -65°C to +150°C

Thermal rise, case to junction (∆TJ)................................................. 13.9°C

Lead soldering temperature (10 seconds) ....................................... +300°C

Power dissipation (TC = +125°C) ..................................................... Duty cycle dependent (see table I power supplies)

1.4 Recommended operating conditions.

Logic Supply voltage range (VL)....................................................... +4.5 V dc to +5.5 V dc

Positive supply voltage range (VCC).................................................. +14.25 V dc to +15.75 V dc

Negative supply voltage (VEE)........................................................... -14.25 V dc to -15.75 V dc

Case operating temperature range (TC)........................................... -55°C to +125°C

Maximum differential input voltage.................................................... 40 Vp-p

1/Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the

maximum levels may degrade performance and affect reliability.

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2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of

this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue

of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation.

SPECIFICATION

DEPARTMENT OF DEFENSE

MIL-PRF-38534 - Hybrid Microcircuits, General Specification for.

STANDARDS

DEPARTMENT OF DEFENSE

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-973 - Configuration Management.

MIL-STD-1553 - Interface Standard for Digital Time Division Command/Response Multiplex Data Bus.

MIL-STD-1835 - Interface Standard for Microcircuit Case Outlines.

HANDBOOKS

DEPARTMENT OF DEFENSE

MIL-HDBK-103 - List of Standard Microcircuits Drawings (SMD's).

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific

exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item performance requirements shall be in accordance with MIL-PRF-38534.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38534 and herein.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Block diagram. The block diagram shall be as specified on figure 3.

3.2.4 Pin functions. Pin functions shall be as specified in table III.

3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as

specified in table I and shall apply over the full specified operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests

for each subgroup are defined in table I.

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3.5 Marking of Device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with

the PIN listed in 1.2 herein. In addition, the manufacturer's vendor similar PIN may also be marked.

3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described

herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for

each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if

any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made

available to the preparing activity (DSCC-VA) upon request.

3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing.

The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturer's product meets the

performance requirements of MIL-PRF-38534 and herein.

3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of

microcircuits delivered to this drawing.

4. QUALITY ASSURANCE PROVISIONS

4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as modified

in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or

function as described herein.

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TABLE I. Electrical performance characteristics.

Test Symbol Conditions 1/

-55°C ≤TC ≤+125°C

unless otherwise specified

Group A

subgroups Device

type Limits Unit

Min Max

Receiver

Differential input impedance ZIN diff DC to 1 MHz 2/All 4 kΩ

Differential input voltage VIN diff 2/All 40 Vp-p

Input threshold VTH Direct coupled,

(across 35Ω load) 4,5,6 All 1.2 Vp-p

Common mode rejection

ratio CMRR DC to 2 MHz 2/ 3/All 40 dB

Common mode voltage CMV DC to 2 MHz 2/ 3/All -10 +10 V

Transmitter

Differential output voltage VOUT

diff Direct coupled,

(across 35Ω load) 4,5,6 All 6.0 9.0 Vp-p

Output rise and fall time tr, tf9,10,11 01 100 180 ns

02,03 100 300 ns

Output noise NOUT 2/ 3/All 14 mVp-p

Logic

High level input voltage VIH VL = 5.5 V 1,2,3 All 2.4 V

Low level input voltage VIL VL = 5.5 V 1,2,3 All 0.7 V

High level input current 4/IIH VL = 5.5 V, VIH = 2.7 V 1,2,3 All -0.7 -0.03 mA

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.

Test Symbol Conditions 1/

-55°C ≤ TC ≤+125°C

unless otherwise specified

Group A

subgroups Device

type Limits Unit

Min Max

High level input current 5/IIH VL = 5.5 V, VIH = 2.7 V 1,2,3 01,03 -20 +20 µA

02 -300 +20

Low level input current 4/IIL VL = 5.5 V, VIL = 0.4 V 1,2,3 01,03 -1.6 -.09 mA

02 -1.6 +.02

Low level input current 5/IIL VIL = 0.4 V 1,2,3 01,03 -20 +20 µA

02 -300 +20

High level output voltage 6/VOH VL = 4.5 V, IOH = 0.3 mA 1,2,3 All 2.7 V

High level output voltage 7/VOH VL = 4.5 V, IOH = 3 mA 1,2,3 All 2.7 V

Low level output voltage 8/VOL VL = 4.5 V, IOL = -1.6 mA 1,2,3 All 0.4 V

Low level output voltage 9/VOL VL = 4.5 V, IOL = -4mA 1,2,3 All 0.4 V

Low level output voltage 7/VOL VL = 4.5 V, IOL = -6 mA 1,2,3 All 0.4 V

Functional test 10/7,8 All pass/

fail

Input capacitance CIf = 1 MHz see 4.3.1c All 50 pF

Input/output capacitance 7/CIO f = 1 MHz see 4.3.1c All 50 pF

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.

Test Symbol Conditions 1/

-55°C ≤ TC ≤+125°C

unless otherwise specified

Group A

subgroups Device

type Limits Unit

Min Max

Power supplies

+5 V dc current drain ILVL = +5.5 V dc, Inputs = 0 V

dc, except 12 MHz clock

input active, All outputs

open

1,2,3 All 160 mA

-15 V dc current drain IEE VEE = -15.75 V dc 1,2,3 All 60 mA

+15 V dc current drain

- idle

- 25% transmit

- 50% transmit

-100% transmit

ICC VCC = +15.75 V dc

1,2,3

All

130

180

280

1/VCC = +15 V, VEE = -15 V, VL = + 5 V unless otherwise specified.

2/This parameter is not tested, but is guaranteed by design.

3/Receiver and transmitter parameters are specified with transformer.

4/IIH and IIL for input pins BRO ENA, ADDRE, ADDRC, ADDRA, ADDRD, ADDRB, and ADDRP.

5/IIH and IIL for all input pins other than in note 4.

6/VOH for all output pins other than in note 7.

7/VOL, VOH, and CIO for pins DB0 through DB15.

8/VOL for output pins A10, A8, A6, HSFAIL, A5, RTFAIL, A11, BITEN, NBGT, A9, A7, GBR, ME, STATEN.

9/VOL for output pins RTADERR, A3, A1, INCMD, DTSTR, DTREQ, A2, A0, DTACK, A4, R/W.

10/Functional tests are performed to verify functionality to MIL-STD-1553 RTU protocol.

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Case X

Inches mm

.018 0.45

.050 1.27

.056 1.42

.075 1.91

.100 2.54

.11 2.8

.25 6.4

1.500 38.10

1.650 41.91

1.800 45.72

1.870 47.50

1.900 48.26

2.100 53.34

FIGURE 1. Case outline(s).

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Case Y

Inches mm

.002 0.05

.003 0.07

.010 0.25

.015 0.38

.050 1.27

.080 2.03

.095 2.41

.171 4.34

.400 10.16

1.600 40.64

2.000 50.80

2.190 55.62

FIGURE 1. Case outline(s) - Continued.

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Case Z

Inches mm

.002 0.05

.003 0.07

.010 0.25

.015 0.38

.050 1.27

.095 2.41

.105 2.66

.200 5.08

.400 10.16

1.600 40.64

2.190 55.62

NOTES:

1. Dimensions are in inches.

2. Metric equivalents are given for general information only.

3. Unless otherwise specified, tolerance is ±.005 (0.13 mm) for three decimals and ±.100 (0.25 mm) for

two place decimals.

4. Case Z is a conductive package.

FIGURE 1. Case outline(s) - Continued.

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Device types 01, 02, and 03

Case outlines XY and Z Case outlines XY and Z

Terminal number Terminal symbol Terminal number Terminal symbol

A10

DB1

DB3

DB5

DB7

DB9

DB11

DB13

DB15

BRO ENA

ADDRE

ADDRC

ADDRA

RTADERR

TXDATAOUT B

VCC B

GND B

RXDATA

DTGRT

INCMD

HSFAIL

DTSTR

RTFAIL

DTREQ

ADBC

TEST 2

A11

ILLCMD

SRQ

BITEN

RXDATAIN A

VL A

VEE A

TXDATAOUT A

NBGT

A10

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

DB12

DB13

DB14

DB15

BRO ENA

GND

ADDRE

ADDRD

ADDRC

ADDRB

ADDRA

ADDRP

RTADERR

TXDATAOUT B

VEE B

VCC B

VL B

GND B

RXDATAIN B

DB0

DB2

DB4

DB6

DB8

DB10

DB12

DB14

GND

ADDRD

ADDRB

ADDRP

TXDATAOUT B

VEE B

VL B

RXDATAIN B

DTACK

R/W

GBR

12 MHz IN

BUF ENA

RESET

RTFLAG

TEST 1

BUSY

SSFLAG

RXDATAIN A

GNDA

VCC A

TXDATAOUT A

STATEN

- - -

NBGT

STATEN

TXDATAOUT A

VEE A

VCC A

VL A

GNDA

RXDATAIN A

RXDATA A

BITEN

SRQ

SSFLAG

ILLCMD

BUSY

A11

TEST 1

TEST 2

RTFLAG

ADBC

RESET

DTREQ

BUF ENA

RTFAIL

12 MHz IN

GBR

DTSTR

R/W

HSFAIL

INCMD

DTACK

DTRGT

FIGURE 2. Terminal connections.

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NOTE: For most user applications, DTACK can be connected directly to BUF ENA.

FIGURE 3. Block diagram.

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TABLE II. Electrical test requirements.

MIL-PRF-38534 test requirements Subgroups

(in accordance with

MIL-PRF-38534, group A test

table)

Interim electrical parameters 1, 4, 7, 9

Final electrical parameters 1*, 2 ,3 ,4 ,5 ,6 ,9, 10, 11

Group A test requirements 1, 2, 3, 4, 5, 6, 9, 10, 11

Group C end-point electrical

parameters 1, 2, 3

End-point electrical parameters for

Radiation Hardness Assurance

(RHA) devices

Not applicable

* PDA applies to subgroup 1.

4.2 Screening. Screening shall be in accordance with MIL-PRF-38534. The following additional criteria shall apply:

a.Burn-in test, method 1015 of MIL-STD-883.

(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level

control and shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test

method 1015 of MIL-STD-883.

(2) TA as specified in accordance with table I of method 1015 of MIL-STD-883.

b.Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests

prior to burn-in are optional at the discretion of the manufacturer.

4.3 Conformance and periodic inspections. Conformance inspection (CI) and periodic inspection (PI) shall be in accordance

with MIL-PRF-38534 and as specified herein.

4.3.1 Group A inspection (CI). Group A inspection shall be in accordance with MIL-PRF-38534 and as follows:

a.Tests shall be as specified in table II herein.

b.Subgroups 7 and 8 shall be omitted.

c.Subgroup 4 (CI and CIO measurement ) shall be measured only for the initial test and after process or design changes

which may affect input and output capacitance.

4.3.2 Group B inspection (PI). Group B inspection shall be in accordance with MIL-PRF-38534.

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4.3.3 Group C inspection (PI). Group C inspection shall be in accordance with MIL-PRF-38534 and as follows:

a.End-point electrical parameters shall be as specified in table II herein.

b.Steady-state life test, method 1005 of MIL-STD-883.

(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level

control and shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test

method 1005 of MIL-STD-883.

(2) TA as specified in accordance with table I of method 1005 of MIL-STD-883.

(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.

4.3.4 Group D inspection (PI). Group D inspection shall be in accordance with MIL-PRF-38534.

4.3.5 Radiation Hardness Assurance (RHA) inspection. RHA inspection is not currently applicable to this drawing.

5. PACKAGING

5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38534.

6. NOTES

6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original

equipment), design applications, and logistics purposes.

6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared

specification or drawing.

6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the

individual documents. This coordination will be accomplished in accordance with MIL-STD-973 using DD Form 1692, Engineering

Change Proposal.

6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application

requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for

coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should

contact DSCC-VA, telephone (614) 692-0544.

6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614)

692-0512.

6.6 Sources of supply. Sources of supply are listed in MIL-HDBK-103 and QML-38534. The vendors listed in MIL-HDBK-103

and QML-38534 have submitted a certificate of compliance (see 3.7 herein) to DSCC-VA and have agreed to this drawing.

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TABLE III. Pin functions.

Function Description

A10 Latched output of the most significant bit (MSB) in the subaddress field of the

command word.

A8 Latched output of the third most significant bit in the subaddress field of the

command word.

A6 Latched output of the least significant bit (LSB) in the subgroups field of the

command word.

DB1 Bi-directional parallel data bus bit 1.

DB3 Bi-directional parallel data bus bit 3.

DB5 Bi-directional parallel data bus bit 5.

DB7 Bi-directional parallel data bus bit 7.

DB9 Bi-directional parallel data bus bit 9.

DB11 Bi-directional parallel data bus bit 11.

DB13 Bi-directional parallel data bus bit 13.

DB15 Bi-directional parallel data bus bit 15 (MSB).

BRO ENA Broadcast enable - When HIGH, this input allows recognition of an RT address of all

ones in the command word as a broadcast message. When LOW , it prevents

response to address 31 unless it was the assigned terminal address.

ADDRE Input of the MSB of the assigned terminal address.

ADDRC Input of the 3rd MSB of the assigned terminal address.

ADDRA Input of the LSB of the assigned terminal address.

RTADERR Output signal used to inform subsystem of an address parity error. If LOW, indicates

parity error and the RT will not respond to any command address to a single terminal. It

will respond to broadcast commands if BRO ENA is HIGH.

TXDATAOUT B LOW output to the primary side of the coupling transformer that connects to the

channel B of the 1553 bus.

VCC B +15 volt input power supply connection for the B channel transceiver.

GND B Power supply return connection for the B channel transceiver.

RXDATA Input from the HIGH side of the primary side of the coupling transformer that connects

to the B channel of the 1553 bus.

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TABLE III. Pin functions - Continued.

Function Description

A3 Multiplexed address line output. When INCMD is LOW, or A6 through A10 are all

zeroes or all ones (mode command), it represents the latched output of the 2nd MSB

in the word count field of the command word. When INCMD is HIGH and A6

through A10 are not all zeroes or all ones, it represents the 2nd LSB of the current

word counter.

A1 Multiplexed address line output. When INCMD is LOW, or A6 through A10 are all

zeroes or all ones (mode command) , it represents the latched output of the 2nd LSB

in the word count field of the command word. When INCMD is HIGH and A6

through A10 are not all zeroes or all ones, it represents the 2nd LSB of the current

word counter.

DTGRT Data transfer grant - Active LOW input signal from the subsystem that informs the

RT, when DTREQ is asserted, to start transfer. Once the transfer is started, DTGRT

can be removed.

INCMD In command - HIGH level output signal used to inform the subsystem that the RT is

presently servicing a command. When low, A0-A4 represent the word count of the

present command. When high, A0-A4 represent the current word counter of non-

mode commands.

HSFAIL Handshake fail - Output signal that goes LOW and stays LOW whenever the

subsystem fails to supply DTGRT in time to do a successful transfer. Cleared by the

next NBGT.

DTSTR DATA strobe - A LOW level output pulse (166 ns) present in the middle of every data

word transfer over the parallel data bus. Used to latch or strobe the data into

memory, FIFOs, registers, etc. Recommend using the rising edge to clock data in.

A5 Address line output that is LOW whenever the command word is being transferred to

the subsystem over the parallel data bus, and is HIGH whenever data words are

being transferred.

RTFAIL Remote terminal failure - latched active LOW output signal to the subsystem to flag

detection of a remote terminal continuous self-test failure. Cleared by the start of the

next message transmission (status word) and set if problem is again detected.

DTREQ Data transfer request - Active LOW output signal to the subsystem indicating that the

RT has data for or needs data from the subsystem and requests a data transfer over

the parallel data bus. Will stay low until transfer timeout has occurred.

ADBC Accept dynamic bus control - Active LOW input signal from subsystem used to set

the dynamic bus control acceptance bit in the status register if the command word

was a valid, legal mode command for dynamic bus control.

TEST 2 Factory test point - DO NOT USE.

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TABLE III. Pin functions - Continued.

Function Description

A11

Latched output of the T/R bit in the command word.

ILLCMD Illegal command - Active LOW input signal from the subsystem, strobes in on the

rising edge of INCMD. Used to define the command word as illegal and to set the

message error bit in the status register.

SRQ Subsystem service request - Input from the subsystem used to control the service

request bit in the status register. If LOW when the status word is updated, the

service request bit will be set; if HIGH, it will be cleared.

BITEN Built-in-test word enable - LOW level output pulse (.5 µs), present when the built-in-

test word is enabled on the parallel data bus.

RXDATAIN A Input from the LOW side of the primary side of the coupling transformer that

connects to the A channel of the 1553 bus.

VL A +5 volt input power supply connection for the A channel transceiver.

VEE A -15 volt input power supply connection for the A channel transceiver.

TXDATAOUT A HIGH output to the primary side of the coupling transformer that connects to the A

channel of the 1553 bus.

NBGT New bus grant - LOW level output pulse (166 ns) used to indicate the start of a new

protocol sequence in response to the command word just received.

A9 Latched output of the 2nd MSB in the subaddress field of the command word.

A7 Latched output of the 2nd LSB in the subaddress field of the command word.

DB0 Bi-directional parallel data bus bit 0 (LSB).

DB2 Bi-directional parallel data bus bit 2.

DB4 Bi-directional parallel data bus bit 4.

DB6 Bi-directional parallel data bus bit 6.

DB8 Bi-directional parallel data bus bit 8.

DB10 Bi-directional parallel data bus bit 10.

DB12 Bi-directional parallel data bus bit 12.

DB14 Bi-directional parallel data bus bit 14.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A5962-87535

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

REVISION LEVEL

DSHEET 18

DSCC FORM 2234

APR 97

TABLE III. Pin functions - Continued.

Function Description

VL+5 volt input power supply connection for RTU digital logic section.

GND Power supply return RTU digital logic connection.

ADDRD Input of the 2nd MSB of the assigned terminal address.

ADDRB Input of the 2nd LSB of the assigned terminal address.

ADDRP Input of address parity bit. The combination of assigned terminal address and ADDRP

must be odd parity for the RT to work.

TXDATAOUT B HIGH, output to the primary side of the coupling transformer that connects to the B

channel of the 1553 bus.

VEE B -15 volt input power supply connection for the B channel transceiver.

VL B +5 volt input power supply connection for the B channel transceiver.

RXDATAIN B Input from the LOW side of primary side of the coupling transformer that connects to the

B channel of the 1553 bus.

A2 Multiplexed address line output. When INCMD is LOW, or A6 through A10 are all

zeroes or all ones (mode command), it represents the latched output of the 3rd MSB in

the word count field of the command word. When INCMD is HIGH and A6 through A10

are not all zeroes or all ones, it represents the 3rd MSB of the current word counter.

A0 Multiplexed address line output. When INCMD is LOW, or A6 through A10 are all

zeroes or all ones (mode command), it represents the latched output of the MSB in the

word count field of the command. When INCMD is HIGH and A6 through A10 are not

all zeroes or all ones, it represents the LSB of the current word counter.

DTACK Data transfer acknowledge - Active LOW output signal during data transfers to or from

the subsystem indicating the RTU has received the DTGRT in response to DTREQ and

is presently doing the transfer. Can be connected directly to (BUF ENA) for control of 3-

state data buffers; and to 3-state address buffer control lines, if they are used.

A4 Multiplexed address line output. When INCMD is LOW or A6 through A10 are all zeroes

or all ones (mode command), it represents the latched output of the MSB in the word

count field of the command word. When INCMD is HIGH and A6 through A10 are not

all zeroes or all ones, it represents the MSB of the current word counter.

R/W

Read/Write - Output signal that controls the direction of the internal data bus buffers.

Normally, the signal is LOW and the buffers drive the data bus. When data is needed

from the subsystem, it goes HIGH to turn the buffers around and the RT now appears as

an input. The signal is HIGH only when DTREQ is active (LOW).

STANDARD

MICROCIRCUIT DRAWING

SIZE

A5962-87535

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

REVISION LEVEL

DSHEET 19

DSCC FORM 2234

APR 97

TABLE III. Pin functions - Continued.

Function Description

GBR Good block received - LOW level output pulse (.5 µs) used to flag the subsystem that a

valid, legal, non-mode receive command with the correct number of data words has

been received without a message error and successfully transferred to the subsystem.

12 MHz IN 12 MHz clock input - Input for the master clock used to run RTU circuits.

BUF ENA Buffer enable - Input used to enable or 3-state the internal data bus buffers when they

are driving the bus. When LOW, the data bus buffers are enabled. Could be connected

to DTACK if RT is sharing the same data bus as the subsystem.

RESET Input resets entire RT when low.

RTFLAG Remote terminal flag - Input signal used to control the terminal flag bit in the status

HIGH, it would be cleared. Normally connected to RTFAIL.

TEST 1 Factory test point - DO NOT USE.

BUSY Subsystem busy - Input from the from the subsystem used to control the busy bit in the

status register. If LOW when the status word is updated, the busy bit will be set; if

HIGH, it will be cleared. If the busy bit is set in the status register, no data will be

requested from the subsystem in response to a transmit command. On receive

commands data will still be transferred to subsystem. For (device type 01 only) on

recieve commands data will be requested from the subsystem in response to transmit

command.

SSFLAG Subsystem flag, Input from the subsystem used to control the subsystem flag bit in the

status register. If LOW when the status word is updated, the subsystem flag will be set;

if HIGH, it will be cleared.

ME Message error - Output signal that goes LOW and stays low whenever there is a format

or word error with the received message over the 1553 data bus. Cleared by the next

NBGT.

RXDATAIN A Input from the HIGH side of the primary side of the coupling transformer that contacts to

the A channel of the 1553 bus.

GNDA Power supply return connection for the A channel transceiver.

VCC A +15 volt input power supply connection for the A channel transceiver.

TXDATAOUT A LOW output to the primary side of the coupling transformer that connects to the A

channel of the 1553 bus.

STATEN Status word enable - Low level active output signal present when the status word is

enabled on the parallel data bus.

STANDARD MICROCIRCUIT DRAWING BULLETIN

DATE: 00-01-31

Approved sources of supply for SMD 5962-87535 are listed below for immediate acquisition information only and shall

be added to MIL-HDBK-103 and QML-38534 during the next revisions. MIL-HDBK-103 and QML-38534 will be revised

to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of

compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revisions

of MIL-HDBK-103 and QML-38534.

Standard

microcircuit drawing

PIN 1/

Vendor

CAGE

number

Vendor

similar

PIN 2/

5962-8753501XA

5962-8753501XC

5962-8753501YA

5962-8753501YC

19645

BUS-65112

BUS-65117

5962-8753502XA

5962-8753502XC

5962-8753502XX 3/

5962-8753502YA

5962-8753502YC

5962-8753502YX 3/

88379

ARX2542-001-2

ARX2542-001-1

ARX2542-001-3

ARX2542-202-2

ARX2542-202-1

ARX2452-202-3

5962-8753503XA

5962-8753503XC

5962-8753503XX 3/

5962-8753503ZA

5962-8753503ZC

5962-8753503ZX 3/

88379

CT-2512-001-2

CT-2512-001-1

CT-2512-001-3

CT-2512-201-2

CT-2512-201-1

CT-2512-201-3

1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the

manufacturer listed for that part. If the desired lead finish is not listed contact the Vendor to determine its

availability.

2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the

performance requirements of this drawing.

3/ This device is available with lead finishes A or C.

Vendor CAGE Vendor name

number and address

50821 ILC Data Device Corporation

105 Wilbur Place

Bohemia, NY 11716

88379 Aeroflex Circuit Technology

35 South Service Road

Plainview NY, 11803

The information contained herein is disseminated for convenience only and the

Government assumes no liability whatsoever for any inaccuracies in the

information bulletin.