LPC11C14FBD48/301, - NXP Semiconductors

1. General description

The LPC11Cx2/Cx4 are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed

for 8/16-bit microcontroller applications, offering performance, low power, simple

instruction set and memory addressing together with reduced code size comp ared to

existing 8/16-bit architectures.

The LPC11Cx2/Cx4 operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC11Cx2/Cx4 includes 16/32 kB of flash memory,

8 kB of data memory, one C_CAN controller, one Fast-mode Plus I2C-bus interface, one

RS-485/EIA-485 UART, two SPI interfaces with SSP features, four general purpose

counter/timers, a 10-bit ADC, and up to 40 general purpose I/O pins.

On-chip C_CAN drivers and flash In-System Programming tools via C_ CAN are included.

In addition, the LPC11C22 and LPC11C24 parts include an on-chip, high-speed CAN

transceiver.

2. Features and benefits

System:

ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

Serial Wire Debug.

System tick timer.

Memory:

32 kB (LPC11Cx4) or 16 kB (LPC11Cx2) on-chip flash program memo ry.

8 kB SRAM data memory.

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

Flash ISP commands can be issued via UART or C_CAN.

Digital peripherals:

General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.

40 GPIO pins on the LPC11C12/C14 parts; 36 GPIO pins on the LPC11C22/C24

parts.

GPIO pins can be used as edge and level sensitive interrupt sources.

High-current output driver (20 mA) on one pin.

High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.

Four general pu rp os e co un te r/ tim er s wi th a total of four cap tu re inpu ts and 13

(LPC11C12/C14) or 12 (LPC11C22/C24) match outputs.

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB

SRAM; C_CAN

Rev. 3 — 27 June 2011 Product data sheet

Product data sheet Rev. 3 — 27 June 2011 2 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Programmable WatchDog Timer (WDT).

Analog peripherals:

10-bit ADC with input multiplexing among 8 pins.

Serial interfaces:

UART with fractional baud rate generation, internal FIFO, and RS-485 support.

Two SPI controllers with SSP features and with FIFO and multi-protocol

capabilities.

I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

C_CAN controller. On-chip C_CAN and CANopen drivers included.

On-chip, high-speed CAN transceiver (parts LPC11C22/C24 only).

Clock generation :

12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used

as a system clock.

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

Clock output function with divider that can reflect the system oscillator, IRC, CPU

clock, or the Watchdog clock.

Power control:

Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

Processor wake-up from Deep-sleep mode via a dedicated start logic using 13 of

the GPIO pins.

Power-On Reset (POR).

Brownout detect with four separate thresholds for interrupt and forced reset.

Unique device serial number for identification.

Single 3.3 V power supply (1.8 V to 3.6 V).

Available as 48-pin LQFP package.

3. Applications

eMetering Industrial and sensor based networks

Elevator systems White goods

Product data sheet Rev. 3 — 27 June 2011 3 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

LPC11C12FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC11C14FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC11C22FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC11C24FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

Table 2. Ordering options

Type number Flash Total

SRAM UART

RS-485 I2C/

Fast+ SPI C_CAN C_CAN with

on-chip

CAN

transceiver

GPIO

pins ADC

channels Package

LPC11C12FBD48/301 16 kB 8 kB 1 1 2 1 no 40 8 LQFP48

LPC11C14FBD48/301 32 kB 8 kB 1 1 2 1 no 40 8 LQFP48

LPC11C22FBD48/301 16 kB 8 kB 1 1 2 1 yes 36 8 LQFP48

LPC11C24FBD48/301 32 kB 8 kB 1 1 2 1 yes 36 8 LQFP48

Product data sheet Rev. 3 — 27 June 2011 4 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

5. Block diagram

(1) CT16B1_MAT0 not available on parts LPC11C22/C24.

Fig 1. LPC11Cx2/Cx4 block diagram

SRAM

8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

16/32 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT RESET

clocks and

controls

SWD

LPC11Cx2/Cx4

002aaf265

slave

slave slave

ROM

slave

AHB-LITE BUS

GPIO ports

PIO0/1/2/3

CLKOUT

IRC

POR

SPI0

10-bit ADC

UART

32-bit COUNTER/TIMER 0

I2C-BUS

WDT

IOCONFIG

CT32B0_MAT[3:0]

AD[7:0]

CT32B0_CAP0

SDA

SCL

RXD

TXD

DTR, DSR, CTS,

DCD, RI, RTS

SYSTEM CONTROL

PMU

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

CT32B1_CAP0

16-bit COUNTER/TIMER 1

CT16B1_MAT[1:0](1)

CT16B1_CAP0

C_CAN (LPC11C12/C14)

CAN_TXD

CAN_RXD

C_CAN/

ON-CHIP TRANSCEIVER

(LPC11C22/C24)

CANL, CANH

STB

VCC, VDD_CAN

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP0

SCK0, SSEL0

MISO0, MOSI0

SCK1, SSEL1

MISO1, MOSI1

SPI1

system bus

Product data sheet Rev. 3 — 27 June 2011 5 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

6. Pinning information

6.1 Pinning

Fig 2. Pin configu ration (LPC11C12/C14)

LPC11C12FBD48/301

LPC11C14FBD48/301

PIO2_6 PIO3_0/DTR

PIO2_0/DTR/SSEL1 R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

R/PIO0_11/AD0/CT32B0_MAT3

XTALIN PIO2_11/SCK0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0

PIO2_7 PIO2_2/DCD/MISO1

PIO2_8 PIO2_10

PIO2_1/DSR/SCK1 PIO3_3/RI

PIO0_3 PIO1_7/TXD/CT32B0_MAT1

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

PIO1_9/CT16B1_MAT0 V

PIO2_4 PIO3_2/DCD

CAN_RXD PIO1_11/AD7

CAN_TXD V

PIO2_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_6/SCK0 SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO0_7/CTS

PIO2_9

PIO2_3/RI/MOSI1

PIO3_1/DSR

002aaf266

Product data sheet Rev. 3 — 27 June 2011 6 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Fig 3. Pin configu ration (LPC11C22/C24)

LPC11C22FBD48/301

LPC11C24FBD48/301

PIO2_6 PIO3_0/DTR

PIO2_0/DTR/SSEL1 R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

VSS R/PIO0_11/AD0/CT32B0_MAT3

XTALIN PIO2_11/SCK0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0

PIO2_7 PIO2_2/DCD/MISO1

PIO2_8 PIO2_10

PIO2_1/DSR/SCK1 PIO3_3/RI

PIO0_3 PIO1_7/TXD/CT32B0_MAT1

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

VDD_CAN VDD

CANL PIO3_2/DCD

CANH PIO1_11/AD7

VCC VSS

GND PIO1_4/AD5/CT32B1_MAT3/WAKEUP

STB SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO0_6/SCK0

PIO0_7/CTS

PIO2_3/RI/MOSI1

PIO3_1/DSR

002aaf909

Product data sheet Rev. 3 — 27 June 2011 7 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

6.2 Pin description

Table 3. L P C11C12/C14 pin description table

Symbol Pin Start

logic

inputs

Type Reset

state

[1]

Description

PIO0_0 to PIO0_11 Port 0 — Port 0 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 0 pins depends

on the function selected through the IOCONFIG register block.

RESET/PIO0_0 3[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going

pulse as short as 50 ns on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and processor

execution to begin at address 0.

I/O - PIO0_0 — General purpose digi tal input/output pin with 10 ns glitch

filter.

PIO0_1/CLKOUT/

CT32B0_MAT2 4[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on

this pin during reset starts the flash ISP command handler via UART

(if PIO0_3 is HIGH) or via C_CAN (if PIO0_3 is LOW).

O- CLKOUT — Clockout pin.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2/SSEL0/

CT16B0_CAP0 10[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.

I/O - SSEL0 — Slave Select for SPI0.

I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3 14[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. This pin is

monitored during reset: Together with a LOW level on pin PIO0_1, a

LOW level starts the flash ISP command handler via C_CAN and a

HIGH level starts the flash ISP command handler via UART.

PIO0_4/SCL 15[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only

if I2C Fast-mode Plus is selected in the I/O configuration register.

PIO0_5/SDA 16[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only

if I2C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/SCK0 22[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO0_7/CTS 23[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current

output driver).

I- CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0 27[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.

I/O - MISO0 — Master In Slave Out for SPI0.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI0/

CT16B0_MAT1 28[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.

I/O - MOSI0 — Master Out Slave In for SPI0.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

29[3] yes I I; PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

Product data sheet Rev. 3 — 27 June 2011 8 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

R/PIO0_11/

AD0/

CT32B0_MAT3

32[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO0_11 — General purpose digital input/output pin.

I- AD0 — A/D converter, input 0.

O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

PIO1_0 to PIO1_11 Port 1 — Port 1 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 1 pins depends

on the function selected through the IOCONFIG register block.

R/PIO1_0/AD1/

CT32B1_CAP0 33[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_0 — General purpose digital input/output pin.

I- AD1 — A/D converter, input 1.

I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R/PIO1_1/AD2/

CT32B1_MAT0 34[5] no - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_1 — General purpose digital input/output pin.

I- AD2 — A/D converter, input 2.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/AD3/

CT32B1_MAT1 35[5] no - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_2 — General purpose digital input/output pin.

I- AD3 — A/D converter, input 3.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

39[5] no I/O I; PU SWDIO — Serial wire debug input/output.

I/O - PIO1_3 — General purpose digital input/output pin.

I- AD4 — A/D converter, input 4.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

40[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch

filter.

I- AD5 — A/D converter, input 5.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I- WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch

filter. This pin must be pu lled HIGH externally to enter Deep

power-down mode and pulled LOW to exit Deep power-down mode.

A LOW-going pulse as short as 50 ns wakes up the part.

PIO1_5/RTS/

CT32B0_CAP0 45[3] no I/O I; PU PIO1_5 — General purpose digital input/output pin.

O- RTS — Request To Send output for UART.

I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6/RXD/

CT32B0_MAT0 46[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.

I- RXD — Receiver input for UART.

O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

Table 3. L P C11C12/C14 pin description table

Symbol Pin Start

logic

inputs

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 27 June 2011 9 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

PIO1_7/TXD/

CT32B0_MAT1 47[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.

O- TXD — Transmitter output for UART.

O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/

CT16B1_CAP0 9[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

PIO1_9/

CT16B1_MAT0 17[3] no I/O I; PU PIO1_9 — General purpose digital input/output pin.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO1_10/AD6/

CT16B1_MAT1 30[5] no I/O I; PU PIO1_10 — General purpose digital input/output pin.

I- AD6 — A/D converter, input 6.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_11/AD7 42[5] no I/O I; PU PIO1_11 — General purpose digital input/output pin.

I- AD7 — A/D converter, input 7.

PIO2_0 to PIO2_11 Port 2 — Port 2 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 2 pins depends

on the function selected through the IOCONFIG register block.

PIO2_0/DTR/

SSEL1 2[3] no I/O I; PU PIO2_0 — General purpose dig ital input/ou tput pin.

I/O - DTR — Data Terminal Rea dy output for UART.

I/O - SSEL1 — Slave Select for SPI1.

PIO2_1/DSR/SCK1 13[3] no I/O I; PU PIO2_1 — General purpose digital input/output pin.

I- DSR — Data Set Ready input for UART.

I/O - SCK1 — Serial clock for SPI1.

PIO2_2/DCD/

MISO1 26[3] no I/O I; PU PIO2_2 — General pu rpose digital input/output pin.

I- DCD — Data Carrier Detect input for UART.

I/O - MISO1 — Master In Slave Out for SPI1.

PIO2_3/RI/MOSI1 38[3] no I/O I; PU PIO2_3 — General purpose digital input/output pin.

I- RI — Ring Indicator input for UART.

I/O - MOSI1 — Master Out Slave In for SPI1.

PIO2_4 18[3] no I/O I ; PU PIO2_4 — General purpose digital input/output pin.

PIO2_5 21[3] no I/O I ; PU PIO2_5 — General pu rpose digital input/output pin.

PIO2_6 1[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin.

PIO2_7 11[3] no I/O I; PU PIO2_7 — General purpose dig ital input/ou tput pin.

PIO2_8 12[3] no I/O I ; PU PIO2_8 — General pu rpose digital input/output pin.

PIO2_9 24[3] no I/O I ; PU PIO2_9 — General pu rpose digital input/output pin.

PIO2_10 25[3] no I/O I ; PU PIO2_10 — General purpose digital input/output pin.

PIO2_11/SCK0 31[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO3_0 to PIO3_3 Port 3 — Port 3 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 3 pins depends

on the function selected through the IOCONFIG register block. Pins

PIO3_4 to PIO3_11 are not av ailable.

Table 3. L P C11C12/C14 pin description table

Symbol Pin Start

logic

inputs

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 27 June 2011 10 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive,

no pull-up/down enabled.

[2] See Figure 26 for reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-d own

mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 25).

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 25).

[6] 5 V tolerant digital I/O pad without pull-up/pull-down resistors.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

PIO3_0/DTR 36[3] no I/O I; PU PIO3_0 — General purpose digital input/output pin.

O- DTR — Data Terminal Rea dy output for UART.

PIO3_1/DSR 37[3] no I/O I; PU PIO3_1 — General pu rpose digital input/output pin.

I- DSR — Data Set Ready input for UART.

PIO3_2/DCD 43[3] no I/O I; PU PIO3_2 — General pu rpose digital input/output pin.

IDCD — Data Carrier Detect input for UART.

PIO3_3/RI 48[3] no I/O I; PU PIO3_3 — General pu rpose digital input/output pin.

I- RI — Ring Indicator input for UART.

CAN_RXD 19[6] no I I; IA CAN_RXD — C_CAN receive data input.

CAN_TXD 20[6] no O I; IA CAN_TXD — C_CAN transmit data output.

VDD 8; 44 - I - Supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

XTALIN 6[7] - I - Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

XTALOUT 7[7] - O - Output from the oscillator amplifier.

VSS 5; 41 - I - Ground.

Table 3. L P C11C12/C14 pin description table

Symbol Pin Start

logic

inputs

Type Reset

state

[1]

Description

Table 4. L P C11C22/C24 pin description table

Symbol Pin Start

logic

inputs

Type Reset

state

[1]

Description

PIO0_0 to PIO0_11 Port 0 — Port 0 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 0 pins depends

on the function selected through the IOCONFIG register block.

RESET/PIO0_0 3[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going

pulse as short as 50 ns on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and processor

execution to begin at address 0.

I/O - PIO0_0 — General purpose digi tal input/output pin with 10 ns glitch

filter.

Product data sheet Rev. 3 — 27 June 2011 11 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

PIO0_1/CLKOUT/

CT32B0_MAT2 4[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on

this pin during reset starts the flash ISP command handler via UART

(if PIO0_3 is HIGH) or via C_CAN (if PIO0_3 is LOW).

O- CLKOUT — Clockout pin.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2/SSEL0/

CT16B0_CAP0 10[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.

I/O - SSEL0 — Slave Select for SPI0.

I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3 14[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. This pin is

monitored during reset: Together with a LOW level on pin PIO0_1, a

LOW level starts the flash ISP command handler via C_CAN and a

HIGH level starts the flash ISP command handler via UART.

PIO0_4/SCL 15[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only

if I2C Fast-mode Plus is selected in the I/O configuration register.

PIO0_5/SDA 16[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only

if I2C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/SCK0 23[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO0_7/CTS 24[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current

output driver).

I- CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0 27[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.

I/O - MISO0 — Master In Slave Out for SPI0.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI0/

CT16B0_MAT1 28[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.

I/O - MOSI0 — Master Out Slave In for SPI0.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

SWCLK/PIO0_10/

SCK0/

CT16B0_MAT2

29[3] yes I I; PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

R/PIO0_11/

AD0/

CT32B0_MAT3

32[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO0_11 — General purpose digital input/output pin.

I- AD0 — A/D converter, input 0.

O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

PIO1_0 to PIO1_11 Port 1 — Port 1 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 1 pins depends

on the function selected through the IOCONFIG register block.

Table 4. L P C11C22/C24 pin description table

Symbol Pin Start

logic

inputs

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 27 June 2011 12 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

R/PIO1_0/AD1/

CT32B1_CAP0 33[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_0 — General purpose digital input/output pin.

I- AD1 — A/D converter, input 1.

I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R/PIO1_1/AD2/

CT32B1_MAT0 34[5] no - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_1 — General purpose digital input/output pin.

I- AD2 — A/D converter, input 2.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/AD3/

CT32B1_MAT1 35[5] no - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_2 — General purpose digital input/output pin.

I- AD3 — A/D converter, input 3.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

39[5] no I/O I; PU SWDIO — Serial wire debug input/output.

I/O - PIO1_3 — General purpose digital input/output pin.

I- AD4 — A/D converter, input 4.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

40[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch

filter.

I- AD5 — A/D converter, input 5.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I- WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch

filter. This pin must be pu lled HIGH externally to enter Deep

power-down mode and pulled LOW to exit Deep power-down mode.

A LOW-going pulse as short as 50 ns wakes up the part.

PIO1_5/RTS/

CT32B0_CAP0 45[3] no I/O I; PU PIO1_5 — General purpose digital input/output pin.

O- RTS — Request To Send output for UART.

I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6/RXD/

CT32B0_MAT0 46[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.

I- RXD — Receiver input for UART.

O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO1_7/TXD/

CT32B0_MAT1 47[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.

O- TXD — Transmitter output for UART.

O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/

CT16B1_CAP0 9[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

PIO1_10/AD6/

CT16B1_MAT1 30[5] no I/O I; PU PIO1_10 — General purpose digital input/output pin.

I- AD6 — A/D converter, input 6.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

Table 4. L P C11C22/C24 pin description table

Symbol Pin Start

logic

inputs

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 27 June 2011 13 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

PIO1_11/AD7 42[5] no I/O I; PU PIO1_11 — General purpose digital input/output pin.

I- AD7 — A/D converter, input 7.

PIO2_0 to PIO2_11 Port 2 — Port 2 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 2 pins depends

on the function selected through the IOCONFIG register block.

PIO2_0/DTR/

SSEL1 2[3] no I/O I; PU PIO2_0 — General purpose dig ital input/ou tput pin.

I/O - DTR — Data Terminal Rea dy output for UART.

I/O - SSEL1 — Slave Select for SPI1.

PIO2_1/DSR/SCK1 13[3] no I/O I; PU PIO2_1 — General purpose digital input/output pin.

I- DSR — Data Set Ready input for UART.

I/O - SCK1 — Serial clock for SPI1.

PIO2_2/DCD/

MISO1 26[3] no I/O I; PU PIO2_2 — General pu rpose digital input/output pin.

I- DCD — Data Carrier Detect input for UART.

I/O - MISO1 — Master In Slave Out for SPI1.

PIO2_3/RI/MOSI1 38[3] no I/O I; PU PIO2_3 — General purpose digital input/output pin.

I- RI — Ring Indicator input for UART.

I/O - MOSI1 — Master Out Slave In for SPI1.

PIO2_6 1[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin.

PIO2_7 11[3] no I/O I; PU PIO2_7 — General purpose dig ital input/ou tput pin.

PIO2_8 12[3] no I/O I ; PU PIO2_8 — General pu rpose digital input/output pin.

PIO2_10 25[3] no I/O I ; PU PIO2_10 — General purpose digital input/output pin.

PIO2_11/SCK0 31[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO3_0 to PIO3_3 Port 3 — Port 3 is a 12-bit I/O port with individual direction and

function controls for each bit. The operation of port 3 pins depends

on the function selected through the IOCONFIG register block. Pins

PIO3_4 to PIO3_11 are not av ailable.

PIO3_0/DTR 36[3] no I/O I; PU PIO3_0 — General purpose digital input/output pin.

O- DTR — Data Terminal Rea dy output for UART.

PIO3_1/DSR 37[3] no I/O I; PU PIO3_1 — General pu rpose digital input/output pin.

I- DSR — Data Set Ready input for UART.

PIO3_2/DCD 43[3] no I/O I; PU PIO3_2 — General pu rpose digital input/output pin.

IDCD — Data Carrier Detect input for UART.

PIO3_3/RI 48[3] no I/O I; PU PIO3_3 — General pu rpose digital input/output pin.

I- RI — Ring Indicator input for UART.

CANL 18 no I/O - LOW-level CAN bus line.

CANH 19 no I/O - HIGH-level CAN bus line.

STB 22 no I - Silent mode control input for CAN transceiver (LOW = Normal mode,

HIGH = silent mode).

VDD_CAN 17 - - - Supply vol tage for I/O level of CAN transceiver.

VCC 20 - - - Supply voltage for CAN transceiver.

Table 4. L P C11C22/C24 pin description table

Symbol Pin Start

logic

inputs

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 27 June 2011 14 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive,

no pull-up/down enabled.

[2] See Figure 26 for reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-d own

mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 25).

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 25).

[6] 5 V tolerant digital I/O pad without pull-up/pull-down resistors.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

GND 21 - - - Ground for CAN transceiver.

VDD 8; 44 - I - Supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

XTALIN 6[7] - I - Input to the oscillator circuit and internal clock generator circuits.

Input voltage must not exceed 1.8 V.

XTALOUT 7[7] - O - Output from the oscillator amplifier.

VSS 5; 41 - I - Ground.

Table 4. L P C11C22/C24 pin description table

Symbol Pin Start

logic

inputs

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 27 June 2011 15 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.2 On-chip flash program memory

The LPC11Cx2/Cx4 conta in 32 kB (LPC11C14/C24) or 16 kB (LPC11C12/C2 2) of on-chip

flash program memory.

7.3 On-chip SRAM

The LPC11Cx2/Cx4 contain a total of 8 kB on-chip static RAM data memory.

7.4 Memory map

The LPC11Cx2/Cx4 incorporates several distinct memory regions, shown in the following

figures. Figure 4 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128

peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32

peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows

simplifying the address decoding for each peripheral.

Product data sheet Rev. 3 — 27 June 2011 16 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

•Controls system exceptions and peripheral interrupts.

•In the LPC11Cx2/Cx4, the NVIC sup ports 3 2 vectored inte rrupts includ ing 13 input s to

the start logic from individual GPIO pins.

Fig 4. LPC11Cx2/Cx4 memory map

0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

16 - 127 reserved

GPIO PIO1

4-7

0x5003 0000

0x5004 0000

GPIO PIO2

GPIO PIO3

8-11

12-15

GPIO PIO0

0-3

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 0000

0x4005 4000

0x4005 8000

0x4005 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART

PMU

I2C-bus

10 - 13 reserved

reserved

23 - 31 reserved

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1000 2000

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

0x1000 0000

8 kB SRAM

LPC11Cx2/Cx4

0x0000 4000

16 kB on-chip flash (LPC11Cx2)

0x0000 8000

32 kB on-chip flash (LPC11Cx4)

16 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors

002aaf268

reserved

SPI0

16-bit counter/timer 1

16-bit counter/timer 0

IOCONFIG

system control

19 C_CAN

reserved

SPI1

flash controller

0xE000 0000

0xE010 0000

private peripheral bus

Product data sheet Rev. 3 — 27 June 2011 17 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

•Four programmable interrupt priority levels, with hardware priority level masking.

•Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral devi ce has one interrupt line con nected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any GPIO pin (total of 40 pins (LPC11C12/C14) or 36 pins (LPC11C22/C24)) regardless

of the selected function, can be programmed to generate an interrupt on a level, or rising

edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be conn ected to the appro priate pins prior to being activated and pr ior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamica lly configured as input s or output s. Multiple output s

can be set or cleared in on e wr ite op e ratio n.

LPC11 Cx2 /Cx4 use accelera te d GPIO functions:

•GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achieved .

•Entire port value can be written in one instruction.

Additionally, any GPIO pin (tot al of 40 pins (LPC11C12/C14) or 36 pins (L PC11C22/C2 4))

providing a digit al function can be programmed to genera te an interrupt on a level, a rising

or falling edge, or both.

7.7.1 Features

•Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

•Direction control of individual bits.

•All GPIO pins default to inputs with pull-ups enabled after reset except for the I2C-bus

true open-drain pins PIO0_4 and PIO0_5.

•Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG

block for each GPIO pin (except PIO0_4 and PIO0_5).

•All GPIO pins (except PIO0_4 and PIO0_5) are pulle d up to 3.3 V (VDD = 3.3 V) if their

pull-up resistor is enabled in the IOCONFIG block.

Product data sheet Rev. 3 — 27 June 2011 18 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

7.8 UART

The LPC11Cx2/Cx4 contain one UART.

Support for RS-4 85 /9 -b it mo d e allo ws bo th software addr ess detection and autom at i c

address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Stan dard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

•Maximum UART data bit rate of 3.125 Mbit/s.

•16 Byte Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•FIFO control mechanism that enables software flow control implementation.

•Support for RS-4 85 /9 -b it mo d e.

•Support for modem control.

7.9 SPI serial I/O controller

The LPC11Cx2/Cx4 contain two SPI controllers. Both SPI controllers support SSP

features.

The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single mas te r an d a sing le

slave can communicate on the bus during a given data transfer. The SPI supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.9.1 Features

•Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

7.10 I2C-bus serial I/O controller

The LPC11Cx2/Cx4 contain one I2C-bus controller.

Product data sheet Rev. 3 — 27 June 2011 19 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-o nly device ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on wheth er the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-m a ste r bu s an d ca n be

controlled by more than one bus master connected to it.

7.10.1 Features

•The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The

I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with diff erent bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mech anism to suspend and

resume serial transfer.

•The I2C-bus can be used for test and diagnostic purposes.

•The I2C-bus controller support s multiple ad dress recognition and a bus monitor mode.

7.11 C_CAN controller

Controller Area Network (CAN) is the definition of a high performance communication

protocol for seri al data communication. The C_ CAN controller is desig ned to provide a full

implement ation of the CAN protocol according to the CAN Specification V e rsion 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a very high level of security.

On-chip C_CAN drivers provide an API for initialization and communication using CAN

and CANopen standards.

7.11.1 Features

•Conforms to protocol version 2.0 parts A and B.

•Supports bit rate of up to 1 Mbit/s.

•Supports 32 Message Objects.

•Each Message Object has its own identifier mask.

•Provides programmable FIFO mode (concatenation of Message Objects).

•Provides maskable interrupts.

•Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

•Provides programmable loop-back mode for self-test operation.

Product data sheet Rev. 3 — 27 June 2011 20 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

•The C_CAN API includes the following functions:

–C_CAN set-up and initialization

–C_CAN send and receive messages

–C_CAN status

–CANopen object dictionary

–CANopen SDO expedited communication

–CANopen SDO segmented communication primitives

–CANopen SDO fall-back handler

•Flash ISP programming via C_CAN supported.

7.11.2 On-chip, high-speed CAN transceiver

Remark: The on-chip CAN transceiver is available on parts LPC11C22/C24 only.

Compared to the LPC11C12/C14, the LPC11C22/C24 supports fewer GPIO functions,

and in addition, one counte r/timer match function is removed to allow interfacing th e CAN

high-speed transceiver to the CAN bus. See Table 4 and Figure 1.

7.11.2.1 Features

•Data rates of up to 1 Mbit/s

•Fully ISO 11898-2 compliant

•Undervoltage detectio n an d the rm al protection

•Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)

7.11.2.2 Normal mode

A LOW level on pin STB selects Normal mode. In this mode, the transceiver is able to

transmit and receive data via the bus lines CANH and CANL (see Figure 28). The

differential receiver converts the analog data on the bus lines into digital data which are

received by the CAN_RXD input of the C_CAN controller.

7.11.2.3 Silent mode

A HIGH level on pin STB selects Silent mode. In Silent mode the transmitter is disabled,

releasing the bus pin s to re ce ssiv e state. All other functions, including the receiver,

continue to operate as in Normal mode. Silent mode can be used to prevent a faulty

C_CAN controller from disrupting all network communications.

7.11.2.4 Undervoltage protection

Should VCC or VDD_CAN drop below their respective undervoltage detection levels

(Vuvd(VCC) and Vuvd (VDD_CAN); see Table 8), the transceiver will switch off and disengage

from the bus (zero load) until VCC and VDD_CAN have recovered.

7.11.2.5 Thermal protection

The output dri vers are protected a gainst overte mperature cond itions. If the virtu al junction

temperature exceeds the shutdown junction temperature, Tj(sd) (see Table 8), the output

drivers will be disabled until the virtual junction temperature falls below Tj(sd).

Product data sheet Rev. 3 — 27 June 2011 21 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

7.11.2.6 Time-out function

A ‘TXD dominant time-out’ timer is started when the CAN_TXD signal of the C_CAN

controller is set LOW. If the LOW state on the CAN_TXD signal persists for longer than

tto(dom)TXD, the transmitter is disabled, releasing the bus lines to recessive state. This

function prevent s a hardware and /or sof tware application failure from driving th e bus lines

to a permanent dominant st ate (blocking all network co mmunications). The TXD dominant

time-out timer is reset when the CAN_TXD signal is set HIGH. The TXD dominant

time-out time also defines the minimum possible bit rate of 40 kbit/s.

7.12 10-bit ADC

The LPC11Cx2/Cx4 contains one ADC. The ADC is a single 10-bit successive

approximation ADC with eight channels.

7.12.1 Features

•10-bit successive approximation ADC.

•Input multiplexing among 8 pins.

•Power-down mode.

•Measurement range 0 V to VDD.

•10-bit conver sio n time  2.44 s (up to 400 kSamples/s).

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition of input pin or timer match signal.

•Individual result registers for each ADC channel to reduce interrupt overhead.

7.13 General purpose external event counter/timers

The LPC11Cx2/Cx4 includes two 32-bit counter /timers and two 16-bit counter/timer s. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specifie d timer values, based on four

match registers. Each counter/timer also includes one capture input to tr ap the timer value

when an input signal transitions, optionally generating an interrupt.

7.13.1 Features

•A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

•Counter or timer op er a tion .

•One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

•Four match registers per timer tha t allow :

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

Product data sheet Rev. 3 — 27 June 2011 22 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

–Toggle on match.

–Do nothing on match.

7.14 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exc ep tion at a fixed time interval (typically 10 ms).

7.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a selectable time

period.

7.15.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by soft ware but requires a har dware reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit timer with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The W atchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential

timing choices of Watchdog operation under different power reduction conditions. It

also provides the ability to run the WDT from an entirely internal source that is not

dependent on an external crystal and its associated components and wiring for

increased reliability.

7.16 Clocking and power control

7.16.1 Crystal oscillators

The LPC11Cx2/Cx4 include three independent oscillators. These are the system

oscillator , the Internal RC oscillator (IRC), and the W atchdog oscillator . Each oscillator can

be used for more than one purpose as required in a particular application.

Following reset, the LPC11Cx2/Cx4 will operate from the Internal RC oscillator until

switched by software. This allows systems to oper ate without any extern al cryst al and the

bootloader code to operate at a known frequency.

See Figure 5 for an overview of the LPC11Cx2/Cx4 clock generation.

Product data sheet Rev. 3 — 27 June 2011 23 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

7.16.1.1 Internal RC oscillator

The IRC may be used as the clock so urce for th e WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC11Cx2/Cx4 use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.16.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

Fig 5. LPC11Cx2/Cx4 clock generatio n block diagram

SYSTEM PLL

IRC oscillator

system oscillator

watchdog oscillator

IRC oscillator

watchdog oscillator

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM CLOCK

DIVIDER

AHB clock 0

(system)

SYSAHBCLKCTRL[1:18]

(AHB clock enable)

AHB clocks 1 to 18

(memories

and peripherals)

SPI0 PERIPHERAL

CLOCK DIVIDER SPI0

SPI1 PERIPHERAL

CLOCK DIVIDER SPI1

UART PERIPHERAL

CLOCK DIVIDER UART

WDT CLOCK

DIVIDER WDT

WDTUEN

(WDT clock update enable)

watchdog oscillator

IRC oscillator

system oscillator CLKOUT PIN CLOCK

DIVIDER CLKOUT pin

CLKOUTUEN

(CLKOUT update enable) 002aae514

main clock

system clock

IRC oscillator

Product data sheet Rev. 3 — 27 June 2011 24 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

7.16.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable betwee n 7.8 kHz and 1.7 MHz. The frequency spread over p rocessing and

temperature is 40 % (see Table 15).

7.16.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output

frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100 s.

7.16.3 Clock output

The LPC11Cx2/Cx4 features a clock output function that routes the IRC oscillator, the

system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.16.4 Wake-up process

The LPC11Cx2/Cx4 begin operation at power-up and when awakened from Deep

power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows

chip operation to resume quickly. If the system oscillator or the PLL is needed by the

application, software will need to enable these features and wait for them to stabilize

before they are used as a clock source.

7.16.5 Power control

The LPC11Cx2/Cx4 support a variety of power control features. There are three special

modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep

power-down mode. The CPU clock rate may also be controlled as needed by changing

clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This

allows a trade-off of power versus processing speed based on application requirements.

In addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any periph era ls th at ar e no t req uired for the a pplica tion. Selected per ipher als have

their own clock divide r wh ich pr ovides even better power control.

7.16.5.1 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

Product data sheet Rev. 3 — 27 June 2011 25 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

7.16.5.2 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all a nalog blo cks are shut

down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for se lf-timed wake-up and BOD pr otection. Deep- sleep mod e allows

for additiona l powe r sa vin gs.

Up to 13 pins total, see Table 3, serve as external wake-up pins to a dedicated start logic

to wake up the chip from Deep-sleep mode.

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source

should be switched to IRC before entering Deep-sleep mode, because the IRC can be

switched on and off glitch-free.

7.16.5.3 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC11Cx2/Cx4 can wake up from Deep power-down mode via the

WAKEUP pin.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from

floating while in Deep power-down mode.

7.17 System control

7.17.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 as input to the start logic has an individual inter rupt in the NVIC interrupt

vector table. The start logic pins can serve as external interrupt pins when the chip is

running. In addition, an input signal on the start logic pins can wake up th e chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.17.2 Reset

Reset has four sources on the LPC11Cx2/Cx4: the RESET pin, the Watchdog reset,

power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage

attains a usable level, starts the IRC and initializes the fla sh co nt ro ller.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

An external pull-up resistor is required on the RESET pin if Deep power-down mode is

used.

7.17.3 Brownout detection

The LPC11Cx2/Cx4 includes four levels for monitoring the voltage on the VDD pin. If this

voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to

the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the

Product data sheet Rev. 3 — 27 June 2011 26 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

NVIC in order to cause a CPU interrupt; if not, so ftware can monitor the signal by readin g

a dedicated status register. Four additional threshold levels can be selected to cause a

forced reset of the chip.

7.17.4 Code security (Code Read Protection - CRP)

This feature of the LPC11Cx2/Cx4 allows user to enable different levels of security in the

system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)

and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details see the LPC11Cx user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mod e is

useful when CRP is required and flash field updates are needed but all sectors can

not be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to the ch ip

via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

the UART.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details see the LPC11Cx user manual.

7.17.5 Bootloader

The bootloader controls initial operation after reset and also provides the means to

program the flash memory. This could be initial programming of a blank device, erasure

and re-programming of a previously programmed device, or programming of the flash

memory by the application program in a running system.

The bootloader code is executed every time the part is reset or powered up. The loader

can either execute the user application code or the ISP command handler via UART or

C_CAN. A LOW level during reset applied to the PIO0_1 pin is co nsidere d as an e xternal

hardware request to start the ISP command handler. The state of PIO0_3 at reset

determines whether the UART (PIO0_3 HIGH) or the C_CAN (PIO0_3 LOW) interface will

be used.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 3 — 27 June 2011 27 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

The C_CAN ISP command handler uses the CANopen protocol and data organization

method. C_CAN ISP commands have the same functionality as UART ISP comma nds.

7.17.6 APB interface

The APB peripherals are located on one APB bus.

7.17.7 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.17.8 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as exte rnal interru pts (see Section 7.17.1).

7.18 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four

breakpoints and two watchpoints is supported.

Product data sheet Rev. 3 — 27 June 2011 28 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage (core

and external rail) on pins VDD 1.8 3.6 V

VIinput voltage 5 V tolerant I/O pins; only valid when the VDD supply

voltage is present [2] 0.5 +5.5 V

Vxvoltage on pin x no time limit; DC value

on pins CANH and CANL 58 +58 V

on pins STB, VCC, VDD_CAN 0.3 +7 V

IDD supply current per supply pin [3] -100mA

ISS ground current per ground pin [3] -100mA

Ilatch I/O latch-up curre n t (0.5VDD) < VI < (1.5VDD);

Tj < 125 C-100mA

Tstg storage temperature non-operating [4] 65 +150 C

Tj(max) maximum junction

temperature -150C

Ptot(pack) total power dissipation

(per package) based on package heat transfer, not device power

consumption -1.5W

VESD electrostatic discharge

voltage human body model;

all pins except CAN on-chip transceiver pins CANL,

CANH, STB, VDD_CAN, VCC, GND on

LPC11C22/C24

[5] 6500 +6500 V

pins CANH and CANL on LPC11C22/C24 [5] 8000 +8000 V

pins STB, VDD_CAN, VCC, GND on

LPC11C22/C24 [5] 4000 +4000 V

Product data sheet Rev. 3 — 27 June 2011 29 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

9. Static characteristics

Table 6. Static characteristics

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD supply voltage (core

and external rail) on pins VDD 1.8 3.3 3.6 V

IDD supply current Active mode; code

while(1){}

executed from flash

system clock = 12 MHz

VDD = 3.3 V

[2][3][4]

[5][6][7] -3-mA

system clock = 50 MHz

VDD = 3.3 V

[2][3][6]

[5][7][8] -9-mA

Sleep mode;

system clock = 12 MHz

VDD = 3.3 V

[2][3][4]

[5][6][7] -2-mA

Deep-sleep mode;

VDD = 3.3 V [2][3][5]

[9] -6-A

Deep power-down mode;

VDD = 3.3 V [2][10] -220-nA

Standard port pins, RESET

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD; on-chip

pull-down resistor

disabled

- 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD;

on-chip pull-up/down

resistors disabled

- 0.5 10 nA

VIinput voltage pin configured to provide

a digital function [11][12]

[13] 0- 5.0V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.4 - V

VOH HIGH-level output

voltage 2.0 V  VDD  3.6 V;

IOH =4 mA VDD  0.4--V

1.8 V  VDD < 2.0 V;

IOH =3 mA VDD  0.4--V

VOL LOW-level output

voltage 2.0 V  VDD  3.6 V;

IOL =4 mA --0.4V

1.8 V  VDD < 2.0 V;

IOL =3 mA --0.4V

Product data sheet Rev. 3 — 27 June 2011 30 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

IOH HIGH-level output

current VOH =V

DD 0.4 V;

2.0 V  VDD  3.6 V

4--mA

1.8 V  VDD < 2.0 V 3--mA

IOL LOW-level output

current VOL =0.4V

2.0 V  VDD  3.6 V 4--mA

1.8 V  VDD < 2.0 V 3--mA

IOHS HIGH-level short-circuit

output current VOH =0V [14] --45 mA

IOLS LOW-level short-circuit

output current VOL =V

DD [14] --50mA

Ipd pull-down current VI=5V 10 50 150 A

Ipu pull-up current VI=0V;

2.0 V  VDD  3.6 V

15 50 85 A

1.8 V  VDD < 2.0 V 10 50 85 A

VDD <V

I<5V 000A

High-drive output pin (PIO0_7)

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD; on-chip

pull-down resistor

disabled

- 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD;

on-chip pull-up/down

resistors disabled

- 0.5 10 nA

VIinput voltage pin configured to provide

a digital function [11][12]

[13] 0- 5.0V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage 2.5 V  VDD  3.6 V;

IOH =20 mA VDD  0.4--V

1.8 V  VDD < 2.5 V;

IOH =12 mA VDD  0.4--V

VOL LOW-level output

voltage 2.0 V  VDD  3.6 V;

IOL =4 mA --0.4V

1.8 V  VDD < 2.0 V;

IOL =3 mA --0.4V

IOH HIGH-level output

current VOH =V

DD 0.4 V;

2.5 V  VDD  3.6 V 20--mA

1.8 V  VDD < 2.5 V 12--mA

Table 6. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 3 — 27 June 2011 31 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] Tamb =25C.

[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; system oscillator disabled; system PLL disabled.

[5] Pin CAN_RXD pulled LOW externally.

[6] BOD disabled.

[7] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to U ART and SPI0/1 disabled in system configuration

block.

[8] IRC disabled; system oscillator enabled; system PLL enabled.

[9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

[10] WAKEUP pin pulled HIGH externally.

[11] Including voltage on outputs in 3-state mode.

[12] VDD supply voltage must be present.

IOL LOW-level output

current VOL =0.4V

2.0 V  VDD  3.6 V 4--mA

1.8 V  VDD < 2.0 V 3--mA

IOLS LOW-level short-circuit

output current VOL =V

DD [14] --50mA

Ipd pull-down current VI=5V 10 50 150 A

Ipu pull-up current VI=0V

2.0 V  VDD  3.6 V

15 50 85 A

1.8 V  VDD < 2.0 V 10 50 85 A

VDD <V

I<5V 000A

I2C-bus pins (PIO0_4 and PIO0_5)

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.05VDD -V

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configured as standard

mode pins

2.0 V  VDD  3.6 V

3.5--mA

1.8 V  VDD < 2.0 V 3 - -

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configure d as Fast -mode

Plus pins

2.0 V  VDD  3.6 V

20--mA

1.8 V  VDD < 2.0 V 16 - -

ILI input leakage current VI=V

DD [15] -24A

VI=5V - 10 22 A

Oscillator pins

Vi(xtal) crystal input voltage 0.5 1.8 1.95 V

Vo(xtal) crystal output voltage 0.5 1.8 1.95 V

Table 6. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 3 — 27 June 2011 32 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

[13] 3-state outputs go into 3-state mode in Deep power-down mode.

[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[15] To VSS.

9.1 ADC characteristics

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 6.

[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 6.

[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 6.

[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 6.

[6] The absolute error (ET) is the maximum difference between the center of the steps of the actu al transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 6.

[7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF.

[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia).

Table 7. ADC static characteristics

Tamb =





C to +85



C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input vol tage 0 - VDD V

Cia analog input capacitance - - 1 pF

EDdifferential linearity error [1][2] -- 1LSB

EL(adj) integral non-linearity [3] -- 1.5 LSB

EOoffset error [4] -- 3.5 LSB

EGgain error [5] --0.6%

ETabsolute er ror [6] -- 4LSB

Rvsi voltage source interface

resistance --40k

Riinput resistance [7][8] --2.5M

Product data sheet Rev. 3 — 27 June 2011 33 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 6. ADC characteristics

002aaf426

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDD − VSS

1024

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 3 — 27 June 2011 34 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

9.2 C_CAN on-chip, high-speed transceiver characteristics

Table 8. Static characteristics

Tamb =40 C to +85 C; VCC = 4.5 V to 5.5 V ; RL=60; unless otherwise specified; all voltages are defined with respect to

ground; positive currents flow into the IC. Also see Figure 28.

Symbol Parameter Conditions Min Typ Max Unit

Supply; pin VCC

VCC supply voltage 4.5 - 5.5 V

ICC supply current Silent mode 0.1 1 2.5 mA

Normal mode

recessive 2.5 5 10 mA

dominant; CAN_TXD = LOW 20 50 70 mA

Vuvd(VCC) undervoltage detection

voltage on pin VCC

3.5 - 4.5 V

I/O level adapter supply; pin VDD_CAN

VDD supply voltage on pin VDD_CAN 2.8 - 5.5 V

IDD supply current on pin VDD_CAN; Normal and Silent

modes

recessive; CAN_TXD = HIGH 10 80 250 A

dominant; CAN_TXD = LOW 50 350 500 A

Vuvd(VDD_CAN) undervoltage detection

voltage on pin VDD_CAN 1.3 - 2.7 V

Mode control inp ut; pin STB

VIH HIGH-level input voltage 0.7VCC -V

CC +0.3 V

VIL LOW-level input voltage 0.3 - 0.3VCC V

IIH HIGH-level input current 1 4 10 A

IIL LOW-level input current Voltage on pin STB = 0 V 10+1 A

Bus lines; pins CANH and CANL

VO(dom) dominant output voltage CAN_TXD = LOW; t < tto(dom)TXD

pin CANH 2.75 3.5 4.5 V

pin CANL 0.5 1.5 2.25 V

Vdom(TX)sym transmitter dominant voltage

symmetry Vdom(TX)sym = VCC VCANH VCANL 400 0 +400 mV

VO(dif)bus bus differential output

voltage CAN_TXD = LOW; t < tto(dom)TXD 1.5 - 3 V

CAN_TX D = HI GH ; recessiv e;

no load 50 - +50 mV

VO(rec) recessive output voltage Normal and Silent modes;

CAN_TX D = HIGH; no load 20.5V

CC 3V

Vth(RX)dif diff erential receiver

threshold voltage Normal and Silent modes

Vcm(CAN)[1] =12 V to +12 V 0.5 0.7 0.9 V

Vhys(RX)dif differential receiver

hysteresis voltage Normal and Silent modes

Vcm(CAN) =12 V to +12 V 50 120 400 mV

IO(dom) dominant output current CAN_TXD = LOW; t < tto(dom)TXD;

VCC =5 V

pin CANH; VCANH =0V 120 70 40 mA

pin CANL; VCANL = 5 V/40 V 40 70 120 mA

Product data sheet Rev. 3 — 27 June 2011 35 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

[1] Vcm(CAN) is the common mode voltage of CANH and CANL.

IO(rec) recessive output current Normal and Silent modes;

CAN_TXD = HIGH;

VCANH =V

CANL =27 V to +32 V

5-+5 mA

ILleakage current VCC =0V; V

CANH =V

CANL =5V 50+5 A

Riinput resistance 9 15 28 k

Riinput resistance deviation between VCANH and VCANL 30+3 %

Ri(dif) differential input resistance 19 30 52 k

Ci(cm) common-mode input

capacitance --20pF

Ci(dif) differential input capacitance - - 10 pF

Temperature protection

Tj(sd) shutdown junction

temperature -190- C

Table 8. Static characteristics …continued

Tamb =40 C to +85 C; VCC = 4.5 V to 5.5 V ; RL=60; unless otherwise specified; all voltages are defined with respect to

ground; positive currents flow into the IC. Also see Figure 28.

Symbol Parameter Conditions Min Typ Max Unit

Table 9. Dy namic characteristics

Tamb =40 C to +85 C; VCC = 4.5 V to 5.5 V; RL=60 unless specified otherwise. All voltages are defined with respect to

ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

tto(dom)TXD TXD dominant time-out time CAN_TXD = LOW; Normal

mode 0.3 1 12 ms

Product data sheet Rev. 3 — 27 June 2011 36 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

9.3 BOD static characteristics

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11Cx

user manual.

9.4 Power consumption

Power measurement s in Active, Sleep , and Deep-sleep mod es were performed under the

following conditions (see LPC11Cx user manual):

•Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

•Configure GPIO pins as outputs using the GPIOnDIR registers.

•Write 0 to all GPIOnDATA registers to drive the outputs LOW.

Table 10. BOD static characteristics[1]

Tamb =25



Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 0

assertion - 1.65 - V

de-assertion - 1.80 - V

interrupt level 1

assertion - 2.22 - V

de-assertion - 2.35 - V

interrupt level 2

assertion - 2.52 - V

de-assertion - 2.66 - V

interrupt level 3

assertion - 2.80 - V

de-assertion - 2.90 - V

reset level 0

assertion - 1.46 - V

de-assertion - 1.63 - V

reset level 1

assertion - 2.06 - V

de-assertion - 2.15 - V

reset level 2

assertion - 2.35 - V

de-assertion - 2.43 - V

reset level 3

assertion - 2.63 - V

de-assertion - 2.71 - V

Product data sheet Rev. 3 — 27 June 2011 37 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Conditions: Tamb = 25 C; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW

externally.

(1) S ystem oscillator and system PLL disabled; IRC enabled.

(2) S ystem oscillator and system PLL enabled; IRC disabled.

Fig 7. Active mode : Typical supply current IDD versus supply voltage VDD for different

system clock frequencies

Conditions: VDD = 3.3 V; active mode entered executing co de

while(1){}

from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW

externally.

(1) S ystem oscillator and system PLL disabled; IRC enabled.

(2) S ystem oscillator and system PLL enabled; IRC disabled.

Fig 8. Active mode : Typical supply current IDD versus temperature for different system

clock frequencies

VDD (V)

1.8 3.63.02.4

002aaf390

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

temperature (°C)

−40 853510 60−15

002aaf391

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

Product data sheet Rev. 3 — 27 June 2011 38 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.

(1) S ystem oscillator and system PLL disabled; IRC enabled.

(2) S ystem oscillator and system PLL enabled; IRC disabled.

Fig 9. Sleep mode: Typical supply current IDD versus temperature for different system

clock frequencies

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF); pin CAN_RXD pulled LOW externally.

Fig 10. Deep-sleep mode: Typical supply current IDD versus temperature for different

supply vo ltages VDD

002aaf392

temperature (°C)

−40 853510 60−15

IDD

(mA)

12 MHz(1)

36 MHz(2)

48 MHz(2)

24 MHz(2)

002aaf394

temperature (°C)

−40 853510 60−15

IDD

(μA)

3.6 V

3.3 V

2.0 V

1.8 V

Product data sheet Rev. 3 — 27 June 2011 39 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Fig 11. Deep power-down mode: Typical supply current IDD versus temperature for

different supply voltages VDD

002aaf457

0.2

0.6

0.4

0.8

IDD

(μA)

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

2.0 V

1.8 V

Product data sheet Rev. 3 — 27 June 2011 40 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

9.5 Peripheral power consumption

The supply current p er peripheral is measured as the differ ence in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Mea sured on a typical sample at Tamb =25 C. Unless

noted otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.

Ta ble 11. Power consump t ion for individual analog and digital blocks

Peripheral Typical supply current in

mA Notes

n/a 12 MHz 48 MHz

IRC 0.27 - - System oscillator running; PLL off;

independent of main clock frequency.

System oscillator

at 12 MHz 0.2 2 - - IRC running; PLL off; independent of main

clock frequency.

Watchdog

oscillator at

500 kHz/2

0.004 - - S ystem oscillator running; PLL off;

independent of main clock frequency.

BOD 0.051 - - Independent of main clock frequency.

Main PLL - 0.21 -

ADC - 0.08 0.29

CLKOUT - 0.12 0.47 Main clock divided by 4 in the CLKOUTDIV

CT16B0 - 0.02 0.06

CT16B1 - 0.02 0.06

CT32B0 - 0.02 0.07

CT32B1 - 0.02 0.06

GPIO - 0.23 0.88 GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

IOCONFIG - 0.03 0.10

I2C - 0.04 0.13

ROM - 0.04 0.15

SPI0 - 0.12 0.45

SPI1 - 0.12 0.45

UART - 0.22 0.82

C_CAN - 0.03 0.1

WDT - 0.02 0.06 Main clock selected as cl ock source fo r the

WDT.

Product data sheet Rev. 3 — 27 June 2011 41 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

9.6 Electrical pin characteristics

Conditions: VDD = 3.3 V; on pin PIO0_7.

Fig 12. High-drive output: Typ i cal HIGH-le vel ou tput voltage VOH versus HIGH-level

output current IOH.

Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 13. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus

LOW-level output voltage VOL

IOH (mA)

0 60402010 5030

002aae990

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aaf019

IOL

(mA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 27 June 2011 42 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD = 3.3 V; standard port pins and PIO0_7.

Fig 14. Typical LOW-level output current IOL versus LOW-level output voltage VOL

Conditions: VDD = 3.3 V; standard port pins.

Fig 15. Typical HIGH-level output voltage VOH versus HIGH-level output source current

IOH

VOL (V)

0 0.60.40.2

002aae991

IOL

(mA)

T = 85 °C

25 °C

−40 °C

IOH (mA)

0 24168

002aae992

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 27 June 2011 43 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD = 3.3 V; standard port pins.

Fig 16. Typical pull-up current Ipu versus input voltage VI

Conditions: VDD = 3.3 V; standard port pins.

Fig 17. Typical pull-do wn current Ipd versus input voltage VI

VI (V)

0 54231

002aae988

−30

−50

−10

Ipu

(μA)

−70

T = 85 °C

25 °C

−40 °C

VI (V)

0 54231

002aae989

Ipd

(μA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 27 June 2011 44 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

10. Dynamic characteristics

10.1 Flash memory

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash

in blocks of 256 bytes.

10.2 External clock

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

Table 12. Flash characteristics

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 10000 100000 - cycles

tret retention time powered 10 - - years

unpowered 20 - - years

ter erase time sector or multiple

consecutive

sectors

95 100 105 ms

tprog programming

time [2] 0.95 1 1.05 ms

Table 13. Dynamic characteristic: external clock

Tamb =





C to +85



C; VDD over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) 0.4--ns

tCLCX clock LOW time Tcy(clk) 0.4--ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Fig 18. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

Product data sheet Rev. 3 — 27 June 2011 45 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

10.3 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.

[3] See the LPC11Cx user manual.

Table 14. Dynamic characteristic: internal oscillators

Tamb =





C to +85



C; 2.7 V



VDD



3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator frequency - 11.88 12 1 2.12 MHz

Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for

2.7 V  VDD  3.6 V and Tamb =40 C to +85 C. Variations between parts may cause the IRC to

fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V.

Fig 19. Internal RC oscillator frequency ver sus temperature

Table 15. Dynamic characteristics: Watchdog oscillator

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc(int) internal oscillator

frequency DIVSEL = 0x1F, FREQSEL = 0x1

in the WDTOSCCTRL register; [2][3] -7.8 - kHz

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register [2][3] - 1700 - kHz

002aaf403

11.95

12.05

12.15

(MHz)

11.85

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

2.0 V

Product data sheet Rev. 3 — 27 June 2011 46 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

10.4 I/O pins

[1] Applies to standard port pins and RESET pin.

10.5 I2C-bus

[1] See the I2C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] Cb = total capacitance of one bus line in pF.

Table 16. Dynamic characteristic: I/O pins[1]

Tamb =





C to +85



C; 3.0 V



VDD



3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

trrise time pin

configured as

output

3.0 - 5.0 ns

tffall time pin

configured as

output

2.5 - 5.0 ns

Table 17. Dynamic characteristic: I2C-bus pins[1]

Tamb =





C to +85



C.[2]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock

frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus 0 1 MHz

tffall time [4][5][6][7] of both SDA and

SCL signals

Standard-mode

- 300 ns

Fast-mode 20 + 0.1  Cb300 ns

Fast-mode Plus - 120 ns

tLOW LOW period of

the SCL clock Standard-mode 4.7 - s

Fast-mode 1.3 - s

Fast-mode Plus 0.5 - s

tHIGH HIGH period of

the SCL clock Standard-mode 4.0 - s

Fast-mode 0.6 - s

Fast-mode Plus 0.26 - s

tHD;DAT data hold time [3][4][8] Standard-mode 0 - s

Fast-mode 0 - s

Fast-mode Plus 0 - s

tSU;DAT data set-up

time

[9][10] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus 50 - ns

Product data sheet Rev. 3 — 27 June 2011 47 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a S tandard-mode I2C-bus system but the requirement tSU;DAT =

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period

of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus

specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

10.6 SPI interfaces

Fig 20. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

HD;DAT

SCL

1 / f

SCL

70 %

30 % 70 %

30 %

VD;DAT

HIGH

LOW

SU;DAT

Table 18. Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions Min Typ Max Unit

SPI master (in SPI mode)

Tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns

when only transmitting [1] 40 ns

tDS data set-up time in SPI mode

2.4 V  VDD  3.6 V

[2] 15 - - ns

2.0 V  VDD < 2.4 V [2] 20 ns

1.8 V  VDD < 2.0 V [2] 24 - - ns

tDH data hold time in SPI mode [2] 0-- ns

tv(Q) data output valid time in SPI mode [2] --10 ns

th(Q) data output hold time in SPI mode [2] 0-- ns

SPI slave (in SPI mode)

Tcy(PCLK) PCLK cycle time 20 - - ns

Product data sheet Rev. 3 — 27 June 2011 48 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

[1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2] Tamb = 40 C to 85 C.

[3] Tcy(clk) = 12  Tcy(PCLK).

[4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.

tDS data set-up time in SPI mode [3][4] 0-- ns

tDH data hold time in SPI mode [3][4] 3  Tcy(PCLK) + 4 - - ns

tv(Q) data output valid time in SPI mode [3][4] --3  Tcy(PCLK) + 11 ns

th(Q) data output hold time in SPI mode [3][4] --2  Tcy(PCLK) + 5 ns

Table 18. Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions Min Typ Max Unit

Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 21. SPI master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

D ATA V ALID DATA V ALID

th(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

tDS tDH

D ATA V ALID DATA V ALID

th(Q)

D ATA V ALID D ATA V ALID

tv(Q)

CPHA = 1

CPHA = 0

002aae829

Product data sheet Rev. 3 — 27 June 2011 49 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 22. SPI slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

cy(clk)

clk(H)

clk(L)

v(Q)

D ATA V ALID DATA V ALID

h(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

v(Q)

D ATA V ALID DATA V ALID

h(Q)

D ATA V ALID D ATA V ALID

CPHA = 1

CPHA = 0

002aae830

Product data sheet Rev. 3 — 27 June 2011 50 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

11. Application information

11.1 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 7:

•The ADC input trace must be short and as close as possible to the LPC11Cx2/Cx4

chip.

•The ADC input traces must be shielded from fast switching digital signals and noisy

power supply line s .

•Because the ADC and the digital co re share the same power sup ply, the power supply

line must be adequately filtered.

•To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

11.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled throug h a cap acitor with

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuate s the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mv (RMS) is needed.

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 23), with an amplitude between 200 mv (RMS) and 1000 mv (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 24 and in

Table 19 and Table 20. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances CX1 and CX2 need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

RS). Capacitance CP in Figure 24 represent s the p arallel p ackage cap acitance and sho uld

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal

manufacturer (see Table 19).

Fig 23. Slave mode operation of the on-chip oscillator

LPC1xxx

XTALIN

100 pF Cg

002aae788

Product data sheet Rev. 3 — 27 June 2011 51 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

11.3 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that th e load cap acitors Cx1, Cx2, and Cx3 in ca se o f

third overtone crystal usage have a common ground plane. The externa l components

must also be connected to the ground plain. Loops must be made as small as possible in

Fig 24. Oscillator modes and models: oscillation mode of op eration and external crystal

model used for CX1/CX2 evaluation

Table 19. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components paramete rs) low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

1 MHz - 5 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 300 39 pF, 39 pF

30 pF < 300 57 pF, 57 pF

5 MHz - 10 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 200 39 pF, 39 pF

30 pF < 100 57 pF, 57 pF

10 MHz - 15 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 60 39 pF, 39 pF

15 MHz - 20 MHz 10 pF < 80 18 pF, 18 pF

Table 20. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components paramete rs) hi gh frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

15 MHz - 20 MHz 10 pF < 180 18 pF, 18 pF

20 pF < 100 39 pF, 39 pF

20 MHz - 25 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 80 39 pF, 39 pF

002aaf424

LPC1xxx

XTALIN XTALOUT

CX2

CX1

XTAL

=CLCP

Product data sheet Rev. 3 — 27 June 2011 52 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

order to keep the no ise couple d in via th e PCB as sm all as po ss ible . A lso parasitic s

should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

11.4 Standard I/O pad configuration

Figure 25 shows the possible pin modes for standard I/O pins with analog input function:

•Digital output driver

•Digital input: Pull-up enabled/disabled

•Digital input: Pull-down enabled/disabled

•Digital input: Repeater mode enabled/disabled

•Analog input

Fig 25. Standard I/O pad configurati on

VDD

ESD

VSS

ESD

VDD

weak

pull-up

weak

pull-down

output enable

repeater mode

enable

output

pull-up enable

pull-down enable

data input

analog input

select analog input

002aaf304

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

Product data sheet Rev. 3 — 27 June 2011 53 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

11.5 Reset pad configuration

11.6 C_CAN with external transceiver (LPC11C12/C14 only)

Fig 26. Reset pad configuration

VSS

reset

002aaf274

VDD

Rpu ESD

ESD

20 ns RC

GLITCH FILTER PIN

Fig 27. Connecting the C_CAN to an external transceiver (LPC1 1C12/C14)

TXD

RXD

LPC11C12/C14

PIOx_y

CAN_TXD

CAN_RXD

GND

VCC

CANH CANH

CANL CANL

5 V

BAT 3 V

VIO

002aaf911

TJF1051

Product data sheet Rev. 3 — 27 June 2011 54 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

11.7 C_CAN with on-chip, high-speed transceiver (LPC11C22/C24 only)

Fig 28. Connecting the CAN high-speed transceiver to the CAN bus (LPC11C22/C24)

GND

CANH CANH

CANL CANL

5 V

3 V

VDD_CAN

002aaf910

LPC11C22/C24

CAN

HIGH-SPEED

TRANSCEIVER C_CAN

CAN_TXD

CAN_RXD

STD

Product data sheet Rev. 3 — 27 June 2011 55 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

12. Package outline

Fig 29. Package outline SOT313-2 (LQFP48)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 7.1

6.9 0.5 9.15

8.85 0.95

0.55 7

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Product data sheet Rev. 3 — 27 June 2011 56 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

13. Soldering

Fig 30. Reflow soldering of the LQFP48 package

SOT313-2

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP48 package

AyBy

D2 (8×)D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx Hy

10.350

0.560 10.350 7.350 7.350

0.500 0.280

1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

Product data sheet Rev. 3 — 27 June 2011 57 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

14. Abbreviations

Table 21. Abbreviations

Acronym Description

ADC Analog-to-Digital Converter

AHB Advanced High-performance Bus

APB Advanced Peripheral Bus

API Application Programming Interface

BOD BrownOut Detection

CAN Controller Area Network

GPIO General Purpose Input/Output

PLL Phase-Locked Loop

RC Resistor-Capacitor

SDO Service Data Object

SPI Serial Peripheral Interface

SSI Serial Synchronous Interface

SSP Synchronous Serial Port

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 3 — 27 June 2011 58 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

15. Revision history

Table 22. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC11CX2_CX4 v.3 20110627 Product data sheet - LPC11C12_C14 v.2

Modifications: •I2C-bus pins configured as standard mode pins , paramete r IOL changed to 3.5 mA

(minimum) for 2.0 V  VDD  3.6 V.

•Parameter Vx added to Table 5 “Limiting values”.

•C_CAN power consumption data added to Table 11.

•ADC sampling frequency corrected in Table 7 (Table note 7).

•Reflow soldering footprint drawing added (Section 13).

•Pull-up level specified in Table 3 and Table 4.

•Parameter Tcy(clk) corrected on Table 18.

•Condition for parameter Tstg in Table 5 updated.

•Table note 4 of Table 5 updated.

•Table 18 T~cy(clk) condition changed from “when only receiving” to “full-duplex mode”

LPC11CX2_CX4 v.2 20101203 Product data sheet - LPC11C12_ C14 v.1

Modifications: •Parts LPC11C22 and LPC11C24 added.

•Pin description for parts LPC11C 22 and LPC11C24 added (Table 4).

•Static characteristics for CAN transceiver added (Table 8).

•Description of high-speed, on-chip CAN transceiver added (LPC11C22/C24). See

Section 7.11.2.

•Application diagram for connecting the C_CAN to an external transceiver added

(Section 11.6).

•Application diagram for high-speed, on-chip CAN transceiver added (Section 11.7).

•Typical value for parameter Nendu added in Table 12 “Flash characteristics”.

•Description of RESET and WAKEKUP pins updated in Table 3.

•PLL output frequency limited to < 100 MHz in Se ction 7.16.2 “System PLL”.

•Parameter Vhys for I2C bus pins: typical value corrected Vhys = 0.05VDD in Table 6.

LPC11C12_C14 v. 1 20100921 Product data sheet - -

Product data sheet Rev. 3 — 27 June 2011 59 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or comple teness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsisten cy or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associate d with their

applications and products.

NXP Semiconductors does not accept any liabil i ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 3 — 27 June 2011 60 of 62

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automotive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive ap plications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 3 — 27 June 2011 61 of 62

continued >>

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Functional description . . . . . . . . . . . . . . . . . . 15

7.1 ARM Cortex-M0 processor. . . . . . . . . . . . . . . 15

7.2 On-chip flash program memory . . . . . . . . . . . 15

7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 15

7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.5 Nested Vectored Interrupt Controller (NVIC) . 16

7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17

7.6 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 17

7.7 Fast general purpose parallel I/O . . . . . . . . . . 17

7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.8 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.9 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 18

7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.10 I2C-bus serial I/O controller . . . . . . . . . . . . . . 18

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.11 C_CAN controller . . . . . . . . . . . . . . . . . . . . . . 19

7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.11.2 On-chip, high-spee d CAN transce iver . . . . . . 20

7.11.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.11.2.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.11.2.3 Silent mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.11.2.4 Undervoltage protection . . . . . . . . . . . . . . . . . 20

7.11.2.5 Thermal protection . . . . . . . . . . . . . . . . . . . . . 20

7.11.2.6 Time-out function . . . . . . . . . . . . . . . . . . . . . . 21

7.12 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.13 Gene ral purpose external event

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 21

7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.14 System tick timer . . . . . . . . . . . . . . . . . . . . . . 22

7.15 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 22

7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.16 Clocking and power control . . . . . . . . . . . . . . 22

7.16.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 22

7.16.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 23

7.16.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 23

7.16.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 24

7.16.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.16.3 Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.16.4 Wake-up process. . . . . . . . . . . . . . . . . . . . . . 24

7.16.5 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 24

7.16.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.16.5.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 25

7.16.5.3 Deep power-down mode . . . . . . . . . . . . . . . . 25

7.17 System control. . . . . . . . . . . . . . . . . . . . . . . . 25

7.17.1 Start logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.17.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.17.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 25

7.17.4 Code security

(Code Read Protection - CRP) . . . . . . . . . . . 26

7.17.5 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.17.6 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 27

7.17.7 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.17.8 External interrupt inputs. . . . . . . . . . . . . . . . . 27

7.18 Emulation and debugging . . . . . . . . . . . . . . . 27

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28

9 Static characteristics . . . . . . . . . . . . . . . . . . . 29

9.1 ADC characteristics . . . . . . . . . . . . . . . . . . . . 32

9.2 C_CAN on-chip, high-speed transceiver

characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34

9.3 BOD static characteristics . . . . . . . . . . . . . . . 36

9.4 Power consumption . . . . . . . . . . . . . . . . . . . 36

9.5 Peripheral power consumption . . . . . . . . . . . 40

9.6 Electrical pin characteristics. . . . . . . . . . . . . . 41

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 44

10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 44

10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 44

10.3 Internal oscillato rs . . . . . . . . . . . . . . . . . . . . . 45

10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.6 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 47

11 Application information . . . . . . . . . . . . . . . . . 50

11.1 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 50

11.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11.3 XTAL Pri nted Circuit Board (PCB) layout

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.4 Standard I/O pad configuration . . . . . . . . . . . 52

11.5 Reset pad configuration. . . . . . . . . . . . . . . . . 53

11.6 C_CAN with external transceiver

(LPC11C12/C14 only) . . . . . . . . . . . . . . . . . . 53

11.7 C_CAN with on-chip, high-speed tra nsceiver

(LPC11C22/C24 only) . . . . . . . . . . . . . . . . . . 54

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 55

NXP Semiconductors LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 June 2011

Document identifier: L PC11CX2_CX4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 57

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 58

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 59

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 59

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17 Contact information. . . . . . . . . . . . . . . . . . . . . 60

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61