October 1992 - Linear Technology

OCTOBER 1992 VOLUME II NUMBER 3

Design Techniques for

Electrostatic Discharge

Protection by Sean Gold

continued on page 8

1. Inductively, when a surface

becomes polarized due to nearby

electric fields

2. Capacitively, when the capaci-

tance of a body at fixed potential

increases

3. Triboelectrically, when two materi-

als exchange charge as result of

friction and are separated.

The third generation mechanism,

triboelectricity, is usually the most

troublesome because the human body

can acquire a substantial charge, up

to 35kV in some cases, depending

upon the relative humidity and electri-

cal properties of the materials involved.

Walking across a wool carpet with

leather shoes on a dry winter day may

generate a charge of 10kV to 15kV,

whereas the same action on a humid

day in the summer may produce less

than 2kV.

Charge Transfer

For charge to affect circuitry, it must

be transferred from the generator. Elec-

trostatic charge may be transferred

between bodies at different potentials

directly, via physical contact, or in-

ductively, via an electrostatic field.

IN THIS ISSUE . . .

COVER ARTICLE

Design Techniques for

Electrostatic Discharge

Protection....................... 1

Sean Gold

Editor's Page .................. 2

Richard Markell

DESIGN FEATURES

LT1190 Family

Ultra-High-Speed

Op Amps Eclipse Prior Art

....................................... 3

John Wright and Mitchell Lee

LTC1196/1198 SAR ADCs

Beat Half-Flashes and Run

on 3 or 5V Supplies ........ 6

William Rempfer and Marco Pan

DESIGN INFORMATION

LT1112/LT1114 Dual/Quad

Precision Op Amps have

Universal Appeal ............ 11

George Erdi

The LTC1157 Dual 3.3V

Micropower MOSFET Driver

....................................... 13

Tim Skovmand

World’s Lowest-Noise Op Amp

Now Available in SO & Unity-

Gain Stable Versions ...... 14

George Erdi and Alexander Strong

DESIGN IDEAS

A Temperature-Compensated,

Voltage-Controlled-Gain

Amplifier Using the LT1228

....................................... 15

Frank Cox

Flash-Memory VPP Generator

....................................... 17

Sean Gold

LCD Bias Supply............. 17

Steve Pietkiewicz

New Device Cameos ........ 18

Since their infancy, integrated-

circuit manufacturers have been

concerned about circuit damage

caused by electrostatic discharge

(ESD). Assembly and packaging pro-

cedures often proved fatal to early

stone-knife and bearskin ICs. Design

and processing techniques improved,

but device geometries shrank, per-

petuating ESD problems. Today, in-

terest in ESD protection goes beyond

handling and assembly considerations.

Portable computers and instrumen-

tation are often subjected to severe

electrical stresses, imposing stringent

demands on exposed circuitry. Digital-

communication interfaces and input

amplifiers must tolerate repetitive ESD

pulses because cable connections fre-

quently come in contact with humans

and other charged bodies. In addition,

products to be sold in European mar-

kets must conform to standards set

forth by the European Committee for

Electrotechnical Standardization

(CENELEC). The standard for ESD,

IEC-801-2, is now under review and

will become mandatory in 1996.

UNDERSTANDING ESD

Even though the most modern ICs

have some form of ESD protection, a

basic understanding of electrostatic

discharge, its causes and its remedies,

is helpful when designing circuits for

electrically harsh environments.

Charge Generation

Both conductors and insulators can

support charge, which can build up in

three ways:

ISO 9000



COMPLIANT

LINEAR TECHNOLOGY

DESIGN FEATURES

Linear Technology Magazine • October 1992

ESD Protection, High-Speed and

Precision Op Amps, and Fast Serial

ADCs Highlight this Issue by Richard Markell

This issue, the last of the year,

spotlights many different topics. ESD

(electrostatic discharge) is a critical

issue for most RS232 designs. Our

lead article presents a careful study of

the causes, cures, and prevention of

electrostatic-discharge damage in

RS232 circuitry. The article presents a

method to virtually assure that your

RS232 design is the best it can be.

LTC has expended time and re-

sources on an intensive program to

ensure that our RS232 devices are as

ESD resistant as we can make them.

Laboratory testing has proven that

our RS232 devices can withstand mul-

tiple 10kV strikes. Line drivers and

line receivers must be more resistant

to ESD than other types of devices

since their inputs and outputs

connect directly to the outside world.

Other devices are hidden inside

instrumentation boxes, on PC boards,

or otherwise shielded from the rigors

experienced by the DB25 (RS232) con-

nector. Making LTC’s RS232 parts

more rugged to the tune of 10kV is

another engineering triumph from the

designers at LTC.

This issue includes two articles on

our high-speed operational amplifi-

ers. The first is a collection of circuits

designed around the low cost LT1190

video amplifier. The second shows tem-

perature compensation of the LT1228

electronic gain control amplifier. Both

of these components and a whole list

of other video amplifiers are products

from LTC’s 600MHz complementary

bipolar process. This proprietary pro-

cess allows IC designers to combine

precision DC specifications with high

speed, resulting in some of the best

video amplifiers in the industry. Watch

for more video amplifiers and other

high-speed products from LTC.

Precision operational amplifiers are

also well represented in this issue with

articles on the new LT1112/1114 dual

and quad surface-mountable op amps.

Also new in the world of op amps is a

surface-mount version of the industry’s

lowest noise op amp, the LT1028. In

addition, the new LT1128 is a unity-

gain-stable version of the LT1028,

which is also available in SO pack-

ages. The LT1028 and the LT1128 are

featured in a short article herein. Last

to be described here, but certainly not

least in performance, are two new A/D

converters. These converters, the

LT1196/1198, challenge half-flash

converters in speed, cost, power con-

sumption, size, and ease of use.

Issue Highlights

Sean Gold leads off this issue with

his article on techniques for staving off

the horrors of ESD. Sean has been at

LTC for four years, during which time

he designed the LT1134, LT1137,

LT1237, LT1330, LT1026 and the

LT1116. He is an avid cyclist, urban

adventurer, and alpine skier, and regu-

larly attends the Foothill College

electronics flea market. Sean’s collec-

tion of mid-60’s oscilloscopes and

instrumentation has made him

extremely popular with the ladies.

Mitchell Lee and John Wright de-

scribe a number of applications for

LTC’s LT1190 high-speed op amp.

Mitchell Lee has been at LTC for two

years as an Applications Engineer. He

has worked in the semiconductor ap-

plications arena (and it certainly is an

arena) for more than 12 years total.

Mitchell’s hobbies include fourth-sea-

son mountaineering and music. Un-

like John, Mitchell doesn’t fish Hat

Creek.

Frank Cox is the newest member

of our Applications Group. Frank

describes the LT1228 100MHz cur-

rent-feedback amplifier with DC gain

control. He has been involved in RF

and video systems for the past eight

years. Frank has been at LTC for only

four months but is already developing

many video and RF circuits using LTC’s

high-speed operational amplifiers.

Frank’s outside interests include fish-

ing and audio systems.

Alexander Strong and George Erdi

describe some new LTC offerings in op

amps, the LT1128 and the LT1028 in

SO packaging. Alex has been at LTC

for more than two years. He has worked

in the semiconductor industry for more

than 12 years, primarily designing op

amps and D/A converters. Alex is a

Vermont native whose interests in-

clude camping, hiking, and racing his

diesel Mercedes at Laguna Seca. Alex

is another loyal patron of the Foothill

flea market.

Marco Pan is the designer and co-

author of the article on the LTC1196/

1198 serial 8-bit A/D converters that

convert at speeds up to 1.3MHz. Marco

has been at LTC for five years and has

been in the industry a total of eight

years. He designed the LTC690 series

of microprocessor supervisory circuits,

LTC1096, LTC1098, LTC1196 and the

LTC1198. Marco’s outside interests

include his family, gardening, and

home improvement.

Short biographies of John Wright,

Willie Rempfer, and George Erdi ap-

peared in previous issues.

EDITOR'S PAGE

Linear Technology Magazine • October 1992

DESIGN FEATURES

1190_3.A eps

–



51ΩLT1190

+5V

–5V

1N5712



20ΩV

L

10nF

TIME (s)

100k

2dB/DIV

100M

1190_2. eps

1M 10M

LT1190

LM118

= –1

= R

= 1k

LT1191

–2

–4

–6

–8

–10

–12

TIME (s)

100k

2dB/DIV

100M

1190_1. eps

1M 10M

LT1191

LT1190

LM118

= +1

= 1k

–2

–4

–6

–8

–10

Introduction

The LT1190 series op amps

combine bandwidth, slew rate, and

output-drive capability to satisfy the

demands of many high-speed appli-

cations. This family offers up to

350MHz gain-bandwidth product,

slew rates of 450V/µs, and yet drives a

150Ω (75Ω, double-terminated) load.

In 50Ω systems, the LT1190 family

can deliver +13.5dBm to a double-

terminated load. These parts are based

on the familiar, easy-to-use, voltage-

mode feedback topology.

Characteristics of the three mem-

bers of the LT1190 series are shown in

Table 1.

LT1190 Family Ultra-High-Speed Op

Amps Eclipse Prior Art by John Wright and

Mitchell Lee

All of the LT1190 series devices

operate on single 5 to 15V supplies, or

split supplies of up to ±8V. Output

current capability is ±50mA.

Careful chip design has made the

LT1190 family quite tolerant of supply-

rail bypassing. In many applications, a

simple 100nF disc ceramic capacitor

from each supply pin to ground is all

that is needed. Where settling time is

an issue, a 4.7µF tantalum capacitor

should be added on each supply pin.

Such a cavalier attitude toward supply

bypassing is a radical departure from

the industry norm.

Another unusual feature common

to the LT1190 family is shutdown.

This allows the user to multiplex out-

puts, gate signals, or conserve power

when an op amp is idle.

Table 1. Characteristics of the LT1190 family

Settling

GBWP SR Time

Part (MHz) (V/µs) Min Gain (0.1%, ns)

LT1190 50 450 +1 140

LT1191 90 450 +1 110

LT1192 350 450 +5 90

Figure 1. Small-signal response A

= +1.

130MHz peaking due to socket and

bypass components

Figure 2. Small-signal response A

= –1

Figure 3. Closed-loop peak detector

Small-Signal Performance

Figures 1 and 2 show the small-

signal performance of the LT1190 and

LT1191 when configured for gains of

+1 and –1. The non-inverting plots

show peaking at 130MHz, which is

characteristic of the socketed test fix-

ture and supply bypass components.

A tight PC-board layout would reduce

the LT1190 peaking to 2dB. The small-

signal performance of an LM118 is

shown for comparison.

Applications

Fast peak detectors place unusual

demands on amplifiers. The output

stage must have a high slew rate in

order to keep up with the intermediate

stages of the amplifier. This condition

causes either a long overload or DC-

accuracy errors. To maintain a high

slew rate at the output, the amplifier

must deliver large currents into the

capacitive load of the detector. Other

problems include amplifier instability

with large capacitive loads and pres-

ervation of output-voltage accuracy.

Detecting Sine Waves

The LT1190 is the ideal candidate

for this application, with a 450V/µs

slew rate, 50mA output current, and

70° phase margin. The closed-loop

peak detector circuit of Figure 3 uses a

Schottky diode inside the feedback

loop to obtain good accuracy. A 20Ω

resistor (R

) isolates the 10nF load and

prevents oscillation.

DC error with a sine-wave input is

plotted in Figure 4 for various input

amplitudes. The DC value is read with

a DVM. At low frequencies, the error is

small and is dominated by the decay of

the detector capacitor between cycles.

DESIGN FEATURES

Linear Technology Magazine • October 1992

Figure 5. Open-loop, high-speed peak detector

–



51ΩLT1190

+5V

–5V

D2

1N5712

D1

1N5712

–5V

FB

10nF

L

1nF



51k

1190_5. eps

–5V



51k

Figure 7. Fast pulse detector

As frequency rises, the error increases

because capacitor charging time de-

creases. During this time the overdrive

becomes a very small portion of a sine

wave cycle. Finally, at approximately

4MHz, the error rises rapidly owing to

the slew-rate limitation of the op amp.

For comparison purposes, the error of

an LM118 is also plotted for V

= 2V

P-P

A Schottky-diode peak detector can

be built with a 1nF capacitor and a

10kΩ pulldown. Although this simple

circuit is very fast, it has limited use-

fulness owing to the error of the diode

threshold and its low input imped-

ance. The accuracy of this simple

detector can be improved with the

LT1190 circuit of Figure 5.

In this open-loop design, D1 is the

detector diode and D2 is a level-

shifting or compensating diode. A load

resistor, R

, is connected to –5V, and

an identical bias resistor, R

, is used

to bias the compensating diode. Equal-

value resistors ensure that the diode

drops are equal. Low values of R

and R

(1kΩ to 10kΩ) provide fast

response, but at the expense of poor

low-frequency accuracy. High values

of R

and R

provide good low-

frequency accuracy but cause the

amplifier to slew-rate limit, resulting

in poor high-frequency accuracy. A

good compromise can be made by

adding a feedback capacitor, C

which enhances the negative slew rate

on the (–) input.

The DC error with a sine-wave in-

put, as read with a DVM, is plotted in

Figure 6. For comparison purposes the

LM118 error is plotted, as well as the

error of the simple Schottky detector.

Pulse Detector

A fast pulse detector can be made

with the circuit of Figure 7. A very fast

input pulse will exceed the amplifier’s

slew rate and cause a long overload

recovery time. Some amount of dV/dt

limiting on the input can help this

overload condition; however, it will

delay the response.

Figure 8 shows the detector error

versus pulse width. Figure 9 is the

response to a 4V

P–P

input pulse that is

Figure 8. Detector error vs. pulse width

80ns wide. The maximum output slew

rate in the photo is 70V/µs. This rate is

set by the 70mA current limit driving

1nF. As a performance benchmark,

the LM118 takes 1.2µs to peak detect

and settle, given the same amplitude

input. This slower response is due, in

part, to the much lower slew rate and

lower phase margin of the LM118.

Instrumentation Amplifier

Rejects High Voltage

Instrumentation amplifiers are nor-

mally used to process slowly varying

outputs from transducers, rather than

PULSE WIDTH (ns)

DC DETECTOR ERROR (%)

100

1190_8. eps

20 40 60 80

= 4V

P-P



dV/dt LIMITING = 1kΩ, 20pF

FREQUENCY (Hz)

DC DETECTOR ERROR (%)

10M 100M

1190_6. eps

SCHOTTKY

= 2V

P-P

SCHOTTKY

= 4V

P-P

SCHOTTKY

= 6V

P-P

= 6 V

P-P

= 2V

P-P

= 4 V

P-P

LT1190

LM118

= 2V

P-P

Figure 6. Open-loop peak-detector error

vs. frequency

–

LT1190

+5V

–5V

D2

1N5712



10k

D1

1N5712

–5V

L

1nF



10k



51Ω

I

20pF

1190_7. eps

–5V



FREQUENCY (Hz)

10k

DC DETECTOR ERROR (%)

100k 1M 10M

1190_4. eps

LT1190

VIN = 6VP-P

LT1190

VIN = 4VP-P

LT1190

VIN = 2VP-P

SLEW RATE LIMIT

LM118

VIN = 2VP-P

Figure 4. Closed-loop peak-detector error

vs frequency

Linear Technology Magazine • October 1992

DESIGN FEATURES

20ns/DIV

B (1V/DIV)

1190_9. eps

A (1V/DIV)

Crystal Oscillator

Op amps have found wide use in

low-frequency (≤100kHz) crystal os-

cillator circuits, but just haven’t had

the bandwidth to operate successfully

at higher frequencies. The LT1190

and LT1191 make excellent gain stages

for high-frequency Colpitts oscillators.

A practical implementation is shown

in Figure 12.

Gain limiting is provided by two

Schottky diodes, which maintain the

output at approximately +11dBm—

sufficient to directly drive +7 or +10dBm

diode-ring mixers. Output-stage clip-

ping is not recommended as a means of

gain limiting, as this increases distor-

tion and allows internal nodes to be

overdriven. The recovery time would

add excessive phase shift in the oscilla-

tor loop, degrading frequency stability.

Distortion performance is good, con-

sidering that the oscillator consists of

one stage and can deliver useful out-

put power. Figure 13 shows a spectral

Figure 9. Open-loop peak detector response

Trace A: output (1 Volt/division)

Trace B: input (1 Volt/division)

–

LT1192

+5V

–5V

1190_10. eps

10k

100Ω

99Ω

CM

120V

P-P

10k

Figure 10. 3.5MHz instrumentation amplifier rejects 120V

P–P

plot of the oscillator’s output. The sec-

ond harmonic is approximately 37dB

down, limited primarily by the clipping

action of the Schottky diodes. Power-

supply rejection is excellent, showing a

frequency sensitivity of approximately

0.1ppm/V. The LT1190 gives accept-

able performance to 10MHz, while the

LT1191 extends the circuit’s operating

range to 20MHz.

fast signals. However, it is possible to

make an instrumentation amplifier

that responds very quickly, with good

common mode rejection. For the cir-

cuit of Figure 10, an LT1192 is used to

obtain 50dB of CMRR from a 120V

P–P

signal. In this application, the CMRR

is limited by the matching of the resis-

tors, which should match to better

than 0.01%.

An LT1192 is used in this applica-

tion because the circuit has a noise

gain of 100, and because the higher

gain bandwidth of the LT1192 allows a

–3dB bandwidth of 3.5MHz. Note also

that the 100:1 attenuation of the

common-mode signal presents a com-

mon-mode voltage to the amplifier of

only 1.2V

P–P

. Figure 11 shows the am-

plifier output for a 1MHz square wave

riding on a 120V

P–P

, 60Hz signal. The

circuit exhibits 50dB rejection of the

common-mode signal.

200ns/DIV

2V/DIV

1190_11. eps

1190_12. eps

–

–5V

51Ω

1kΩ

+5V

1N5711

330pF

75pF

3.579545MHz

LT1190 TO NETWORK

ANALYZER

= 50Ω)

100kΩ

Figure 12. High-frequency Colpitts oscillator

Figure 11. Output of instrumentation amplifier with a

1MHz square wave riding on 120V

P–P

at the input

FREQUENCY (MHz)

–80

OUTPUT POWER (dBm)

–70

–50

–30

–10

1190_13. eps

–60

–40

–20

4567 91011128

Figure 13. Oscillator output spectrum

DESIGN FEATURES

Linear Technology Magazine • October 1992

INTRODUCTION

The LTC1196/1198 are 600ns,

1.2MHz sampling 8-bit A/D convert-

ers packaged in tiny 8-pin SO pack-

ages and operating on 3V to 6V

supplies. The on-chip sample-and-

holds have full-accuracy input band-

widths of 1MHz. The ADCs draw only

10mW from a 3V supply or 50mW

from a 5V supply and the LTC1198

powers down to leakage current be-

tween conversions.

The LTC1196 has differential in-

puts and offers the highest sample

rate (1.2MHz). The LTC1198 converts

two input channels, single ended or

differentially. These converters pro-

vide system designers with previously

impossible levels of performance in an

extremely small space. This article will

discuss the ADCs’ advantages, design

techniques, 3V and 5V performance,

and application considerations.

SIZE, SPEED, COST,

AND POWER ADVANTAGES

The new LTC1196/1198 offer

smaller size, better speed, lower cost,

and much lower power dissipation

than half-flash converters.

Size

The LTC1196/1198 can provide con-

siderable space savings over half-flash

ADCs for three reasons: First, the tiny

SO-8 package and minimum number

of external components makes the

ADCs’ configuration small compared

to those of the 20-pin alternatives.

Second, the low power dissipation and

high-impedance inputs cut the space

requirements in the power supply and

signal-conditioning circuitry. Third, the

serial interface to a processor, digital

ASIC, or logic system requires only

three wires and only three pins on the

receiving system. This saves board

LTC1196/1198 SO-8 Packaged SAR

ADCs Beat Half-Flashes in Any Arena

and Run on 3 or 5V Supplies by William Rempfer

and Marco Pan

Figure 2. I

vs. sample rate for LTC1196 and

LTC1198 operating on 5V and 2.7V supplies

Figure 1. The LTC1196/1198 (right) can

provide considerable space savings over

half-flash ADCs (left)

SAMPLE RATE (Hz)

0.01

SUPPLY CURRENT, ICC (mA)

0.1

100 10k 100k 1M

1196_2. eps

0.001 1k

LTC1196 VCC = 5V

LTC1196 VCC = 2.7V

LTC1198 VCC = 5V

LTC1198 VCC = 2.7V

space and allows the ADC to be located

close to the signal source, making the

physical configuration more flexible

and smaller than the 11-wire-I/O half-

flash alternatives. With the LTC1196/

1198, an extremely small configura-

tion can be implemented, as shown in

Figure 1. The system is 3V powered

and is 100% surface mountable.

Speed

The LTC1196 and LTC1198 beat

half-flash ADCs on speed. They offer

equivalent sample rates and three

times wider input-sampling band-

widths than well known half-flash

products such as the AD7821,

ADC08061, or ML2261. With 600ns

conversion times, 1.2MHz sampling

rates, and 1MHz full-accuracy input

bandwidths, the LTC1196/1198 are

more than a match for half-flash ADCs.

Cost

he LTC1196/1198 reduce system

cost relative to half-flash ADCs in

a number of ways. First, they offer

tremendous price/performance advan-

tages when their sticker prices are

compared to those of half-flash con-

verters in this speed range. Second,

the savings in board space can trans-

late into a cheaper system or a system

that wasn’t even possible with older

technology. Third, 3V operation can

eliminate the cost of a regulated

supply in 3V battery systems or the

cost of generating a separate 5V supply

in 3V systems. Fourth, reduced-span

operation can reduce the cost of signal-

conditioning circuitry. Finally, the re-

duced power consumption and power

shutdown can reduce the cost of the

system power supply or batteries.

Power

The power savings of the new ADCs,

and especially of the LTC1198, can be

very large. Their power consumption

when operating on a 5V rail is equal to

that of a half-flash converter. Power

consumption can be reduced two ways.

Using a 3V supply lowers the power

consumption on both devices by a

factor of five, to 10mW. The LTC1198

can reduce power even more because it

shuts down whenever it is not convert-

ing. Figure 2 shows the supply current

versus sample rate for the LTC1196

and the LTC1198 on 3V and 5V.

Linear Technology Magazine • October 1992

DESIGN FEATURES

INTERNAL DESIGN:

GETTING HALF-FLASH SPEEDS

WITH AN SAR CONVERTER

The LTC1196/1198 design uses the

successive-approximation technique

to achieve remarkable speed from a

low-cost n-well CMOS process. To

achieve its 600ns conversion time and

1.2MHz sample rate, bit tests are per-

formed every 70ns. To digitize 1MHz

input signals to full accuracy, the

sample-and-hold has a 3dB band-

width of 10MHz and acquires and

settles in less than 100ns.

The partitioning of the 70ns bit-test

time is shown in Figure 3. One cycle

consists of the DAC switching and

settling, the comparator making a de-

cision, and the SAR latching the bit

value and updating the DAC.

The capacitive DAC design settles

to 0.02% in 30ns. The design and

layout of the DAC is critical to achiev-

ing this speed. The settling time con-

stant must be less than 3.5ns.

The comparator is an ultra-fast,

auto-zeroed, sampled-data compara-

tor. It is a redesign of the comparator

used in the LTC1272 12-bit, 3µs sam-

pling ADC. Its design includes cas-

caded stages of low gain and has an

extremely wide (200MHz) small-signal

bandwidth. It is designed to minimize

disturbance to the power supply lines

APPLICATION

CONSIDERATIONS

Analog Considerations

The LTC1196/1198 are remarkably

easy to use. They will yield excellent

performance if some simple rules are

followed for board layout, bypassing,

and driving the reference and analog

inputs. (For a more detailed discus-

sion see Linear Technology Volume I,

Number 2, pp. 9–10 and the LTC1196/

1198 data sheet.)

Board layout should include an ana-

log ground plane to which all analog

circuitry is referenced. Low-inductance

ground and supply lines are recom-

mended. Also, the input signal should

be routed away from digital circuitry.

If the power supply is clean, by-

passing the ADC requires only a 0.1µF

capacitor, because the power-supply

transients produced within the chip

have been minimized. A surface-mount

chip cap. or a ceramic cap. with short

leads will give very good results.

Figure 4. LTC1196 conversion timing

and responds to a 0.5mV overdrive

in 20ns.

Figure 4 shows the conversion

timing for the LTC1196. The con-

version takes 8.5 clock cycles and

the total cycle time is 12 clock

cycles. These correspond to a con-

version time of 600ns and a sample

rate of 1.2MHz at the maximum

14.3MHz clock frequency. The sample-

and-hold acquires the analog input

from the end of a conversion to the

start of the next. At that time it goes

into hold mode and the conversion

starts.

3V VERSUS 5V

PERFORMANCE COMPARISON

The performance comparison in

Table 1 shows that using a 3V supply

gives great savings in power with only

modest reductions in speed. The power

dissipation drops by a factor of five

when the supply is reduced to 3V. The

converter slows down somewhat but

still gives excellent performance on a

3V rail. It converts in 1.6µs, samples

at 450kHz, and provides a 500kHz

linear-input bandwidth, making it the

fastest 3V ADC on the market. Getting

rid of 80% of the power loss makes 3V

operation very attractive.

Dynamic accuracy is excellent on

both 5V and 3V. The ADCs typically

provide 49.3dB or 7.9ENOBs (Effec-

tive Number Of Bits) of dynamic accu-

racy at both 3 and 5V. The noise floor is

extremely low, corresponding to a tran-

sition noise of less than 0.1LSB. DC

accuracy includes ±0.5LSB total un-

adjusted error at 5V. At 3V, linearity

error is ±0.5LSB while total unad-

justed error increases to ±1LSB.

continued on page 12

Table 1. 5V/3V performance comparison

LTC1196/1198 5V 3V

PDISS 50mW 10mW

Max fSAMPLE 1.2MHz 450kHz

Min tCONV 600ns 1.6µs

INL (Max) 0.5LSB 0.5LSB

Typical ENOBs 7.9 @ 300kHz 7.9 @ 100kHz

Linear Input 1MHz 500kHz

Bandwidth

(ENOBs >7)

1196_3. eps

20ns

DAC SETTLES COMPARATOR

LATCHES

BIT VALUE

SAR

UPDATES

DAC

20ns30ns

70ns

Figure 3. Bit-test timing sequence

1196_4. eps

CONV

(8.5 CLKs)

OUT

CLK

B0B2

CYC

(12 CLKs)

B6NULL BITB0 B7 B5 B3 B1 Hi-ZHi-Z

NULL

BIT

SMPL

(3.5 CLKs)

SMPL

DESIGN FEATURES

Linear Technology Magazine • October 1992

esd_1.eps

1kV/DIV

5ms/DIV

Figure 4. Human-body model circuit for ESD pulses

ESD, continued from page 1

The human body can store 20 to 30

millijoules of energy, but, because of

the body’s relatively high source im-

pedance, not all of that energy can be

transferred during a discharge.

ESD pulses exhibit a slowly decay-

ing exponential response, but the rise

time can be extremely fast. (Figure 1)

ESD often contains frequency compo-

nents well into the GHz range. At such

frequencies, nearby cables and cir-

cuit-board traces look like receiving

antennas that can pick up ESD noise.

ESD Damage

Early ICs were especially suscep-

tible to ESD-induced oxide damage at

low voltages. Discharges of less than

500V, which were commonly gener-

ated during assembly and handling,

were sufficient to cause damage. Dam-

age often occurred where the oxide’s

dielectric strength was weakest. The

trouble spots were usually in regions

where metal from a pad passed over

thin oxide—often an n+ diffusion. Rec-

ognition of this problem and improved

processing techniques have eliminated

this type of damage.

Damage from ESD is fundamentally

the result of a transfer of energy. Heat

can destroy junctions and metalliza-

tion when excessive energy dissipates

within the chip. Intense electrostatic

fields can also break down junctions or

thin oxide preceding a destructive en-

ergy transfer. Figures 2 and 3 show

some typical examples of ESD damage.

ESD noise can also drive circuitry

into invalid or locked-up states that

are not necessarily destructive. By

definition, such “soft errors” are cor-

rected by cycling the power supply or

by forcing the circuit back into a valid

operating state. If a soft error induces

a high-current condition, prolonged

heating may destroy an unprotected

device. Systems can be made resilient

to soft errors using digital control

to detect invalid states and reset the

circuit.

Circuit Models for ESD

The need to generate ESD pulses for

test purposes prompted the develop-

ment of a circuit model based on the

charge storage characteristics of the

human body. The switching circuit

shown in Figure 4 consists of a 100pF

high-voltage capacitor discharged

through a 1.5kΩ resistor. The energy

delivered to the load in each pulse is

E = (1/2)CV

× (R

+ R

). Test

equipment based on this circuit model

was used to determine the ESD toler-

ances quoted here.

ESD PROTECTION

TECHNIQUES

Any action that eliminates the charge

generator, circumvents charge trans-

fer, or enhances the circuit’s ability to

absorb energy will increase a circuit’s

tolerance of ESD. Eliminating the ubiq-

uitous charge generators or disrupting

charge transfer are difficult tasks be-

cause they demand strict control of the

circuit’s operating environment. A more

practical approach is to limit ESD en-

try points by shielding the circuit’s

enclosure and covering the exposed

connectors when they are not in use.

Another practical remedy is to in-

crease a circuit’s ability to absorb

energy by clamping the exposed pins

esd_4.eps

DISCHARGE

SWITCH

S

1.5kΩ

S

100pF

C

50MΩ TO 100MΩ

HIGH-VOLTAGE

DC SUPPLY R

DISCHARGE

TIP

DISCHARGE

RETURN

CONNECTION

Figure 1. 3.5kV ESD pulse. (Photo taken with a

low-capacitance voltage divider and a Tek type

P6103 high-voltage probe)

Figure 3. Removing metallization reveals

junction damage between the emitter and

the collector of a lateral PNP transistor

Figure 2. ESD damage results in a resistive

short from a bond pad to a thin oxide n+ region

on an unprotected bipolar IC

Linear Technology Magazine • October 1992

DESIGN FEATURES

esd_7.eps

DIGITAL

CIRCUITS

EQUIVALENT

DECOUPLING

NETWORK

BUS

= 1Ω

ESD CLAMP

S

1.5kΩ

PREFERRED

RETURN PATH

HIGH-VOLTAGE

DC SUPPLY

Figure 7. Circuit model for ESD current flow

turned off or powered down. When the

transceiver is on and significant ESD

discharge occurs, the resulting cur-

rent may de-bias internal circuitry

and cause nondestructive soft errors.

Observations have shown these errors

to be highly dependent upon the logi-

cal state of the transceiver.

Filters

When extremely high levels of ESD

protection are required, an external

LC filter can be used for additional

protection. The circuit in Figure 6 has

a 10MHz cutoff frequency with 40dB/

decade rolloff, which is sufficient to

drop ESD energy into a range that

can be safely dissipated within the

transceiver.

PC Board Layout

Energy shunted through an ESD

clamp can still cause problems if the

ground path’s return inductance is

large enough to create a sizable voltage

drop. Such voltage drops may damage

unprotected components that share

the common ground line. Consider the

circuit model shown in Figure 7. Sup-

pose the return path to ground

presents a 1Ω impedance at ESD fre-

quencies. The voltage V

at the local

ground is approximately V

= V

) = V

/1500. If there is poor

common-mode coupling to V

, the

digital ICs sharing the common ground

will be damaged when V

exceeds

+0.7V. This condition occurs when

the peak ESD voltage is greater than

8.55kV. Using a low-inductance

ground plane, or, preferably, isolating

the return path to low impedance

ground, is therefore essential for good

ESD protection.

esd_5.eps

RS232

RECEIVER

RS232

TRANSMITTER

ESD

CLAMP ESD

CLAMP

AC COUPLING

CAPACITORS

Figure 5. Older interface designs used

external ESD clamps

esd_6.eps

RS232

LINE

50pF

5µHRS232 RECEIVER

LOGIC

OUTPUT

50pF

5µHRS232 DRIVER

FERRITE BEADS

RS232

LINE LOGIC

INPUT

to ground with fast-acting avalanche

diodes or dedicated transient suppres-

sors (Figure 5). Discrete suppressors

are widely available and are extremely

effective. Designers are often reluctant

to use discrete suppressors because

they are expensive—at up to $0.40/

pin they can sometimes exceed the

cost of the IC. Transient suppressors

also introduce stray capacitance, which

may prohibit their use in high-speed

circuits.

Designers are often reluctant

to use discrete suppressors

because they are expensive...

they can sometimes exceed

the cost of the IC.

The LT1237 RS232 transceiver in-

corporates the clamps for diverting

ESD energy on chip. These active struc-

tures quickly respond to positive or

negative signals at threshold voltages

higher than RS232 signals but below

destructive levels for the device. The

path of high current flow is through

large pn junctions, which increase the

device’s capacity to absorb energy.

The LT1237’s ESD structures can ab-

sorb human-body-model discharges

of >10kV. The resulting current flow is

insignificant when the transceiver is

Figure 6. External LC filters provide

protection from very high levels of ESD,

yet cost less than discrete suppressors

Sometimes the high current path is

not directly to ground. In the example

with the LT1237, ESD currents flow

through the device’s substrate, which

is connected to the negative charge

pump output, V

–

. V

–

is AC coupled to

ground through a 0.1µF storage ca-

pacitor, which must have low effective

series resistance (ESR) to prevent dam-

aging voltage drops. Adding a few

hundred picofarads of low ESR ca-

pacitance in parallel with the primary

storage capacitor effectively reduces

ESR at ESD frequencies.

When using discrete transient sup-

pressors or filters, place components

as close as possible to the connector

with short paths to the return plane.

Increasing the distance, or the series

resistance, between the entry point

and the sensitive device diminishes

the ESD energy transferred.

ESD pulses can easily arc from one

trace to another when the spacing be-

tween traces is narrow. Increasing the

spacing between the circuit board traces

or surrounding signal lines with a sepa-

rate return plane is helpful in prevent-

ing ESD energy from arcing between

pins. Arcing occurs slowly compared

with ESD rise time, so air spark gaps

Linear Technology Magazine • October 1992

esd_8.eps

1kV/DIV

0.5ms/DIV

DESIGN FEATURES

Anatomy of the

LT1237 RS232 Port

The LT1237 is a complete RS232

port, designed specifically for bat-

tery-powered computers and instru-

mentation. The device contains three

drivers, five receivers, and a regu-

lated charge pump to reduce sup-

ply current. Supply current is

typically 6mA, but the device can be

shut down with two separate logic

controls. The driver-disable pin

shuts off the charge pump and the

drivers, leaving all receivers active,

SUPPLY

= 4mA. The ON/OFF pin

shuts down all circuitry except for

one micropower receiver, I

SUPPLY

60µA. The active receiver is useful

for detecting start-up signals. The

LT1237 operates up to 120kbaud,

and is fully compliant with all RS232

specifications and fault conditions.

The flow-through pinout and the

LT1237’s ability to use small sur-

face-mount capacitors helps reduce

the interface’s overall footprint. Con-

nections to the RS232 cable are

protected with internal ESD struc-

tures that can withstand repetitive

±10kV human-body-model ESD

pulses.

Triboelectric charging should not be confused with

the primal creatures who worship the Tektronix

547 oscilloscope, and are often referred to as a

“tribe-o-electricals.”

References:

1. Linear Technology 1990 Databook, pp.15–23 to

15–34.

2. Clarke, O. and Neill, D., “Electrical-Transient

Immunity: A Growing Imperative For System

Design,” Electronic Design, Jan 23, 1992,

pp. 83–98.

3. Boxleitner, W., “How to defeat electrostatic dis-

charge,” IEEE Spectrum, August 1989, pp. 36–40.

4. Matisoff, B., Handbook of Electrostatic Discharge

Controls, Van Nostrand Reinhold, 1986.

Do not do this! Instead, AC

couple the grounds so they are

shorted at ESD frequencies.

DC Isolation

ESD transients should not

be confused with DC and low-

frequency ground faults that

occur when circuits with large

differences in ground poten

tial are connected together.

The amount of energy trans-

ferred during a ground fault

can be vastly greater than the

energy of an ESD pulse. To

guard against ground faults requires

a circuit with true DC isolation. A fully

isolated RS232 transceiver design is

described in Linear Technology's

Design Note 27.

CONCLUSION

The techniques described here can-

not entirely eliminate ESD problems,

but understanding ESD’s nature and

using careful circuit design will help

protect against its intrusion.

alone will not protect circuitry from

ESD. Spark gaps are, in fact, useful

for limiting the ESD energy. Figure 8

shows a 300µs delay between the

initial ESD rise and the activation of a

10 mil spark gap.

The connections to the cable shield

affect noise and ESD performance.

Designers may feel inclined to float

the cable shield with respect to local

ground to avoid circulating currents

due to differences in ground potential.

Figure 10. A typical application circuit for the LT1237 under digital control

RX 5 OUT (LOW-Q)

esd_box.eps

218

1712

1514

TO LINE

TO LOGIC

2 x 0.1µF0.1µF

1.0µF

2 x 0.1µF

LT1237

0.1µF

5V V

RX 2 IN

DRIVER 2 OUT

RX 1 IN

DRIVER 1 OUT

RX 5 IN (LOW-Q)

DRIVER 3 OUT

RX 4 IN

RX 3 IN

ON/OFF

RX 3 OUT

RX 2 OUT

DRIVER 2 IN

RX 1 OUT

GND

DRIVER 3 IN

RX 4 OUT

DRIVER 1 IN

DRIVER DISABLE

RING DETECT IN

RECEIVE

ONLY MODE

SHUTDOWN

CONTROL OUT

µ CONTROLLER

–

Figure 8. 10-mil spark gap limits ESD duration

Linear Technology Magazine • October 1992

The LT1112 and LT1114 are dual

and quad universal precision op amps.

The universal description is justified

by the fact that all important precision

specifications have been optimized:

1. Microvolt offset voltage: the low

cost grades (including the small-

outline, 8-pin surface-mount pack-

age) are guaranteed to 75µV

2. Drift guaranteed to 0.5µV/°C

(0.75µV/°C low cost grades)

3. Bias and offset currents are in the

picoampere range, even at 125°C

4. Low noise: 0.32µV peak-to-peak,

0.1Hz to 10Hz

5. Supply current is 400µA max.

per amplifier

6. Voltage gain is in excess of one

million

Therefore, there are very few preci-

sion op-amp applications, where the

LT1112/LT1114 will not be the dual

or quad op amp of choice. They can be

stocked as the universal dual or quad

and used without time-consuming

error-budget calculations. Table 1 lists

the guaranteed specifications.

LT1112/LT1114 Dual/Quad Precision Op

Amps have Universal Appeal by George Erdi

Figure 1. Standard S8 pin configuration and LTC proprietary S8 pin configuration

Table 1. LT1112 dual, LT1114 quad

low-cost grades, guaranteed specifications

= ±15V, T

= 25°C

Parameter Typical Min/Max Units

Offset Voltage 25 75 µV

Drift with Temperature

Plastic/CERDIP 0.2 0.75 µV/°C

SO-8 0.4 1.3 µV/°C

Offset Current 60 230 pA

Bias Current 80 280 pA

Noise 0.1 to 10Hz 0.32 — µVP–P

At 1kHz 13 20 nV/√Hz

Supply Current/Amp 350 450 µA

Gain 5000 800 V/mV

CMRR 136 115 dB

Table 3. Specifications for low-cost grades

with ±1.0V supplies, T

= 25°C

Parameter Typical Min/Max Units

Offset Voltage 45 130 µV

Drift with Temperature

Plastic/CERDIP 0.25 — µV/°C

SO-8 0.45 — µV/°C

Supply Current/Amp 320 420 µA

Common-Mode

Range +250, –320 — mV

Swing (Light Load) ±270 — mV

DESIGN INFORMATION

Standard SO8

Dual-Pin Configuration

The LT1112 is the first dual op

amp offered by Linear Technology

with the standard SO8 pin configu-

ration (Figure 1), i.e., the pin loca-

tions are identical to the plastic or

CERDIP packages. Note that the in-

dustry-standard package is called

the SO8 package. To order this pack-

age type, add S8 to the LTC part

number, as illustrated in Figure 1.

Matching Specifications

In addition to the outstanding specs

of Table 1, the LT1112 and LT1114

also provide a full set of matching

specifications, facilitating their use in

such matching-dependent applica-

tions as two and three op amp instru-

mentation amplifiers (Table 2). The

performance of these instrumenta-

tion amplifiers will be limited by the

matching parameters only—not

by the specifications of the individual

amplifiers (Figure 2).

Guaranteed Specs

for ±1.0V Supplies

Another set of specifications is

furnished for ±1V supplies. This, com-

bined with the low 320µA supply

current per amplifier, allows the

Table 2. Guaranteed matching specifications

of low-cost grades, V

= ±15V, T

= 25°C

Parameter Typical Min/Max Units

Offset Voltage Match 40 130 µV

Drift with Temperature

Plastic/CERDIP 0.3 1.0 µV/°C

SO-8 0.5 1.9 µV/°C

Non-Inverting

Bias Current Match 100 500 pA

Common-Mode

Rejection Match 136 113 dB

Power-Supply

Rejection Match 130 112 dB

1OUT A

–IN A

+IN A

–

+IN B

–IN B

OUT B

TOP VIEW

S8 PACKAGE

8-LEAD PLASTIC SOIC

1+IN A

–

+IN B

–IN B OUT B

OUT A

–IN A

TOP VIEW

S8 PACKAGE

8-LEAD PLASTIC SOIC

1112_1.eps

LT1112S8 LT1013DS8

LT1057S8

LT1078S8

LT1124CS8

LT1126CS8

Linear Technology Magazine • October 1992

Digital Considerations

The LTC1196/1198 will interface

via three or four wires to ASICs, PLDs,

microprocessors, DSPs, and shift reg-

isters. To run at its fastest conversion

rate (600ns) it must be clocked at

14.3MHz. HC logic families and any

high speed ASIC or PLD will easily

interface to the ADC at that speed.

Connection to a microprocessor or

DSP serial port is very easy. It requires

no additional hardware, but the speed

will be limited by the clock rate of the

microprocessor or DSP. The TMS320

family’s 7MHz serial-port clock rate is

the fastest available at the present

time. This limits the conversion time of

the LTC1196/1198 to about 1µs. Full-

speed operation can still be achieved

with 3V ASICs, PLDs or HC logic cir-

cuits. Check the clock frequency and

timing specifications of your particular

ASIC or PLD.

The reference input can be driven

with standard voltage references. By-

passing the reference with at least

0.1µF is recommended to keep the

high-frequency impedance low. Some

references require a small resistor in

series with the bypass cap for fre-

quency stability. See the individual

reference data sheets for details.

To achieve the full sampling rate,

the analog input should be driven with

a low-impedance source (<100Ω) or a

high-speed op amp (e.g., the LT1223,

LT1191, or LT1226). Higher-imped-

ance sources or slower op amps can

easily be accommodated by allowing

more time between conversions for the

analog input to settle.

CONCLUSION

The new LTC1196 and LTC1198

must be considered as an alternative to

half-flash ADCs in high-speed data

acquisition systems because of their

high conversion speeds, small size, low

cost, low power consumption, and their

ability to operate on both 3V and 5V

power supplies.

DESIGN INFORMATION

–

1112_2.eps

–

R4

100Ω

0.5%

OUTPUT

R7

9.88k

0.5%

R9

200Ω

R5

100Ω

0.5%

R1

10k

R3

2.1k

R8

200Ω

R2

10k

INPUT+

1/2 LT1112

OR

1/4 LT1114

LT1097 OR

1/4 LT1114

B OR C

GAIN = 1000

R6

10k 

0.5%

R10

C1

33pF

1/2 LT1112

OR

1/4 LT1114

INPUT–

TRIM R8 FOR GAIN

TRIM R9 FOR DC COMMON MODE REJECTION

TRIM R10 FOR AC COMMON MODE REJECTION

TYPICAL PERFORMANCE OF THE 

INSTRUMENTATION AMPLIFIER:

INPUT OFFSET VOLTAGE = 40µV

OFFSET VOLTAGE DRIFT = 0.3µV/°C

INPUT BIAS CURRENT = 80pA

INPUT OFFSET CURRENT = 100pA

INPUT RESISTANCE = 800GΩ

INPUT NOISE = 0.5µVP-P

Figure 2. Three op amp instrumentation amp with gain = 100

–

1112_4.eps

–

TOTAL SUPPLY CURRENT = 700µA.

WORKS WITH BATTERIES DISCHARGED TO ±1.3V.

AT ±1.5V: MAXIMUM LOAD CURRENT = 800µA;

CAN BE INCREASED WITH OPTIONAL R

, R

;

AT R

= R

= 750Ω LOAD CURRENT = 2mA.

TEMPERATURE COEFFICIENT LIMITED BY

REFERENCE = 20ppm/°C.

15k

1/2 LT1112

LT1004-1.2 20k

0.1%

+0.617V

+1.5V

20k

0.1%

– 0.617V

100pF

(OPTIONAL)

–1.5V

(OPTIONAL)

Figure 3. Dual-output reference

operates on two AA cells

LT1112/LT1114 to be powered by two

nearly discharged AA cells (Table 3).

A dual-output, buffered reference

application is shown in Figure 3.

Figure 3 works on two AA batteries,

which can be discharged to ±1.3V. With

two equal 20k resistors, two equal but

opposite-sign reference voltages are

available. Changing the ratio of the two

0.1% resistors allows for other values:

one positive and one negative.

LTC1196/1198, continued from page 7

INPUT FREQUENCY, fIN (Hz)

EFFECTIVE NUMBER OF BITS, ENOBs

1k 100k 1M

1196_5. eps

010k

VCC = 3V

fSAMPLE = 450kHz

VCC = 5V

fSAMPLE = 1.2MHz

Figure 5. LTC1196/1198 ENOBs

vs. input frequency

Linear Technology Magazine • October 1992

A 3.3V-powered MOSFET driver is

now available. The LTC1157 dual mi-

cropower MOSFET driver makes it pos-

sible to switch either supply- or

ground-referenced loads through a low

DS(ON)

, N-channel switch. N-channel

switches are required at 3.3V because

P-channel MOSFETs do not have guar-

anteed R

DS(ON)

with V

= 3.3V. The

LTC1157's internal charge pump

boosts the gate-drive voltage 5.4V

above the positive rail (8.7V above

ground), fully enhancing a logic-level,

N-channel MOSFET for 3.3V high-

side switching applications.

The LTC1157 Dual 3.3V

Micropower MOSFET Driver by Tim Skovmand

voltage to drive a logic-level, high-side

N-channel switch into full enhance-

ment. This combination of a low R

DS(ON)

MOSFET switch and micropower gate

drive produces the maximum switch

efficiency in 3.3V and 5V high-side

switch applications.

Typical Applications

Figure 3 illustrates how two sur-

face-mount MOSFETs and the

LTC1157 (also available in 8-pin SO

packaging) can be used to switch two

3.3V loads. The gate rise and fall times

are typically in the tens of microsec-

onds, but can be slowed by adding two

resistors and a capacitor, as shown on

the second channel. Slower rise and

fall times are sometimes required to

reduce the start-up current demands

of large supply capacitors, which might

otherwise glitch the main supply.

DESIGN INFORMATION

GATE-TO-SOURCE VOLTAGE (V)

DRAIN-TO-SOURCE RESISTANCE (Ω)

0.1

100

2.0 4.0 6.0 7.0

1157_2.eps

0.01 3.0 5.02.5 4.5 6.53.5 5.5

LTC1157 SUPPLY VOLTAGE

3.0V, 3.3V, 3.6V

Figure 2. R

DS(ON)

vs V

for typical

logic level, N-channel MOSFET switch

Figure 1. Gate voltage above supply

vs. supply voltage

Figure 3. LTC1157 used to switch two 3.3V loads

SUPPLY VOLTAGE (V)

GATE

– V

(V)

2.0 4.0 6.0

1157_1.eps

03.0 5.02.5 4.53.5 5.5

1157_3.eps

IN1

IN2

LTC1157

GND

µP OR

CONTROL

LOGIC

3.3V LOAD

LARGE

SUPPLY

CAPACITOR

IRLR024

10µF

3.3V

3.3V LOAD

1k100k

0.1µF

Logic Level MOSFET Switches

Figure 2 is a graph of R

DS(ON)

versus

for a typical logic-level, N-channel

MOSFET switch. The R

DS(ON)

drops

dramatically as the gate voltage is

taken above the threshold voltage

(1–2V) and begins to flatten off at

about 3.5V. Further gate drive does

not significantly reduce the R

DS(ON)

because the MOSFET channel is al-

ready fully enhanced. By mapping the

LTC1157 supply voltage onto Figure

2, it can be seen that the on-chip

charge pump produces ample gate

On-Chip Charge Pump

The charge pump is completely on-

chip and therefore requires no external

components to generate the higher gate

voltage. Figure 1 is a graph of gate

voltage above supply versus supply

voltage. The charge pump has been

designed to be very efficient, requiring

only 3 microamps in the standby mode

and 80 microamps while delivering 8.7V

to the power MOSFET gate. This makes

the LTC1157 particularly well suited

for battery-powered applications, which

benefit from micropower operation.

Linear Technology Magazine • October 1992

The LT1028 was introduced in 1986.

With its 0.85nV/√Hz noise (less than

that of a 50Ω resistor) it became the

lowest voltage-noise op amp, wresting

the title from the LT1007, which fea-

tures noise of 2.5nV/√Hz. The LT1028

combined minuscule noise with

excellent precision and high-speed

specifications (Table 1).

Six years later, the LT1028 is still

the reigning low-noise champion. In

addition, the LT1028 is now available

in the 8-pin small-outline surface-

mount package—designated as the

LT1028CS8. For many op amps, as-

sembly shifts in the surface-mount

packages necessitate a loosening of

specifications compared to other pack-

ages. For the LT1028CS8, spec

relaxation is not necessary. The

“C” designation indicates that the

LT1028CS8’s specifications are iden-

tical to the LT1028CH, LT1028CJ8,

and LT1028CN8.

The LT1028 is stable in closed-loop

gains of +2 or –1, not as a voltage

follower. At first glance, this should

never be a problem, since proper use of

the LT1028 always involves amplifica-

tion of microvolt-level signals to take

advantage of its low noise. However, to

optimize noise, the bandwidth of the

amplifier should be limited to the band-

width of the signal being processed. In

many applications, the only conve-

nient means of limiting bandwidth is

to connect a capacitor (C

) in parallel

with the feedback resistor. At high

frequencies this capacitor becomes a

short, requiring a unity-gain-stable

amplifier.

Enter the LT1128

The LT1028 is stable for many com-

binations of R

, R

, and C

The LT1128,

however, is unconditionally stable for

all values of R

, R

, and C

Another example which requires

unity-gain stability is shown in

The World’s Lowest-Noise Op Amp is

Now Available in 8-pin SO and in a

Unity-Gain Stable Version by George Erdi

and Alexander Strong

Figure 1.

Here, a heavy capacitive load,

, is isolated from the op amp’s output

by resistor R1. The extra phase shift

caused by the R1, C

pole is eliminated

from consideration by the presence of

C1, which shorts the op amp’s output

to its input at high frequencies.

Op amp instrumentation amplifiers

usually have op amps with a fixed gain

greater than one at the input stage

(Figure 2). At low frequencies, decom-

pensated op amps work well, but at

high frequencies and with one input

grounded, the virtual ground begins to

lose its integrity. As the frequency of

the input signal increases, the ampli-

tude at the virtual ground increases,

making the virtual ground look

inductive, eventually requiring a unity-

gain-stable amplifier. The LT1028 can

be made stable under these conditions

with bypass capacitors and a little

experimenting, but the LT1128 is un-

conditionally stable.

The LT1028/LT1128 team offers the

user excellent AC performance, un-

conditional DC stability, and the low-

est noise available in an op amp. All of

these features are now available in the

SO8 surface mount package.

Table 1. LT1028/LT1128 Comparison

LT1028A/ LT1028C/

1128A 1128C Units

VOS 40 80 µV Max

TCVOS 0.8 1.0 µV/°C Max

IB±90 ±180 nA Max

en10kHz 1.0 1.0 nV/√Hz Typ

1kHz 0.85 0.9 nV/√Hz Typ

1kHz (100% tested) 1.1 1.2 nV/√Hz Max

AVOL RL = 1k 5.0 5.0 V/µV Min

SR 1028 11.0 11.0 V/µs Min

1128 5.0 4.5 V/µs Min

GBW 1028 fo = 20kHz 50 50 MHz Min

1128 fo = 200kHz 13 11 MHz Min

Figure 2. Three op amp, ultra-low noise instrumentation amplifier

1028_2.eps

–

LT1128

1028_3.eps

–

10k300Ω

300Ω

820

56Ω

820

10k

LT1128

LT1037

AC SIGNAL INCREASES WITH

FREQUENCY AT THIS NODE GAIN = 1000

INPUT REFERRED NOISE = 1.5nV/√Hz at 1kHz

WIDE BAND NOISE = 1.4µV

RMS

IF BAND LIMITED TO DC TO 100kHz = 0.6µV

RMS

GAIN BANDWIDTH PRODUCT = 400MHz

AC V

Figure 1. Driving a heavy capacitive load

DESIGN INFORMATION

Linear Technology Magazine • October 1992

It is often convenient to control the

gain of a video or intermediate fre-

quency (IF) circuit with a voltage. The

LT1228, along with a suitable voltage-

to-current converter circuit, forms a

versatile gain-control building block

ideal for many of these applications.

In addition to gain control over video

bandwidths, this circuit can add a

differential input and has sufficient

output drive for 50Ω systems.

The transconductance of the

LT1228 is inversely proportional to

absolute temperature at a rate of –

0.33%/°C. For circuits using closed-

loop gain control (i.e., IF or video

automatic gain control) this tempera-

ture coefficient does not present a

problem. However, open-loop gain-con-

trol circuits that require accurate gains

may require some compensation. The

circuit described here uses a simple

thermistor network in the voltage-to-

current converter to achieve this com-

pensation. Table 1 summarizes the

circuit’s performance.

A Temperature-Compensated,

Voltage-Controlled-Gain

Amplifier Using the LT1228 by Frank Cox

Input Signal Range 0.5V – 3.0V pk

Desired Output Voltage 1.0V pk

Frequency Range 0Hz – 5MHz

Operating Temperature Range 0°C – 50°C

Supply Voltages ±15V

Output Load 150Ω (75Ω + 75Ω)

Control Voltage vs

Gain Relationship 0V to 5V Min to Max Gain

Gain Variation

Over Temperature ±3% from Gain at 25°C

Table 1. Characteristics of example

Figure 1 shows the complete sche-

matic of the gain-control amplifier.

Please note that these component

choices are not the only ones that will

work nor are they necessarily the best.

This circuit is intended to demonstrate

one approach out of many for this very

versatile part and, as always, the

designer’s engineering judgment must

be fully engaged. Selection of the

values for the input attenuator,

gain-set resistor, and current-feedback-

amplifier resistors is relatively straight-

forward, although some iteration is

usually necessary. For the best band-

width, remember to keep the gain-set

resistor, R1, as small as possible, and

the set current as large as possible

Figure 1. Differential-input, variable-gain amplifier

(with due regard for gain compression).

The voltage-controlled current source

SET

) is detailed in the boxed section.

Several of these circuits have been

built and tested using various gain

options and different thermistor val-

ues. Test results for one of these

circuits are shown in Figure 2. The

gain error versus temperature for this

circuit is well within the limit of ±3%.

Compensation over a much wider range

of temperatures or to tighter tolerances

is possible, but would generally re-

quire more sophisticated methods,

such as multiple thermistor networks.

The VCCS is a standard circuit with

the exception of the current-set resis-

tor R5, which is made to have a

temperature coefficient of –0.33%/°C.

R6 sets the overall gain and is made

adjustable to trim out the initial toler-

ance in the LT1228 gain characteristic.

A resistor (R

) in parallel with the ther-

mistor will tend, over a relatively small

range, to linearize the change in

resistance of the combination with tem-

perature. R

trims the temperature

coefficient of the network to the desired

value.

DESIGN IDEAS

Figure 2. Gain error for circuit in Figure 1

plus temperature compensation circuit shown

in Figure 3 (normalized to gain at 25°C)

1228_1. eps

VCON

–

ISET

R4

–15V

RG

82.5

RF

750

R2

274

R3

274

R3A

10.7k

R2A

10.7k

+15V

4.7µF

ROUT

RLOAD

CFA

R1

806

4.7µF

TEMPERATURE (°C)

–25

–3

ERROR (%)

–2

–1

–12.5 12.5 50 75

1228_5. eps

0 37.5 62.5

GAIN = 6dB

GAIN = 3dB

GAIN = –6dB

Linear Technology Magazine • October 1992

VCCS Design Steps

Measure or obtain from the data

sheet the thermistor resistance at

three equally spaced temperatures

(in this case 0°C, 25°C, and 50°C).

Find R

from:

(R0 × R25 + R25 × R50 - 2 × R0 × R50)

(R0 + R50 - 2 × R25)

where R0 = thermistor resistance at 0°C

R25 = thermistor resistance at 25°C

R50 = thermistor resistance at 50°C

Resistor R

is placed in parallel

with the thermistor. This network

has a temperature dependence

that is approximately linear over

the range given (0°C–50°C).

3. The parallel combination of the

thermistor and R

||R

) has a

temperature coefficient of resis-

tance (temp. co.) given by:

4. T

he desired temp. co. to compen-

sate the LT1228 gain tempera-

ture dependence is –0.33%/°C.

A series resistance (R

) is added to

the parallel network to trim its

temp. co. to the proper value. R

given by:

whereT

HIGH

= the high temperature

LOW

= the low temperature

= the thermistor

5. R6 contributes to the resultant

temp and so is made large with

respect to R5.

6. The other resistors are calculated

to give the desired range of I

SET

This procedure was performed us-

ing a variety of thermistors (one

possible source is BetaTHERM corpo-

ration—phone 508-842-0516). Figure

5 shows typical results reported as

errors normalized to a resistance with

a –0.33%/°C temperature coefficient.

As a practical matter, the thermistor

need only have about a 10% tolerance

for this gain accuracy. The sensitivity

of the gain accuracy to the thermistor

tolerance is decreased by the linear-

ization network, in the same ratio as

is the temperature coefficient; The

room temperature gain may be

trimmed with R6. Of course, particu-

lar applications require analysis of

aging stability, interchangeability,

package style, cost, and the contribu-

tions of the tolerances of the other

components in the circuit.

(temp. co. R

||R

)

(0.33) × (R

||R

)-(R

||R

)

Voltage-Controlled Current Source (VCCS)

with a Compensating Temperature Coefficient

temp. co. RP||RT = )((

DESIGN IDEAS

Figure 3. Voltage-controlled current source (VCCS) with a

compensating temperature coefficient

CON

(V)

SET

(MIN)

1228_4. eps

SET

(MAX)

TEMPERATURE (°C)

–10

RESISTANCE (Ω)

12k

14k

1228_3a. eps

0 102030405060

10k

COMPENSATED NETWORK

THERMISTOR

Figure 6. Thermistor-network resistance

normalized to a resistor with exact

–0.33%/°C temp. co.

TEMPERATURE (°C)

–60

–12

ERROR (%)

–10

–8

–4

–2

–40 0 40 80

1228_3b. eps

–20 20 60

–6

)

1228_2. eps

–

LT1006

50pF

R6

266k

R7

2.26M

CON

S

4320

P

1780

R8

150k 2N3906

SET

= R6 V

R5 R8 R7

2.2k3A1

= REF VoHoge

Figure 5. Thermistor and thermistor

network resistance vs. temperature

Figure 4. Voltage control of I

SET

with

temperature compensation

R0||RP - R50||RP 100

R25||RP THIGH -T

LOW

Linear Technology Magazine • October 1992

SHUTDOWN

5V/DIV 0

VPP



5V/DIV

Nonvolatile “flash” memories require

a well-controlled 12V bias (VPP) for

programming. The tolerance on VPP is

±5% for 12V memories. Excursions in

VPP above 14V or below –0.3V are

destructive. VPP is often generated with

a boost regulator whose output follows

the input supply when shut down. It is

sometimes desirable to force VPP to 0V

when the memory is not in use or in

read-only mode.

The circuit in Figure 1 generates a

smoothly rising 12V, 60mA supply that

drops to 0V under logic control. Shortly

after driving the SHUTDOWN pin high,

Even with the additional losses in-

troduced by Q1, efficiency is 83% with

a 60mA load. Line and load regulation

are both less than 1%. Output ripple is

about 100mV under light loads. Qui-

escent current drops to 400µA when

shut down. All components shown in

Figure 1 are available in surface mount

packages, making the circuit well suited

for flash memory cards and other ap-

plications where minimizing pc-board

space is critical.

Flash-Memory VPP Generator

Shuts Down with 0V Output by Sean Gold

DESIGN IDEAS

the LT1109-12 switching regulator

drives L1, producing high-voltage

pulses at the device’s switch pin (Fig-

ure 2). The 1N5818 Schottky diode

rectifies these pulses and charges a

reservoir capacitor C2. Q1 functions

as a low-on-resistance pass element.

The 1N4148 diode clamps Q1 for re-

verse voltage protection. The circuit

does not overshoot or display unruly

dynamics, because the regulator gets

its DC feedback directly from the out-

put at Q1’s collector. Minor slew aber-

rations are due to Q1’s switching

characteristics.

1109a_1.eps

GND

VIN SW

LT1109A-12

VPP

12V AT 60mA

1N5818

4.5 < VIN < 5.5

SHUTDOWN PROGRAM

SHUTDOWN

33µH

C3

1µF

C1

22µF

1N4148

SENSE

C2

22µF

Q1

2N4403

5kΩ

Figure 1. Boost-mode switching regulator with low R-on pass transistor

for flash-memory programming

LCD Bias Supply by Steve Pietkiewicz

regulation is less than 0.2% from 3.3V

to 2V inputs. Although load regulation

suffers somewhat because

the –24V output is not directly

regulated, it measures 2% for

loads from 1mA to 7mA. The

circuit will deliver 7mA from a

2V input at 75% efficiency.

An LCD requires a bias supply for

contrast control. The supply’s variable

negative output permits adjustment of

display contrast. Relatively little power

is involved, easing RF radiation and

efficiency requirements. An LCD bias

generator is shown in Figure 1. In this

circuit, U1 is an LT1173 micropower

DC-to-DC converter. The 3V input is

converted to +24V by U1’s switch, L2,

D1, and C1. The switch pin (SW1) also

drives a charge pump composed of C2,

C3, D2, and D3 to generate –24V. Line

3V

2 AA

CELL

R1

100

OPERATE SHUTDOWN

* TOKO 262LYF-0092K

D4

1N4148 C3

22µF

R2

120k

R4

2.21M

C1

0.1µF

C2

4.7µF

D3

1N5818

D2

1N5818

OUTPUT 

–12V TO –24V

L1*

100µH

1173_1.eps

U1

LT1173

LIM

SW1

SW2GND

D1

1N5818

R3

100k

OUTPUT

+12V TO +24V

Figure 2. Input and output waveforms for the

flash-memory programming circuit

Figure 1. DC to DC Converter Generates LCD Bias

Linear Technology Magazine • October 1992

New Device Cameos

LT1201/LT1202: High-Speed,

Low-Power, Dual and Quad

Operational Amplifiers

The LT1201 is a dual version of the

LT1200 high-speed, low-power opera-

tional amplifier; the LT1202 is a quad

version. Each unity-gain-stable am-

plifier has an 11MHz gain bandwidth,

50V/µs slew rate, and 430ns settling

time to 0.1% (10V step), and draws

only 1mA of quiescent supply current.

The LT1201/1202 are ideal choices

for applications where power consump-

tion and board space must be mini-

mized. With 1mV maximum offset

voltage, 100nA maximum offset cur-

rent, and 8V/mV open-loop gain com-

bined with fast settling, the LT1201/

1202 are excellent choices for fast

data-acquisition systems.

Each amplifier can drive a 2kΩ load

to ±12V from a ±15V supply and can

drive 500Ω to ±3V on ±5V supplies.

The amplifiers are stable with all ca-

pacitive loads, which makes them use-

ful as buffers or for driving A-to-D

converters. Wideband active filters are

another excellent application, espe-

cially where power consumption is

critical due to battery operation.

The LT1201 comes in the industry-

standard pinout in 8-lead plastic

mini-DIP or 8-lead, small-outline sur-

face-mount package. The LT1202

comes in 14-lead plastic DIP.

LT1208/LT1209: 50MHz,

400V/µs Dual and Quad

Operational Amplifiers

The LT1208 is a dual version of the

LT1224 high-speed operational am-

plifier; the LT1209 is a quad version.

Each amplifier is unity-gain stable

with 50MHz gain bandwidth, 400V/µs

slew rate, 90ns settling time to 0.1%

(10V step), and 7mA of supply current.

The LT1208 and LT1209 are ideal

choices for applications where high

speed is essential and board space

must be minimized.

The LT1208/1209 DC specifications

include 2mV maximum offset voltage,

400nA maximum offset current, and

The LTC1154 High-Side,

Microprocessor-Compatible,

Micropower MOSFET Driver

The LTC1154 single micropower gate

driver is designed to drive a standard

N-channel power MOSFET in a high-

side switch configuration. The LTC1154

contains an on-chip charge pump so

that less expensive, lower R

DS(ON)

N-

channel MOSFETs can be used in place

of P-channel switches. The charge pump

requires no external components and

has been designed to be very efficient,

requiring only microamps to operate.

All of the circuitry to drive, control,

and protect the power MOSFET and

load, and to interface to a host micro-

processor, are provided by the

LTC1154. The input is compatible with

both TTL and CMOS logic families and

the standby current with the input

switched off is only 8 microamps from

a 5V supply. The quiescent current

rises to 85 microamps when the switch

is turned on and the charge pump is

producing 12V from a 5V supply. An

active-low enable input is provided to

control multiple LTC1154 switches in

banks. An open-drain status output is

provided to advise the microprocessor

when a fault condition exists at the

output of the switch. If an over-current

condition is detected at the drain end of

the power MOSFET, the output is

latched off and the status pin is pulled

low. A built-in 10-microsecond delay

ensures that the LTC1154 protection

circuitry is not false triggered by tran-

sient load or power-supply conditions.

A longer RC delay can be added exter-

nally to accommodate loads with large

transient start-up current require-

ments, such as lamps or DC motors.

The versatile microprocessor inter-

face, coupled with the comprehensive

protection features and micropower

operation, make the LTC1154 the ideal

choice for applications that require

maximum efficiency and protection on

a lean power budget. And the 8-lead

SO packaging makes it the ideal choice

for applications with a lean board-

space budget.

7V/mV open-loop gain. The outputs

can drive a 500Ω load to ±12V with a

±15V supply and can drive 150Ω to

±3V on a ±5V supply.

The amplifiers are stable with all

capacitive loads, which makes them

useful as buffers or in cable-driving

applications. The excellent settling time

lends itself to data-acquisition appli-

cations, such as DAC current-to-volt-

age converters and A-to-D input

buffers. Other applications include

wide-band active filters, RF amplifica-

tion, and video amplifiers.

The LT1208 comes in the industry-

standard pinout in an 8-lead plastic

mini-DIP or 8-lead small-outline sur-

face-mount package. The LT1209

comes in 14-lead plastic DIP.

The LTC1250 Very-Low-Noise

Bridge Op Amp

The LTC1250 is a zero-drift op amp

optimized for use with bridge trans-

ducers. It features typical 0.1Hz–10Hz

noise of 0.65µV

P–P

and 0.1Hz–1Hz

noise of 0.2µV

P–P

, making it ideal for

use with low noise, low frequency sig-

nals. The LTC1250’s 10µV maximum

offset, 50nV/°C maximum drift, and

±150pA maximum bias currents keep

DC errors negligible. The zero-drift

loop samples the input at 5kHz, allow-

ing signals up to 2.5kHz to be ampli-

fied with no aliasing. All of the zero-drift

circuitry is integrated on-chip, allow-

ing the LTC1250 to plug into standard

op-amp sockets with no additional

external components.

The LTC1250 has an enhanced

CMOS output stage capable of swing-

ing ±4V into 1kΩ with ±5V supplies; it

will swing to within millivolts of the rail

into lighter loads. 10V/µs slew rate

and 1.5MHz gain bandwidth allow the

LTC1250 to track input transients.

The inputs recover from overload in

1.5ms, many times faster than stan-

dard zero-drift op amps with external

capacitors. The LTC1250 is ideally

suited for electronic scales, pressure

transducers, and low-frequency digi-

tizing applications.

NEW DEVICE CAMEOS

Linear Technology Magazine • October 1992

LT1269: 4A, 100kHz, High-

Efficiency Switching Regulator

A new integrated switching

regulator IC, the LT1269, allows high-

efficiency converters to be constructed

using smaller inductors than were re-

quired with previous devices.

Similar to the LT1271 and other

members of LTC’s 5-pin integrated

switching-regulator family, the LT1269

contains a 100kHz current-mode PWM

control section, a fully integrated 4A

high-efficiency switch, and fault pro-

tection on a single chip. It can be

operated in all standard switching con-

figurations, including buck (step-

down), boost (step-up), flyback,

inverting, and others.

Used with a companion control chip,

the LT1432, the LT1269 can be used to

make a very-high-efficiency 5V step-

down regulator for use with the typical

NiCad and Nickel-Hydride battery

packs used in portable computers. In

addition to providing high efficiency

(≈90%) at load currents of 1A and

beyond, the device, when used with the

LT1432, accomplishes the difficult task

of maintaining high efficiency under

low power-demand conditions. Such

conditions are encountered in portable

computers when power-management

schemes such as “suspend-mode” are

employed.

A 3.3V version of the LT1432 that

allows the LT1269 to be used to gener-

ate 3.3V logic supplies with high

efficiency is now available (see below).

The LT1269 comes in a 5-lead TO-220

and a 5-lead DD surface-mount pack-

age is planned for future release.

LT1432: 3.3 High-Efficiency,

Step-Down Switching-

Regulator Controller

The LT1432-3.3 is an 8-pin control

chip designed to work in conjunc-

tion with LTC’s family of 5-pin

integrated switching regulators to

make very-high-efficiency 3.3V

switching regulators with advanced

power-management capability.

High efficiency at nominal output

currents from 0.1A to over 3A is

achieved by employing one of LTC’s

LT1070 family of low-loss switching

regulators in buck mode, while using

the LT1432-3.3 for feedback signal

conditioning. Portable, battery-powered

systems achieve significant power sav-

ings for increased battery life by using

an idle or “suspend” mode when the

system is not actively in use. Notebook

computers typically employ such a

power-saving scheme. In the suspend

mode, when output load demand is

light, the LT1432-3.3 can place the

main regulator into a “burst” mode to

maintain high efficiency at low load

currents (0 to 50mA). A logic-compat-

ible shutdown pin is included that,

when taken high, shuts the entire regu-

lator down.

The LT1432-3.3 is offered in an

8-lead SOIC package and an 8-pin

mini-DIP.

LT1129: 700mA Low-Iq,

Low-Dropout Regulator

The LT1129 is a low-dropout regu-

lator with ultra-low quiescent current

and shutdown current. The device can

supply over 700mA of output current

with a dropout voltage of 0.4V at maxi-

mum output. The low 50µA quiescent

current in operating mode and 30µA in

shutdown mode is perfect for battery

powered operation. This quiescent cur-

rent does not rise in the dropout region

as it does with other low-dropout PNP

regulators.

Other features of the LT1129 in-

clude the ability to operate with

small output capacitors. Stability is

guaranteed with only 3.3µF of output

capacitance, whereas other low-drop-

out regulators require as much as

100µF. The input of the LT1129 may be

connected to ground, or reverse input

voltages may be applied without cur-

rent flow from the output to the input.

This makes LT1129 ideal for back-up

power applications where the output is

held high while the input is at ground.

The device is available in 5-lead TO-

220 and surface mount DD packages.

New Publications

AN49: Illumination Circuitry for

Liquid Crystal Displays (Tripping the

Light Fantastic...) Liquid crystal dis-

plays have become almost universal in

NEW DEVICE CAMEOS

For further information on

the above or any other devices

mentioned in this issue of Linear

Technology, use the reader service

card or call the LTC literature-

service number: (800) 637-5545.

Ask for the pertinent data sheets

and application notes.

Information furnished by Linear Technology Cor-

poration is believed to be accurate and reliable.

However, no responsibility is assumed for its use.

Linear Technology makes no representation that

the circuits described herein will not infringe on

existing patent rights.

portable instruments and computers.

In dimly lit environments some form of

backlighting is required to make the

LCD panel readable. The preferred light

source is a cold-cathode fluorescent

lamp, otherwise known as a “CCFL.”

CCFLs are relatively efficient light

sources, but they require special power

supplies to develop high starting and

running voltages (up to 1kV). AN49

explains the nature of the CCFL as a

load, and tells how to design a suitable

power supply.

The circuits described in AN49 pre-

serve the overall efficiency of the CCFL

to extend battery life in portable sys-

tems and eliminate “hot spots” inside

the product.

AN51: Power Conditioning for

Notebook and Palmtop Systems Note-

book and palmtop systems need a

multiplicity of regulated voltages de-

veloped from a single battery. Small

size, light weight, and high efficiency

are mandatory for competitive solu-

tions in this area. Small increases in

efficiency extend battery life, making

the final product much more usable

with no increase in weight. Addition-

ally, high efficiency minimizes the heat

sinks needed on the power-regulating

components, further reducing system

weight and size.

AN51 presents a collection of twenty

circuits that represent state-of-the-art

solutions to power-supply problems in

portable computing products. These

circuits were designed for high effi-

ciency and small size, and cover every

requirement from battery charging to

LCD-bias generation.

Linear Technology Magazine • October 1992

LINEAR TECHNOLOGY CORPORATION

1630 McCarthy Boulevard

Milpitas, CA 95035-7487

(408) 432-1900

Literature Department (800) 637-5545

FRANCE

Linear Technology S.A.R.L.

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FAX: 33-1-46314613

GERMANY

Linear Technology GMBH

Untere Hauptstr. 9

D-8057 Eching

Germany

Phone: 49-89-3194710

FAX: 49-89-3194821

JAPAN

Linear Technology KK

5F YZ Building

4-4-12 Iidabashi Chiyoda-Ku

Tokyo, 102 Japan

Phone: 81-3-3237-7891

FAX: 81-3-3237-8010

KOREA

Linear Technology Korea Branch

Namsong Building, #505

Itaewon-Dong 260-199

Yongsan-Ku, Seoul

Korea

Phone: 82-2-792-1617

FAX: 82-2-792-1619

SINGAPORE

Linear Technology Pte. Ltd.

101 Boon Keng Road

#02-15 Kallang Ind. Estates

Singapore 1233

Phone: 65-293-5322

FAX: 65-292-0398

TAIWAN

Linear Technology Corporation

Rm. 801, No. 46, Sec. 2

Chung Shan N. Rd.

Taipei, Taiwan, R.O.C.

Phone: 886-2-521-7575

FAX: 886-2-562-2285

UNITED KINGDOM

Linear Technology (UK) Ltd.

The Coliseum, Riverside Way

Camberley, Surrey GU15 3YL

United Kingdom

Phone: 011-44-276-677676

FAX: 011-44-276-64851

International

Sales Offices

CENTRAL REGION

Linear Technology Corporation

Chesapeake Square

229 Mitchell Court, Suite A-25

Addison, IL 60101

Phone: (708) 620-6910

FAX: (708) 620-6977

NORTHEAST REGION

Linear Technology Corporation

One Oxford Valley

2300 E. Lincoln Hwy., Suite 306

Langhorne, PA 19047

Phone: (215) 757-8578

FAX: (215) 757-5631

NORTHWEST REGION

Linear Technology Corporation

782 Sycamore Dr.

Milpitas, CA 95035

Phone: (408) 428-2050

FAX: (408) 432-6331

SOUTHEAST REGION

Linear Technology Corporation

17060 Dallas Parkway

Suite 208

Dallas, TX 75248

Phone: (214) 733-3071

FAX: (214) 380-5138

SOUTHWEST REGION

Linear Technology Corporation

22141 Ventura Boulevard

Suite 206

Woodland Hills, CA 91364

Phone: (818) 703-0835

FAX: (818) 703-0517

U.S. Area

Sales Offices

World Headquarters

Linear Technology Corporation

1630 McCarthy Boulevard

Milpitas, CA 95035-7487

Phone: (408) 432-1900

FAX: (408) 434-0507

DESIGN TOOLS

Applications on Disk

NOISE DISK

This IBM-PC (or compatible) progam allows the user to

calculate circuit noise using LTC op amps, determine the

best LTC op amp for a low noise application, display the

noise data for LTC op amps, calculate resistor noise, and

calculate noise using specs for any op amp.

Available at no charge.

SPICE MACROMODEL DISK

This IBM-PC (or compatible) high density diskette contains

the library of LTC op amp SPICE macromodels. The

models can be used with any version of SPICE for general

analog circuit simulations. The diskette also contains work-

ing circuit examples using the models, and a demonstration

copy of PSPICE

by MicroSim.

Available at no charge.

Technical Books

1990 Linear Databook — This 1,440 page collection

of data sheets covers op amps, voltage regulators,

references, comparators, filters, PWMs, data conversion

and interface products (bipolar and CMOS), in both com-

mercial and military grades. The catalog features well over

300 devices.

$10.00

1992 Linear Databook Supplement — This 1248 page

supplement to the

1990 Linear Databook

is a collection of

all products introduced since then. The catalog contains full

data sheets for over 140 devices. The

1992 Linear Databook

Supplement

is a companion to the

1990 Linear Databook

which should not be discarded.

$10.00

Linear Applications Handbook — 928 pages full of

application ideas covered in depth by 40 Application Notes

and 33 Design Notes. This catalog covers a broad range of

“real world” linear circuitry. In addition to detailed, systems-

oriented circuits, this handbook contains broad tutorial

content together with liberal use of schematics and scope

photography. A special feature in this edition includes a 22-

page section on SPICE macromodels.

$20.00

Monolithic Filter Handbook — This 232 page book comes

with a disk which runs on PCs. Together, the book and disk

assist in the selection, design and implementation of the

right switched capacitor filter circuit. The disk contains

standard filter responses as well as a custom mode. The

handbook contains over 20 data sheets, Design Notes and

Application Notes.

$40.00

SwitcherCAD Handbook — This 144 page manual, in-

cluding disk, guides the user through SwitcherCAD – a

powerful PC software tool which aids in the design and

optimization of switching regulators. The program can cut

days off the design cycle by selecting topologies, calculat-

ing operating points and specifying component values and

manufacturer's part numbers.

$20.00