CMOS SDRAM K4S281633D-RL/N/P 8Mx16 SDRAM 54CSP (VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V) Revision 1.0 February 2002 Rev. 1.0 Feb. 2002 K4S281633D-RL/N/P CMOS SDRAM Revision History Revision 0.0 (February 21. 2001, Target) * First generation of 128Mb Low Power SDRAM without special function (VDD 3.0V, VDDQ 3.0V) Revision 0.1 (June 4. 2001, Target) * Addition of DC Current value. Revision 0.2 (June 20. 2001, Target) * Changed device name from low power sdram to mobile dram. Revision 0.3 (August 1. 2001, Target) * Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part. * Change of tOH from 3ns to 3.5ns. * Change VIH min. from 2.0 V to 0.8xV DDQ and V OH min. from 2.4V to 0.9xV DDQ. Revision 0.4 (October 6. 2001, Preliminary) * Changed DC current. * Changed of CL2 tSAC from 6ns to 7ns and CL3 tSAC from 6.5ns to 7ns for -75 part. * Changed of CL2 tSAC from 6.5ns to 8ns and CL1 tSAC from 18ns to 20ns for -1L part. * Changed of tOH from 3ns to 2.5ns. * Changed of tSS from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1L part. * Integration of VDDQ 1.8V device and 2.5V device. * Changed VIH min. from 0.8xVDDQ to 0.9xVDDQ and VOH min. from 0.9xVDDQ to 0.95xVDDQ. * Changed VIL max. from 0.8V to 0.3V and VOL min. from 0.4V to 0.2V. * Changed IOH from -0.1mA to -2mA and IOL from 0.1mA to 2mA. * Erased -15 bin and added -1H bin. Revision 0.5 (October 12. 2001, Preliminary) * Changed VIH min. from 0.9xVDDQ to 2.0V and VOH min. from 0.95xVDDQ to 2.4V. * Changed VIL max. from 0.3V to 0.8V and VOL min. from 0.2V to 0.4V. Revision 0.6 (November 7. 2001, Preliminary) * Changed VIH min. from 2.0V to 2.2V and VIL max. from 0.8V to 0.5V. Revision 1.0 (Feb. 2002, Final) * Final specification. * Changed tRDL from 2CLK to 10ns for -75 / -1H / -1L part. * Changed tDAL from 2CLK+tRP to tRDL+tRP. Rev. 1.0 Feb. 2002 CMOS SDRAM K4S281633D-RL/N/P 2M x 16Bit x 4 Banks SDRAM in 54CSP FEATURES GENERAL DESCRIPTION * 3.0V & 3.3V power supply. The K4S281633D is 134,217,728 bits synchronous high data * LVTTL compatible with multiplexed address. rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNGs high performance CMOS * Four banks operation. * MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). * All inputs are sampled at the positive going edge of the system clock. * Burst read single-bit write operation.. technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION * DQM for masking. Part No. * Auto refresh. K4S281633D-RL/N/P75 * 64ms refresh period (4K cycle). * Commercial Temperature Operation (-25C ~ 70 C). Extended Temperature Operation (-25C ~ 85C). Industrial Temperature Operation (-40C ~ 85C). * 54balls CSP. K4S281633D-RL/N/P1H Max Freq. Interface Package 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=2) LVTTL 54 CSP K4S281633D-RL/N/P1L 100MHz(CL=3)*1 -RL ; Low Power, Operating Temperature : -25'C~70'C. -RN ; Low Power, Operating Temperature : -25'C~85'C. -RP : Low Power, Operating Temperature : -40C ~ 85 C. Note : 1. In case of 40MHz Frequency, CL1 can be supported. FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select Output Buffer Sense AMP Row Decoder ADD Row Buffer Refresh Counter 2M x 16 2M x 16 2M x 16 DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 2M x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE LDQM UDQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.0 Feb. 2002 CMOS SDRAM K4S281633D-RL/N/P Package Dimension and Pin Configuration < Bottom View*1 > < Top View*2 > E1 54Ball(6x9) CSP 9 8 7 6 5 4 3 2 1 A 2 3 7 8 9 V DDQ DQ0 VD D V SS DQ15 VSSQ B DQ14 DQ13 V DDQ VSSQ DQ2 DQ1 C C DQ12 DQ11 VSSQ V DDQ DQ4 DQ3 D D DQ10 DQ9 V DDQ VSSQ DQ6 DQ5 E DQ8 NC V SS VD D LDQM DQ7 F F UDQM CLK CKE CAS RAS WE G G NC A11 A9 BA0 BA1 CS H H A8 A7 A6 A0 A1 A10 J J V SS A5 A4 A3 A2 VD D e A B D D1 1 E D/2 E E/2 *2: Top View A Pin Function CLK System Clock CS Chip Select CKE Clock Enable A0 ~ A 11 Address BA0 ~ BA 1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable *1: Bottom View L(U)DQM Data Input/Output Mask < Top View*2 > DQ 0 ~ 15 Data Input/Output V DD /VSS Power Supply/Ground V DDQ /VSSQ Data Output Power/Ground A1 Max. 0.20 Pin Name Encapsulant b z #A1 Ball Origin Indicator SEC Week RXXX K4S281633D [Unit:mm] Symbol Min Typ Max A 0.90 0.95 1.00 A1 0.30 0.35 0.40 E - 8.00 - E1 - 6.40 - D - 8.00 - D1 - 6.40 - e - 0.80 - b 0.40 0.45 0.50 z - - 0.08 Rev. 1.0 Feb. 2002 CMOS SDRAM K4S281633D-RL/N/P ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VI N, V OUT -1.0 ~ 4.6 V Voltage on V D D supply relative to Vss V DD , VDDQ -1.0 ~ 4.6 V TS T G -55 ~ +150 C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS = 0V, TA =Commercial, Extended, Industrial Temperature) Parameter Symbol Min Typ Max Unit VD D 2.7 3.0 3.6 V V DDQ 2.7 3.0 3.6 V Input logic high voltage VI H 2.2 3.0 V DDQ +0.3 V 1 Input logic low voltage VIL -0.3 0 0.5 V 2 Output logic high voltage VO H 2.4 - - V I O H = -2mA Output logic low voltage V OL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Note : 1. VIH (max) = 5.3V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V V IN VDDQ . Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V V OUT V DDQ. CAPACITANCE(VD D = 3.0V & 3.3V, TA = 23C, f = 1MHz, VREF Pin =0.9V 50 mV) Symbol Min Max Unit CCLK 2.0 4.0 pF CIN 2.0 4.0 pF Address CADD 2.0 4.0 pF D Q0 ~ DQ15 COUT 3.5 6.0 pF Clock RAS, CAS, WE, CS, CKE, DQM Note Rev. 1.0 Feb. 2002 CMOS SDRAM K4S281633D-RL/N/P DC CHARACTERISTICS Recommended operating conditions(Voltage referenced to V SS = 0V, TA =Commercial, Extended, Industrial Temperature) Parameter Symbol Operating Current (One Bank Active) Precharge Standby Current in power-down mode ICC1 ICC2P ICC2 N I CC2NS Active Standby Current in non power-down mode (One Bank Active) Burst length = 1 tRC t R C(min) IO = 0 mA -75 -1H -1L 80 75 75 CKE V IL (max), t CC = 10ns 0.5 ICC2 PS CKE & CLK V IL (max), tCC = Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Version Test Condition ICC3P I CC3NS Operating Current (Burst Mode) ICC4 Refresh Current ICC5 Note mA 1 mA 0.5 CKE V IH (min), CS V I H(min), tCC = 10ns Input signals are changed one time during 20ns 12 CKE V IH (min), CLK V IL (max), tCC = Input signals are stable 10 CKE V IL (max), t CC = 10ns 7 mA ICC3 PS CKE & CLK V IL (max), tCC = ICC3 N Unit mA 7 CKE V IH (min), CS V I H(min), tCC = 10ns Input signals are changed one time during 20ns 23 mA CKE V IH (min), CLK V IL (max), tCC = Input signals are stable 20 mA IO = 0 mA Page burst 4Banks Activated tC C D = 2CLKs tRC tRC (min) 130 130 110 mA 1 170 170 155 mA 2 -RL Self Refresh Current ICC6 CKE 0.2V -RN -RP 3 500 uA 4 5 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S281633D-RL** 4. K4S281633D-RN** 5. K4S281633D-RP** 6. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL =V DDQ /V SSQ) Rev. 1.0 Feb. 2002 CMOS SDRAM K4S281633D-RL/N/P AC OPERATING TEST CONDITIONS (V DD = 2.7V ~ 3.6V, TA =Commercial, Extended, Industrial Temperature) Parameter Value Unit 2.4 / 0.4 V 0.5 x VDDQ V tr/tf = 1/1 ns Output timing measurement reference level 0.5 x VDDQ V Output load condition See Fig. 2 AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time VDDQ Vtt = 0.5 x VDDQ 1200 50 V OH (DC) = 2.4V, IO H = -2mA V OL (DC) = 0.4V, IOL = 2mA Output 870 Output Z0 = 50 30pF 30pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER(AC operating conditions unless otherwise noted) Parameter Version Symbol - 75 -1H -1L Unit Note Row active to row active delay tRRD (min) 15 20 20 ns 1 RAS to CAS delay tRCD (min) 20 20 24 ns 1 Row precharge time tRP (min) 20 20 24 ns 1 tRAS (min) 45 50 60 ns 1 Row active time tRAS (max) Row cycle time tRC (min) Last data in to row precharge t RDL(min) Last data in to Active delay 100 ns 1 10 ns 2 tDAL (min) tRDL + tRP - 3 Last data in to new col. address delay t CDL(min) 1 CLK 2 Last data in to burst stop tB D L(min) 1 CLK 2 Col. address to col. address delay tCCD (min) 1 CLK 4 ea 5 Number of valid output data 65 70 us CAS latency=3 2 CAS latency=2 1 CAS latency=1 - 84 0 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum 2CLK tDAL is required to complete row precharge. 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. Rev. 1.0 Feb. 2002 CMOS SDRAM K4S281633D-RL/N/P AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter - 75 Symbol Min CAS latency=3 CLK cycle time CAS latency=2 tC C 10 tSAC CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 tO H CAS latency=1 Min -1L Max 10 1000 - CAS latency=3 CAS latency=2 Max 7.5 CAS latency=1 CLK to valid output delay -1H 10 Min Unit Note ns 1 ns 1,2 ns 2 Max 10 1000 - 12 1000 25 5.4 7 7 7 7 8 - - 20 2.5 2.5 2.5 2.5 2.5 2.5 - - 2.5 3 3 ns 3 CLK high pulse width tC H 2.5 CLK low pulse width tCL 2.5 3 3 ns 3 Input setup time tSS 2.0 2.5 2.5 ns 3 Input hold time tSH 1.0 1.5 1.5 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CAS latency=3 CLK to output in Hi-Z CAS latency=2 tSHZ CAS latency=1 5.4 7 7 7 7 8 - - 20 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev. 1.0 Feb. 2002 CMOS SDRAM K4S281633D-RL/N/P SIMPLIFIED TRUTH TABLE(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) COMMAND Register Mode Register Set CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X X X Auto Refresh Refresh Exit H L L H H H X X X X L L H H X V X L H L H X V H Bank Active & Row Addr. H Read & Column Address Auto Precharge Disable H Write & Column Address Auto Precharge Disable Auto Precharge Enable H X L H L L X H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X H X X X Entry H L L H H H H X X X L V V V V Auto Precharge Enable Burst Stop Bank Selection All Banks Clock Suspend or Active Power Down A 11, A9 ~ A0 1, 2 Exit L DQM H No Operation Command H H X X H X X X L H H H X 3 3 3 Row Address L Column Address (A 0~A 8 ) H L Column Address (A 0~A 8 ) H Precharge Power Down Mode Note 3 H L Precharge A10 /AP H Entry Self Refresh BA 0,1 X V L X H 4 4, 5 4 4, 5 6 X X X X X X V X X X 7 Note : 1. OP Code : Operand Code A0 ~ A11 & BA 0 ~ BA 1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA 1 : Bank select addresses. If both BA0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A10 /AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). Rev. 1.0 Feb. 2002 K4S281633D-RL/N/P CMOS SDRAM Note : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. Rev. 1.0 Feb. 2002 DEVICE OPERATIONS CMOS SDRAM A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS Address BA0 ~ BA1*1 A11 ~ A10/AP A9 Function "0" Setting for Normal MRS RFU W.B.L A8 A7 A6 Test Mode A5 A4 CAS Latency A3 A2 BT A1 A0 Burst Length Normal MRS Mode Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved Length 1 0 1 Reserved 1 0 1 Reserved Reserved 0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved Write Burst Length A9 Mode Select BA1 0 BA0 0 Mode Setting for Normal MRS Full Page Length : 512(x16) B. Power Up Sequence 1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Power is applied to VDD and VDDQ (simultaneously). 3. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 4. Issue precharge commands for all banks of the devices. 5. Issue 2 or more auto-refresh commands. 6. Issue a mode register set command to initialize the mode register. Note : 1. In order to assert normal MRS, BA0 and BA1 should set "0" absolutely. ELECTRONICS DEVICE OPERATIONS CMOS SDRAM C. BURST SEQUENCE 1. BURST LENGTH = 4 Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 2. BURST LENGTH = 8 Initial Address Sequential Interleave A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 ELECTRONICS DEVICE OPERATIONS CMOS SDRAM D. DEVICE OPERATIONS ADDRESSES of 64Mb ADDRESSES of 128Mb BANK ADDRESSES (BA0 ~ BA1) BANK ADDRESSES (BA0 ~ BA1) : In case x 16 : In case x 16 This SDRAM is organized as four independent banks of This SDRAM is organized as four independent banks of 1,048,576 words x 16 bits memory arrays. The BA 0 ~ BA 1 inputs 2,097,152 words x 16 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and pre- are latched at bank active, read, write, mode register set and pre- charge operations. charge operations. : In case x 32 : In case x 32 This SDRAM is organized as four independent banks of 524,288 This SDRAM is organized as four independent banks of words x 32 bits memory arrays. The BA0 ~ BA1 inputs are latched 1,048,576 words x 32 bits memory arrays. The BA0 ~ BA1 inputs at the time of assertion of RAS and CAS to select the bank to be are latched at the time of assertion of RAS and CAS to select the used for the operation. The bank addresses BA0 ~ BA 1 are bank to be used for the operation. The bank addresses BA0 ~ BA1 latched at bank active, read, write, mode register set and pre- are latched at bank active, read, write, mode register set and pre- charge operations. charge operations. ADDRESS INPUTS (A0 ~ A11) ADDRESS INPUTS (A0 ~ A11) : In case x 16 : In case x 16 The 20 address bits are required to decode the 1,048,576 word locations are multiplexed into 12 address input pins (A0 ~ A 11 ). The 12 bit row addresses are latched along with RAS and BA 0 ~ The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (A0 ~ A11 ). BA 1 during bank activate command. The 8 bit column addresses The 12 bit row addresses are latched along with RAS and BA0 ~ BA 1 during bank activate command. The 9 bit column addresses are latched along with CAS, WE and BA 0 ~ BA1 during read or are latched along with CAS, WE and BA 0 ~ BA 1 during read or write command. write command. : In case x 32 : In case x 32 The 19 address bits are required to decode the 524,288 word The 20 address bits are required to decode the 1,048,576 word locations are multiplexed into 11 address input pins (A0 ~ A10 ). locations are multiplexed into 12 address input pins (A0 ~ A11 ). The 12 bit row addresses are latched along with RAS and BA0 ~ The 11 bit row addresses are latched along with RAS and BA 0 ~ BA 1 during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA 0 ~ BA1 during read or write command. ELECTRONICS BA 1 during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA 0 ~ BA 1 during read or write command. DEVICE OPERATIONS CMOS SDRAM D. DEVICE OPERATIONS ADDRESSES of 256Mb BANK ADDRESSES (BA0 ~ BA1) ADDRESSES of 512Mb BANK ADDRESSES (BA0 ~ BA1) : In case x 16 : In case x 16 This SDRAM is organized as four independent banks of This SDRAM is organized as four independent banks of 4,194,304 words x 16 bits memory arrays. The BA0 ~ BA 1 inputs 8,388,608 words x 16 bits memory arrays. The BA 0 ~ BA 1 inputs are latched at the time of assertion of RAS and CAS to select the are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 bank to be used for the operation. The bank addresses BA0 ~ BA 1 are latched at bank active, read, write, mode register set and pre- are latched at bank active, read, write, mode register set and pre- charge operations. charge operations. : In case x 32 : In case x 32 This SDRAM is organized as four independent banks of 2,097,152 words x 32 bits memory arrays. The BA0 ~ BA 1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations. ADDRESS INPUTS (A0 ~ A12) This SDRAM is organized as four independent banks of 4,194,304 words x 32 bits memory arrays. The BA 0 ~ BA 1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA 1 are latched at bank active, read, write, mode register set and precharge operations. ADDRESS INPUTS (A0 ~ A12) : In case x 16 : In case x 16 The 22 address bits are required to decode the 4,194,304 word The 23 address bits are required to decode the 8,388,608 word locations are multiplexed into 13 address input pins (A0 ~ A 12 ). locations are multiplexed into 13 address input pins (A0 ~ A12 ). The 13 bit row addresses are latched along with RAS and BA0 ~ The 13 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 9 bit column addresses BA 1 during bank activate command. The 10 bit column addresses are latched along with CAS, WE and BA0 ~ BA 1 during read or are latched along with CAS, WE and BA0 ~ BA 1 during read or write command. write command. : In case x 32 : In case x 32 The 21 address bits are required to decode the 2,097,152 word The 22 address bits are required to decode the 8,388,608 word locations are multiplexed into 12 address input pins (A0 ~ A 12 ). locations are multiplexed into 13 address input pins (A0 ~ A12 ). The 12 bit row addresses are latched along with RAS and BA0 ~ The 13 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 9 bit column addresses BA 1 during bank activate command. The 9 bit column addresses are latched along with CAS, WE and BA0 ~ BA 1 during read or are latched along with CAS, WE and BA0 ~ BA 1 during read or write command. write command. ELECTRONICS DEVICE OPERATIONS CMOS SDRAM D. DEVICE OPERATIONS (continued) CLOCK (CLK) DQM OPERATION The clock input is used as the reference for all SDRAM opera- The DQM is used to mask input and output operations. It works tions. All operations are synchronized to the positive going edge similar to OE during read operation and inhibits writing during of the clock. The clock transitions must be monotonic between VIL write operation. The read latency is two cycles from DQM and and VI H. During operation with CKE high all inputs are assumed to zero cycle for write, which means DQM masking occurs two be in a valid state (low or high) for the duration of set-up and hold cycles later in read cycle and occurs in the same cycle during time around positive edge of the clock in order to function well Q write cycle. DQM operation is synchronous with the clock. The perform and I C C specifications. DQM signal is important during burst interruptions of write with read or precharge in the SDRAM. Due to asynchronous nature of CLOCK ENABLE (CKE) the internal write, the DQM operation is critical to avoid unwanted The clock enable(CKE) gates the clock onto SDRAM. If CKE goes or incomplete writes when the complete burst write is not low synchronously with clock (set-up and hold time are the same required. Please refer to DQM timing diagram also. as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + t SS " before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. NOP and DEVICE DESELECT When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored. MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ An and BA 0 ~ BA 1 in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A0 ~ A2 , burst type uses A3 , CAS latency (read latency from column address) use A4 ~ A6 , vendor specific options or test mode use A 7 ~ A 8 , A 10 /AP ~ An and BA0 ~ BA 1 . The write burst length is programmed using A9 . A 7 ~ A 8 , A 10 / AP ~ An and BA0 ~ BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. ELECTRONICS DEVICE OPERATIONS CMOS SDRAM D. DEVICE OPERATIONS (continued) EXTENDED MODE REGISTER SET (EMRS) The SDRAM has four internal banks in the same chip and shares The extended mode register stores the data for selecting partial self refresh or temperature compensated self refresh. EMRS part of the internal circuitry to reduce chip area, therefore it cycle is not mandatory and the EMRS command needs to be issued only when either PASR or TCSR is used. The default state noise generated during sensing of each bank of SDRAM is high, without EMRS command issued is +85 C and all 4 banks refreshed. The extended mode register is written by asserting restricts the activation of four banks simultaneously. Also the requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD (min) specifies the minimum low on CS, RAS, CAS, WE and high on BA1 ,low on BA0(The DDR SDRAM should be in all bank precharge with CKE already time required between activating different bank. The number of high prior to writing into the extended mode register). The state of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS and calculated similar to tRCD specification. The minimum time WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the the complete row of dynamic cells is determined by tRAS (min). extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 - A2 are used for partila self refresh and A3 - A4 are used for Temprature compensated self refresh. "Low" on BA1 and "High" on BA0 are used for EMRS. All the other address pins except A0,A1,A2, BA1, BA0 must be set to low for proper EMRS operation. Refer to clock cycles required between different bank activation must be required for the bank to be active to initiate sensing and restoring Every SDRAM bank activate command must satisfy Rt AS (min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tR A S(max). The number of cycles for both tR A S(min) and t RAS (max) can be calculated similar to tRCD specification. the table for specific codes. BURST READ BANK ACTIVATE. The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD (min) from the time of bank activation. tRCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD (min) with cycle time of the clock and then rounding off the result to the next higher integer. The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tR C D(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. ELECTRONICS DEVICE OPERATIONS CMOS SDRAM D. DEVICE OPERATIONS (continued) BURST WRITE AUTO PRECHARGE The burst write command is similar to burst read command and is The precharge operation can also be performed by using auto pre- used to write data into the SDRAM on consecutive clock cycles in charge. The SDRAM internally generates the timing to satisfy adjacent addresses depending on burst length and burst tRAS (min) and "t RP " for the programmed burst length and CAS sequence. By asserting low on CS, CAS and WE with valid col- latency. The auto precharge command is issued at the same time umn address, a write burst is initiated. The data inputs are pro- as burst read or burst write by asserting high on A10 /AP. If burst vided for the initial address in the same clock cycle as the burst read or burst write by asserting high on A10 /AP, the bank is left write command. The input buffer is deselected at the end of the active until a new command is asserted. Once auto precharge burst length, even though the internal writing can be completed command is given, no new commands are possible to that particu- yet. The writing can be completed by issuing a burst read and lar bank until the bank achieves idle state. DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tR D L after the last data input to be written into the active row. See DQM OPERATION also. AUTO REFRESH The storage cells of 64Mb, 128Mb and 256Mb SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. ALL BANKS PRECHARGE An auto refresh command is issued by asserting low on CS, RAS and CAS with high on CKE and WE. All banks can be precharged at the same time by using Precharge The auto refresh command can only be asserted with both banks all command. Asserting low on CS, RAS, and WE with high on being in idle state and the device is not in power down mode (CKE A 10 /AP after all banks have satisfied tRAS (min) requirement, per- is high in the previous cycle). The time required to complete the forms precharge on all banks. At the end of tRP after performing auto refresh operation is specified by t RC (min). The minimum num- precharge to all the banks, all banks are in idle state. ber of clock cycles required can be calculated by driving tRC with clock cycle time and them rounding up to the next higher integer. PRECHARGE The precharge operation is performed on an active bank by asserting low on CS, RAS, WE and A 10 /AP with valid BA0 ~ BA 1 of the bank to be precharged. The precharge command can be asserted anytime after tRAS (min) is satisfied from the bank active command in the desired bank. tR P is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tR AS (max). Therefore, each bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. ELECTRONICS The auto refresh command must be followed by NOP's until the auto refresh operation is completed. All banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The 64Mb and 128Mb SDRAM's auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms. The 256Mb SDRAM's auto refresh cycle can be performed once in 7.8us or a burst of 8192 auto refresh cycles once in 64ms. DEVICE OPERATIONS D. DEVICE OPERATIONS (continued) SELF REFRESH The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS, RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRC before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 8192 auto refresh cycles for 256Mb and burst 4096 auto refresh cycles for 128Mb and 64Mb immediately after exiting in self refresh mode. ELECTRONICS CMOS SDRAM DEVICE OPERATIONS CMOS SDRAM E. BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write (BL=4) 2) Clock Suspended During Read (BL=4) CLK CLK CMD WR CMD CKE RD CKE Masked by CKE Masked by CKE Internal CLK Internal CLK DQ(CL2) D0 D1 D2 D3 DQ(CL2) DQ(CL3) D0 D1 D2 D3 DQ(CL3) Q0 D Q01 Q2 Q3 Q0 Q1 Q2 Not Written Q3 Suspended Dout 2. DQM Operation 1) Write Mask (BL=4) 2) Read Mask (BL=4) CLK CLK CMD CMD WR DQM RD DQM Masked byDQM DQ(CL2) D0 DQ(CL3) D0 D1 DQ(CL2) D3 D1 Q0 Hi-Z DQ(CL3) D3 Masked by DQM Hi-Z Q2 Q3 Q1 Q2 DQM to Data-in Mask = 0 3) DQM with Clock Suspended (Full Page Read) DQM to Data-out Mask = 2 *2 CLK CMD RD CKE DQM DQ(CL2) Q0 Hi-Z Hi-Z DQ(CL3) Q2 Q1 Hi-Z Hi-Z Q4 Q3 *Note : 1. CKE to CLK disable/enable = 1CLK. 2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L" 3. DQM masks both data-in and data-out. ELECTRONICS Q3 Hi-Z Hi-Z Q6 Q7 Q8 Q5 Q6 Q7 DEVICE OPERATIONS CMOS SDRAM 3. CAS Interrupt (I) 1) Read interrupted by Read (BL=4) *1 CLK CMD RD RD ADD A B DQ(CL2) QA0 DQ(CL3) QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 tCCD *2 2) Write interrupted by Write (BL=2) CLK CLK CMD 3) Write interrupted by Read (BL=2) WR CMD WR WR tCCD * 2 tCCD * 2 ADD A B DQ DA 0 DB 0 RD ADD DB 1 tCDL *3 A B DQ(CL2) DA 0 DQ(CL3) DA 0 tCDL *3 *Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst. By "CAS Interrupt", to stop burst read/write by CAS access ; read and write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK) ELECTRONICS QB0 QB1 QB0 QB1 DEVICE OPERATIONS CMOS SDRAM 4. CAS Interrupt (II) : Read Interrupted by Write & DQM (a) CL=2, BL=4 CLK i) CMD RD WR DQM DQ ii) CMD D0 RD D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 WR DQM Hi-Z DQ iii) CMD D0 RD WR DQM Hi-Z DQ iv) CMD D0 RD WR DQM Q0 DQ Hi-Z D0 *1 D3 (b) CL=3, BL=4 CLK i) CMD RD WR DQM DQ ii) CMD D0 RD D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 WR DQM D0 DQ iii) CMD RD WR DQM D0 DQ iii) CMD RD WR DQM Hi-Z DQ iv) CMD D0 RD WR DQM DQ Q0 Hi-Z *1 D0 D3 *Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. ELECTRONICS DEVICE OPERATIONS CMOS SDRAM 5. Write Interrupted by Precharge & DQM 1) tRDL = 1 CLK 2) tRDL = 2CLK CLK CLK *3 WR CMD *3 PRE WR CMD PRE *2 *2 DQM DQM DQ D0 D1 DQ D2 D0 D1 D2 Masked by DQM Masked by DQM *Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. 6. Precharge 1) Normal Write BL=4 & tRDL=1CLK BL=4 & tRDL=2CLK CLK CLK CMD WR DQ D0 PRE D1 D2 D3 CMD WR DQ D0 PRE D1 D2 D3 tRDL *1 tRDL * 1 2) Normal Read (BL=4) CLK *2 CMD RD PRE 1 DQ(CL2) Q0 Q1 Q2 Q3 Q0 Q1 Q2 2 DQ(CL3) Q3 7. Auto Precharge 1) Normal Write (BL=4) 2) Normal Read (BL=4) CLK CMD DQ CLK ACT WR D0 D1 D2 CMD DQ(CL2) tRDL =1CLK CMD WR DQ D0 tDAL =1CLK D1 D2 RD D3 +20ns*4 ACT DQ(CL3) Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 D3 Auto Precharge Starts * 3 tRDL =2CLK tDAL =2CLK +20ns * 4 Auto Precharge Starts @tRDL=1CLK *3 Auto Precharge Starts@tRDL=2CLK *3 *Note : 1. SAMSUNG can support tR D L=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommends tRDL=2 CLK. 2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tR P from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal 4. tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=1CLK+20ns and 2CLK+20ns ,recommends tDAL=2CLK+20ns. ELECTRONICS DEVICE OPERATIONS CMOS SDRAM 8. Burst Stop & Interrupted by Precharge 1) Normal Write BL=4 & tRDL=1CLK BL=4 & tRDL=2CLK CLK CLK CMD WR PRE CMD DQM DQ WR PRE DQM D0 D1 DQ D2 D0 D1 tRDL*1 D2 tRDL*1 2) Write Burst Stop (BL=8) 3) Read Interrupted by Precharge (BL=4) CLK CLK WR CMD CMD STOP DQM DQ(CL2) DQ D0 D1 D2 D3 DQ(CL3) RD PRE Q0 Q1 Q0 1 Q1 tBDL *2 4) Read Burst Stop (BL=4) CLK CMD RD STOP 1 DQ(CL2) Q0 DQ(CL3) Q1 Q0 Q1 2 9. MRS 1) Mode Register Set CLK *4 CMD PRE MRS tRP ACT 2CLK *Note : 1. SAMSUNG can support t RDL=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommends tRDL=2 CLK. 2. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectively. 4. PRE : All banks precharge is necessary. MRS can be issued only at all banks precharge state. ELECTRONICS 2 DEVICE OPERATIONS CMOS SDRAM 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit 2) Power Down (=Precharge Power Down) Exit CLK CLK CKE CKE tSS Internal CLK tSS Internal CLK *1 CMD RD *2 CMD NOP ACT 11. Auto Refresh & Self Refresh 1) Auto Refresh ~ CLK *4 PRE CMD CKE tRP tRC Note 6 ~ ~ 2) Self Refresh *5 AR ~~ ~ CMD CLK *4 CMD PRE SR CMD tRP ~ ~ CKE tRC *Note : 1. Active power down : one or more banks active state. 2. Precharge power down : all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tR C from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, all banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh mode, all inputs except CKE will be don't cared, and outputs will be in Hi-Z state. For the time interval of tRC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh cycle (4096 cycles for 64Mb & 128Mb, 8192 cycles for 256Mb) is recommended. ELECTRONICS DEVICE OPERATIONS CMOS SDRAM 12. About Burst Type Control Sequential Counting At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=1, 2, 4, 8 and full page. Interleave Counting At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting. Basic MODE Random MODE Random column Access tCCD = 1 CLK Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM. 13. About Burst Length Control Basic MODE 1 At MRS A2,1,0 = "000". At auto precharge, t RAS should not be violated. 2 At MRS A2,1,0 = "001". At auto precharge, t RAS should not be violated. 4 At MRS A2,1,0 = "010". 8 At MRS A2,1,0 = "011". Full Page Special MODE BRSW Random MODE Burst Stop RAS Interrupt (Interrupted by Precharge) Interrupt MODE CAS Interrupt ELECTRONICS At MRS A2,1,0 = "111". Wrap around mode(infinite burst length) should be stopped by burst stop. RAS interrupt or CAS interrupt. At MRS A9 = "1". Read burst =1, 2, 4, 8, full page write Burst =1. At auto precharge of write, tRAS should not be violated. tB D L= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively Using burst stop command, any burst length control is possible. Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. tRDL = 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. DEVICE OPERATIONS CMOS SDRAM FUNCTION TRUTH TABLE (TABLE 1) Current State IDLE Row Active Read Write Read with Auto Precharge Write with Auto Precharge Precharging CS RAS CAS WE BA Address H X L H L Action Note X X X X NOP H H X X NOP H H L X X ILLEGAL 2 L H L X BA CA, A10/AP ILLEGAL 2 L L H H BA RA L L H L BA A 10/AP L L L H X X L L L L OP code OP code H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL L H L H BA CA, A10/AP Begin Read ; latch CA ; determine AP L H L L BA CA, A10/AP Begin Read ; latch CA ; determine AP L L H H BA RA ILLEGAL L L H L BA A 10/AP Precharge Row (& Bank) Active ; Latch RA NOP 4 Auto Refresh or Self Refresh 5 Mode Register Access 5 L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Row Active) L H H H X X NOP (Continue Burst to End --> Row Active) L H H L X X Term burst --> Row active L H L H BA CA, A10/AP Term burst, New Read, Determine AP L H L L BA CA, A10/AP Term burst, New Write, Determine AP L L H H BA RA L L H L BA A 10/AP ILLEGAL 2 2 3 2 Term burst, Precharge timing for Reads L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Row Active) L H H H X X NOP (Continue Burst to End --> Row Active) L H H L X X Term burst --> Row active L H L H BA CA, A10/AP Term burst, New read, Determine AP 3 L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3 L L H H BA RA L L H L BA A 10/AP L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Precharge) L H H H X X NOP (Continue Burst to End --> Precharge) L H H L X X ILLEGAL L H L X BA L L H X BA RA, RA1 0 ILLEGAL L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Precharge) L H H H X X NOP (Continue Burst to End --> Precharge) L H H L X X ILLEGAL L H L X BA L L H X BA RA, RA1 0 ILLEGAL ILLEGAL 2 Term burst, precharge timing for Writes 3 CA, A10/AP ILLEGAL 2 CA, A10/AP ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Idle after tR P L H H H X X NOP --> Idle after tR P L H H L X X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A 10/AP NOP --> Idle after tR P 4 ELECTRONICS DEVICE OPERATIONS CMOS SDRAM FUNCTION TRUTH TABLE (TABLE 1) Current State Row Activating Refreshing Mode Register Accessing CS RAS CAS WE BA Address Action Note L L L X X X ILLEGAL H X X X X X NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L X X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A 10/AP ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Idle after tR C L H H X X X NOP --> Idle after tR C L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL H X X X X X NOP --> Idle after 2 clocks L H H H X X NOP --> Idle after 2 clocks L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL Abbreviations : RA = Row Address NOP = No Operation Command BA = Bank Address CA = Column Address AP = Auto Precharge *Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle. 2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A1 0/AP). 5. Illegal if any bank is not idle. ELECTRONICS DEVICE OPERATIONS CMOS SDRAM FUNCTION TRUTH TABLE (TABLE 2) Current State Self Refresh All Banks Precharge Power Down All Banks Idle Any State other than Listed above CKE (n-1) CKE n CS RAS CAS WE Address H X X X X X X Exit Self Refresh --> Idle after tRFC (ABI) L H H X X X X Exit Self Refresh --> Idle after tRFC (ABI) 6 L H L H H H X Exit Self Refresh --> Idle after tRFC (ABI) 6 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI 7 L H L H H L X ILLEGAL 7 L H L H L X X ILLEGAL L H L L X X X ILLEGAL Action Note L L X X X X X NOP (Maintain Low Power Mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down 8 H L L H H L X ILLEGAL 8 H L L H L X X ILLEGAL H L L L H H RA Row (& Bank) Active H L L L L H X Enter Self Refresh H L L L L L 8 OP Code Mode Register Access L L X X X X X NOP H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend next cycle 9 L H X X X X X Exit Clock Suspend next cycle 9 L L X X X X X Maintain Clock Suspend Abbreviations : ABI = All Banks Idle, RA = Row Address *Note : 6. CKE low to high transition is asynchronous. 7. CKE low to high transition is asynchronous if restarts internal clock. A minimum setup time 1CLK + tSS must be satisfied before any command other than exit. 8. Power down and self refresh can be entered only from the both banks idle state. 9. Must be a legal command. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 Power Up Sequence Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read Cycle at Different Bank @Burst Length=4 Page Write Cycle at Different Bank @Burst Length=4, tRDL=1CLK Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK Read & Write Cycle at Different Bank @Burst Length=4 Read & Write Cycle With Auto Precharge l @Burst Length=4 Read & Write Cycle With Auto Precharge ll @Burst Length=4 Clock Suspension & DQM Operation Cycle @CAS Letency=2, Burst Length=4 Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=1CLK Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK Burst Read Single bit Write Cycle @Burst Length =2 Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4 Self Refresh Entry & Exit Cycle & Exit Cycle Mode Register Set Cycle Auto Refresh Cycle ELECTRONICS TIMING DIAGRAM CMOS SDRAM Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK tCL tCC HIGH CKE tRAS tRC *Note 1 tSH CS tRCD tRP tSS tSH RAS tSS tCCD tSH CAS tSH ADDR Ra tSS Ca Cb Cc Rb tSS *Note 2 *Note 2,3 *Note 2,3 BA0 ~ BA 1 BS BS BS A 10 /AP Ra *Note 2,3 *Note 4 BS *Note 3 *Note 3 *Note 2 BS BS *Note 3 *Note 4 Rb tRAC tSH tSAC Qa DQ Db tSLZ tOH Qc tSS tSH WE tSS tSS tSH DQM Row Active Read Write Read Row Active Precharge : Don't care ELECTRONICS TIMING DIAGRAM CMOS SDRAM *Note : 1. All input except CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0~BA1. 64Mb/128Mb 256Mb Active & Read/Write BA0 BA1 BA0 BA1 0 0 0 0 Bank A 0 1 1 0 Bank B 1 0 0 1 Bank C 1 1 1 1 Bank D 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command 64Mb/128Mb 256Mb A10/AP 0 1 Operation BA0 BA1 BA0 BA1 0 0 0 0 Disable auto precharge, leave bank A active at end of burst. 0 1 1 0 Disable auto precharge, leave bank B active at end of burst. 1 0 0 1 Disable auto precharge, leave bank C active at end of burst. 1 1 1 1 Disable auto precharge, leave bank D active at end of burst. 0 0 0 0 Enable auto precharge, precharge bank A at end of burst. 0 1 1 0 Enable auto precharge, precharge bank B at end of burst. 1 0 0 1 Enable auto precharge, precharge bank C at end of burst. 1 1 1 1 Enable auto precharge, precharge bank D at end of burst. 4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted. 64Mb/128Mb A10/AP 256Mb Precharge BA0 BA1 BA0 BA1 0 0 0 0 0 Bank A 0 0 1 1 0 Bank B 0 1 0 0 1 Bank C 0 1 1 1 1 Bank D 1 x x x x All Banks ELECTRONICS TIMING DIAGRAM CMOS SDRAM : Don't care Power Up Sequence 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 ~ ~ High level is necessary ~ CKE 5 ~ ~ 1 ~ 0 CLOCK CS ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ BA 0 ~ ~ High level is necessary Precharge (All Banks) Auto Refresh RAa RAa ~ DQM ~ WE Key ~ ~ ~ High-Z DQ tRC ~ A 10 /AP ~ ~ ~ ~ ~ ~ BA 1 ~ ~ ADDR ~ ~ CAS ~ ~ RAS tRC ~ ~ ~ ~ ~ ~ ~ ~ tRP Auto Refresh Power Up Sequence Mode Register Set Row Active (A-Bank) 1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Power is applied to VDD and VDDQ (simultaneously). 3. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 4. Issue precharge commands for all banks of the devices. 5. Issue 2 or more auto-refresh commands. 6. Issue a mode register set command to initialize the mode register. Note : 1. In order to assert normal MRS, BA0 and BA1 should set "0" absolutely. ELECTRONICS 19 TIMING DIAGRAM CMOS SDRAM Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE tRC *Note 1 CS tRCD RAS *Note 2 CAS ADDR Ra Ca Rb Cb BA 0 BA 1 A10 /AP Ra Rb tOH Qa0 CL=2 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tRAC *Note 3 tSAC tSHZ tRDL *Note 4 DQ tOH CL=3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 tRAC *Note 3 tSAC tSHZ Db2 Db3 tRDL *Note 4 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ ) after the clcok. 3. Access time from Row active command. tCC *(t RCD + CAS latency - 1) + tSAC 4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) ELECTRONICS TIMING DIAGRAM CMOS SDRAM Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE tRC *Note 1 CS tRCD RAS *Note 2 CAS ADDR Ra Ca Rb Cb BA 0 BA 1 A10 /AP Ra Rb tOH Qa0 CL=2 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tRAC *Note 3 tSAC tSHZ tRDL *Note 4 DQ tOH CL=3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 tRAC *Note 3 tSAC tSHZ Db2 Db3 tRDL *Note 4 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ ) after the clcok. 3. Access time from Row active command. tCC *(t RCD + CAS latency - 1) + tSAC 4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) ELECTRONICS TIMING DIAGRAM CMOS SDRAM Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS tRCD RAS *Note 2 CAS ADDR Ra Ca Cb Cc Cd Rb BA 0 BA 1 A10 /AP Rb Ra tRDL Qa0 CL=2 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 DQ tDAL CL=3 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 *Note 4 Dd1 tCDL WE *Note 1 *Note 3 DQM Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) Row Adiwe (A-Bank) : Don't care *Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. tDAL, last data in to active delay, is 1CLK + 20ns ELECTRONICS TIMING DIAGRAM CMOS SDRAM Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS tRCD RAS *Note 2 CAS ADDR Ra Ca Cb Cc Cd Rb BA 0 BA 1 A10 /AP Rb Ra tRDL Qa0 CL=2 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 DQ tDAL CL=3 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 *Note 4 Dd1 tCDL WE *Note 1 *Note 3 DQM Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) Row Active (A-Bank) : Don't care *Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. tDAL ,last data in to active delay, is 2CLK + 20ns. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Page Read Cycle at Different Bank @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE *Note 1 CS RAS *Note 2 CAS ADDR RAa RBb RAa RBb CAa RCc CBb RDd CCc CDd BA 0 BA 1 A10 /AP RCc CL=2 QAa0 RDd QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 QAa0 QAa1 QBb0 QBb2 QCc0 QCc1 QCc2 QDd0 DQ CL=3 QAa2 QBb1 QDd1 QDd2 WE DQM Row Active (A-Bank) Read (A-Bank) Row Active (B-Bank) Read (B-Bank) Row Acive (C-Bank) Read (C-Bank) Row Active (D-Bank) Precharge (A-Bank) Read (D-Bank) Precharge (D-Bank) Precharge (C-Bank) Precharge (B-Bank) : Don't care *Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Page Write Cycle at Different Bank @Burst Length=4, tRDL=1CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS *Note 2 CAS ADDR RAa RBb CAa RAa RBb CBb RCc RDd RCc RDd DBb0 DBb1 DBb2 DBb3 CCc CDd BA 0 BA 1 A 10/AP DAa0 DQ DAa1 DAa2 DAa3 DCc0 DCc1 DDd0 tCDL DDd1 DDd2 tRDL WE *Note 1 DQM Row Active (A-Bank) Write (A-Bank) Row Active (B-Bank) Write (B-Bank) Row Active (C-Bank) Row Active (D-Bank) Write (D-Bank) Precharge (All Banks) Write (C-Bank) : Don't care *Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS *Note 2 CAS ADDR RAa RBb CAa RAa RBb CBb RCc RDd RCc RDd DBb0 DBb1 DBb2 DBb3 CCc CDd BA 0 BA 1 A 10/AP DAa0 DQ DAa1 DAa2 DAa3 DCc0 DCc1 DDd0 tCDL DDd1 DDd2 tRDL WE *Note 1 DQM Row Active (A-Bank) Write (A-Bank) Row Active (B-Bank) Write (B-Bank) Row Active (C-Bank) Row Active (D-Bank) Write (D-Bank) Precharge (All Banks) Write (C-Bank) : Don't care *Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Read & Write Cycle at Different Bank @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa RDb CDb RBc RDb RBc CBc BA 0 BA 1 A10 /AP RAa tCDL CL=2 QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 DDb0 DDb1 DDb2 DDb3 DDb0 DDb1 DDb2 DDb3 *Note 1 QBc0 QBc1 QBc2 QBc0 QBc1 DQ CL=3 QAa3 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (D-Bank) Write (D-Bank) Read (B-Bank) Row Active (B-Bank) : Don't care *Note : 1. tCDL should be met to complete write. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Read & Write Cycle with Auto Precharge I @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa RBb RAa RBb CAa CBb RAc CAc BA 0 BA 1 A10 /AP DQ CL=2 RAc QAa0 QAa1 CL=3 QAa0 QBb0 QBb1 QBb2 QBb3 QAa1 QBb0 QBb1 QBb2 QBb3 DAc0 DAc1 DAc0 DAc1 WE DQM Row Active (A-Bank) Read with Auto Pre charge (A-Bank) Row Active (B-Bank) Read without Auto precharge(B-Bank) Auto Precharge Start Point (A-Bank)* Note1 Precharge (B-Bank) Row Active (A-Bank) Write with Auto Precharge (A-Bank) : Don't care *Note1: When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if Read(Write) command without auto precharge is issued at B-Bank before A-Bank auto precharge starts, A-Bank auto precharge will start at B-Bank read command input point . - any command can not be issued at A-Bank during tRP after A-Bank auto precharge starts. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Read & Write Cycle with Auto Precharge II @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR Ra Ca Rb Cb BA 0 BA 1 A10 /AP DQ Ra Rb CL=2 Qa0 CL=3 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qb0 Qa3 Qb1 Qb0 Qb2 Qb1 Qb3 Qb2 Qb3 WE DQM *Note1 Row Active (A-Bank) Read with Auto Precharge (A-Bank) Auto Precharge Start Point (A-Bank) Row Active (B-Bank) Read with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) : Don't care *Note 1: Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point ELECTRONICS TIMING DIAGRAM CMOS SDRAM Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CS RAS CAS ADDR Ra Ca Cb Cc BA 0 BA 1 A 1 0/AP Ra Qa0 DQ Qa1 Qa2 Qa3 Qb0 tSHZ Qb1 Dc0 Dc2 tSHZ WE *Note 1 DQM Row Active Read Clock Suspension Read Write DQM Read DQM Write DQM Write Clock Suspension : Don't care *Note1 : DQM is needed to prevent bus contention. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA 0 BA 1 A10 /AP RAa 1 CL=2 QAa0 QAa1 QAa2 CL=3 QAa0 QAa3 1 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 DQ 2 QAa1 QAa2 QAa3 QAa4 2 QAb4 QAb5 WE DQM Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. At full page mode, burst is finished by burst stop or precharge. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at every burst length. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=1CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA 0 BA 1 A 10/AP RAa tBDL tRDL *Note 1,2 *Note 1 DQ DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. At full page mode, burst is finished by burst stop or precharge. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA 0 BA 1 A 10/AP RAa tBDL tRDL *Note 1,2 *Note 1 DQ DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. At full page mode, burst is finished by burst stop or precharge. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Burst Read Single bit Write Cycle @Burst Length=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK *Note 1 HIGH CKE CS RAS *Note 2 CAS ADDR RAa CAa RBb CAb RCc CBc CCd BA 0 BA 1 A10 /AP RAa RBb CL=2 DAa0 CL=3 DAa0 RCc QAb0 QAb1 DBc0 QCd0 QCd1 DQ QAb0 QAb1 DBc0 QCd0 QCd1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank) Row Active (C-Bank) Read (C-Bank) Precharge (C-Bank) Write with Auto Precharge (B-Bank) : Don't care *Note : 1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that t RAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 2 3 4 5 6 7 8 9 tSS 11 12 13 14 15 16 17 18 19 tSS *Note 1 tSS *Note 2 ~ *Note 2 ~ ~ CKE 10 ~ 1 ~ ~ 0 CLOCK ~ ~ ~ ~ Ra Ca ~ ~ A 10/AP Ra ~ ~ ~ ~ BA ~ ~ ADDR ~ ~ CAS ~ ~ RAS ~ ~ ~ ~ CS ~ ~ ~ ~ *Note 3 ~ ~ ~ WE DQM Precharge Power-down Entry Qa0 Qa1 Qa2 ~ ~ ~ ~ DQ ~ ~ ~ tSHZ Row Active Precharge Power-down Exit Active Power-down Entry Read Precharge Active Power-down Exit : Don't Care *Note : 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tss prior to Row active command. 3. Can not violate minimum refresh specification. (64ms) ELECTRONICS TIMING DIAGRAM CMOS SDRAM Self Refresh Entry & Exit Cycle 2 3 *Note 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ~ 1 ~ ~ 0 CLOCK *Note 4 tRCmin *Note 6 ~ *Note 1 *Note 3 ~ CKE A 10/AP Hi-Z DQM Self Refresh Entry ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ WE ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Hi-Z ~ ~ DQ ~ ~ ~ BA0 ~BA1 ~ ~ ~ ~ ~ ~ ADDR ~ ~ ~ ~ ~ ~ CAS *Note 7 ~ ~ ~ RAS *Note 5 ~ ~ CS ~ ~ tSS Self Refresh Exit Auto Refresh : Don't care *Note : TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tR A S is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 4K cycle(64Mb ,128Mb) or 8K cycle(256Mb) of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. ELECTRONICS TIMING DIAGRAM CMOS SDRAM Mode Register Set Cycle 0 1 2 3 4 5 Auto Refresh Cycle 6 7 8 09 110 211 312 13 4 514 HIGH 716 8 17 918 10 19 HIGH ~ ~ CKE 615 ~ ~ ~ ~ CLOCK CS tRC RAS ~ ~ ~ ~~ ~ *Note 2 ~ ~ ~ ~ *Note 1 CAS *Note 3 ADDR Key Ra BA0 Hi-Z Hi-Z ~ ~ ~ ~ DQ ~ ~ BA1 ~ ~ ~ ~ WE DQM MRS New Command Auto Refresh New Command : Don't care * All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note : 1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. ELECTRONICS