K4S281633D-RP1H - Samsung - Datasheet.Global

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

Revision 1.0

February 2002

8Mx16

SDRAM 54CSP

(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

Revision History

Revision 0.0 (February 21. 2001, Target)

• First generation of 128Mb Low Power SDRAM without special function (VDD 3.0V, VDDQ 3.0V)

Revision 0.1 (June 4. 2001, Target)

• Addition of DC Current value.

Revision 0.2 (June 20. 2001, Target)

• Changed device name from low power sdram to mobile dram.

Revision 0.3 (August 1. 2001, Target)

• Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part.

• Change of tOH from 3ns to 3.5ns.

• Change VIH min. from 2.0 V to 0.8xVDDQ and VOH min. from 2.4V to 0.9xVDDQ.

Revision 0.4 (October 6. 2001, Preliminary)

• Changed DC current.

• Changed of CL2 tSAC from 6ns to 7ns and CL3 tSAC from 6.5ns to 7ns for -75 part.

• Changed of CL2 tSAC from 6.5ns to 8ns and CL1 tSAC from 18ns to 20ns for -1L part.

• Changed of tOH from 3ns to 2.5ns.

• Changed of tSS from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1L part.

• Integration of VDDQ 1.8V device and 2.5V device.

• Changed VIH min. from 0.8xVDDQ to 0.9xVDDQ and VOH min. from 0.9xVDDQ to 0.95xVDDQ.

• Changed VIL max. from 0.8V to 0.3V and VOL min. from 0.4V to 0.2V.

• Changed IOH from -0.1mA to -2mA and IOL from 0.1mA to 2mA.

• Erased -15 bin and added -1H bin.

Revision 0.5 (October 12. 2001, Preliminary)

• Changed VIH min. from 0.9xVDDQ to 2.0V and VOH min. from 0.95xVDDQ to 2.4V.

• Changed VIL max. from 0.3V to 0.8V and VOL min. from 0.2V to 0.4V.

Revision 0.6 (November 7. 2001, Preliminary)

• Changed VIH min. from 2.0V to 2.2V and VIL max. from 0.8V to 0.5V.

Revision 1.0 (Feb. 2002, Final)

• Final specification.

• Changed tRDL from 2CLK to 10ns for -75 / -1H / -1L part.

• Changed tDAL from 2CLK+tRP to tRDL+tRP.

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

• 3.0V & 3.3V power supply.

• LVTTL compatible with multiplexed address.

• Four banks operation.

• MRS cycle with address key programs.

-. CAS latency (1 & 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation..

• DQM for masking.

• Auto refresh.

• 64ms refresh period (4K cycle).

• Commercial Temperature Operation (-25°C ~ 70°C).

Extended Temperature Operation (-25°C ~ 85°C).

Industrial Temperature Operation (-40°C ~ 85°C).

• 54balls CSP.

FEATURES The K4S281633D is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 2,097,152 words by 16

bits, fabricated with SAMSUNG′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock and I/O transactions are possible

on every clock cycle. Range of operating frequencies, program-

mable burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

GENERAL DESCRIPTION

2M x 16Bit x 4 Banks SDRAM in 54CSP

Bank Select

Data Input Register

2M x 16

Sense AMP

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Address Register

Row Buffer

Refresh Counter

Row DecoderCol. Buffer

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

CLK CKE CS RAS CAS WE LDQM

LWE

LDQM

DQi

CLK

ADD

LCAS LWCBR

2M x 16

Timing Register

UDQM

* Samsung Electronics reserves the right to change products or specification without notice.

FUNCTIONAL BLOCK DIAGRAM

ORDERING INFORMATION

-RL ; Low Power, Operating Temperature : -25’C~70’C.

-RN ; Low Power, Operating Temperature : -25’C~85’C.

-RP : Low Power, Operating Temperature : -40°C ~ 85°C.

Note :

1. In case of 40MHz Frequency, CL1 can be supported.

Part No. Max Freq. Interface Package

K4S281633D-RL/N/P75 133MHz(CL=3)

100MHz(CL=2) LVTTL 54 CSP

K4S281633D-RL/N/P1H 100MHz(CL=2)

K4S281633D-RL/N/P1L 100MHz(CL=3)*1

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

54Ball(6x9) CSP

123789

A VSS DQ15 VSSQ VDDQ DQ0 VDD

BDQ14 DQ13 VDDQ VSSQ DQ2 DQ1

CDQ12 DQ11 VSSQ VDDQ DQ4 DQ3

DDQ10 DQ9 VDDQ VSSQ DQ6 DQ5

EDQ8 NC VSS VDD LDQM DQ7

FUDQM CLK CKE CAS RAS WE

GNC A11 A9 BA0 BA1 CS

HA8 A7 A6 A0 A1 A10

JVSS A5 A4 A3 A2 VDD

Pin Name Pin Function

CLK System Clock

CS Chip Select

CKE Clock Enable

A0 ~ A11 Address

BA0 ~ BA1Bank Select Address

RAS Row Address Strobe

CAS Column Address Strobe

WE Write Enable

L(U)DQM Data Input/Output Mask

DQ0 ~ 15 Data Input/Output

VDD/VSS Power Supply/Ground

VDDQ/VSSQ Data Output Power/Ground

Package Dimension and Pin Configuration

< Bottom View*1 >

< Top View*2 >

*2: Top View

Symbol Min Typ Max

A0.90 0.95 1.00

A10.30 0.35 0.40

E-8.00 -

E1-6.40 -

D-8.00 -

D1-6.40 -

e-0.80 -

b0.40 0.45 0.50

z- - 0.08

[Unit:mm]

5 2 16 3489 7

D/2

EE/2

Encapsulant

Max. 0.20

#A1 Ball Origin Indicator

*1: Bottom View

K4S281633D

SEC Week RXXX

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

DC OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to VSS = 0V, TA =Commercial, Extended, Industrial Temperature)

Note :

1. VIH (max) = 5.3V AC. The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD 2.7 3.0 3.6 V

VDDQ 2.7 3.0 3.6 V

Input logic high voltage VIH 2.2 3.0 VDDQ+0.3 V1

Input logic low voltage VIL -0.3 00.5 V2

Output logic high voltage VOH 2.4 - - VIOH = -2mA

Output logic low voltage VOL - - 0.4 VIOL = 2mA

Input leakage current ILI -10 -10 uA 3

CAPACITANCE(VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)

Pin Symbol Min Max Unit Note

Clock CCLK 2.0 4.0 pF

RAS, CAS, WE, CS, CKE, DQM CIN 2.0 4.0 pF

Address CADD 2.0 4.0 pF

DQ0 ~ DQ15 COUT 3.5 6.0 pF

ABSOLUTE MAXIMUM RATINGS

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD1W

Short circuit current IOS 50 mA

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

DC CHARACTERISTICS

Recommended operating conditions(Voltage referenced to VSS = 0V, TA =Commercial, Extended, Industrial Temperature)

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S281633D-RL**

4. K4S281633D-RN**

5. K4S281633D-RP**

6. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Parameter Symbol Test Condition Version Unit Note

-75 -1H -1L

Operating Current

(One Bank Active) ICC1 Burst length = 1

tRC ≥ tRC(min)

IO = 0 mA 80 75 75 mA 1

Precharge Standby Current

in power-down mode ICC2PCKE ≤ VIL(max), tCC = 10ns 0.5 mA

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞0.5

Precharge Standby Current

in non power-down mode

ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns 12

ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 10

Active Standby Current

in power-down mode ICC3PCKE ≤ VIL(max), tCC = 10ns 7mA

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞7

Active Standby Current

in non power-down mode

(One Bank Active)

ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns 23 mA

ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 20 mA

Operating Current

(Burst Mode) ICC4

IO = 0 mA

Page burst

4Banks Activated

tCCD = 2CLKs

130 130 110 mA 1

Refresh Current ICC5 tRC ≥ tRC(min) 170 170 155 mA 2

Self Refresh Current ICC6 CKE ≤ 0.2V

-RL

500 uA

-RN 4

-RP 5

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. Minimum 2CLK tDAL is required to complete row precharge.

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

Parameter Symbol Version Unit Note

- 75 -1H -1L

Row active to row active delay tRRD(min) 15 20 20 ns 1

RAS to CAS delay tRCD(min) 20 20 24 ns 1

Row precharge time tRP(min) 20 20 24 ns 1

Row active time tRAS(min) 45 50 60 ns 1

tRAS(max) 100 us

Row cycle time tRC(min) 65 70 84 ns 1

Last data in to row precharge tRDL(min) 10 ns 2

Last data in to Active delay tDAL(min) tRDL + tRP -3

Last data in to new col. address delay tCDL(min) 1CLK 2

Last data in to burst stop tBDL(min) 1CLK 2

Col. address to col. address delay tCCD(min) 1CLK 4

Number of valid output data

CAS latency=3 2

ea 5

CAS latency=2 1

CAS latency=1 -0

AC OPERATING TEST CONDITIONS (VDD = 2.7V ~ 3.6V, TA =Commercial, Extended, Industrial Temperature)

Parameter Value Unit

AC input levels (Vih/Vil) 2.4 / 0.4 V

Input timing measurement reference level 0.5 x VDDQ V

Input rise and fall time tr/tf = 1/1 ns

Output timing measurement reference level 0.5 x VDDQ V

Output load condition See Fig. 2

VDDQ

1200Ω

870Ω

Output

30pF

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Vtt = 0.5 x VDDQ

50Ω

Output

30pF

Z0 = 50Ω

(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Parameter Symbol - 75 -1H -1L Unit Note

Min Max Min Max Min Max

CLK cycle time

CAS latency=3

tCC

7.5

1000

1000 ns 1

CAS latency=2 10 10 12

CAS latency=1 - - 25

CLK to valid output delay

CAS latency=3

tSAC

5.4 7 7

ns 1,2

CAS latency=2 7 7 8

CAS latency=1 - - 20

Output data hold time

CAS latency=3

tOH

2.5 2.5 2.5

ns 2

CAS latency=2 2.5 2.5 2.5

CAS latency=1 - - 2.5

CLK high pulse width tCH 2.5 3 3 ns 3

CLK low pulse width tCL 2.5 3 3 ns 3

Input setup time tSS 2.0 2.5 2.5 ns 3

Input hold time tSH 1.0 1.5 1.5 ns 3

CLK to output in Low-Z tSLZ 1 1 1 ns 2

CLK to output in Hi-Z

CAS latency=3

tSHZ

5.4 7 7

CAS latency=2 7 7 8

CAS latency=1 - - 20

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

SIMPLIFIED TRUTH TABLE(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

Note :

1. OP Code : Operand Code

A0 ~ A11 & BA 0 ~ BA1 : Program keys. (@MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are the same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency

is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).

COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A 11,

A9 ~ A0Note

Refresh

Auto Refresh HHLL LHX X 3

Self

Refresh

Entry L 3

Exit LHLH H H X X 3

HX X X 3

Bank Active & Row Addr. HXL L H H X V Row Address

Read &

Column Address Auto Precharge Disable HXLHLHX V LColumn

Address

(A0~A8)

Auto Precharge Enable H4, 5

Write &

Column Address Auto Precharge Disable HXLHLLX V LColumn

Address

(A0~A8)

Auto Precharge Enable H4, 5

Burst Stop HXLH H LX X 6

Precharge Bank Selection HXL L HLXVLX

All Banks XH

Clock Suspend or

Active Power Down Entry HLHX X X XXLV V V

Exit LHX X X X X

Precharge Power Down Mode

Entry HLHX X X X

LH H H

Exit LHHX X X X

LV V V

DQM HX V X 7

No Operation Command HXHX X X X X

LH H H

K4S281633D-RL/N/P

Rev. 1.0 Feb. 2002

CMOS SDRAM

Note :

1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is

potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product con-

tained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

Normal MRS Mode

Test Mode CAS Latency Burst Type Burst Length

A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1

0 0 Mode Register Set 0 0 0 Reserved 0Sequential 0 0 0 1 1

0 1 Reserved 0 0 1 11Interleave 0 0 1 2 2

1 0 Reserved 0 1 0 2Mode Select 0 1 0 4 4

1 1 Reserved 0 1 1 3BA1 BA0 Mode 0 1 1 8 8

Write Burst Length 1 0 0 Reserved

0 0 Setting

for Nor-

mal MRS

1 0 0 Reserved Reserved

A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved

0Burst 1 1 0 Reserved 1 1 0 Reserved Reserved

1Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved

Full Page Length : 512(x16)

A. MODE REGISTER FIELD TABLE TO PROGRAM MODES

Address BA0 ~ BA1*1 A11 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function "0" Setting for

Normal MRS RFU W.B.L Test Mode CAS Latency BT Burst Length

1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Power is applied to VDD and VDDQ (simultaneously).

3. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

4. Issue precharge commands for all banks of the devices.

5. Issue 2 or more auto-refresh commands.

6. Issue a mode register set command to initialize the mode register.

Note : 1. In order to assert normal MRS, BA0 and BA1 should set "0" absolutely.

B. Power Up Sequence

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

C. BURST SEQUENCE

1. BURST LENGTH = 4

Initial Address Sequential Interleave

A1A0

0 0 0 1 2 3 0 1 2 3

0 1 1 2 3 0 1 0 3 2

1 0 2 3 0 1 2 3 0 1

1 1 3 0 1 2 3 2 1 0

2. BURST LENGTH = 8

Initial Address Sequential Interleave

A2A1A0

0000123456701234567

0011234567010325476

0102345670123016745

0113456701232107654

1004567012345670123

1015670123454761032

1106701234567452301

1117012345676543210

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

BANK ADDRESSES (BA0 ~ BA1)

: In case x 16

This SDRAM is organized as four independent banks of

1,048,576 words x 16 bits memory arrays. The BA 0 ~ BA1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~ BA1

are latched at bank active, read, write, mode register set and pre-

charge operations.

: In case x 32

This SDRAM is organized as four independent banks of 524,288

words x 32 bits memory arrays. The BA0 ~ BA1 inputs are latched

at the time of assertion of RAS and CAS to select the bank to be

used for the operation. The bank addresses BA0 ~ BA1 are

latched at bank active, read, write, mode register set and pre-

charge operations.

ADDRESS INPUTS (A0 ~ A11)

: In case x 16

The 20 address bits are required to decode the 1,048,576 word

locations are multiplexed into 12 address input pins (A0 ~ A11).

The 12 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 8 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

: In case x 32

The 19 address bits are required to decode the 524,288 word

locations are multiplexed into 11 address input pins (A0 ~ A10).

The 11 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 8 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

ADDRESSES of 64Mb

D. DEVICE OPERATIONS

BANK ADDRESSES (BA0 ~ BA1)

: In case x 16

This SDRAM is organized as four independent banks of

2,097,152 words x 16 bits memory arrays. The BA0 ~ BA1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~ BA1

are latched at bank active, read, write, mode register set and pre-

charge operations.

: In case x 32

This SDRAM is organized as four independent banks of

1,048,576 words x 32 bits memory arrays. The BA0 ~ BA1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~ BA1

are latched at bank active, read, write, mode register set and pre-

charge operations.

ADDRESS INPUTS (A0 ~ A11)

: In case x 16

The 21 address bits are required to decode the 2,097,152 word

locations are multiplexed into 12 address input pins (A0 ~ A11).

The 12 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 9 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

: In case x 32

The 20 address bits are required to decode the 1,048,576 word

locations are multiplexed into 12 address input pins (A0 ~ A11).

The 12 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 8 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

ADDRESSES of 128Mb

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

D. DEVICE OPERATIONS

BANK ADDRESSES (BA0 ~ BA1)

: In case x 16

This SDRAM is organized as four independent banks of

4,194,304 words x 16 bits memory arrays. The BA0 ~ BA 1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~ BA1

are latched at bank active, read, write, mode register set and pre-

charge operations.

: In case x 32

This SDRAM is organized as four independent banks of

2,097,152 words x 32 bits memory arrays. The BA0 ~ BA 1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~ BA1

are latched at bank active, read, write, mode register set and pre-

charge operations.

ADDRESS INPUTS (A0 ~ A12)

: In case x 16

The 22 address bits are required to decode the 4,194,304 word

locations are multiplexed into 13 address input pins (A0 ~ A12).

The 13 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 9 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

: In case x 32

The 21 address bits are required to decode the 2,097,152 word

locations are multiplexed into 12 address input pins (A0 ~ A12).

The 12 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 9 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

ADDRESSES of 256Mb

BANK ADDRESSES (BA0 ~ BA1)

: In case x 16

This SDRAM is organized as four independent banks of

8,388,608 words x 16 bits memory arrays. The BA0 ~ BA1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~ BA1

are latched at bank active, read, write, mode register set and pre-

charge operations.

: In case x 32

This SDRAM is organized as four independent banks of

4,194,304 words x 32 bits memory arrays. The BA0 ~ BA1 inputs

are latched at the time of assertion of RAS and CAS to select the

bank to be used for the operation. The bank addresses BA0 ~ BA1

are latched at bank active, read, write, mode register set and pre-

charge operations.

ADDRESS INPUTS (A0 ~ A12)

: In case x 16

The 23 address bits are required to decode the 8,388,608 word

locations are multiplexed into 13 address input pins (A0 ~ A12).

The 13 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 10 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

: In case x 32

The 22 address bits are required to decode the 8,388,608 word

locations are multiplexed into 13 address input pins (A0 ~ A12).

The 13 bit row addresses are latched along with RAS and BA0 ~

BA1 during bank activate command. The 9 bit column addresses

are latched along with CAS, WE and BA0 ~ BA1 during read or

write command.

ADDRESSES of 512Mb

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

D. DEVICE OPERATIONS (continued)

CLOCK (CLK)

The clock input is used as the reference for all SDRAM opera-

tions. All operations are synchronized to the positive going edge

of the clock. The clock transitions must be monotonic between VIL

and VIH. During operation with CKE high all inputs are assumed to

be in a valid state (low or high) for the duration of set-up and hold

time around positive edge of the clock in order to function well Q

perform and ICC specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock onto SDRAM. If CKE goes

low synchronously with clock (set-up and hold time are the same

as other inputs), the internal clock is suspended from the next

clock cycle and the state of output and burst address is frozen as

long as the CKE remains low. All other inputs are ignored from the

next clock cycle after CKE goes low. When all banks are in the

idle state and CKE goes low synchronously with clock, the

SDRAM enters the power down mode from the next clock cycle.

The SDRAM remains in the power down mode ignoring the other

inputs as long as CKE remains low. The power down exit is syn-

chronous as the internal clock is suspended. When CKE goes

high at least "1CLK + tSS " before the high going edge of the clock,

then the SDRAM becomes active from the same clock edge

accepting all the input commands.

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SDRAM performs no

operation (NOP). NOP does not initiate any new operation, but is

needed to complete operations which require more than single

clock cycle like bank activate, burst read, auto refresh, etc. The

device deselect is also a NOP and is entered by asserting CS

high. CS high disables the command decoder so that RAS, CAS,

WE and all the address inputs are ignored.

DQM OPERATION

The DQM is used to mask input and output operations. It works

similar to OE during read operation and inhibits writing during

write operation. The read latency is two cycles from DQM and

zero cycle for write, which means DQM masking occurs two

cycles later in read cycle and occurs in the same cycle during

write cycle. DQM operation is synchronous with the clock. The

DQM signal is important during burst interruptions of write with

read or precharge in the SDRAM. Due to asynchronous nature of

the internal write, the DQM operation is critical to avoid unwanted

or incomplete writes when the complete burst write is not

required. Please refer to DQM timing diagram also.

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various oper-

ating modes of SDRAM. It programs the CAS latency, burst type,

burst length, test mode and various vendor specific options to

make SDRAM useful for variety of different applications. The

default value of the mode register is not defined, therefore the

mode register must be written after power up to operate the

SDRAM. The mode register is written by asserting low on CS,

RAS, CAS and WE (The SDRAM should be in active mode with

CKE already high prior to writing the mode register). The state of

address pins A0 ~ An and BA0 ~ BA1 in the same cycle as CS,

RAS, CAS and WE going low is the data written in the mode reg-

ister. Two clock cycles is required to complete the write in the

mode register. The mode register contents can be changed using

the same command and clock cycle requirements during opera-

tion as long as all banks are in the idle state. The mode register is

divided into various fields depending on the fields of functions.

The burst length field uses A0 ~ A2, burst type uses A3, CAS

latency (read latency from column address) use A4 ~ A6, vendor

specific options or test mode use A7 ~ A8, A10 /AP ~ An and BA0 ~

BA1. The write burst length is programmed using A9. A7 ~ A8, A10/

AP ~ An and BA0 ~ BA1 must be set to low for normal SDRAM

operation. Refer to the table for specific codes for various burst

length, burst type and CAS latencies.

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

D. DEVICE OPERATIONS (continued)

EXTENDED MODE REGISTER SET (EMRS)

The extended mode register stores the data for selecting partial

self refresh or temperature compensated self refresh. EMRS

cycle is not mandatory and the EMRS command needs to be

issued only when either PASR or TCSR is used. The default state

without EMRS command issued is +85°C and all 4 banks

refreshed. The extended mode register is written by asserting

low on CS, RAS, CAS, WE and high on BA1 ,low on BA0(The

DDR SDRAM should be in all bank precharge with CKE already

high prior to writing into the extended mode register). The state of

address pins A0 ~ A11 in the same cycle as CS, RAS, CAS and

WE going low is written in the extended mode register. Two clock

cycles are required to complete the write operation in the

extended mode register. The mode register contents can be

changed using the same command and clock cycle requirements

during operation as long as all banks are in the idle state. A0 - A2

are used for partila self refresh and A3 - A4 are used for Tempra-

ture compensated self refresh. "Low" on BA1 and "High" on BA0

are used for EMRS. All the other address pins except A0,A1,A2,

BA1, BA0 must be set to low for proper EMRS operation. Refer to

the table for specific codes.

BANK ACTIVATE.

The bank activate command is used to select a random row in an

idle bank. By asserting low on RAS and CS with desired row and

bank address, a row access is initiated. The read or write opera-

tion can occur after a time delay of tRCD(min) from the time of

bank activation. tRCD is an internal timing parameter of SDRAM,

therefore it is dependent on operating clock frequency. The mini-

mum number of clock cycles required between bank activate and

read or write command should be calculated by dividing tRCD(min)

with cycle time of the clock and then rounding off the result to the

next higher integer.

The SDRAM has four internal banks in the same chip and shares

part of the internal circuitry to reduce chip area, therefore it

restricts the activation of four banks simultaneously. Also the

noise generated during sensing of each bank of SDRAM is high,

requiring some time for power supplies to recover before another

bank can be sensed reliably. tRRD(min) specifies the minimum

time required between activating different bank. The number of

clock cycles required between different bank activation must be

calculated similar to tRCD specification. The minimum time

required for the bank to be active to initiate sensing and restoring

the complete row of dynamic cells is determined by tRAS(min).

Every SDRAM bank activate command must satisfy tRAS(min)

specification before a precharge command to that active bank can

be asserted. The maximum time any bank can be in the active

state is determined by tRAS(max). The number of cycles for both

tRAS(min) and tRAS(max) can be calculated similar to tRCD specifi-

cation.

BURST READ

The burst read command is used to access burst of data on con-

secutive clock cycles from an active row in an active bank. The

burst read command is issued by asserting low on CS and CAS

with WE being high on the positive edge of the clock. The bank

must be active for at least tRCD(min) before the burst read com-

mand is issued. The first output appears in CAS latency number

of clock cycles after the issue of burst read command. The burst

length, burst sequence and latency from the burst read command

is determined by the mode register which is already programmed.

The burst read can be initiated on any column address of the

active row. The address wraps around if the initial address does

not start from a boundary such that number of outputs from each

I/O are equal to the burst length programmed in the mode regis-

ter. The output goes into high-impedance at the end of the burst,

unless a new burst read was initiated to keep the data output gap-

less. The burst read can be terminated by issuing another burst

read or burst write in the same bank or the other active bank or a

precharge command to the same bank. The burst stop command

is valid at every page burst length.

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

D. DEVICE OPERATIONS (continued)

BURST WRITE

The burst write command is similar to burst read command and is

used to write data into the SDRAM on consecutive clock cycles in

adjacent addresses depending on burst length and burst

sequence. By asserting low on CS, CAS and WE with valid col-

umn address, a write burst is initiated. The data inputs are pro-

vided for the initial address in the same clock cycle as the burst

write command. The input buffer is deselected at the end of the

burst length, even though the internal writing can be completed

yet. The writing can be completed by issuing a burst read and

DQM for blocking data inputs or burst write in the same or another

active bank. The burst stop command is valid at every burst

length. The write burst can also be terminated by using DQM for

blocking data and procreating the bank tRDL after the last data

input to be written into the active row. See DQM OPERATION

also.

ALL BANKS PRECHARGE

All banks can be precharged at the same time by using Precharge

all command. Asserting low on CS, RAS, and WE with high on

A10/AP after all banks have satisfied tRAS (min) requirement, per-

forms precharge on all banks. At the end of tRP after performing

precharge to all the banks, all banks are in idle state.

PRECHARGE

The precharge operation is performed on an active bank by

asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1

of the bank to be precharged. The precharge command can be

asserted anytime after tRAS(min) is satisfied from the bank active

command in the desired bank. tRP is defined as the minimum

number of clock cycles required to complete row precharge is cal-

culated by dividing tRP with clock cycle time and rounding up to

the next higher integer. Care should be taken to make sure that

burst write is completed or DQM is used to inhibit writing before

precharge command is asserted. The maximum time any bank

can be active is specified by tRAS(max). Therefore, each bank

activate command. At the end of precharge, the bank enters the

idle state and is ready to be activated again. Entry to Power down,

Auto refresh, Self refresh and Mode register set etc. is possible

only when all banks are in idle state.

AUTO PRECHARGE

The precharge operation can also be performed by using auto pre-

charge. The SDRAM internally generates the timing to satisfy

tRAS(min) and "tRP" for the programmed burst length and CAS

latency. The auto precharge command is issued at the same time

as burst read or burst write by asserting high on A10/AP. If burst

read or burst write by asserting high on A10/AP, the bank is left

active until a new command is asserted. Once auto precharge

command is given, no new commands are possible to that particu-

lar bank until the bank achieves idle state.

AUTO REFRESH

The storage cells of 64Mb, 128Mb and 256Mb SDRAM need to be

refreshed every 64ms to maintain data. An auto refresh cycle

accomplishes refresh of a single row of storage cells. The internal

counter increments automatically on every auto refresh cycle to

refresh all the rows. An auto refresh command is issued by

asserting low on CS, RAS and CAS with high on CKE and WE.

The auto refresh command can only be asserted with both banks

being in idle state and the device is not in power down mode (CKE

is high in the previous cycle). The time required to complete the

auto refresh operation is specified by tRC(min). The minimum num-

ber of clock cycles required can be calculated by driving tRC with

clock cycle time and them rounding up to the next higher integer.

The auto refresh command must be followed by NOP's until the

auto refresh operation is completed. All banks will be in the idle

state at the end of auto refresh operation. The auto refresh is the

preferred refresh mode when the SDRAM is being used for normal

data transactions. The 64Mb and 128Mb SDRAM’s auto refresh

cycle can be performed once in 15.6us or a burst of 4096 auto

refresh cycles once in 64ms. The 256Mb SDRAM’s auto refresh

cycle can be performed once in 7.8us or a burst of 8192 auto

refresh cycles once in 64ms.

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

SELF REFRESH

The self refresh is another refresh mode available in the SDRAM.

The self refresh is the preferred refresh mode for data retention

and low power operation of SDRAM. In self refresh mode, the

SDRAM disables the internal clock and all the input buffers except

CKE. The refresh addressing and timing are internally generated

to reduce power consumption.

The self refresh mode is entered from all banks idle state by

asserting low on CS, RAS, CAS and CKE with high on WE. Once

the self refresh mode is entered, only CKE state being low mat-

ters, all the other inputs including the clock are ignored in order to

remain in the self refresh mode.

The self refresh is exited by restarting the external clock and then

asserting high on CKE. This must be followed by NOP's for a mini-

mum time of tRC before the SDRAM reaches idle state to begin

normal operation. If the system uses burst auto refresh during nor-

mal operation, it is recommended to use burst 8192 auto refresh

cycles for 256Mb and burst 4096 auto refresh cycles for 128Mb

and 64Mb immediately after exiting in self refresh mode.

D. DEVICE OPERATIONS (continued)

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

1) Clock Suspended During Write (BL=4)

1. CLOCK Suspend

D0D1D2D3

CLK

CMD

CKE

Internal

CLK

DQ(CL2)

DQ(CL3)

Masked by CKE

2) Clock Suspended During Read (BL=4)

Not Written

1) Write Mask (BL=4)

2. DQM Operation

D0D1D3

CLK

CMD

DQM

DQ(CL2)

DQ(CL3)

Masked byDQM

2) Read Mask (BL=4)

Q0Q2Q3

Q1Q2Q3

Masked by DQM

DQM to Data-in Mask = 0 DQM to Data-out Mask = 2

Hi-Z

3) DQM with Clock Suspended (Full Page Read) *2

CLK

CMD

CKE

DQ(CL2)

DQ(CL3)

Q0Q4Q7Q8Q2

Q3Q6Q7Q1

Hi-Z

DQM

*Note : 1. CKE to CLK disable/enable = 1CLK.

2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"

3. DQM masks both data-in and data-out.

E. BASIC FEATURE AND FUNCTION DESCRIPTIONS

Q0Q1Q2

Q0Q1Q2Q3

Masked by CKE

Suspended Dout

CLK

CMD

CKE

Internal

CLK

DQ(CL2)

DQ(CL3)

CLK

CMD

DQM

DQ(CL2)

DQ(CL3)

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

1) Read interrupted by Read (BL=4) *1

3. CAS Interrupt (I)

CLK

CMD

ADD

RD RD

A B

QA0QB1QB2QB3QB0

tCCD *2

2) Write interrupted by Write (BL=2) 3) Write interrupted by Read (BL=2)

WR WR

A B

tCCD *2

DA0DB1DB0

tCDL *3

CLK

CMD

ADD

WR RD

A B

tCCD *2

tCDL *3

DA0QB1QB0

DQ(CL2)

DQ(CL3)

*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.

By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.

2. tCCD : CAS to CAS delay. (=1CLK)

3. tCDL : Last data in to new column address delay. (=1CLK)

DQ(CL2)

DQ(CL3)

CLK

CMD

ADD

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

4. CAS Interrupt (II) : Read Interrupted by Write & DQM

*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.

D1D2

D1D2D3D0

RD WR

Hi-Z

RD WR

Q0D1D2D3D0

Hi-Z

(a) CL=2, BL=4

CLK

i) CMD

DQM

ii) CMD

DQM

iii) CMD

DQM

iv) CMD

DQM

(b) CL=3, BL=4

CLK

i) CMD

DQM

DQ D1D2

D1D2D3D0

RD WR

D1D2D3D0

RD WR

D1D2D3D0

Hi-Z

ii) CMD

DQM

iii) CMD

DQM

iii) CMD

DQM

iv) CMD

DQM

DQ Q0*1

Hi-Z

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.

2. To inhibit invalid write, DQM should be issued.

3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge

interrupt but only another bank precharge of four banks operation.

5. Write Interrupted by Precharge & DQM

6. Precharge

tRDL*1

2) Normal Read (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

RD PRE

Q0Q1Q2Q3

*Note : 1. SAMSUNG can support tRDL=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommends tRDL=2 CLK.

2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.

3. The row active command of the precharge bank can be issued after tRP from this point.

The new read/write command of other activated bank can be issued from this point.

At burst read/write with auto precharge, CAS interrupt of the same bank is illegal

4. tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=1CLK+20ns and 2CLK+20ns ,recommends tDAL=2CLK+20ns.

7. Auto Precharge

D0D1D2

CLK

CMD

1) Normal Write (BL=4) 2) Normal Read (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

Q0Q1Q2Q3

Auto Precharge Starts *3

D0D1D2

CLK

CMD

DQM

Masked by DQM

WR PRE *3

1) tRDL = 1 CLK 2) tRDL = 2CLK

Auto Precharge Starts @tRDL=1CLK *3

Auto Precharge Starts@tRDL=2CLK *3

D0D1D2

CLK

CMD

WR PRE

1) Normal Write

BL=4 & tRDL=2CLK

D0D1D2

CLK

CMD

WR PRE

BL=4 & tRDL=1CLK

tRDL*1

D0D1D2

CLK

CMD

DQM

Masked by DQM

WR PRE *3

ACT

D0D1D2

CMD

ACT

tRDL =1CLK

tRDL =2CLK

tDAL =1CLK +20ns*4

tDAL =2CLK +20ns*4

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

*Note :

1. SAMSUNG can support tRDL=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommends tRDL=2 CLK.

2. tBDL : 1 CLK ; Last data in to burst stop delay.

Read or write burst stop command is valid at every burst length.

3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectively.

4. PRE : All banks precharge is necessary.

MRS can be issued only at all banks precharge state.

8. Burst Stop & Interrupted by Precharge

3) Read Interrupted by Precharge (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

RD PRE

Q0Q1

9. MRS

CLK

PRE

1) Mode Register Set

4) Read Burst Stop (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

RD STOP

Q0Q1

MRS ACT

tRP 2CLK

CMD

D0D1D2

CLK

CMD

WR PRE

1) Normal Write

tRDL*1

D0D1D2

CLK

CMD

WR STOP

2) Write Burst Stop (BL=8)

DQM

tBDL *2

D0D1D2

CLK

CMD

WR PRE

tRDL*1

DQM

BL=4 & tRDL=1CLK BL=4 & tRDL=2CLK

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

*Note : 1. Active power down : one or more banks active state.

2. Precharge power down : all banks precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.

No precharge commands are required after auto refresh command.

During tRC from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, all banks must be idle state.

5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh mode, refresh interval and refresh operation are performed internally.

After self refresh entry, self refresh mode is kept while CKE is low.

During self refresh mode, all inputs except CKE will be don't cared, and outputs will be in Hi-Z state.

For the time interval of tRC from self refresh exit command, any other command can not be accepted.

Before/After self refresh mode, burst auto refresh cycle (4096 cycles for 64Mb & 128Mb, 8192 cycles for 256Mb)

is recommended.

10. Clock Suspend Exit & Power Down Exit

CLK

CKE

CMD RD

1) Clock Suspend (=Active Power Down) Exit

tSS

CLK

CKE

CMD

2) Power Down (=Precharge Power Down) Exit

Internal

CLK

NOP

tSS

Internal

CLK

11. Auto Refresh & Self Refresh

CLK

CMD

1) Auto Refresh

CKE

PRE AR CMD

tRP tRC

CLK

CMD

2) Self Refresh

CKE

PRE SR CMD

tRP tRC

Note 6

ACT

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

12. About Burst Type Control

Basic

MODE

Sequential Counting At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8)

BL=1, 2, 4, 8 and full page.

Interleave Counting At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8)

BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting.

Random

MODE Random column Access

tCCD = 1 CLK

Every cycle Read/Write Command with random column address can realize Random

Column Access.

That is similar to Extended Data Out (EDO) Operation of conventional DRAM.

13. About Burst Length Control

Basic

MODE

1At MRS A2,1,0 = "000".

At auto precharge, tRAS should not be violated.

2At MRS A2,1,0 = "001".

At auto precharge, tRAS should not be violated.

4At MRS A2,1,0 = "010".

8At MRS A2,1,0 = "011".

Full Page At MRS A2,1,0 = "111".

Wrap around mode(infinite burst length) should be stopped by burst stop.

RAS interrupt or CAS interrupt.

Special

MODE BRSW At MRS A9 = "1".

Read burst =1, 2, 4, 8, full page write Burst =1.

At auto precharge of write, tRAS should not be violated.

Random

MODE Burst Stop tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively

Using burst stop command, any burst length control is possible.

Interrupt

MODE

RAS Interrupt

(Interrupted by Precharge)

Before the end of burst, Row precharge command of the same bank stops read/write

burst with Row precharge.

tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.

During read/write burst with auto precharge, RAS interrupt can not be issued.

CAS Interrupt Before the end of burst, new read/write stops read/write burst and starts new

read/write burst.

During read/write burst with auto precharge, CAS interrupt can not be issued.

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

FUNCTION TRUTH TABLE (TABLE 1)

Current

State CS RAS CAS WE BA Address Action Note

IDLE

HX X X X X NOP

LH H H X X NOP

LHHLX X ILLEGAL 2

LHLX BA CA, A10/AP ILLEGAL 2

L L H H BA RA Row (& Bank) Active ; Latch RA

L L HLBA A10/AP NOP 4

LLLHX X Auto Refresh or Self Refresh 5

L L L L OP code OP code Mode Register Access 5

Row

Active

HX X X X X NOP

LH H H X X NOP

LHHLX X ILLEGAL 2

LHLHBA CA, A10/AP Begin Read ; latch CA ; determine AP

LHL L BA CA, A10/AP Begin Read ; latch CA ; determine AP

L L H H BA RA ILLEGAL 2

L L HLBA A10/AP Precharge

LLLX X X ILLEGAL

Read

HX X X X X NOP (Continue Burst to End --> Row Active)

LH H H X X NOP (Continue Burst to End --> Row Active)

LHHLX X Term burst --> Row active

LHLHBA CA, A10/AP Term burst, New Read, Determine AP

LHL L BA CA, A10/AP Term burst, New Write, Determine AP 3

L L H H BA RA ILLEGAL 2

L L HLBA A10/AP Term burst, Precharge timing for Reads

LLLX X X ILLEGAL

Write

HX X X X X NOP (Continue Burst to End --> Row Active)

LH H H X X NOP (Continue Burst to End --> Row Active)

LHHLX X Term burst --> Row active

LHLHBA CA, A10/AP Term burst, New read, Determine AP 3

LHL L BA CA, A10/AP Term burst, New Write, Determine AP 3

L L H H BA RA ILLEGAL 2

L L HLBA A10/AP Term burst, precharge timing for Writes 3

LLLX X X ILLEGAL

Read with

Auto

Precharge

HX X X X X NOP (Continue Burst to End --> Precharge)

LH H H X X NOP (Continue Burst to End --> Precharge)

LHHLX X ILLEGAL

LHLX BA CA, A10/AP ILLEGAL

L L HX BA RA, RA10 ILLEGAL 2

LLLX X X ILLEGAL

Write with

Auto

Precharge

HX X X X X NOP (Continue Burst to End --> Precharge)

LH H H X X NOP (Continue Burst to End --> Precharge)

LHHLX X ILLEGAL

LHLX BA CA, A10/AP ILLEGAL

L L HX BA RA, RA10 ILLEGAL 2

LLLX X X ILLEGAL

Precharging

HX X X X X NOP --> Idle after tRP

LH H H X X NOP --> Idle after tRP

LHHLX X ILLEGAL 2

LHLX BA CA ILLEGAL 2

L L H H BA RA ILLEGAL 2

L L HLBA A10/AP NOP --> Idle after tRP 4

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

*Note :

1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.

2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the

state of that bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).

5. Illegal if any bank is not idle.

Abbreviations : RA = Row Address BA = Bank Address

NOP = No Operation Command CA = Column Address AP = Auto Precharge

FUNCTION TRUTH TABLE (TABLE 1)

Current

State CS RAS CAS WE BA Address Action Note

Row

Activating

LLLX X X ILLEGAL

HX X X X X NOP --> Row Active after tRCD

LH H H X X NOP --> Row Active after tRCD

LHHLX X ILLEGAL 2

LHLX BA CA ILLEGAL 2

L L H H BA RA ILLEGAL 2

L L HLBA A10/AP ILLEGAL 2

LLLX X X ILLEGAL

Refreshing

HX X X X X NOP --> Idle after tRC

LHHX X X NOP --> Idle after tRC

LHLX X X ILLEGAL

L L HX X X ILLEGAL

LLLX X X ILLEGAL

Mode

Accessing

HX X X X X NOP --> Idle after 2 clocks

LH H H X X NOP --> Idle after 2 clocks

LHHLX X ILLEGAL

LHLX X X ILLEGAL

L L X X X X ILLEGAL

CMOS SDRAMDEVICE OPERATIONS

ELECTRONICS

FUNCTION TRUTH TABLE (TABLE 2)

Current

State CKE

(n-1) CKE

nCS RAS CAS WE Address Action Note

Self

Refresh

HX X X X X X Exit Self Refresh --> Idle after tRFC (ABI)

LHHX X X X Exit Self Refresh --> Idle after tRFC (ABI) 6

LHLHHHXExit Self Refresh --> Idle after tRFC (ABI) 6

LHLHHLXILLEGAL

LHLHLX X ILLEGAL

LHL L X X X ILLEGAL

L L X X X X X NOP (Maintain Self Refresh)

All

Banks

Precharge

Power

Down

HX X X X X X INVALID

LHHX X X X Exit Power Down --> ABI

LHLHHHXExit Power Down --> ABI 7

LHLHHLXILLEGAL 7

LHLHLX X ILLEGAL

LHL L X X X ILLEGAL

L L X X X X X NOP (Maintain Low Power Mode)

All

Banks

Idle

HHX X X X X Refer to Table 1

HLHX X X X Enter Power Down

HLLHHHXEnter Power Down 8

HLLHHLXILLEGAL 8

HLLHLX X ILLEGAL

HLLLH H RA Row (& Bank) Active

HL L L L HXEnter Self Refresh 8

HL L L L L OP Code Mode Register Access

L L X X X X X NOP

Any State

other than

Listed

above

HHX X X X X Refer to Operations in Table 1

HLX X X X X Begin Clock Suspend next cycle 9

LHX X X X X Exit Clock Suspend next cycle 9

L L X X X X X Maintain Clock Suspend

*Note :

6. CKE low to high transition is asynchronous.

7. CKE low to high transition is asynchronous if restarts internal clock.

A minimum setup time 1CLK + tSS must be satisfied before any command other than exit.

8. Power down and self refresh can be entered only from the both banks idle state.

9. Must be a legal command.

Abbreviations : ABI = All Banks Idle, RA = Row Address

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1

Power Up Sequence

Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK

Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK

Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK

Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK

Page Read Cycle at Different Bank @Burst Length=4

Page Write Cycle at Different Bank @Burst Length=4, tRDL=1CLK

Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK

Read & Write Cycle at Different Bank @Burst Length=4

Read & Write Cycle With Auto Precharge l @Burst Length=4

Read & Write Cycle With Auto Precharge ll @Burst Length=4

Clock Suspension & DQM Operation Cycle @CAS Letency=2, Burst Length=4

Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=1CLK

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK

Burst Read Single bit Write Cycle @Burst Length =2

Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4

Self Refresh Entry & Exit Cycle & Exit Cycle

Mode Register Set Cycle

Auto Refresh Cycle

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1

: Don't care

tRCD

*Note 1

tSS

tSH

tRP

tCCD

tSS

tSH

tRAC tSAC

tSLZ tOH

tSH

tSS

tSH

tSS tSH

CLOCK

CKE

RAS

CAS

ADDR

BA0 ~ BA1

A10/AP

DQM

Row Active Read Write Read Row Active

Precharge

tCH

tCC tCL

tRAS

tRC

HIGH

tSH

tSS

*Note 2,3 *Note 2,3 *Note 4

*Note 4*Note 3

*Note 3

RbCcCbCaRa

BS BS BS BS BS BS

Ra Rb

QcDbQa

*Note 2,3*Note 2 *Note 2

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

*Note :

1. All input except CKE & DQM can be don't care when CS is high at the CLK high going edge.

2. Bank active & read/write are controlled by BA0~BA1.

64Mb/128Mb 256Mb Active & Read/Write

BA0 BA1 BA0 BA1

0 0 0 0 Bank A

0 1 1 0 Bank B

1 0 0 1 Bank C

1 1 1 1 Bank D

3. Enable and disable auto precharge function are controlled by A10/AP in read/write command

A10/AP 64Mb/128Mb 256Mb Operation

BA0 BA1 BA0 BA1

0 0 0 0 Disable auto precharge, leave bank A active at end of burst.

0 1 1 0 Disable auto precharge, leave bank B active at end of burst.

1 0 0 1 Disable auto precharge, leave bank C active at end of burst.

1 1 1 1 Disable auto precharge, leave bank D active at end of burst.

0 0 0 0 Enable auto precharge, precharge bank A at end of burst.

0 1 1 0 Enable auto precharge, precharge bank B at end of burst.

1 0 0 1 Enable auto precharge, precharge bank C at end of burst.

1 1 1 1 Enable auto precharge, precharge bank D at end of burst.

4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted.

A10/AP 64Mb/128Mb 256Mb Precharge

BA0 BA1 BA0 BA1

0 0 0 0 0 Bank A

0 0 1 1 0 Bank B

0 1 0 0 1 Bank C

0 1 1 1 1 Bank D

1x x x x All Banks

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Power Up Sequence : Don't care

CLOCK

CKE

RAS

CAS

ADDR

BA0

A10/AP

DQM

Precharge Auto Refresh Auto Refresh Mode Register Set

Row Active

BA1

RAa

(All Banks)

(A-Bank)

tRP tRC

High level is necessary

High-Z

High level is necessary

tRC

Key

1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Power is applied to VDD and VDDQ (simultaneously).

3. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

4. Issue precharge commands for all banks of the devices.

5. Issue 2 or more auto-refresh commands.

6. Issue a mode register set command to initialize the mode register.

Note : 1. In order to assert normal MRS, BA0 and BA1 should set "0" absolutely.

Power Up Sequence

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK

HIGH

: Don't care

*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data

is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.

3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC

4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)

*Note 1

tRC

tRCD

*Note 2

tRDL

tSHZ *Note 4

tOH

tRAC

*Note 3 tSAC

tSAC

tRAC

*Note 3

tOH

BA0

BA1

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

Ra Rb

Qa0 Qa1 Qa2 Qa3

Db0 Db1 Db2 Db3

Ra Ca Rb Cb

DQM

Row Active

(A-Bank) Precharge

(A-Bank) Row Active

(A-Bank) Write

(A-Bank) Precharge

(A-Bank)

Read

(A-Bank)

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK

HIGH

: Don't care

*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data

is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.

3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC

4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)

*Note 1

tRC

tRCD

*Note 2

tRDL

tSHZ *Note 4

tOH

tRAC

*Note 3 tSAC

tSAC

tRAC

*Note 3

tOH

BA0

BA1

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

Ra Rb

Qa0 Qa1 Qa2 Qa3

Db0 Db1 Db2 Db3

Ra Ca Rb Cb

DQM

Row Active

(A-Bank) Precharge

(A-Bank) Row Active

(A-Bank) Write

(A-Bank) Precharge

(A-Bank)

Read

(A-Bank)

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK

HIGH

Row Active

(A-Bank) Read

(A-Bank) Write

(A-Bank) Precharge

(A-Bank)

: Don't care

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write

command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge

before end of burst. Input data after Row precharge cycle will be masked internally.

4. tDAL, last data in to active delay, is 1CLK + 20ns

Read

(A-Bank)

tRCD

*Note 2

tRDL

*Note 1 *Note 3

tCDL

Qa0 Qa1 Qb0 Qb1 Qb2

Qa0 Qa1 Qb0 Qb1

Dc0 Dc1 Dd0 Dd1

Write

(A-Bank)

BA0

BA1

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

DQM

Ra Ca Cb Cc Cd

tDAL *Note 4

Row Adiwe

(A-Bank)

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK

HIGH

Row Active

(A-Bank) Read

(A-Bank) Write

(A-Bank) Precharge

(A-Bank)

: Don't care

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write

command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge

before end of burst. Input data after Row precharge cycle will be masked internally.

4. tDAL ,last data in to active delay, is 2CLK + 20ns.

Read

(A-Bank)

tRCD

*Note 2

tRDL

*Note 1 *Note 3

tCDL

Qa0 Qa1 Qb0 Qb1 Qb2

Qa0 Qa1 Qb0 Qb1

Dc0 Dc1 Dd0 Dd1

Write

(A-Bank)

BA0

BA1

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

DQM

Ra Ca Cb Cc Cd

tDAL *Note 4

Row Active

(A-Bank)

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Page Read Cycle at Different Bank @Burst Length=4

HIGH

Row Active

(A-Bank) Read

(C-Bank)

Precharge

(B-Bank)

Read

(D-Bank)

: Don't care

*Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.

2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

Row Active

(B-Bank)

*Note 2

*Note 1

Row Acive

(C-Bank)

Read

(B-Bank)

Precharge

(A-Bank)

Row Active

(D-Bank) Precharge

(C-Bank)

Precharge

(D-Bank)

BA0

BA1

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

DQM

QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2

RAa RBb RCc RDd

RAa RBb CAa RCc CBb RDd CCc CDd

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Page Write Cycle at Different Bank @Burst Length=4, tRDL=1CLK

HIGH

Row Active

(A-Bank) Write

(A-Bank) Row Active

(D-Bank) Write

(D-Bank)

: Don't care

*Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.

Row Active

(B-Bank)

tRDL

Row Active

(C-Bank)

Precharge

(All Banks)

tCDL

Write

(B-Bank)

Write

(C-Bank)

*Note 1

BA0

BA1

ADDR

CAS

RAS

CKE

CLOCK

DQM

A10/AP

RAa RBb CAa CBb RCc RDd CCc CDd

RCc RDd

RAa RBb

*Note 2

DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK

HIGH

Row Active

(A-Bank) Write

(A-Bank) Row Active

(D-Bank) Write

(D-Bank)

: Don't care

*Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.

Row Active

(B-Bank)

tRDL

Row Active

(C-Bank)

Precharge

(All Banks)

tCDL

Write

(B-Bank)

Write

(C-Bank)

*Note 1

BA0

BA1

ADDR

CAS

RAS

CKE

CLOCK

DQM

A10/AP

RAa RBb CAa CBb RCc RDd CCc CDd

RCc RDd

RAa RBb

DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2

*Note 2

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Read & Write Cycle at Different Bank @Burst Length=4

HIGH

RAa

Row Active

(A-Bank) Write

(D-Bank)

Row Active

(B-Bank)

: Don't care

*Note : 1. tCDL should be met to complete write.

Read

(A-Bank)

RAa

CDb RBc

*Note 1

tCDL

RDbCAa

RBc

Row Active

(D-Bank)

Precharge

(A-Bank) Read

(B-Bank)

CBc

RDb

BA0

BA1

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

DQM

QAa0 QAa1 QAa2 QAa3

DDb0 DDb1 DDb2 DDb3

QBc0 QBc1 QBc2

QBc0 QBc1

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Read & Write Cycle with Auto Precharge I @Burst Length=4

HIGH

Row Active

(A-Bank)

: Don't care

*Note1: When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.

- if Read(Write) command without auto precharge is issued at B-Bank before A-Bank auto precharge starts, A-Bank

auto precharge will start at B-Bank read command input point .

- any command can not be issued at A-Bank during tRP after A-Bank auto precharge starts.

Row Active

(B-Bank)

Read with

Auto Pre

charge

(A-Bank)

Write with

Auto Precharge

(A-Bank)

Row Active

(A-Bank)

BA0

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

DQM

QAa0 QAa1 QBb0 QBb1

RAa RBb CAa

RAa RBb

RAcCBb

QBb2 QBb3

Read without Auto

precharge(B-Bank)

Auto Precharge

Start Point

(A-Bank)*Note1

Precharge

(B-Bank)

DAc0 DAc1

DAc0 DAc1QBb2 QBb3

CAc

RAc

BA1

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Read & Write Cycle with Auto Precharge II @Burst Length=4

HIGH

Row Active

(A-Bank)

: Don't care

*Note 1: Any command to A-bank is not allowed in this period.

tRP is determined from at auto precharge start point

Read with

Auto Precharge

(A-Bank)

Auto Precharge

Start Point

(A-Bank)

Row Active

(B-Bank)

Read with

Auto Precharge

(B-Bank)

BA0

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

DQM

Qa0 Qa1 Qa2 Qa3

Qb0 Qb1 Qb2 Qb3

Ra Ca

CbRb

*Note1

Auto Precharge

Start Point

(B-Bank)

BA1

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4

Row Active Clock

Suspension Read Write

DQM

: Don't care

Clock

Suspension

Read

*Note 1

tSHZ tSHZ

Write

DQM

Write

Read DQM

*Note1 : DQM is needed to prevent bus contention.

BA0

BA1

ADDR

CAS

RAS

CKE

CLOCK

DQM

A10/AP

Ra Ca Cb Cc

Dc2Dc0Qb1Qb0Qa3Qa2Qa1Qa0

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst

HIGH

Row Active

(A-Bank)

: Don't care

*Note : 1. At full page mode, burst is finished by burst stop or precharge.

2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.

Both cases are illustrated above timing diagram. See the label 1, 2 on them.

But at burst write, Burst stop and RAS interrupt should be compared carefully.

Refer the timing diagram of "Full page write burst stop cycle".

3. Burst stop is valid at every burst length.

Precharge

(A-Bank)

Burst StopRead

(A-Bank) Read

(A-Bank)

BA0

BA1

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

DQM

QAa0 QAa1 QAa2 QAa3 QAa4

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

RAa CAa CAb

RAa

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=1CLK

Row Active

(A-Bank) Burst Stop Write

(A-Bank) Precharge

(A-Bank)

: Don't care

Write

(A-Bank)

*Note 1,2

tBDL

*Note : 1. At full page mode, burst is finished by burst stop or precharge.

2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding

memory cell. It is defined by AC parameter of tRDL.

DQM at write interrupted by precharge command is needed to prevent invalid write.

DQM should mask invalid input data on precharge command cycle when asserting precharge

before end of burst. Input data after Row precharge cycle will be masked internally.

3. Burst stop is valid at every burst length.

HIGH

tRDL

BA0

BA1

ADDR

CAS

RAS

CKE

CLOCK

DQM

A10/AP

DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5

RAa CAa CAb

RAa

*Note 1

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK

Row Active

(A-Bank) Burst Stop Write

(A-Bank) Precharge

(A-Bank)

: Don't care

Write

(A-Bank)

tBDL

*Note : 1. At full page mode, burst is finished by burst stop or precharge.

2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding

memory cell. It is defined by AC parameter of tRDL.

DQM at write interrupted by precharge command is needed to prevent invalid write.

DQM should mask invalid input data on precharge command cycle when asserting precharge

before end of burst. Input data after Row precharge cycle will be masked internally.

3. Burst stop is valid at every burst length.

HIGH

tRDL

BA0

BA1

ADDR

CAS

RAS

CKE

CLOCK

DQM

A10/AP

DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5

RAa CAa CAb

RAa

*Note 1,2

*Note 1

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Burst Read Single bit Write Cycle @Burst Length=2

HIGH

Row Active

(A-Bank) Row Active

(C-Bank)

Write with

Auto Precharge

(B-Bank)

: Don't care

*Note : 1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).

At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.

Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,

the next cycle starts the precharge.

Write

(A-Bank)

*Note 1

Row Active

(B-Bank) Read

(C-Bank)

Read with

Auto Precharge

(A-Bank)

Precharge

(C-Bank)

*Note 2

BA0

BA1

A10/AP

CL=2

CL=3

ADDR

CAS

RAS

CKE

CLOCK

DQM

DAa0

QAb0 QAb1

QAb0 QAb1 DBc0

DBc0 QCd0 QCd1

QCd0 QCd1

RAa CAa RBb CAb RCc CBc CCd

RCcRAa RBb

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4

Precharge

Power-down

Entry

: Don’t Care

*Note : 1. Both banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least 1CLK + tss prior to Row active command.

3. Can not violate minimum refresh specification. (64ms)

*Note 1

Precharge

tSS

*Note 2

ADDR

CAS

RAS

CKE

CLOCK

DQM

A10/AP

tSS

Ra Ca

Qa0 Qa1 Qa2

Row Active

Precharge

Power-down

Exit

Active

Power-down

Entry

Active

Power-down

Exit

Read

tSHZ

*Note 3

*Note 2

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Self Refresh Entry & Exit Cycle

Self Refresh Entry

: Don't care

*Note : TO ENTER SELF REFRESH MODE

1. CS, RAS & CAS with CKE should be low at the same clcok cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.

3. The device remains in self refresh mode as long as CKE stays "Low".

cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5. CS starts from high.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 4K cycle(64Mb ,128Mb) or 8K cycle(256Mb) of burst auto refresh is required before self refresh entry and

after self refresh exit if the system uses burst refresh.

*Note 1

*Note 7

Hi-Z Hi-Z

Self Refresh Exit Auto Refresh

tSS

*Note 2

*Note 3

*Note 4 tRCmin *Note 6

*Note 5

BA0~BA1

ADDR

CAS

RAS

CKE

CLOCK

DQM

A10/AP

TIMING DIAGRAM CMOS SDRAM

ELECTRONICS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Mode Register Set Cycle

HIGH

MRS Auto Refresh

: Don't care

*Note : 1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode

2. Minimum 2 clock cycles should be met before new RAS activation.

3. Please refer to Mode Register Set table.

New

Command New Command

Hi-Z Hi-Z

tRC

HIGH

MODE REGISTER SET CYCLE

* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

Auto Refresh Cycle

ADDR

CAS

RAS

CKE

CLOCK

DQM

Key Ra

*Note 3

*Note 1

*Note 2

0 1 2 3 4 5 6 7 8 9 10

BA1

BA0