2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit
nano
DAC
™
with I
2
C-Compatible Interface, Tiny SC70 Package
AD5602/AD5612/AD5622
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Single 8-/10-/12-bit DAC, 2 LSB INL
6-lead SC70 package
Micropower operation: max 100 μA @ 5 V
Power-down to <150 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
I2C®-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
On-chip output buffer amplifier, rail-to-rail operation
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
AD5602/AD5612/AD5622
V
DD
V
OU
T
GND
POWER-ON
RESET
DAC
REGISTER 8-/10-/12-BIT
DAC
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
OUTPUT
BUFFER
RESISTOR
NETWORK
REF(+)
SCL SDA
05446-001
ADDR
Figure 1.
Table 1. Related Devices
Part No. Description
AD5601/AD5611/AD5621 2.7 V to 5.5 V, <100 μA, 8-/10-/12-bit
nanoDAC D/A with SPI® interface in
a tiny SC70 package
GENERAL DESCRIPTION
The AD5602/AD5612/AD5622, members of the nanoDAC
family, are single, 8-/10-/12-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply, consuming <100 μA
at 5 V. These DACs come in tiny SC70 packages. Each DAC
contains an on-chip precision output amplifier that allows rail-
to-rail output swing to be achieved.
The AD5602/AD5612/AD5622 use a 2-wire I2C-compatible
serial interface that operates in standard (100 kHz), fast
(400 kHz), and high speed (3.4 MHz) modes.
The references for AD5602/AD5612/AD5622 are derived from
the power supply inputs to give the widest dynamic output range.
Each part incorporates a power-on reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place to the device. The parts contain a power-down
feature that reduces the current consumption of the devices to
<100 nA at 3 V and provides software-selectable output loads
while in power-down mode. The parts are put into power-down
mode over the serial interface. The low power consumption of
the AD5602/AD5612/AD5622 in normal operation makes them
ideally suited for use in portable battery-operated equipment. The
typical power consumption is 0.4 mW at 5 V.
PRODUCT HIGHLIGHTS
1. Available in 6-lead SC70.
2. Maximum 100 μA power consumption, single-supply
operation. These parts operate from a single 2.7 V to 5.5 V
supply typically consuming 0.2 mW at 3 V and 0.4 mW at
5 V, making them ideal for battery-powered applications.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/μs.
4. Reference derived from the power supply.
5. Standard, fast, and high speed mode I2C interface.
6. Designed for very low power consumption.
7. Power-down capability. When powered down, the DAC
typically consumes <150 nA at 3 V.
8. Power-on reset and brownout detection.
AD5602/AD5612/AD5622
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Specifications..................................................................................... 3
I2C Timing Specifications............................................................ 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Ter mi no log y .................................................................................... 14
Theory of Operation ...................................................................... 15
D/A Section................................................................................. 15
Resistor String............................................................................. 15
Output Amplifier........................................................................ 15
Serial Interface ................................................................................ 16
Input Register.............................................................................. 16
Power-On Reset .......................................................................... 17
Power-Down Modes .................................................................. 17
Write Operation.......................................................................... 18
Read Operation........................................................................... 19
High Speed Mode....................................................................... 20
Applications..................................................................................... 21
Choosing a Reference as Power Supply................................... 21
Bipolar Operation....................................................................... 21
Power Supply Bypassing and Grounding................................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
6/05—Revision 0: Initial Version
AD5602/AD5612/AD5622
Rev. 0 | Page 3 of 24
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A, B, W, Y Versions1
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE DAC output unloaded
Resolution Bits
AD5602 8
AD5612 10
AD5622 12
Relative Accuracy2
AD5602 ±0.5 LSB B, Y versions
AD5612 ±0.5 LSB B, Y versions
±4 LSB A version
AD5622 ±2 LSB B, Y versions
±6 LSB A, W versions
Differential Nonlinearity2 ±1 LSB Guaranteed monotonic by design
Zero Code Error 0.5 10 mV All 0s loaded to DAC register
Offset Error ±0.063 ±10 mV
Full-Scale Error 0.5 mV All 1s loaded to DAC register
Gain Error ±0.0004 ±0.037 % of FSR
Zero Code Error Drift 5 μV/°C
Gain Temperature Coefficient 2 ppm of FSR/°C
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 VDD V
Output Voltage Settling Time 6 10 μs Code ¼ to ¾
Slew Rate 0.5 V/μs
Capacitive Load Stability 470 pF RL = ∞
1000 pF RL = 2 kΩ
Output Noise Spectral Density 120 nV/Hz DAC code = midscale, 10 kHz
Noise 2
DAC code = midscale, 0.1 Hz to 10 Hz
bandwidth
Digital-to-Analog Glitch Impulse 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.2 nV-s
DC Output Impedance 0.5 Ω
Short Circuit Current 15 mA VDD = 3 V/5 V
LOGIC INPUTS (SDA, SCL)
IIN, Input Current ±1 μA
VINL, Input Low Voltage 0.3 × VDD V
VINH, Input High Voltage 0.7 × VDD V
CIN, Pin Capacitance 2 pF
VHYST, Input Hysteresis 0.1 × VDD V
LOGIC OUTPUTS (OPEN DRAIN)
VOL, Output Low Voltage 0.4 V ISINK = 3 mA
0.6 V ISINK = 6 mA
Floating-State Leakage Current ±1 μA
Floating-State Output Capacitance 2 pF
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD (Normal Mode) DAC active and excluding load current
VDD = 4.5 V to 5.5 V 75 100 μA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 60 90 μA VIH = VDD and VIL = GND
AD5602/AD5612/AD5622
Rev. 0 | Page 4 of 24
A, B, W, Y Versions1
Parameter Min Typ Max Unit Test Conditions/Comments
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V 0.3 1 μA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 0.15 1 μA VIH = VDD and VIL = GND
POWER EFFICIENCY
IOUT/IDD 96 % ILOAD = 2 mA, VDD = 5 V
1 Temperature ranges for A, B versions: −40°C to +125°C, typical at 25°C.
2 Linearity calculated using a reduced code range 64 to 4032.
3 Guaranteed by design and characterization, not production tested.
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted1.
Table 3.
Limit at TMIN, TMAX
Parameter Conditions2Min Max Unit Description
fSCL3Standard mode 100 KHz Serial clock frequency
Fast mode 400 KHz
High speed mode, CB = 100 pF B 3.4 MHz
High speed mode, CB = 400 pF B 1.7 MHz
t1Standard mode 4 μs tHIGH, SCL high time
Fast mode 0.6 μs
High speed mode, CB = 100 pF B60 ns
High speed mode, CB = 400 pF B120 ns
t2Standard mode 4.7 μs tLOW, SCL low time
Fast mode 1.3 μs
High speed mode, CB = 100 pF B160 ns
High speed mode, CB = 400 pF B320 ns
t3Standard mode 250 ns tSU;DAT, data setup time
Fast mode 100 ns
High speed mode 10 ns
t4Standard mode 0 3.45 μs tHD;DAT, data hold time
Fast mode 0 0.9 μs
High speed mode, CB = 100 pF B0 70 ns
High speed mode, CB = 400 pF B0 150 ns
t5Standard mode 4.7 μs tSU;STA, set-up time for a repeated start
Fast mode 0.6 μs condition
High speed mode 160 ns
t6Standard mode 4 μs tHD;STA, hold time (repeated) start condition
Fast mode 0.6 μs
High speed mode 160 ns
t7Standard mode 4.7 μs tBUF, bus free time between a stop and a
Fast mode 1.3 μs start condition
t8Standard mode 4 μs tSU;STO, set up time for a stop condition
Fast mode 0.6 μs
High speed mode 160 ns
t9Standard mode 1000 ns tRDA, rise time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF B10 80 ns
High speed mode, CB = 400 pF B20 160 ns
AD5602/AD5612/AD5622
Rev. 0 | Page 5 of 24
Limit at TMIN, TMAX
Parameter Conditions2Min Max Unit Description
t10 Standard mode 300 ns tFDA, fall time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF B10 80 ns
High speed mode, CB = 400 pF B20 160 ns
t11 Standard mode 1000 ns tRCL, rise time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF B10 40 ns
High speed mode, CB = 400 pF B20 80 ns
t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated
Fast mode 300 ns start condition and after an acknowledge bit
High speed mode, CB = 100 pF B10 80 ns
High speed mode, CB = 400 pF B20 160 ns
t12 Standard mode 300 ns tFCL, fall time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF B10 40 ns
High speed mode, CB = 400 pF B20 80 ns
tSP4Fast mode 0 50 ns Pulse width of spike suppressed
High speed mode 0 10 ns
1 See Figure 2. High speed mode timing specification applies to the AD5602/AD5612/AD5622-1 only. Standard and fast mode timing specifications apply to both the
AD5602/AD5612/AD5622-1 and AD5602/AD5612/AD5622-2.
2 CB refers to the capacitance on the bus line.
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
4 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns or 10 ns for fast mode or high speed mode, respectively.
05446-002
SCL
S
D
A
PS S P
t
8
t
6
t
5
t
3
t
10
t
9
t
4
t
6
t
1
t
7
t
2
t
11
t
12
Figure 2. 2-Wire Serial Interface Timing Diagram
AD5602/AD5612/AD5622
Rev. 0 | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND –0.3 V to + 7.0 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
VOUT to GND –0.3 V to VDD + 0.3 V
Operating Temperature Range
Extended Automotive (W, Y Versions) –40°C to +125°C
Extended industrial (A, B Versions) −40°C to + 85°C
Storage Temperature Range –65°C to +160°C
Maximum Junction Temperature 150°C
SC70 Package
θJA Thermal Impedance 332°C/W
θJC Thermal Impedance 120°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
ESD 2.0 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5602/AD5612/AD5622
Rev. 0 | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADDR
1
SCL
2
SDA
3
V
OUT
6
GND
5
V
DD
4
AD5602/
AD5612/
AD5622
TOP VIEW
(Not to Scale)
05446-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address. See Table 6.
2 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register.
3 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input register. It
is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
4 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND.
5 GND Ground. The ground reference point for all circuitry on the part.
6 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
AD5602/AD5612/AD5622
Rev. 0 | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
DAC CODE
INL ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
–1.0
–0.8
–0.6
–0.4
–0.2
0 1000500 20001500 350030002500 4000
V
DD
= 5V
T
A
= 25°C
05446-004
Figure 4. Typical AD5622 Integral Nonlinearity Error
DAC CODE
DNL ERROR (LSB)
0.15
0
–0.20
–0.15
–0.10
0.10
–0.05
0.05
0 1000500 20001500 350030002500 4000
V
DD
= 5V
T
A
= 25°C
05446-005
Figure 5. Typical AD5622 Differential Nonlinearity Error
DAC CODE
INL ERROR (LSB)
0.25
0.20
0.15
0.10
0.05
0
–0.25
–0.20
–0.15
–0.10
–0.05
0 400200 600 800 1000
V
DD
= 5V
T
A
= 25°C
05446-047
Figure 6. Typical AD5612 Integral Nonlinearity Error
DAC CODE
DNL ERROR (LSB)
0.05
0.04
0.03
0.02
0.01
0
–0.05
–0.04
–0.03
–0.02
–0.01
0 400200 600 800 1000
V
DD
= 5V
T
A
= 25°C
05446-048
Figure 7. Typical AD5612 Differential Nonlinearity Error
DAC CODE
INL ERROR (LSB)
0.06
0.04
0.02
0
–0.06
–0.04
–0.02
0 10050 150 200 250
V
DD
= 5V
T
A
= 25°C
05446-049
Figure 8. Typical AD5602 Integral Nonlinearity Error
DAC CODE
DNL ERROR (LSB)
0.015
0.010
0.005
0
–0.015
–0.005
–0.010
0 10050 150 200 250
V
DD
= 5V
T
A
= 25°C
05446-050
Figure 9. Typical AD5602 Differential Nonlinearity Error
AD5602/AD5612/AD5622
Rev. 0 | Page 9 of 24
DAC CODE
TUE (LSB)
1
0
–7
–6
–5
–4
–3
–2
–1
0 1000500 20001500 350030002500 4000
V
DD
= 5V
T
A
= 25°C
05446-006
Figure 10. Typical AD5622 Total Unadjusted Error
V
DD
(V)
INL ERROR (LSB)
0.8
0.6
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
2.7 3.2 4.23.7 5.24.7
T
A
= 25°C MAX INL
MIN INL
05446-007
Figure 11. AD5622 INL Error vs. Supply
V
DD
(V)
TUE (LSB)
0
–8
–7
–6
–5
–4
–3
–2
–1
2.7 3.2 4.23.7 5.24.7
T
A
= 25°C
MAX TUE
MIN TUE
05446-008
Figure 12. AD5622 Total Unadjusted Error vs. Supply
V
DD
(V)
DNL ERROR (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.3
–0.2
–0.1
2.7 3.2 4.23.7 5.24.7
T
A
= 25°C
MAX DNL
MIN DNL
05446-009
Figure 13. AD5622 DNL Error vs. Supply
TEMPERATURE (
°C
)
INL ERROR (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.3
–0.2
–0.1
–40 0–20 604020 12010080
MAX INL = 5V
MAX INL = 3V
MIN INL = 5V
MIN INL = 3V
05446-010
Figure 14. AD5622 INL Error vs. Temperature (3 V/5 V Supply)
TEMPERATURE (
°C
)
TUE (LSB)
8
7
6
5
4
3
0
1
2
–40 0–20 604020 12010080
MAX TUE = 5V
MAX TUE = 3V
MIN TUE = 5V
MIN TUE = 3V
05446-011
Figure 15. AD5622 Total Unadjusted Error vs. Temperature (3 V/5 V Supply)
