CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCT OBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Function, Pinout, and Drive Compatible
With FCT, F, and AM29841 Logic
D
Reduced VOH (Typically = 3.3 V) Versions of
Equivalent FCT Functions
D
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D
Ioff Supports Partial-Power-Down Mode
Operation
D
Matched Rise and Fall Times
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Fully Compatible With TTL Input and
Output Logic Levels
D
High-Speed Parallel Latches
D
Buffered Common Latch-Enable Input
D
3-State Outputs
D
CY54FCT841T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D
CY74FCT841T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing
latches and provide additional data width for wider address/data paths or buses carrying parity . The ’FCT841T
devices are buffered 10-bit-wide versions of the FCT373 function.
The ’FCT841T devices’ high-performance interface is designed for high-capacitance-load drive capability, while
providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance
bus loading in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME I/O DESCRIPTION
D I Latch data inputs
LE I Latch-enable input. The latches are transparent when LE is high.
Input data is latched on the high-to-low transition.
Y O 3-state latch outputs
OE I Output-enable control. When OE is low , the outputs are enabled.
When OE is high, the outputs are in the high-impedance (off) state.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
LE
CY54FCT841T ...D PACKAGE
CY74FCT841T ...P, Q, OR SO PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGE†SPEED
(ns) ORDERABLE
PART NUMBER TOP-SIDE
MARKING
QSOP – Q Tape and reel 5.5 CY74FCT841CTQCT FCT841C
SOIC SO
Tube 5.5 CY74FCT841CTSOC
FCT841C
40
°
Cto85
°
C
SOIC
–
SO
Tape and reel 5.5 CY74FCT841CTSOCT
FCT841C
–
40°C
to
85°C
DIP – P Tube 6.5 CY74FCT841BTPC CY74FCT841BTPC
SOIC SO
Tube 9 CY74FCT841ATSOC
FCT841A
SOIC
–
SO
Tape and reel 9 CY74FCT841ATSOCT
FCT841A
–55°C to 125°C CDIP – D Tube 10 CY54FCT841ATDMB
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS INTERNAL
OUTPUTS FUNCTION
OE LE D O Y
H X X X Z
HHLLZZ
HHHHZ
H L X NC Z Latched (Z)
L H L L L
Trans
p
arent
LHHHH
Transparent
L L X NC NC Latched
H = High logic level, L = Low logic level, X = Don’t care,
NC = No change, Z = High-impedance state
logic diagram (positive logic)
OE
To Nine Other Channels
1
13
223
LE
D0
LE
DY0
Q
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input voltage range –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output voltage range –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output current (maximum sink current/pin) 120 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): P package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): Q package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): SO package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature range with power applied, TA –65°C to 135°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
CY54FCT841T CY74FCT841T
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current –12 –32 mA
IOL Low-level output current 32 64 mA
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
CY54FCT841T CY74FCT841T
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK
VCC = 4.5 V, IIN = –18 mA –0.7 –1.2
V
V
IK VCC = 4.75 V, IIN = –18 mA –0.7 –1.2
V
VCC = 4.5 V, IOH = –12 mA 2.4 3.3
VOH
VCC = 4 75 V
IOH = –32 mA 2V
V
CC =
4
.
75
V
IOH = –15 mA 2.4 3.3
VOL
VCC = 4.5 V, IOL = 32 mA 0.3 0.55
V
V
OL VCC = 4.75 V, IOL = 64 mA 0.3 0.55
V
Vhys All inputs 0.2 0.2 V
II
VCC = 5.5 V, VIN = VCC 5
µA
I
IVCC = 5.25 V, VIN = VCC 5µ
A
IIH
VCC = 5.5 V, VIN = 2.7 V ±1
µA
I
IH VCC = 5.25 V, VIN = 2.7 V ±1µ
A
IIL
VCC = 5.5 V, VIN = 0.5 V ±1
µA
I
IL VCC = 5.25 V, VIN = 0.5 V ±1µ
A
IOZH
VCC = 5.5 V, VOUT = 2.7 V 10
µA
I
OZH VCC = 5.25 V, VOUT = 2.7 V 10 µ
A
IOZL
VCC = 5.5 V, VOUT = 0.5 V –10
µA
I
OZL VCC = 5.25 V, VOUT = 0.5 V –10 µ
A
I‡
VCC = 5.5 V, VOUT = 0 V –60 –120 –225
mA
I
OS
‡
VCC = 5.25 V, VOUT = 0 V –60 –120 –225
mA
Ioff VCC = 0 V, VOUT = 4.5 V ±1±1µA
ICC
VCC = 5.5 V, VIN ≤ 0.2 V, VIN ≥VCC – 0.2 V 0.1 0.2
mA
I
CC VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥VCC – 0.2 V 0.1 0.2
mA
∆ICC
VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2
mA
∆I
CC VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2
mA
ICCD¶
VCC = 5.5 V, One input switching at 50% duty cycle,
Outputs open, OE = GND, LE = VCC,
VIN ≤ 0.2 V or VIN ≥VCC – 0.2 V 0.06 0.12 mA/
I
CCD
¶
VCC = 5.25 V, One input switching at 50% duty cycle,
Outputs open, OE = GND, LE = VCC,
VIN ≤ 0.2 V or VIN ≥VCC – 0.2 V 0.06 0.12 MHz
†Typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus
and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,
prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In
any sequence of parameter tests, IOS tests should be performed last.
§Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
¶This parameter is derived for use in total power-supply calculations.
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
CY54FCT841T CY74FCT841T
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
#
VCC =55V
One bit switching
at f1 = 10 MHz VIN ≤ 0.2 V or
VIN ≥VCC – 0.2 V 0.7 1.4
#
VCC
=
5
.
5
V
,
Outputs open,
1
at 50% duty cycle VIN = 3.4 V or GND 1 2.4
#
,
OE = GND,
LE = VCC 10 bits switching
at f1 = 2.5 MHz VIN ≤ 0.2 V or
VIN ≥VCC – 0.2 V 1 3.2||
IC#
1
at 50% duty cycle VIN = 3.4 V or GND 4.1 13.2||
mA
I
C
#
VCC = 5 25 V
One bit switching
at f1 = 10 MHz VIN ≤ 0.2 V or
VIN ≥VCC – 0.2 V 0.7 1.4
mA
VCC
=
5
.
25
V
,
Outputs open,
1
at 50% duty cycle VIN = 3.4 V or GND 1 2.4
,
OE = GND,
LE = VCC 10 bits switching
at f1 = 2.5 MHz VIN ≤ 0.2 V or
VIN ≥VCC – 0.2 V 1 3.2||
1
at 50% duty cycle VIN = 3.4 V or GND 4.1 13.2||
Ci5 10 5 10 pF
Co9 12 9 12 pF
†Typical values are at VCC = 5 V, TA = 25°C.
#IC= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
IC= Total supply current
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH= Duty cycle for TTL inputs high
NT= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY54FCT841AT CY74FCT841AT CY74FCT841BT CY74FCT841CT
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
twPulse duration, LE high 5 4 4 4 ns
tsu Setup time, data before LE↑2.5 2.5 2.5 2.5 ns
thHold time, data after LE↑3 2.5 2.5 2.5 ns
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM TO
TEST LOAD
CY54FCT841AT CY74FCT841AT
UNIT
PARAMETER
(INPUT) (OUTPUT)
TEST
LOAD
MIN MAX MIN MAX
UNIT
tPLH
D
Y
C
L
= 50 pF, 1.5 10 1.5 9
ns
tPHL
D
Y
L,
RL = 500 Ω1.5 10 1.5 9
ns
tPLH
D
Y
C
L
= 300 pF, 1.5 15 1.5 13
ns
tPHL
D
Y
L,
RL = 500 Ω1.5 15 1.5 13
ns
tPLH
LE
Y
C
L
= 50 pF, 1.5 13 1.5 12
ns
tPHL
LE
Y
L,
RL = 500 Ω1.5 13 1.5 12
ns
tPLH
LE
Y
C
L
= 300 pF, 1.5 20 1.5 16
ns
tPHL
LE
Y
L,
RL = 500 Ω1.5 20 1.5 16
ns
tPZH
OE
Y
C
L
= 50 pF, 1.5 13 1.5 11.5
ns
tPZL
OE
Y
L,
RL = 500 Ω1.5 13 1.5 11.5
ns
tPZH
OE
Y
C
L
= 300 pF, 1.5 25 1.5 23
ns
tPZL
OE
Y
L,
RL = 500 Ω1.5 25 1.5 23
ns
tPHZ
OE
Y
C
L
= 5 pF, 1.5 9 1.5 7
ns
tPLZ
OE
Y
L,
RL = 500 Ω1.5 9 1.5 7
ns
tPHZ
OE
Y
CL = 50 pF, 1.5 10 1.5 8
ns
tPLZ
OE
Y
L
RL = 500 Ω1.5 10 1.5 8
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM TO
TEST LOAD
CY74FCT841BT CY74FCT841CT
UNIT
PARAMETER
(INPUT) (OUTPUT)
TEST
LOAD
MIN MAX MIN MAX
UNIT
tPLH
D
Y
C
L
= 50 pF, 1.5 6.5 1.5 5.5
ns
tPHL
D
Y
L,
RL = 500 Ω1.5 6.5 1.5 5.5
ns
tPLH
D
Y
C
L
= 50 pF, 1.5 13 1.5 13
ns
tPHL
D
Y
L,
RL = 500 Ω1.5 13 1.5 13
ns
tPLH
LE
Y
C
L
= 50 pF, 1.5 8 1.5 6.4
ns
tPHL
LE
Y
L,
RL = 500 Ω1.5 8 1.5 6.4
ns
tPLH
LE
Y
C
L
= 300 pF, 1.5 15.5 1.5 15
ns
tPHL
LE
Y
L,
RL = 500 Ω1.5 15.5 1.5 15
ns
tPZH
OE
Y
C
L
= 50 pF, 1.5 8 1.5 6.5
ns
tPZL
OE
Y
L,
RL = 500 Ω1.5 8 1.5 6.5
ns
tPZH
OE
Y
C
L
= 300 pF, 1.5 14 1.5 12
ns
tPZL
OE
Y
L,
RL = 500 Ω1.5 14 1.5 12
ns
tPHZ
OE
Y
C
L
= 5 pF, 1.5 6 1.5 5.7
ns
tPLZ
OE
Y
L,
RL = 500 Ω1.5 6 1.5 5.7
ns
tPHZ
OE
Y
CL = 50 pF 1.5 7 1.5 6
ns
tPLZ
OE
Y
L
RL = 500 Ω, 1.5 7 1.5 6
ns
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
(see Note B)
Output
W aveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈3.5 V
0 V
VOL + 0.3 V
≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
S1 7 V
500 ΩGND
From Output
Under Test
CL = 50 pF
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH – 0.3 V
500 Ω
500 Ω
1.5 V1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-88575013A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
CY54FCT841ATDMB ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
CY54FCT841ATLMB ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
CY74FCT841ATSOC ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841ATSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841ATSOCG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841ATSOCT ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841ATSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841ATSOCTG4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841BTPC ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CY74FCT841BTPCE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CY74FCT841CTQCT ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT841CTQCTE4 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT841CTQCTG4 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT841CTSOC ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841CTSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841CTSOCG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841CTSOCT ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841CTSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT841CTSOCTG4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CY74FCT841ATSOCT SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
CY74FCT841CTQCT SSOP/
QSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CY74FCT841CTSOCT SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CY74FCT841ATSOCT SOIC DW 24 2000 346.0 346.0 41.0
CY74FCT841CTQCT SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0
CY74FCT841CTSOCT SOIC DW 24 2000 346.0 346.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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