BENEFITS AND FEATURES
Completely Manages All Timekeeping Functions
o Real-Time Clock Counts Seconds,
Minutes, Hours, Date of the Month, Month,
Day of the Week, and Year with Leap-Year
Compensation Valid Up to 2100
o 31 x 8 Batter y-Backed General-Purpose
RAM
Simple Serial Port Interfaces to Most
Microcontrollers
o Simple 3-Wire Interface
o TTL-Compatible (VCC = 5V)
o Single-Byte or Multiple-Byte (Burst Mode)
Data Transfer for Read or Write of Clock or
RAM Data
Low Power Operation Extends Battery Backup
Run Time
o 2.0V to 5.5V Full Operation
o Uses Less Than 300nA at 2.0V
8-Pin DIP and 8-Pin SO Minimizes Required
Space
Optional Industrial Temperature Range: -40°C
to +85°C Supports Operation in a Wide Range
of Applications
Underwriters Laboratories® (UL) Recognized
PIN CONFIGURATIONS
ORDERING INFORMATION
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK*
DS1302+
0°C to +70°C
8 PDIP (300 mils)
DS1302
DS1302N+
-40°C to +85°C
8 PDIP (300 mils)
DS1302
DS1302S+
0°C to +70°C
8 SO (208 mils)
DS1302S
DS1302SN+
-40°C to +85°C
8 SO (208 mils)
DS1302S
DS1302Z+
0°C to +70°C
8 SO (150 mils)
DS1302Z
DS1302ZN+
-40°C to +85°C
8 SO (150 mils)
DS1302ZN
+Denotes a lead-free/RoHS-compliant package.
*An N anywhere on the top mark indicates an industrial temperature grade devi c e. A + anywhere on the top mark indicates a lead-f ree devi ce.
UL is a registered trademark of Underwriters Laborat ori es, Inc.
DS1302
Trickle-Charg e Timekeeping Chip
VCC1
SCLK
I/O
CE
VCC2
X1
X2
GND
8
7
6
5
1
2
3
4
DS1302
VCC2
X1
X2
GND
VCC1
SCLK
I/O
CE
8
7
6
5
1
2
3
4
SO (208 mils/150 mils)
DS1302
TOP VIEW
1 of 13 REV: 3/15
DS1302 Trickle-Charge Timekeeping Chip
DETAILED DESCRIPTION
The DS1302 trickle-charge timekeeping chip contains a real-time clock/calendar and 31 bytes of static RAM. It
communicates with a m icroprocessor via a simple serial interface. The real-time clock/calendar provides se conds,
minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for
months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or
12-hour format with an AM/PM indicator.
Interfac ing the DS 1302 wit h a mic roprocess or is sim plified b y using s ync hronous serial com m unication. On ly three
wires are required to communicate with the clock/RAM: CE, I/O (data line), and SCLK (serial clock). Data can be
transf erred to and from the clock/R AM 1 b yte at a tim e or in a burst of up to 31 bytes. T he DS1302 is des igned to
operate on very low power and retain data and clock information on less than 1µW.
The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202, the
DS1302 has the additional features of dual power pins for primary and backup power supplies, programmable
trickle charger for VCC1, and seven additional bytes of scratchpad memory.
OPERATION
Figure 1 shows the main elements of the serial timekeeper: shift register, control logic, oscillator, real-time clock,
and RAM.
TYPICAL OPERATING CIRCUIT
DS1302
CPU
V
CC
V
CC2
SCLK
CE
GND
X2
X1
VCC
I/O
V
CC1
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DS1302 Trickle-Charge Timekeeping Chip
Figure 1. Block Diagram
TYPICAL OPERATING CHARACTERISTIC S
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
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DS1302 Trickle-Charge Timekeeping Chip
PIN DESCRIPTION
PIN NAME FUNCTION
1 VCC2
Prim ary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a
backup source to maintain the time and date in the absence of primary power. The
DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 +
0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the
DS1302.
2 X1 Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is
designed for operation with a crystal having a specified load capacitance of 6pF.
For more information on crystal selection and crystal layout considerations, refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The
DS1302 can also be driven by an external 32.768kHz oscillator. In this
configuration, the X1 pin is connected to the external oscillator signal and the X2 pin
is floated.
3 X2
4 GND Ground
5 CE Input. CE signal must be asserted high during a read or a write. This pin has an
internal 40k Ω (typ) pulldown resistor to ground. Note: Previous data sheet revisions
referred to CE as RST. The functionality of the pin has not changed.
6 I/O Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire
interface. This pin has an internal 40kΩ (typ) pulldown resistor to ground.
7 SCLK Input. SCLK is used to synchronize data movement on the serial interface. This pin
has an internal 40k
Ω
(typ) pulldown resistor to ground.
8 VCC1
Low-Power Operation in Single Supply and Battery-Operated Systems and Low-
Power Battery Backup. In systems using the trickle charger, the rechargeable
energy source is connected to this pin. UL recognized to ensure against reverse
charging current when used with a lithium battery. Go to www.maxim-
ic.com/TechSupport/QA/ntrl.htm.
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DS1302 Trickle-Charge Timekeeping Chip
OSCILLATOR CIRCUIT
The DS1302 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 1 shows a
functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is
usually less than one second.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional
error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the
oscillator circuit may result in the clock running fast. Figure 2 shows a typical PC board layout for isolating the
cr ystal and os cillator from noise. R efer to Applicat ion Note 58: Cry stal Considera tions for Dallas Real-T ime Clocks
for detailed information.
Table 1. Crystal Specifications*
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal Frequency fO 32.768 kHz
Series Resistance ESR 45 kΩ
Load Capacitance CL 6 pF
*The crystal, t races, and crystal input pins should be isolated from RF generating signals. Refer to
Applic ation Note 58: Crystal Considerati ons for Dallas Real-Time C locks for additional specifications.
Figure 2. Typical PC Board Layou t for Crystal
COMMAND BYTE
Figure 3 shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) m ust be a logic
1. If it is 0, writes to the DS1302 will be disabled. Bit 6 s pecif ies c lock/calendar dat a if logic 0 or RAM dat a if lo gic 1.
Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation
(input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).
Figure 3. Address/ Comm and Byte
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
GND
NOTE: A VOI D ROU TI NG SIGN A LS IN THE
CROSSHATCHED AREA (UPPER LEFT-
HAND QUADRANT) OF THE PACKAGE
UNLESS TH ER E IS A GROUND PL AN E
BETWEE N THE SI GN AL LIN E AND THE
PACKAGE.
1RAM
CK A4 A3 A2 A1 A0 RD
WR
76543210
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DS1302 Trickle-Charge Timekeeping Chip
CE AND CLOCK CONTROL
Driving the CE input high initiates all data transfers. The CE input serves two functions. First, CE turns on the
control logic that allows access to the shift register for the address/command sequence. Second, the CE signal
provides a method of terminating either single-byte or multiple-byte CE data transfer.
A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data m ust be valid during
the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data
transf er term inates and the I/O p in goes t o a h igh-im pedance s tate. Figure 4 s hows data tr ansf er. At po wer -up, C E
must be a logic 0 until VCC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state.
DATA INPU T
Following the eight SCLK cycles tha t inp ut a write comm and b yte, a data b yte is in put on th e ris ing e dg e of the nex t
eight SCLK c ycles. Additional SCLK cycles are ignored should the y inadvertently occur. Data is input starting with
bit 0.
DATA OUTP UT
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the
next eigh t SCL K c ycles. N ote th at t he firs t data bit to be tr ansm itted occurs on the f irst f alling edge after the las t bit
of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur
so long as CE remains high. This operat ion permits continuous burst mode read capability. Also, the I/O pin is tri-
stated upon each rising edge of SCLK. Data is output starting with bit 0.
BURST MODE
Burst m ode can be specified for either the clock /calendar or the R AM registers by addressing location 31 decim al
(address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or
write. T here is no dat a storage cap acity at loc ations 9 thr ough 31 in th e Clock /Calendar Regist ers or loc ation 31 in
the RAM registers. Reads or writes in burst mode start with bit 0 of address 0.
W hen writing t o th e c lock registers i n the b ur st mode, the f irs t eigh t regis t er s must be written i n order f or the data t o
be transf erred. Howe ver, when writ ing to RAM in burs t mode it is not neces sary to write all 31 b ytes for the data to
transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not.
CLOCK/CALENDAR
The tim e and calend ar inf ormation is obtain ed by r e ading t he ap propr i ate reg is ter b ytes. Table 3 illustrates th e R T C
registers . The time and ca lendar are s et or initiali zed by writing t he appropriat e register bytes . The contents of the
time and calendar registers are in the binary-coded decimal (BCD) format.
The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries
result in undefined operation.
W hen readin g or writing th e time and date regis ters, sec ondary (user) buf fers are used to pr event errors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers the rising edge of CE.
The c ountdown chain is res et whenever th e seconds r egister is writte n. Write transf ers occur on the f alling edge of
CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be
written within 1 second.
The DS1302 can b e run in either 12-hour or 24-hour m ode. Bit 7 of the hours register is defined as the 12- or 24-
hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour m ode, bit 5 is the AM/PM bit with
logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be
re-initialized wh ene ver the 12/24 bit is changed.
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DS1302 Trickle-Charge Timekeeping Chip
CLOCK HALT FLAG
Bit 7 of the s ec onds re gis te r is def in ed as th e c l ock halt (C H) flag. When this b it is s et to lo gic 1, t he clock os cilla tor
is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When
this bit is written to logic 0, the clock will start. The initial power-on state is not defined.
WRITE-PROTECT BIT
Bit 7 of the c ontr ol reg ist er i s the wr ite-prot ec t bit . The first seven b its (bits 0 to 6) are f or c ed to 0 and al ways read 0
when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit
prevents a write operation to any other register. The initial power-on state is not defined. Therefore, the WP bit
should be cleared before attempting to write to the device.
TRICKLE-CHARGE REGISTER
This r egister controls t he trick le-charge charac teristics of the DS1302. T he simplif ied s chematic of Figure 5 shows
the basic components of the tr ickle charger . T he tr ick le-c harge s el ect (TCS) bits (bits 4 to 7) c ontr o l the selection of
the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other
patterns will disable the tr ickle char ger. The DS1302 powers up with the trick le charger disabled. The diode select
(DS) bits (bits 2 an d 3) sel ect whether one di ode or t wo diodes ar e connecte d bet ween VCC2 a nd VCC1. If DS is 01,
one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled
independe ntly of TCS. T he RS bits (b its 0 an d 1) sele ct the res istor that is conn ected bet ween VCC2 and VCC1. T he
resistor and diodes are selected by the RS and DS bits as shown in Table 2.
Table 2. Trickle Charger Resistor and Diode Select
TCS
BIT 7 TCS
BIT 6 TCS
BIT 5 TCS
BIT 4 DS
BIT 3 DS
BIT 2 RS
BIT 1 RS
BIT 0 FUNCTION
X X X X X X 0 0 Disabled
X X X X 0 0 X X Disabled
X X X X 1 1 X X Disabled
1 0 1 0 0 1 0 1 1 Diode, 2kΩ
1 0 1 0 0 1 1 0 1 Diode, 4kΩ
1 0 1 0 0 1 1 1 1 Diode, 8kΩ
1 0 1 0 1 0 0 1 2 Diod es, 2k Ω
1 0 1 0 1 0 1 0 2 Diod es, 4k Ω
1 0 1 0 1 0 1 1 2 Diod es, 8k Ω
0 1 0 1 1 1 0 0 Initial power-on state
Diode and resistor selection is determined by the user according to the maximum current desired for battery or
super cap charging. The maximum charging current can be calculated as illustrated in the following example.
Assume that a system power supply of 5V is applied to VCC2 and a super cap is connected to VCC1. Also assume
that the trickle charger has been enabled with one diode and resistor R1 between VCC2 and VCC1. The maximum
current IMAX would therefore be calculated as follows:
IMAX = (5.0V – diode drop) / R1 ≈ (5.0V – 0.7V) / 2kΩ ≈ 2.2mA
As the super cap charges, the voltage drop between VCC2 and VCC1 decreases and therefore the charge current
decreases.
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DS1302 Trickle-Charge Timekeeping Chip
CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst mode operation. In this mode, the first eight clock/calendar
registers can be consecutively read or written (see Table 3) starting with bit 0 of address 0.
If the write-protect bit is set high when a write c lock /calendar burs t mode is specified, no data tra nsfer will occ ur to
any of the eight clock /calendar reg isters (this includes the control reg ister). The tr ickle charger is not accessible in
burst mode.
At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time
information is read f rom t hese s ec ondar y re gister s, whi le the cl oc k may continue t o r un. T his elim inates th e n eed to
re-read the registers in case of an update of the main registers during a read.
RAM
The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.
RAM BURST MODE
The RAM c ommand b yte specifies bur st m ode operation. In this mode, the 31 R AM register s can be cons ecutivel y
read or written (see Table 3) starting with bit 0 of address 0.
REGISTER SUMMARY
A register data format summary is shown in Table 3.
CRYSTAL SELECTION
A 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal selected for
use should have a specified load capacitance (CL) of 6pF. For more information on crystal selection and crystal
layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clock s .
Figure 4. Data Transfer Summary
A1 A2 A3 A4 R/C1
CE
SCLK
I/O
R/WA0 D1 D2 D3 D4 D5 D6 D7D0
SINGLE-BYTE READ
A1 A2 A3 A4 R/C1
CE
SCLK
I/O
R/WA0 D1 D2 D3 D4 D5 D6 D7D0
SINGLE-BYTE WRITE
NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE EN D OF THE BU RST.
8 of 13
DS1302 Trickle-Charge Timekeeping Chip
Table 3. Register Address/Definition
RTC
READ WRITE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RANGE
81h
80h
CH
10 Seconds
Seconds
00–59
83h
82h
10 Minutes
Minutes
00–59
85h 84h 12/24 0
10
Hour Hour 1–12/0–23
AM/PM
87h
86h
0
0
10 Date
Date
1–31
89h 88h 0 0 0
10
Month
Month 1–12
8Bh
8Ah
0
0
0
0
0
Day
1–7
8Dh
8Ch
10 Year
Year
00–99
8Fh
8Eh
WP
0
0
0
0
0
0
0
—
91h
90h
TCS
TCS
TCS
TCS
DS
DS
RS
RS
—
CLOCK BURST
BFh
BEh
RAM
C1h
C0h
00-FFh
C3h
C2h
00-FFh
C5h
C4h
00-FFh
.
.
.
.
.
.
.
.
.
FDh
FCh
00-FFh
RAM BURST
FFh
FEh
Figure 5. Programmable Trickle Charger
2KΩ
4kΩ
8kΩ
R1
R3
R2
VCC2 VCC1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0
TRICKLE CHARG E REGISTER (90h write, 91h read )
1 0F 16 SELECT
NOTE: ONLY 1010b ENABLES CHARGER 1 OF 2
SELECT 1 OF 3
SELECT
TCS
0-3
= TRICK LE CHARGER S E L E CT
DS
0-1
= DIODE SELECT
ROUT
0-1
= RESISTOR SELECT
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DS1302 Trickle-Charge Timekeeping Chip
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………………….-0.5Vto +7.0V
Operating Temperature Range, Commercial………………………………………………………………….0°C to +70°C
Operating Temperature Range, Industrial (IND)……………………………………………………………-40°C to +85°C
Storage Temperature Range……………………………………………………………………………..….-55°C to +125°C
Soldering Temperature (leads, 10 seconds)………………………………………………………………..………….260°C
Soldering Temperature (surface mount)………………………………………………..…….See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may c ause permanent damage to the devic e. Thes e are stress ratings only,
and functional operat ion of the device at these or any other conditions beyond those indicated in the operational sect ions of the specifications is
not implied. Exposure to the absolute maximum rating condit i ons for extended periods may aff ect device reliabi l i ty.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC1, VCC2
V
CC1,
VCC2
(Notes 2, 10) 2.0 3.3 5.5 V
Logic 1 Input VIH (Note 2) 2.0
V
CC
+
0.3
V
Logic 0 Input VIL VCC = 2.0V (Note 2) -0.3 +0.3 V
VCC = 5V
-0.3
+0.8
DC ELECTRICAL CHARACTERISTICS
(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Leakage ILI (Notes 5, 13) 85 500 µA
I/O Leakage ILO (Notes 5, 13) 85 500 µA
Logic 1 Output (IOH = -0.4mA)
VOH
VCC = 2.0V
(Note 2)
1.6
V
Logic 1 Output (IOH = -1.0mA)
VCC = 5V
2.4
Logic 0 Output (IOL = 1.5mA)
VOL
VCC = 2.0V
(Note 2)
0.4
V
Logic 0 Output (IOL = 4.0mA)
VCC = 5V
0.4
Active Supply Current
(Osc illator En abled) ICC1A
VCC1 = 2.0V
CH = 0
(Notes 4, 11)
0.4
mA
VCC1 = 5V
1.2
Timekeeping Current
(Osc illator En abled) ICC1T
VCC1 = 2.0V
CH = 0
(Notes 3, 11,13)
0.2
0.3
µA
VCC1 = 5V
0.45
1
Standby Current (Oscillator
Disabled) ICC1S
VCC1 = 2.0V
CH = 1
(Notes 9, 11, 13)
1
100
nA
VCC1 = 5V
1
100
IND
5
200
Active Supply Current
(Osc illator En abled) ICC2A
VCC2 = 2.0V
CH = 0
(Notes 4, 12)
0.425
mA
VCC2 = 5V
1.28
Timekeeping Current
(Osc illator En abled) ICC2T
VCC2 = 2.0V
CH = 0
(Notes 3, 12)
25.3
µA
VCC2 = 5V
81
Standby Current (Oscillator
Disabled) ICC2S VCC2 = 2.0V
CH = 1
(Notes 9, 12)
25 µA
VCC2 = 5V
80
Trickle-Charge Resistors
R1
2
kΩ
R2
4
R3
8
Trickle-Charge Diode Voltage
Drop VTD
0.7 V
10 of 13
DS1302 Trickle-Charge Timekeeping Chip
CAPACITANCE
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS
Input Capacitance CI 10 pF
I/O Capacitance CI/O 15 pF
AC ELECTRICAL CHARACTERISTICS
(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data to CL K Se t up tDC
VCC = 2.0V
(Note 6)
200
ns
VCC = 5V
50
CLK to Data Hold tCDH
VCC = 2.0V
(Note 6)
280
ns
VCC = 5V
70
CLK to Data Delay tCDD
VCC = 2.0V
(Notes 6, 7, 8)
800
ns
VCC = 5V
200
CLK Low Time tCL
VCC = 2.0V
(Note 6)
1000
ns
VCC = 5V
250
CLK High Time tCH
VCC = 2.0V
(Note 6)
1000
ns
VCC = 5V
250
CLK Frequency tCLK
VCC = 2.0V
(Note 6)
0.5
MHz
VCC = 5V
DC
2.0
CLK Rise and Fall tR, tF
VCC = 2.0V
2000
ns
VCC = 5V
500
CE to CLK Setup tCC
VCC = 2.0V
(Note 6)
4
µs
VCC = 5V
1
CLK to CE Hold tCCH
VCC = 2.0V
(Note 6)
240
ns
VCC = 5V
60
CE Inactive Time tCWH
VCC = 2.0V
(Note 6)
4
µs
VCC = 5V
1
CE to I/O High Impedance tCDZ
VCC = 2.0V
(Note 6)
280
ns
VCC = 5V
70
SCLK to I/O High Impedance tCCZ
VCC = 2.0V
(Note 6)
280
ns
VCC = 5V
70
Note 1:
Limits at -40°C are guaranteed by design and are not pr oduction t ested.
Note 2:
All vol tages are referenc ed to ground.
Note 3:
ICC1T and ICC2T are specified with I/O open, CE and SCLK set to a logic 0.
Note 4:
ICC1A and ICC2A are spec if ied with the I /O pin open, CE high, SCLK = 2M Hz at VCC = 5V; SCLK = 500kHz, VCC = 2.0V.
Note 5:
CE, SCLK, and I/O all have 40kΩ pulldown res istors to ground.
Note 6:
Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time.
Note 7:
Measur ed at VOH = 2.4V or VOL = 0.4V.
Note 8:
Load capacitance = 50pF.
Note 9:
ICC1S and ICC2S are spec if ied with CE, I/O, and SCLK open.
Note 10:
VCC = VCC2, when VCC2 > VCC1 + 0.2V; VCC = VCC1, when VCC1 > VCC2.
Note 11:
VCC2 = 0V.
Note 12: VCC1 = 0V.
Note 13: Typical val ues are at +25°C.
11 of 13
DS1302 Trickle-Charge Timekeeping Chip
Figure 6. Timing Diagram: Read Data Transfer
CE
SCLK
I/O
t
DC
t
CDH
t
CC
t
CDZ
t
CDD
t
R
t
F
t
CL
t
CH
ADDRESS/COMMAND BYTE READ DATA BYTE
t
CCZ
Figure 7. Timing Diagram: Write Data Transfer
CE
SCLK
I/O t
DC
t
CDH
t
CC
t
R
t
F
t
CL
t
CCH
t
CWH
ADDRESS/COMMAND BYTE W RITE DATA BYTE
t
CH
CHIP INFORMATION
TRANSISTOR COUNT: 11,500
THERMAL INFORMATION
PACKAGE THETA-JA
(°C/W) THETA-JC
(°C/W)
8 DIP
110
40
8 SO (150 mils)
170
40
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 PDIP — 21-0043
8 SO (208 mils) — 21-0262
8 SO (150 mils) — 21-0041
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DS1302 Trickle-Charge Timekeeping Chip
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
120208
Removed the leaded parts and references to the 16-pin SO package. 1, 4, 12
In the Features section, changed the 31 x 8 RAM feature to indicate that it is
battery backed.
1
Updated Figure 1 and removed original Figure 2 (oscillator circuit). 3, 5
Added a new Table 2 for the trickle charger resistor and diode select. 7
Replaced the timing diagrams (Figures 6 and 7). 12
Added Package Information table. 12
3/15
Updated Benefits and Features section
1
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