
BCR 35PN
Oct-19-19991
NPN/PNP Silicon Digital Transistor Array
• Switching circuit, inverter, interface circuit,
driver circuit
• Two (galvanic) internal isolated NPN/PNP
Transistors in one package
• Built in bias resistor (R1=10kΩ, R2=47kΩ)
Tape loading orientation
VPS05604
6
3
1
5
4
2
EHA07193
123
456
W1s
Direction of Unreeling
Top View Marking on SOT-363 package
(for example W1s)
corresponds to pin 1 of device
Position in tape: pin 1
opposite of feed hole side
EHA07176
654
321
C1 B2 E2
C2B1E1
1
R
R2
R1
R2
TR1
TR2
Type Marking Pin Configuration Package
BCR 35PN WUs 1=E1 2=B1 3=C2 4=E2 5=B2 6=C1 SOT-363
Maximum Ratings
Parameter Symbol Value Unit
Collector-emitter voltage VCEO 50 V
Collector-base voltage VCBO 50
Emitter-base voltage VEBO 6
Input on Voltage Vi(on) 20
DC collector current IC100 mA
Total power dissipation, TS = 115 °C Ptot 250 mW
Junction temperature Tj150 °C
Storage temperature Tst
-65 ... 150
Thermal Resistance
Junction ambient 1) RthJA K/W
≤ 275
Junction - soldering point RthJS ≤ 140
1) Package mounted on pcb 40mm x 40mm x 1.5mm / 0.5cm 2 Cu