AT27C4096
1
Features
•Fast Read Access Time - 55 ns
•Low Power CMOS Operation
– 100
µ
A Maximum Standb y
– 40 mA Maximum Active at 5 MHz
•JEDE C Standard Packag es
– 40-Lead 600 mil PDIP
– 44-Lead PLCC
– 40-Lead TSOP (10 mm x 14 mm)
•Direct Upgrade from 512K bit, 1M bit, and 2M bit
(AT27C516, AT27C1024, and AT27C2048) EPROMs
•5V ± 10% Power Supply
•High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
•Rapid™ Programming Algorithm - 50
µ
s/w ord (typical)
•CMOS and TTL Compatible Inputs and Outputs
•Integrated Product Identification Code
•Commercial and Industrial Temperature Ranges
Description
The AT27C4096 is a low-power, high-performance 4,194,304-bit one-time program-
mable re ad only memory (OTP EP ROM) organiz ed 256K by 16 bits . It requir es a sin-
gle 5V power su pply in norma l read mo de operation . Any wor d can be access ed in
less th an 55 ns, el iminating th e need fo r speed-redu cing WAIT s tates. The by-16
organization makes this part ideal for high-performance 16- and 32-bit microprocessor
systems.
TSOP Top View
Type 1
PDIP Top View
PLCC Top View
4-Megabit
(256K x 16 )
OTP EPROM
AT27C4096
0311E-A–06/97
Pin Configuratio ns
Note: Both GND pins must be
connected.
Pin Name Function
A0 - A17 Addresses
O0 - O15 Outputs
CE Chip Enable
OE Output Enable
NC No Connect
(continued)
AT27C4096
2
Description
In read mode, the AT27C4096 typically consumes 15 mA.
Standby mode supply current is typically less than 10
µ
A.
The AT27C4096 is available in industry standard
JEDEC-approved one-time programmable (OTP) plastic
PDIP, PL CC, and TSOP packa ges. The device features
two-line control (CE, OE) to eliminate bus contention in
high-speed systems.
With high density 256K word storage capability, the
AT27C4096 al lows fi rmware to be stored re liably an d to be
accessed by the system without the delays of mass storage
media.
Atmel’s AT27C4096 has additional features that ensure
high quality and efficient production use. The Rapid™ Pro-
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Program-
ming time is typically only 50
µ
s/word. The Integrated Prod-
uct Id entific ation Code electr onically identifi es the dev ice
and manufacturer . This feature is used by industry stan-
dard programming equipment to select the proper program-
ming algorithms and voltages.
System Considerations
Switching between active and standby conditions via the
Chip Enabl e pi n may pr od uce tr ansient volta ge e xcur sion s.
Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device
non-c onformanc e. At a min imum, a 0. 1
µ
F high frequency,
low inherent inductance, ceramic capacitor should be uti-
lized for each dev ice. This capacitor shoul d be connected
between the VCC and Ground terminals of the device, as
close to the device as possible. Additionally, to stabilize the
supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7
µ
F bulk electrolytic capacitor should
be utili zed, agai n conn ected be tween the VCC and Grou nd
terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected
to the array.
AT27C4096
3
Block Diag ram
Operating Modes
Notes: 1. X can be VIL or VIH.
2. Refer to the Programming characteristics.
3. VH = 12.0 ± 0.5V.
4. Two iden tifier w ords ma y be selected. All Ai in puts are held lo w (V IL), exc ept A9 , w hic h is s et to VH, a nd A0, w h ich i s toggled
low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.
5. Standby VCC current (ISB) is specified with VPP = V CC. VCC > VPP will cause a slight increa se in I SB.
Mode/Pin CE OE Ai VPP Outputs
Read VIL VIL Ai X(1) DOUT
Output Disable X VIH X X High Z
Standby VIH XXX
(5) High Z
Rapid Program(2) VIL VIH Ai VPP DIN
PGM Verify VIH VIL Ai VPP DOUT
PGM Inhibit VIH VIH XV
PP High Z
Product Identification(4) VIL VIL A9 = VH(3)
A0 = VIH or VIL
A1 - A17 = VIL VCC Identification Code
Absolute Maximum Ratings*
Temperature Under Bias ......................-55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the d e v ice. Th is is a stress rating only an d
functio nal oper ati on of the de vi ce at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolu te maximum rating
conditions f or exten ded periods ma y aff ect de vice
reliability.
Note: Maximum voltage is -0.6V dc which may undershoot
to -2.0V for pulses of less than 20 ns. Maximum out-
put pin voltage is VCC + 0.75V dc which may over-
shoot to +7.0V for pulses of less than 20 ns.
Storage Temperature............................-65°C to +150°C
Voltage on Any Pin with
Respect to Ground...............................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ............................-2.0V to +14.0V(1)
VPP Supply Voltage with
Respect to Ground.............................-2.0V to +14.0V(1)
AT27C4096
4
DC and AC Operating Conditions for Read Operation
AT27C4096
-55 -70 -90 -12 -15
Operating Temperature
(Case) Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
AC Characteristics for Read Operation
Note: 2, 3, 4, 5. See the AC Waveforms for Read Operation diagram.
AT27C4096
-55 -70 -90 -12 -15
Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Units
tACC(3) Address to
Output D elay CE = OE
= VIL 55 70 90 120 150 ns
tCE(2) CE to Output Delay O E = VIL 55 70 90 120 150 ns
tOE(2)(3) OE to Output Delay CE = VIL 20 30 35 40 50 ns
tDF(4)(5) OE or CE High to
Output Flo at,
whichever occ urre d
first 20 20 20 30 35 ns
tOH(4) Output Hold from
Address, CE or OE,
whichever occ urre d
first 77000ns
DC and Operating Characteristics f o r Read Operation
Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP
.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and
IPP
.
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC ± 1
µ
A
ILO Output Leakage Current VOUT = 0V to VCC ± 5
µ
A
IPP1(2) VPP(1) Read/Standby Current VPP = VCC 10
µ
A
ISB VCC(1) Standby Current
ISB1 (CMOS)
CE = VCC ± 0.3V 100
µ
A
ISB2 (TTL)
CE = 2.0 to VCC + 0.5V 1mA
I
CC VCC Active Current f = 5 MHz, IOUT = 0 mA,
CE = VIL 40 mA
VIL Input Low Voltage -0.6 0.8 V
VIH Input High Voltage 2.0 VCC + 0.5 V
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output Hi gh Voltage IOH = -400
µ
A2.4V
AT27C4096
5
AC Waveforms for Read Operation(1)
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after th e address is valid w ithout impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
Input Test Waveforms and Measurement Levels
For -55 devices o nly:
tR, tF < 5 ns (10% to 90%)
For -70, -90, -12 and -15 devices:
tR, tF < 20 ns (10% to 90%)
Pin Capacitance
(f = 1 MHz T = 25°C)(1)
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Typ Max Units Conditions
CIN 410pF V
IN = 0V
COUT 812pF V
OUT = 0V
Output Test Load
Note: CL = 100 pF including jig
capacitance, except for
the -45 and -55 devices,
wher e CL = 30 pF.
AT27C4096
6
Programming Waveforms(1)
Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27C4096, a 0.1
µ
F capacitor is required across VPP and ground to suppress spurious voltage
transients.
DC Programming Characteristics
TA = 25 ± 5°C, V CC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Symbol Parameter Test Conditions Min Max Units
ILI Input Load Current VIN = VIL, VIH ±10
µ
A
VIL Input Low Level -0.6 0.8 V
VIH Input High Level 2.0 VCC + 0.7 V
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = -400
µ
A2.4 V
I
CC2 VCC Supply Current
(Program and Verify) 50 mA
IPP2 VPP Supply Current CE = VIL 30 mA
VID A9 Product Identification Voltage 11.5 12.5 V
AT27C4096
7
AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven
—see tim ing diagram .
3. Program Pulse width tolerance is 50
µ
sec ± 5%.
Symbol Parameter Test Conditions(1)
Limits
UnitsMin Max
tAS Address Setup Time
Input Rise and Fall Times
(10% to 90%) 20ns
Input Pulse Levels
0.45V to 2.4V
Input Timing Reference Level
0.8V to 2.0V
Output Timing Reference Level
0.8V to 2.0V
2
µ
s
tOES OE Setup Time 2
µ
s
tDS Data Setup Time 2
µ
s
tAH Address Hold Time 0
µ
s
tDH Data Hold Time 2
µ
s
tDFP OE High to Output Float Delay(2) 0 130 ns
tVPS VPP Setup Ti me 2
µ
s
tVCS VCC Setup Time 2
µ
s
tPW CE Program Pulse Width(3) 47.5 52.5
µ
s
tOE Data Valid from OE 150 ns
tPRT VPP Pulse Rise Time During
Programming 50 ns
Atmel’s 27C4096 Inter g rated Product Identification Code
Codes
Pins
Hex DataA0 015-08 O7 O6 O5 O4 O3 O2 O1 O0
Manufacturer 0 0 00011110001E
Device Type 1 0 1111010000F4
AT27C4096
8
Rapid Programming Algorithm
A 50
µ
s CE pulse width is used to program. The address is
set to the first l ocation. VCC is rais ed to 6.5V and V PP is
raised to 13.0V. Each address is first programmed with one
50
µ
s CE pulse without verification. Then a verifica-
tion/reprog ramming loop is executed for each address. In
the event a wo rd fail s to pas s veri ficati on, up to 10 su cces-
sive 50
µ
s pulses are applied with a verification after each
pulse. If the word fails to verify after 10 pulses have been
applied, the part is considered failed. After the word verifies
properly, the next address is selected until all have been
checked. VPP is then lowere d to 5.0V an d VCC to 5.0V . All
words are read again and compared with the original data
to determine if the device passes or fails.
AT27C4096
9
Ordering Informat ion
tACC (ns)
ICC (mA )
Ordering Code Package Operation RangeActive Standby
55 40 0.1 AT27C4096-55JC
AT27C4096-55PC
AT27C4096-55VC
44J
40P6
40V
Commercial
(0°C to 70°C)
40 0.1 AT27C4096-55JI
AT27C4096-55PI
AT27C4096-55VI
44J
40P6
40V
Industrial
(-40°C to 85°C)
70 40 0.1 AT27C4096-70JC
AT27C4096-70PC
AT27C4096-70VC
44J
40P6
40V
Commercial
(0°C to 70°C)
40 0.1 AT27C4096-70JI
AT27C4096-70PI
AT27C4096-70VI
44J
40P6
40V
Industrial
(-40°C to 85°C)
90 40 0.1 AT27C4096-90JC
AT27C4096-90PC
AT27C4096-90VC
44J
40P6
40V
Commercial
(0°C to 70°C)
40 0.1 AT27C4096-90JI
AT27C4096-90PI
AT27C4096-90VI
44J
40P6
40V
Industrial
(-40°C to 85°C)
120 40 0.1 AT27C4096-12JC
AT27C4096-12PC
AT27C4096-12VC
44J
40P6
40V
Commercial
(0°C to 70°C)
40 0.1 AT27C4096-12JI
AT27C4096-12PI
AT27C4096-12VI
44J
40P6
40V
Industrial
(-40°C to 85°C)
150 40 0.1 AT27C4096-15JC
AT27C4096-15PC
AT27C4096-15VC
44J
40P6
40V
Commercial
(0°C to 70°C)
40 0.1 AT27C4096-15JI
AT27C4096-15PI
AT27C4096-15VI
44J
40P6
40V
Industrial
(-40°C to 85°C)
Package Typ e
44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
40V 40 Lead, Plastic Thin Small Outline Package (TSOP) 10 x 14 mm
