clocks sdctl cpu sdctl CPUPAL cpu romcard sequoia clocks sheet 1, CPU, PAL and 3.3V to 5V buffers romcard sheet 2, sdram and address and data buffers sdctl isa sequoia cpu VIDEO sequoia TVOUT sequoia clocks clocks vl vl romcard sequoia sequoia sdctl cpu sequoia SDRAM clocks tv tv tv clocks vl clocks sheet 3, Video controller, VGA and LCD outputs isa sequoia clocks sheet 4, TV output encoder and filter CLOCKS vl sequoia clocks clocks sheet 5, clock generation and ROM card interface SEQUOIA clocks clocks sequoia sequoia clocks sheet 6, SEQUOIA core logic, boot rom and IDE interface isa PCIUMI vl vl sequoia clocks isa sheet 7, PCI bridge, UMI1 and UMI0 isa AUDIO clocks clocks SUPERIO ser1t ser1shdn ser2t isa clocks vBat ir sheet 8, super I/O, keyboard/mouse and parallel ports sequoia isa sheet 10, audio (mike in, headphone out) and gameport POWER vBat pBat rcRst Makes p5000*, p3300* and p2000* pwrgood Sheet 12, power supply and backup battery ser1t ser1shdn ser2t clocks ir sequoia SERIAL ser1t ser1shdn ser2t clocks ir sequoia sheet 9, RS232 interface and IR interface vBat sequoia.pBat sequoia.rcrst Ether isa isa vl sequoia.pwrgood Sheets 13 to 16 show the bypass capacitors and are included as required by the other sheets sequoia vl sequoia sheet 11, Ethernet Title: NC Reference Design By: Mark Hayter $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.19 $ Version: Rev 4 Systems Research Center Palo Alto, CA u0: gnd* nc* gnd* gnd* gnd* 51 48 49 52 50 gnd* gnd* 131 130 gnd* p3300* p3300* gnd* gnd* gnd* 142 140 56 66 67 68 p3300* c0 c1 c2 c3 gnd* abe gnd* nc* 57 139 138 69 70 121 72 65 71 SA110 u3: cclk clocks.cpumclk nc* 128 clk mclk nmclk tms tdo tdi tck trst 123 124 tp2: TP SharkPal MACH231-6 3V3 world testclk tck_byp sna pwrslp mse mccfg0 mccfg1 mccfg2 58 62 60 61 abort dbe wait reset fiq irq config adr cccfg0 [2..31] cccfg1 be cccfg2 [0..3] cccfg3 ape abe data spdf [0..31] resetout clocks.nmclk nc* ~mreq ~rw nc* nc* 59 seq mreq rw clf lock 26 4 36 127 141 143 144 wait maloa [0..2] malob mclk mreq rw .a [] .~be cpu [2..4] [] alow [2..4] .a [10..12] [] amid [10..12] [23..31] [] ahi tp3: TP 28 m0 i15:33R 27 m1 i16:33R Rh Rh 68 m2 i17:33R 66 m3 i18:33R 7 m4 i19:33R Rh Rh Rh 6 m5 [] uC .d 82 52 i25:1K p5000* test1 test2 vl.~boff i20:33R Rh R8x33 70 40 72 [] a1 b1 [8] [8] cpu.d[8..15] [] a2 b2 [8] [8] i22:1K dbe 1 .muxsel .~rasA .~rasB .~casA .~casB .~weA .~weB .~cs .rdoeab .~rdoeba gnd* sysDdir sysaen sysden sysddir bootmd 17 25 sdctl.bootmd 15 24 LVC04 vl.sreset 3 4 abe .hold .~reset .hlda vl .adr[23] .adr[22] ~res tp23: isa.~refresh TP sequoia.intr clocks.forcpu 5 6 ~irq 9 8 cclk 11 10 ~fiq fiq TP sequoia.smi 13 33 13 67 30 23 83 romcard.wp clk486 35 hold reset hlda ba23 ba22 refresh flashwp Keep cclk path short or add terminator cpu.d[16..23] cpu.d[24..31] [] [] tp8: tp11: 24 i3:1K 9 ads brdy rdy blast memldev ba31 ba27 ba25 vldnc vlmnio romcardcs romcardoe romcardwe 50 45 49 8 48 46 51 39 69 .~ads .~brdy .~rdy .~blast .~local[0] .adr[31] .adr[27] .adr[25] .dnc .mnio 10 18 i7:1K c1 i8:1K i4:1K c2 i9:1K 1 3 i6:1K c3 i10:1K Rhi .~rdy i13:4K7 Rhi 4 i11:1K [] cpu.a[10..17] [] 1 a1 b1 [8] [8] a2 b2 [8] [8] [] [16..23] [] [24..31] oe1 oe2 dir1 dir2 48 25 tp25: a1 b1 [8] [8] a2 b2 [8] [8] [] [2..9] [] [10..17] [2..5] [] 24 dir1 dir2 oe1 oe2 t [4] tp27: TP4 48 [6..9] [] 25 t [4] ~sysAen vl.adr u7: 74FCT164245 F164245h 3V3 5V TP cpu.a[18..21] cpu.a[22] cpu.a[23] cpu.a[24] cpu.a[26] cpu.~be cpu.a[27] cpu.a[29] cpu.a[30] ~rw gnd* [] 41 40 38 37 [] 30 29 27 26 Note:2 pairs used sheet 2 b1: p3300* vl.~loc0or1 6 cpu.a[2..9] abe Rhi abt Rhr p5000* 25 3V3 or 5V Rhi Rh lor 2 48 TP4 .~brdy i12:4K7 Rhi Rh ACT00 oe1 oe2 a1 [4] a14 a15 a16 a17 b1 [4] b14 b15 b16 b17 [] 12 [18..21] [22] [23] [24] [26] a2l [4] a24 a25 a26 a27 b2l [4] b24 b25 b26 b27 [] vl.~be 8 9 11 Rhi Rh i5:1K dir1 dir2 74FCT164245 FT164245 3V3 5V romcard.~cs romcard.~oe romcard.~we 19 c0 Rh u2: vl.~local[0] vl.~local[1] [4] ~sysDen p3300* clear FIQ Rh t u6: p5000* cpu.a[27] Note: expected use is smi causes FIQ pc[4] configured as gpcs3 used to p5000* i2:1K [] 3V3 or 5V 1 sysDdir Selectively populate res high or low to set core speed 12 [0..3] 74FCT164245 FT164245 3V3 5V tp9: tp24: [8..15] u5: vl 81 u1: 2 [] vl.data 5V world clocks.vlcopy Note: LVC04 is ok with 5V inputs 1 [0..7] TP TP bootmd high on reset ~sysAen ~sysDen sysDdir 16 Rhi vl.hlda [] ~sysDen Rhi either t1 [] tp26: TP4 cpu.d[0..7] 3V3 or 5V 38 muxsel rasa rasb casa casb wea web cs [0..7] rdoeab rdoeba cpudbe [23..31] [] 74FCT164245 FT164245 3V3 5V [0..2] abt dbe nwait ~res ~fiq ~irq 122 65 u4: Note: If the pulldowns on nwait and dbe are removed the CPU input pads will be driven past maximum Vih sdctl gnd* nwait i21:1K 24 Rhi .maA uA [] R6x33 .maB uB [] 5 Bypass (sheet 16) 20 22 23 nc* nc* nc* vl.wnr 3V3 or 5V 1 pwr 19 abe 24 dir1 dir2 oe1 oe2 48 25 10 pairs of 0.1uF and 0.001uF p5000* 9 8 14.31818MHz f2 10 i24:33R ~sysAen clocks.clk14mb Note: 2 pairs used sheet 6 b2: Rh OSC p5000* p5000* 4 1 gnd* 2 vcc oe gnd out 3 12 f0 p5000* 11 13 f1 i23:33R Rh clocks.clk14m pwr Bypass Note: dir is high for a->b (sheet 16) 10 pairs of 0.1uF and 0.001uF Title: cpu/pal 1 of 16 By: Mark Hayter $Date: 1997/05/16 23:22:15 $ RCS $Revision: 1.36 $ Version: Rev 4 Systems Research Center Palo Alto, CA Note: the slightly perverse assignment of the 32 data bits to the 64 sdram bits results from the way CS0 and CS2 are connected on the module u4: u2: 74LVC257 LVC257 3V3 part latA5 cpu.a[13] u1: 74FCT3573 FCT3573i 3V3 part cpu.a [5] [6] [7] [8] [9] [21] [22] [23] 2 3 5 cpu.a[14] 6 11 2 3 4 5 6 7 8 9 d0 d1 d2 d3 d4 d5 d6 d7 o0 o1 o2 o3 o4 o5 o6 o7 19 18 17 16 15 14 13 12 latA6 latA7 latA8 latA9 latA21 latA22 latA23 cpu.a[15] 10 14 cpu.a[16] 13 a0 a1 b0 b1 c0 c1 d0 d1 sdctl.maA madr 1 s zb zc 4 m3 i23:33R [3] latA23 latA22 Rh 7 m4 i24:33R 9 m5 i25:33R sdctl.~weA sdctl.~cs[0] sdctl.~cs[1] sdctl.~cs[2] sdctl.~cs[3] latA21 latA22 clocks.sdramA sdctl.~casA sdctl.~rasA [5] Rh zd i26:33R 12 15 gnd* oe 11 le oe 1 [6] 74LVC257 LVC257 3V3 part gnd* 126 tiehi Rh m6 123 [4] u3: sdctl.muxsel [] 38 za Rh sdctl.muxsel [] 132 27 30 114 45 129 122 39 [] 111 115 128 Note: this latch shuts when the mux swings to cas address 13 a0 a1 b0 b1 c0 c1 d0 d1 1 s 2 cpu.a[17] 3 5 cpu.a[18] 6 11 cpu.a[19] gnd* cpu.a[20] sdctl.muxsel 10 14 tiehi za 4 m7 i27:33R 63 [] [] [] [] [0..15] [0..15] [16..31] [16..31] u7: 74FCT163501 FT163501 3V3 part [16] cke0 cke1 zb 7 m8 i28:33R u5: dqmb0 dqmb1 dqmb2 dqmb3 dqmb4 dqmb5 dqmb6 dqmb7 28 sda scl sa0 sa1 sa2 82 29 46 47 112 113 130 131 83 [0] [1] [0] [1] [2] [3] [2] [3] [0..15] gnd* sdbeA i7:10K i8:10K [] g0 24 g1 26 Rh [8] zc 9 m9 i29:33R sdctl.maB [] [] zd oe i30:33R 12 m10 15 gnd* ma10ap 38 Rh latA23 latA22 123 126 sdctl.~weB sdctl.~cs[4] sdctl.~cs[5] sdctl.~cs[6] sdctl.~cs[7] latA21 latA22 clocks.sdramB sdctl.~casB sdctl.~rasB (sheet 15) 132 27 30 114 45 129 122 39 [] 111 115 128 i5:1K tiehi 63 Rh [] cpu.d[0..15] 33 g2 i14:10K 31 g3 i13:10K Rhr gnd* sdctl.rdoeab gnd* clocks.dbus 1 2 55 oeba oeab leba leab clkab clkba 30 sdctl.~rdoeba gnd* clocks.dbus 27 28 sequoia.sda sequoia.scl 165 166 gnd* 167 u8: 74FCT163501 FT163501 3V3 part SDDIMM dll [16] dlh [16] dhl [16] dhh malo [0..2] mami [3..9] ma10ap ma11 ma12 ma13 we s0 s1 s2 s3 ba0 ba1 ck [0..3] cas ras [] [] [] [] [0..15] [0..15] [16..31] [16..31] gnd* cke0 cke1 dqmb0 dqmb1 dqmb2 dqmb3 dqmb4 dqmb5 dqmb6 dqmb7 28 sda scl sa0 sa1 sa2 82 29 46 47 112 113 130 131 83 165 166 [0] [1] [0] [1] [2] [3] [2] [3] i9:10K [] g4 24 g5 26 Rh i10:10K Rh sdctl.rdoeab gnd* clocks.dbus [16] 5 pairs of 0.1uF and 0.001uF p3300* b [16] b16 b17 Rhr [16..31] [9] Rh a [16] a16 a17 Rh Rh Note: Gets two pairs of bypass caps from sheet 1 Bypass5 [3..9] [7] Note: muxsel is high for RAS, low for CAS pwr dll [16] dlh [16] dhl [16] dhh malo mami ma10ap ma11 ma12 ma13 we s0 s1 s2 s3 ba0 ba1 ck [0..3] cas ras [0..2] Rh tiehi p3300* dramData SDDIMM 1 2 55 a [16] a16 a17 b [16] b16 b17 oeba oeab leba leab clkab clkba [] cpu.d[16..31] 33 g6 i11:10K 31 g7 i12:10K Rhr gnd* Rhr 27 28 30 gnd* clocks.dbus sdbeB sequoia.sda sequoia.scl p3300* gnd* 167 i4:1K i3:1K Rhr p3300* Rhr Note: sda/scl is I2C made in software through sequoia and open collector (5V world) buffers u6: 74FCT3574 FCT3574i 3V3 part cpu.~be[3] cpu.~be[3] cpu.~be[2] cpu.~be[2] cpu.~be[1] cpu.~be[1] cpu.~be[0] cpu.~be[0] clocks.nmclk 2 3 4 5 6 7 8 9 11 d0 d1 d2 d3 d4 d5 d6 d7 cp o0 o1 o2 o3 o4 o5 o6 o7 p3300* 19 b0 i15:33R 18 b1 i16:33R 17 b2 i17:33R 16 b3 i18:33R 15 b4 i19:33R 14 b5 i20:33R 13 b6 i21:33R 12 b7 i22:33R Rh Rh Rh Rh Rh Rh Rh Rh oe 1 sdctl.bootmd sdbeB[3] sdbeA[3] sdbeB[2] sdbeA[2] sdbeB[1] sdbeA[1] sdbeB[0] sdbeA[0] i31:10K Rhr i32:10K Rhr i33:10K Rhr i34:10K Rhr i35:10K Rhr i36:10K Rhr i37:10K Rhr i38:10K Rhr Note: bootmd is high (outputs disabled) on reset Title: SDRAM 2 of 16 By: Mark Hayter $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.23 $ Version: Rev 4 Systems Research Center Palo Alto, CA Note: This connector has the same pinout as the C&T development kit connector u5: vl LCDcon Note: The LCD section is for experimentation. The RFI filters suggested by C&T are not fitted The signals are simply brought out to a connector adrc[0..7] [] [8..15] [] pmid [0..7] [] plow [8..15] .~reset .~ads .mnio .wnr 207 22 31 11 tp10: 23 TP Tried using sequoia.pc[3] for standby, but chip must be out of standby during reset or it does not configure .~rdy .~local[1] .~be .adr[2..27] .data .~local[1] .vlbus2 .clk32k .clk14m clocks 24 25 [] [] [] 27 i54:100K c0 154 Rh 203 reset ads mnio wnr rdyrtn lrdy ldev be [0..3] adr [2..27] data [0..31] lclk c32khz xtal1 p p5000* 178 i1:1K u1: shfclk 70 shfclk 13 shfclk flm 67 flm 11 flm Rh 99 adra [] dataa [] adra [] data [0..15] adr [0..8] 14 29 28 13 27 rasab0a casal casah weaa oeab data [0..15] [] 160 m2 159 m3 157 Rhr i5:33R Rhr adr [0..8] m4 155 ras casl cash we oe 29 28 13 rasab0b casbl casbh weab [8] i55:4K7 [2] i34:4K7 [11] = Panel ID0 [3] i35:4K7 Rhi i36:4K7 m 69 m 7 m [13] = Panel ID2 [5] i37:4K7 [14] = Panel ID3 [6] i38:4K7 8 de [15] = Sw defined dataa [7] i39:4K7 Rhi Rhi Link enavdd enavee enavdd enavee 62 61 de enbk cvcc0 205 i17:47uF cgnd0 cvcc1 202 rasab0 casal casah wea cgnd1 208 hsync 65 Note: for these power pins Cv gnd* care must be taken with pVideo* layout. C&T 65550 data book section A.10 page A-4 i22:10R cvcc1 206 eeok v12ok vddok i18:0.1uF Cva6 Rhr i19:0.1uF i20:47uF i21:0.1uF Cv Cva6 Cv vsync oeab0 64 5 enabkl 3 veesafe v12000safe vddsafe data adra [] adr [0..8] 2 1 LcdPwr VGAcon Might want fuse to +5V on VGA pwr gnd* 126 m6 125 Rhr casbl casbh data [0..15] adra [] adr [0..8] 27 m7 123 m8 124 adrc nc* nc* nc* nc* nc* 14 29 28 13 rasab1a casal casah weba i11:33R Rhr i12:33R [] 101 104 103 102 100 i41: tv.v hsync vsout 14 vsync rout 1 red gout 2 green 3 blue Fb i42: red rasab1 web 60 ro i51:220pF Cv i43: green 58 go ca [0..8] blue rasc cascl casch wec oec 57 rset 55 rs i52:220pF Cv i44: bo i25a:37R5 i26a:37R5 i27a:37R5 bout Fb i53:220pF i24:560R Rhr Cv Rv Rv tv.b Rv tv.g dataa datab [] 29 28 13 rasab1b casbl casbh webb 9 i13:33R Rhr 42 66 i14:33R Rhr 158 27 142 108 80 pwr: 181 LINK i27b:37R5 gnd* mad mbd Rvi bvcc0 bvcc1 agnd dvcc mvcca mvccb mvccc avcc Rvi gnd* Rvi gnd* 56 gnd* nc* nc* nc* nc* Note: If no TV out is needed a and b can be replaced with a 75R for each of i25-27 avcc 59 i46: ivcc0 ivcc1 i29:22uF i30:0.1uF i31:0.047uF Cva5 Cv Cv Note: care must be taken with placing these caps 10 syncrtn 5 grnd id3 id2 id1 id0 DBAV99 i48: DBAV99 15 4 12 11 i50: DBAV99 gnd* pVideo* For the latest revision 65550 C&T recomend that the core only be run at 3.3V. This is a change from earlier revs, there is at least gnd* one problem (probably timing) so rev 4 has a link to allow both voltages i26b:37R5 [0..15] [] [0..15] 14 8 redrtn grnrtn bluertn 6 tv.r 7 i25b:37R5 bus, memory and digital i/o 5V power NOTE: remove i55 for 5V operation 13 Rhr 27 p5000* p3300* p5000* pwr hsout Fb Fb MT16C257 [] 9 Rhr Dram512kx8 datab nc* i40: tv.h i10:33R u4: ras casl cash we oe gnd* Cv m5 Rhr i9:33R MT16C257 [0..15] Rhi enavdd Rhr i16:0.1uF href aa pVideo* i15:10R Rhi Rhr i8:33R Dram512kx8 [] Rhi [4] i7:33R u3: dataa Rhi Rhi Fb ras casl cash we oe Rhi [12] = Panel ID1 i23:1000pF 14 i33:4K7 lp i22:1000pF Rhr MT16C257 adra 156 m1 Rhr i4:33R i6:33R Dram512kx8 [] m0 Rhr i3:33R [6] 10 Cv u2: datab i2:33R i32:4K7 lp [0..8] ras casl cash we oe [5] 68 stndby MT16C257 [0] = high VL-bus [2] = high 1x clock [5] = low extclk 14.3MHz [6] = low A26,A27 [7] = high test disable [8] = low IVcc = 3.3V [10] = low EDO lp Cv c1 Dram512kx8 [0..7] [0..15] cvcc0 p5000* plcd [] adra ptop [8] Chips F65550B CT65550 (VL-bus) i28:4.7uH Induct i56:0.1uF i57:0.1uF i58:0.001uF Cv Cv Cv p5000* Note: i24, the 560R res on rset must be 1% or better i25, i26 and i27 pulldowns must be 2% or better pwr Bypass (sheet 16) 10 pairs of 0.1uF and 0.001uF 3 of 16 Title: Video By: Mark Hayter $Date: 1997/05/12 06:22:39 $ RCS $Revision: 1.27 $ Version: Rev 4 Systems Research Center Palo Alto, CA tv AD724 c8:0.1uF .r vr 6 rin vg 7 gin Ch c9:0.1uF .g r1:75R cmps 10 vo c1:220uF or i1: oc compout RCA Rh Ch Cha8 Fb c10:0.1uF .b vb 8 bin 16 hsync vsync Ch r2:75R .h .v 15 luma 11 vy c2:220uF yr i2: yc yout Rh Cha8 Fb DIN4 sequoia.pc[3] 5 p5000* p5000* f*4 NTSC clocks.clk14m 12 1 3 p5000* gnd* 14 encd select crma stnd fin dpos apos 9 r3:75R vc cr c3:220uF Cha8 c5:0.1uF c6:0.1uF c7:10uF Cv Cv Cva4 agnd cout 43 2 1 p5000* 4 Cva4 dgnd i3: Fb 2 c4:10uF 13 cc Rh gnd* Title: TV out 4 of 16 By: Mark Hayter $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.10 $ Version: Rev 4 Systems Research Center Palo Alto, CA u1: Note: think about rom data bus when roms not active does it need tie offs, or for the PAL to keep it active? 74FCT16245 FCT16245 5V part vl.data[0..7] vl.data[8..15] [] [] 1 romcard.~oe a1 b1 [8] [8] a2 b2 [8] [8] dir1 dir2 24 oe1 oe2 [] u7:33.333MHz OSC [0..7] p5000* vcc oe gnd 4 1 [] [8..15] gnd* 2 out 3 c33 i17:33R clocks.clk33m Rh u5: 74FCT388915T F388915t 3V3 part 48 25 romcard.~cs p3300* 8 vccan 9 lf lock qq u2: 74FCT16245 FCT16245 5V part lf Note: Clock ordering set for rev.4 layout nc* nc* 19 26 i4:24R clocks.sdramA[1] Rh vl.data[16..23] vl.data[24..31] [] [] 1 romcard.~oe a1 b1 [8] [8] a2 b2 [8] [8] dir1 dir2 24 oe1 oe2 [] [] [16..23] i1:10uF i2:0.1uF i3:0.1uF Cva4 Cv Cvr 10 p3300* p3300* p3300* gnd* 48 25 romcard.~cs 14 clocks.sdramA[0] Rh i6:24R gnd* [24..31] q0 i5:24R q0 12 18 4 6 clocks.sdramB[0] Rh gndan freqsel pllen oenrst refsel q1 i7:24R q1 16 clocks.sdramB[1] Rh i8:24R clocks.sdramA[2] Rh q2 i9:24R q2 21 clocks.sdramA[3] Rh i10:24R clocks.sequref u3: 74FCT16244 FCT16244 5V part [2..5] [6..9] [10..13] [14..17] [] a1 [4] a2 [4] a3 [4] a4 [] [] [] y1 1 y2 vl.adr 25 gnd* 24 [2..5] [] [6..9] [] [10..13] [] [14..17] romData [] data i21:0.1uF i22:0.1uF i23:0.1uF i24:0.1uF Cv Cv Cv Cv y3 q3 i11:24R q3 23 romAdr [] [4] 5 adr [4] u4: romcard.~cs romcard.~oe ~romwe 29 q4 q5 2 i13:30R q4 70 romcard.wp vl.~reset 74FCT827 FCT827 5V part 33 i14:56R q5 clocks.cpumclk Rh ck33 25 i15:51R clocks.vlcopy Rh i27:51R Rh ckfb wp reset 31 clocks.dbus Rh feedback qd2 ce oe wr 55 clocks.nmclk Rh 28 [2..25] y4 clocks.sdramB[3] Rh i12:36R gnd* [0..31] clocks.sdramB[2] Rh sync0 sync1 ROMconn [4] oe1 oe2 oe3 oe4 48 [] 11 Recomended bypass caps: one per digital vcc p3300* [4] [4] 7 gnd* u6: 74ACT74 [18..25] romcard.~we sequoia.sda [] 10 11 1 gnd* 13 a y [8] [8] a8 a9 y8 y9 [] [18..25] ACT74 i25:10K p5000* p5000* p5000* Rhi 15 14 sequoia.smart[3] Note: This is a rev 3 change it was to gpiob[0], but that was needed for the smart card detect oe1 oe2 1 4 2 clocks.clk14mb sequoia.pBat C4069 c1 1 vcc 14 2 i19:15pF c2 i20:32.768KHz cx p5000* p5000* 3 13 10 12 Ch XTAL 11 r0 s0 d0 cp0 r1 s1 d1 cp1 q0 5 qb0 6 q1 9 qb1 nc* clk7m cc i26:47R cb i16:47R 8 c3 3 clocks.clk3m Rh Note: these are the ISA clock divided by 4, ie 3.5795MHz ish i18:1M 4 clocks.forcpu Rh Rhi clocks.clk32k 5 6 gnd* 9 8 nc* gnd* 11 10 nc* gnd* 13 12 nc* Note: 7 bypass pairs this sheet, 3 for sheet 7. p5000* pwr Bypass (sheet 16) 10 pairs of 0.1uF and 0.001uF 7 gnd gnd* Title: Clocks 5 of 16 By: Mark Hayter $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.26 $ Version: Rev 4 Systems Research Center Palo Alto, CA u1: PT86C768A2 vl SEQUOIA1 .adr[2..27] .adr[31] [] The sequoia burst bus needs pullups on the control lines if the power-down feature is used the bd data lines also need pullups adr [2..27] a31 172 tp17: TP tp18: TP .~brdy nc* 162 .~ads .~be .~blast .~brdy 155 [] 160 153 i1:10K p5000* s0 158 161 nc* 35 p5000* i2:10K s1 163 nc* 40 p5000* i3:10K tp19: s2 159 sequoia.nmi 173 .~rdy tp20: TP .wnr 149 Rhi .mnio .~rdy 150 Rh .hlda TP 152 Rh .dnc .~eads 156 sequoia.smi p5000* i5:10K sequoia.pc[4] Rh .sreset nc* .wnr nc* clocks.clk33m clko1 clocks.sequref i48:47R Rhr sequoia.pwrgood sequoia.rcrst isa.reset .~reset nc* 37 33 32 38 157 151 59 167 s5 165 55 56 34 65 67 39 sequoia.pBat 148 bc1:1uF gnd* Cvt3 bc2:0.1uF Cv a20m ads be [0..3] blast brdy cache dnc eads flush hitm hlda ken lock mnio nmi rdy smi smiact sreset stpclk wnr wbnwt clkin cpuclko1 cpuclko2 pwrgood rcrst rstcpu rstdrv spndrst vcccore1 vcccore2 bc3:0.1uF dramwe ma0a ma0b ma [1..11] mden ca3a ca3b cwe [0..1] sramce tagd0 tagd7 tagwe css3 c32kin gpio [0..3] gpiob [0..1] pc [0..9] swtch lb vlb acpwr nc* 93 bads i23:10K ma0a ma0b ma 121 120 [] bdev 127 128 [1] [0] 174 144 s6 i27:100K s7 i28:100K i25:100K 135 125 gnd* [] [] vl.adr 47 s8 i30:100K 122 s9 i31:100K 123 sa i32:100K 124 sb i33:100K gnd* irq8 kbcs kbrst master romcs bads bd [0..7] bdev bser fs1xclk 81 68 66 54 69 [] 82 83 80 ma0a i6:100K p5000* gnd* i55:4k7 160/176 package .~lrdy Rh Rhi ma[1] i7:100K gnd* not DLC processor gnd* reserved Rhi ma[2] i8:100K ma[3] i9:100K Rhi p5000* BD delay Rhi ma[4] i10:100K ma[5] i11:100K gnd* other CPU type gnd* reserved Rhi Rhi ma[6] i12:100K ma[7] i13:100K p5000* bads,bdev delay misc config gnd* misc config [2..0] = rev 4 Rhi ma[8] i14:100K Rhi ma[9] i15:100K p5000* misc config i16:100K ma[11] i17:100K ma0b i18:100K gnd* reserved gnd* internal RTC bads bd 144 [] bdev bser fs1xclk p5000* 143 141 146 142 171 [] i49:22R Rhi 166 sd 159 161 162 165 163 4 3 [] 41 160 172 se 140 119 [] 137 Rhi gnd* so Rh i50:33R Rhi i51:33R Rh clocks.vlbus2 [4] [4] 24 u5: [] y2 Am29F040 [6..9] 157 tp13: TP [4] y3 [] [10..13] [] [14..17] [0..18] adr [] [0..18] [4] oe1 oe2 oe3 oe4 y4 .sd[0..7] ce 22 ~romCs oe 24 .~memr [0..7] [4] we 31 .~memw .sa i38:0R BootROM: Pin out ok for rom/eprom/flash 128kx8, 256kx8, 512kx8 +5V flash may be programmed in system +12V flash may need adr[18] disconnected and the pin tied to p5000* (its Vpp) data [] [18] Rh isa Note: only loads on adr 18 are ROM and UMI0 PT86C718A2 bads bd [0..7] bdev bser fs1xclk bint brdy d [0..31] ferr hitm hlda hold ignne intr lgnt0 lreq0 local [0..2] lrdy nmi rdy deturbo rstdrv gpio [4..7] in14mhz cpuclk u6: aen bale dack [0..3] dtack [5..7] drq [0..3] drq2 [5..7] iochk iochrdy iocs16 ior iow irq1 irq [3..12] irqh [14..15] master memcs16 memr memw refresh sa0 sa1 sbhe sd [0..15] smemr smemw sysclk tc zws ided7 idebufen idecs [0..1] turbo 115 123 [] [] [] [] 117 118 124 51 sf i39:33R 50 sg i40:33R Rh Rh 94 [] [] 116 111 113 sh i41:33R 114 si i42:33R Rh Rh 121 108 109 110 [] 49 sj i43:33R 48 sk i44:33R sl i45:33R Rh Rh 122 Rh 84 120 74HCT244 .aen .bale .~dack[0..3] .~dack[5..7] .drq[0..3] .drq[5..7] .~iochk .iochrdy .~iocs16 .~ior .~iow .irq[1] .irq[3..12] .irq[14..15] .~master .~memcs16 .~memr .~memw .~refresh .sa[0] .sa[1] .~sbhe .sd .~smemr .~smemw .clk .tc .~zws HCT244i .sa[0] .sa[1] .sa[2] ~ideCs[0] ~ideCs[1] .bale .~iow .~ior 136 [] 126 2 6 8 11 13 15 17 gnd* 19 127 139 42 s8 nc* 12 9 5 3 isa.~ior [] a 19 g dir 1 [8] adr hcs 25 balel iow ior [] data 28 23 iochrdy 27 .iochrdy [0..2] [] b irq iocs16 reset 32 .irq[14] .~iocs16 1 ~ideres 31 [8..15] vl.~reset [8] ideData 74HCT245 HCT245i [0] [1] [2] [3] [4] [5] [6] ided7 2 a0 a1 a2 a3 a4 a5 a6 a7 3 4 5 6 7 8 9 1 18 b0 b1 b2 b3 b4 b5 b6 b7 17 16 15 14 13 12 11 [0] [1] [2] [3] [4] [5] [6] [7] Note: This IDE interface uses the ISA command pins directly therefore if TURBO mode is used (EIDE) other ISA peripherals may get confused. This should be tested and the restriction of only standard IDE modes may be imposed. g dir i52:33R sp Rh p5000* i47:33R Rh u8: .sd Rhi p5000* T3904 Rh [] [0..1] ideale ~idew ~ider 7 [] HCT245 .sd[8..15] 19 i53:1K idea ~hcs 74HCT245 isa.~ior i46:100K 14 IDEcon u7: ~ideBufEn ~ideCs nc* saEn 16 [0..15] sn saen spkr xddir [0] [1] [2] [0] [1] 18 y0 y1 y2 y3 y4 y5 y6 y7 a0 a1 a2 a3 a4 a5 a6 a7 g1 g2 4 1 135 clocks.vlbus1 Rh clko1 48 [] y1 Note: Bypass caps (0.1uF and 0.001uF each) for address buffer and bootROM from sheet 1 [2..5] SEQUOIA2 Rhi ma[10] 1 saEn p5000* sequoia.umics isa.~master ~romCs i37:20K gnd* Rh .~reset sequoia.smart[4..7] clocks.clk14m [] a1 a2 a3 [4] a4 [4] vl.adr[18] Rhi gnd* [] 25 TP u2: .~brdy .data See register 100H of Sequoia-1 TP gnd* tp12: isa.irq[8] i34:4K7 Rhi nc* sequoia.~ferr i36:100K p5000* Rh .hlda .hold nc* sequoia.intr .~lgnt0 .~lreq0 .~local .~lrdy sequoia.nmi .~rdy [] [4] Rhi [1] Rhi 70 Rh i29:4K7 [1] Rhi Rhi [] tp16: Rhr note inverted wrt others! i35:4K7 [2..5] [6..9] [10..13] [14..17] Rhi clocks.clk32k sequoia.smart[0..3] sequoia.gpiob sequoia.pc [] u4: 74FCT16244 FCT16244 5V part Rhi nc* nc* 57 Cv p5000* p5000* p5000* Rhi i26:100K Rhi 136 pwr Sqbypass (sheet 13) 9x0.1uF, 5x1uF, 4x10uF for Sequoia plus 3x0.1uF for IDE buffers p5000* nc* nc* cwe nc* [] p5000* Rhi nc* 92 p5000* Rhi i24:10K sp:TP The 'beep' speaker gizmo plugs in here TWOPIN i54:0.01uF sm Cv sequoia.pc[0] gnd* Title: Sequoia 6 of 16 By: Mark Hayter $Date: 1997/05/16 00:47:47 $ RCS $Revision: 1.37 $ Version: Rev 4 Systems Research Center Palo Alto, CA Configiuration links p5000* i73:4K7 p5000* i17:4K7 p5000* i18:4K7 pci.~gnt[0] pclk synchronous pci.~gnt[1] Select IRQ14,15 not req/gnt2 pci.~gnt[3] Select blast not hiaddr Rh Rh Rh u1: VT82C505 VL -- PCI vl Note: only use of these adr bits i69:4k7 clocks.vlbus1 .~ads .mnio .wnr .dnc .~be .adr .data .~local[2] .adr[28] Rh i70:4k7 .adr[29] Rh i71:4k7 gnd* .adr[30] Rh Note: pullups for unpopulated bridge i1:4K7 p5000* .~local[2] Rhi .~rdy .~rdy .~loc0or1 .~lreq0 .~lgnt0 .~blast .~brdy .~reset Note: lreq0 pullup for PCLK=CCLK i2:4K7 p5000* .~lreq0 Rhi p5000* i3:4K7 cclk ads mio wr dc be [0..3] ca [2..31] cd [0..31] ldevo lrdy rdyrtn ldevi lreqo lgnti blast brdy reset 1 2 3 4 [] [] [] 115 105 103 104 116 117 148 96 152 p0 Rh 149 nc* 101 wback eads 136 isa.~iochk 97 [5] [9..11] nc* [15] isa.irq iochk irq5 irq [9..11] irq14 irq15 143 [] 102 147 pclk frame ad [0..31] cbe [0..3] irdy trdy stop devsel par perr serr lock req0 req1 gnt0 gnt1 req3 gnt3 inta intb intc intd UMIPCI 151 46 [] [] 160 137 142 141 139 138 5 121 129 128 118 119 159 120 98 99 15 16 clocks.vlbus1 .~frame .ad .~cbe .~irdy .~trdy .~stop .~devsel .par .~perr vl.~boff .~lock .~req[0] .~req[1] .~gnt[0] .~gnt[1] .~req[3] .~gnt[3] .~inta .~intb .~intc .~intd p5000* .~frame .ad .~inta .~intb .~intc .~intd .~gnt[0] .~req[0] i50:2K7 Rhi .~irdy .~trdy .~stop .~devsel i51:2K7 Rhi i52:2K7 Rhi i53:2K7 Rhi i54:2K7 .~cbe clocks.vlbus1 .~frame .~irdy .~devsel .~lock i68:2K7 p5000* Rh i67:2K7 p5000* Rh .par Rhi .~perr .~serr .~lock .~req[0] .~req[1] .~req[3] i55:2K7 Rhi i56:2K7 Rhi i57:2K7 Rhi i58:2K7 Rhi i59:2K7 Rhr i60:2K7 Rhr .~inta .~intb .~intc .~intd i61:2K7 [] 17 117 217 18 118 218 [] 21 221 22 222 23 p1 223 p2 24 224 vl.~reset .ad[17] .~trdy .~stop .~perr .~serr Rhi i62:2K7 Rhi i63:2K7 Rhi i64:2K7 Rhi 25 225 26 226 27 227 ad [0..31] inta intb intc intd gnt req cbe [0..3] clk frame irdy devsel lock sdone sbo par rst idsel trdy stop perr serr Note: idsel comes from ad[17]. Don't care abput loading since there is only one UMI slot. Additional PCI devices could use ad[18..31] but then loading might become an issue. This selection makes the UMI slot be PCI config device 6 Note: Only config type 0 cycles supported by VIA chip, so no bridges on the UMI pci These are two holes for standoffs to fix the umi cards. Basically 0.153 hole with min .180 clearance UMIISA nc* p5000* .sa vl.adr[19..25] sequoia.umics i72:4K7 Rhi isa gnd* i21:100K .irq[1] Rh gnd* i4:10K gnd* i5:10K .drq[0] gnd* i22:100K gnd* i23:100K Rh gnd* i6:10K gnd* i7:10K .drq[1] .drq[2] gnd* i24:100K gnd* i25:100K .drq[3] i9:10K gnd* i10:10K .irq[6] i36: Rh .drq[5] gnd* Rh gnd* .irq[5] Rh Rh i8:10K .irq[4] Rh Rh gnd* .irq[3] Rh Rh i26:100K .drq[6] gnd* i27:100K .drq[7] gnd* i28:100K Rh .irq[9] i29:100K .~ior gnd* Rh i12:10K i13:10K .~iow gnd* i14:10K .irq[12] i31:100K .irq[14] Rh .~memr gnd* Rh p5000* i30:100K Rh Rh p5000* i32:100K .irq[15] Rh .~memw Rh p5000* i40:330R .~refresh Rh p5000* i41:330R .~iocs16 Rh p5000* i16:4K7 .~iochk Rh p5000* i15:1K Rh out .sd[0..7] i37: .irq[11] Rh p5000* in .irq[10] Rh gnd* i11:10K p5000* Rh Rh p5000* R8x10K .irq[7] Rh .iochrdy p5000* i42:330R .~zws Rh p5000* i43:330R .~master Rh p5000* i44:330R Rh .~memcs16 mnt1: Hole153 Note: 3 pairs of bypass caps from sheet 5 R8x10Ka p5000* in out .sd[8..15] .aen .bale .reset .~dack[3] .~dack[5] .~dack[6] .drq[3] .drq[5] .drq[6] .~iochk .iochrdy .~iocs16 .~ior .~iow .tc .clk .~zws .~memr .~memw .~memcs16 .~refresh .~sbhe .~smemr .~smemw .sd .irq[10] .irq[11] .irq[12] .~master [] [] 211 12 112 212 13 113 213 14 114 214 15 115 215 16 216 17 117 217 18 218 19 119 219 20 220 [] 122 124 126 118 sa [0..18] sah [19..25] upcs aen bale reset dacka dackb dackc drqa drqb drqc iochk iochrdy iocs16 ior iow tc clk zws memr memw memcs16 refresh sbhe smemr smemw sd [0..15] irqa irqb irqc master nc* mnt2: Hole153 Note: umics may be useful for upper address bit decoding Note: address lines 19..25 are not used on internal isa nor by most networking chips, so they come unbuffered from the vl bus Title: Pci and Umis 7 of 16 By: Mark Hayter $Date: 1997/05/13 18:11:02 $ RCS $Revision: 1.30 $ Version: Rev 4 Systems Research Center Palo Alto, CA p5000* i15:4K7 Rvi i16:4K7 Rvi Filter Note: National recommend six 0.1uF bypass caps ~md ~mdata u1: PC87307 Note:Internal 30k pulldown ser1t.out .sa[0..15] [] .aen 30 .sd[0..7] [] .~dack[0..3][] .drq[0..3] [] .iochrdy 32 .irq[1] 36 .irq[3..12] [] FDC,KBC,RTC inactive ser2t.dtr No X bus i1:10K ser2t.rts p5000* Rhi i2:10K ser2t.out Clock source 32.768kHz p5000* Rhi sequoia.~ferr 48 ser1t.dtr i3:10K ser1t.rts .irq[15] .reset .~ior .tc .~iow .~zws PnP Motherboard, config @015Ch p5000* Rhi i4:10K ir.irsl2 p5000* not NSC test Rhi nc* nc* nc* nc* nc* nc* p5000* pwr IObypass (sheet14) 12x0.1uF Note: Six of these go to sheet 9 35 34 31 99 92 97 95 91 96 89 93 98 nc* 68 71 72 [] [] 67 159 69 66 i6: vBat 33 84 s0 Rh 51 90 nc* nc* nc* gpio1 gpio2 nc* nc* i5:10K 49 94 nc* nc* nc* nc* nc* nc* p5000* s5 64 DBAS16 p5000* ~softres s6 Rh i9:10K gnd* s7 i7: i8:1K s8 clocks.clk32k nc* i39: sequoia.pwrgood DBAS16i u2:93C46hostid i36:10K 65 156 DBAS16 Rh p5000* u3:93C86 microwire SerROM EEPROM dualMDIN6 DualMD6 isa microwire SerROM EEPROM 50 62 63 adr [0..15] aen data [0..7] dack [0..3] drq [0..3] iochrdy irq1 irq [3..12] irq14 irq15 mr rd tc wr zws densel dir drate0 dskcng hdsel index rdata step trk0 wdata wgate wp cs0 cs1 cs2 gpio1 [0..6] gpio2 [3..7] onctl por ring switch vbat vcch wdo x1 x1c x2c mdat mclk kbdat kbclk p12 p16 p17 p20 p21 105 ~mclk 104 Lower ~mc 1 103 102 nc* nc* nc* nc* nc* 106 107 108 109 110 nc* gnd* TS 2 3 4 5 p5000* nc* i17:4K7 6 i18:4K7 Upper ir irrx2id0 irrx1 irtx irsl0id2 irsl1id1 irsl2 id3 79 gpio20 157 80 81 158 78 77 70 cts2 dcd2 dsr2 dtr2 ri2 rts2 sin2 sout2 141 cts1 dcd1 dsr1 dtr1 ri1 rts1 sin1 sout1 131 142 143 144 145 146 147 148 132 133 134 135 136 137 138 l1 l2 l3 l4 l5 l6 .id0 .rx1 .tx .id2 .id1 .irsl2 .id3 Rvi 11 Rvi nc* gnd* ~kd ~kdata 12 13 14 15 nc* ~kc ~kclock i35:10K ser1shdn ser2t .cts .dcd .dsr .dtr .ri .rts .in .out ser1t .cts .dcd .dsr .dtr .ri .rts .in .out 16 u1 u2 u3 u4 u5 u6 p5000* Rhi p5000* xp Fb25 mkpwr PTC i19:1000pF Cv gnd* p5000* i20:4K7 PPORT Parallel i30:680pF ppack Rhi i21:4K7 Chi i31:330pF ppafd Rhi ack afd_dsrtb astrb busy err init pd [0..7] pe slct stb 113 s1 i10:33R Rhr 119 s2 i11:33R Rhi 118 111 s3 i12:33R Rhr 116 117 [] ppdx i13: 8 R8x33 115 114 112 Rv s4 i14:33R Rh ppack ppafd ppspr ppbusy pperr ppinit ppd pppe ppslct ppstb 10 14 17 11 15 16 [] 12 13 1 i22:4K7 ack afd selectpr busy err init data [0..7] paper select strobe Chi ppspr Rhi i23:4K7 i32:680pF ppbusy Rhi i24:4K7 Chi pperr Rhi i25:4K7 ppinit Rhi 8 i26: ppd R8x4k7 i27:4K7 i33: 8 C8x330 pppe Rhi i28:4K7 ppslct Rhi i29:4K7 ppstb i34:330pF Rhi Chi gpio1[0] gpio1[1] gpio1[2] gpio1[3] 1 4 3 2 i38:10K Rvi gpio1[4] gpio1[1] gpio1[2] gpio1[3] cs do di clk Note: hostid is pre-programmed with a Digital UID for the network interface 1 4 3 2 cs do di clk gnd* i37:10K Note: this 16kbit eeprom is nonvolatile storage for the firmware to keep settings, it is partitioned by Digital, NCI and FirmWorks Rvi gnd* Title: SuperIO 8 of 16 By: Mark Hayter $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.28 $ Version: Rev 4 Systems Research Center Palo Alto, CA MAX211 v1p 12 c1p Note: Either the link wire or board mounting LED may be used u4: u1: i23:'330R' ACT05 vp p5000* Rhi gnd* vp 13 Ledlnk sequoia.pc[5] i3:'0.1uF' 1 Note: pc[5] and pc[6] can be programmed to flash leds i24:'330R' l0 2 Rhi i1:'0.1uF' Cv v1m v2p 14 15 ser1t Cv sequoia.pc[6] 16 c2m vm gnd* 7 t1i t2i t3i t4i t1o t2o t3o t40 6 20 21 8 5 26 22 19 gnd* l1 4 gnd* gnd* i29:'5mm,yellow' LED 17 vm 2 nc* sequoia.pc[7] Cv 1 28 7 3 24 r1o r1i r2o r2i r3o r3i r4o r4i r5o r5i shdn en ser1r.in ser1r.cts ser1r.dcd ser1r.ri ser1r.dsr ser1shdn 9 4 27 23 18 25 8 1 9 6 yl LED 9 i26:'330R' l3 8 gl Rh sequoia.pc[9] gnd* 5 rxd cts dcd ri dsr 2 l2 6 Note: These two leds are only populated on debug or development boards i30:'5mm,green' dtr rts txd 4 i25:'330R' Rh sequoia.pc[8] ser1r.dtr ser1r.rts ser1r.out 3 5 RS232 9pin D gnd .in .cts .dcd .ri .dsr 3 i5:'0.1uF' v2m .dtr .rts .out BILED i4:'0.1uF' c1m c2p i2:'0.1uF' Cv p5000* Cv 11 sequoia.gpiob[1] sequoia.scl 10 13 Note: these are not really sequoia signals but open collector versions at 3.3V they are used to make the I2C for SDRAM type detect sequoia.sda 12 The IR from the SuperIO supports IRDA and Consumer IR Only 38kHz consumer IR is provided here TX frequency is set by software, but receiver module is tuned ir p5000* i15:'4K7' .id0 Rhr .id1 i16:'4K7' .id2 i17:'4K7' .id3 i18:'4K7' Id links for CIR only, don't do plug'n'play stage 2 Rhr Rhr gnd* Rhr p5000* i19:'15K' Rhi .rx1 3 p5000* i20:'330R' virtx 2 Rhi Smartcard interface uses Sequoia GPIO bits [0..7] Smart[0..3] always inputs on reset, [4..7] may be parity 0 - high to power card 2 - card data in 1 - high to reset card 3 - card detect in (low if card) 4 - clock for card 5 - data for card 1 p5000* 7 0 0 1 1 6 0 1 0 1 data, clock o/c 3.579MHz clock, gpio data gpio clock, gpio data 3.579MHz clock, uart out vs vg TFMS5380 Sharp ir options are IS1U60 rx module (38kHz) and GL560 or GL561 IRled. Note that packages differ! T2907A i8:'10K' Other rx module options are TMFS5nn0 For nn = 30, 33, 36, 37, 38, 40, 56 as the center frequency in kHz c3 i21:4.7uF Rh u3: ACT05 Cva4 gnd* gnd* i32:'10K' sequoia.smart[0] 1 2 Rh c4 i31:'470R' p5000* Rh ir1: Note: Use 3.579 MHz clock (cpu core clock) here It is in the required 1MHz - 5MHz range u2: sequoia.smart[1] 74F153 3 TSIP5201 smvcc 4 F153 gnd* 6 clocks.clk3m 5 sequoia.smart[4] 4 3 i0a i1a ya i2a i3a ea irir 5 c0 7 gnd* 11 13 sequoia.smart[6..7] i0b i1b yb i2b i3b eb 1 ~cardIns 9 11 10 15 c2 i6:'4K7' 13 Rh sel [2] p5000* 12 i7:'4K7' smin irdr Note: TSSP4400 are similar with light output on side Alternatively put the IR LEDs in right angle mounts Rhr i13:'4K7' 8 i22:'14R' ISO7816 Rh 9 p5000* [] TSIP5201 SMRTPINS Rh Rh 10 12 ser2t.out 6 i12:'4K7' c1 sequoia.smart[5] Note: Nat Semi IR front end reference suggests use of two IR LEDs. ir2: i11:'4K7' 1 smrst smclk nc* gnd* nc* smio nc* 3 5 7 2 4 6 8 c1vcc c2rst c3clk c4rsvd1 c5gnd c6vpp c7io c8rsvd2 ird i27:'14R' Rhi 4 2 MMF T2N02 ELT1 .tx This hole sits between the IR LEDs to allow a cable to be used to bezel mounted LEDs in place of pcb mounted ones gnd* Onehole 1 3 gnd* Rh i9:'0R' smin ser2t.in p5000* slot i14:'4K7' gnd* Rh 9 Rh 10 i10:'0R' Rh sequoia.smart[2] sequoia.gpiob[0] i33:'470R' Rh Note: This is a rev 3 change gpiob[0] is Wake0 and can trigger a FIQ both on card insert and card removal carddet1 carddet2 These holes are for supports for the smartcard reader when a bare board is used sm0: nc* Hole125 nc* sm1: Hole125 Title: Serial I/O 9 of 16 By: Mark Hayter $Date: 1997/05/12 00:28:29 $ RCS $Revision: 1.29 $ Version: Rev 4 Systems Research Center Palo Alto, CA Note: four 0.1uF bypass capacitors (as suggested by ESS) shown on sheet 11 The audio is designed to use either the ES888 or ES1887 codec The main difference is that the 1887 includes FM synth, it is also more expensive (about $3 more) The 1887 is also slightly more configurable Software for the 888 should work with the 1887 apart from a few lines of setup code (and the lack of synth) GamePort .reset .~ior .~iow .sa[0..11] .aen .sd[0..7] .sd[8..15] 78 72 73 [] 9 [] [] reset iorb iowb adr [0..11] aen datal [0..7] datah [8..15] nc* clocks.clk14m Note: Use xtal here if the clk14m is not accurate enough .irq[9] .irq[5] .irq[7] .irq[10] .irq[15] p5000* i1:1K 77 70 69 68 67 65 66 63 64 61 62 59 60 amode gnd* Rh 76 71 .drq[0] .~dack[0] .drq[1] .~dack[1] .drq[3] .~dack[3] .drq[5] .~dack[5] 22 52 nc* nc* nc* 19 20 21 i2: p5000* avcc 41 irqa irqb irqc irqd irqe vdda1 55 i11:2K2 mi mo miout moout Rhr i12:2K2 15 12 Rh p5000* i14:2K2 i15:2K2 i13: i16:2K2 i17:2K2 pg pGame Fb25 PTC 1 i18:150pF 8 9 Cv Rvi ta tb tc td drqa dackba drqb dackbb fmcsb drqc dackbc frmstb fs drqd dclk dackbd dr dx amode fmsel pcspki voldn volup mute 56 32 31 30 29 28 27 26 25 Rvi 2 7 10 14 i19:0.01uF i20:0.01uF Cv Cv ta tb tc td gnd* i21:0.01uF i22:0.01uF Cv Cv i23:2K2 Rhi i24:2K2 Rhi i25:2K2 Rhi i26:2K2 i27:1M i29:1M i31:1M i28:0.01uF Rvi 18 Cv Cv i32:0.01uF Rvi x1 y1 x2 y2 3 6 11 13 Rvi 81 82 83 86 5 Cv 4 gnd* nc* nc* nc* nc* nc* fmsel 80 Note: Slight difference between 888 and 1887 for the DSP serial port. This arrangement should be fine for not using the port i35:4K7 gnd* The frmsrb out from the 888 becomes fsr in on the 1887 The fs in on the 888 becomes fsx in on the 1887 For using the port on both chips these would have to be linked in the 1887 case and not in the 888 case. For never using leave unlinked and rely on the internal pulldowns gpo0 gpo1 54 nc* nc* 85 nc* nc* 53 44 gnd1 gnd2 Right Jack Below this line is the analog power/ground domain nc* nc* i36:0.1uF vref x1 y1 x2 y2 15 pin (2 row) female D over three 3.5mm jacks Rhr 84 sw1 sw2 sw3 sw4 i34:0.01uF Cv nc* 79 pwr1 pwr2 pwr3 i33:1M i30:0.01uF Rvi midii midio Rvi Rhi msd mclk vref Rvi sa sb sc sd Fb25 302 310 rsig3 rsw3 Ch agnd i3:10uF i4:0.1uF Cva4 Cv i53:0.22uF i54:0.22uF Ch Ch i0 46 i1 47 i2 37 i3 38 Ch auxl auxr foutl 33 Ch Ch i5 36 35 fdxo cinl 42 cil foutr 34 fr mic 39 cinr 43 pcspko aoutr mic 50 Rhr i39:0.22uF 45 40 agnd i41:10uF i42:0.1uF Cva4 Cv rl nc* 202 210 rsig2 rsw2 nc* 49 i52:0.22uF aoutl com3 Center Jack cir cmr rl 48 3+ p1 vcc 8 i44:10K o1 aord Rh cmr gnda 301 lsig3 lsw3 Mono mike input avcc aor Rhr 311 i40:1000pF Ch cmr 303 Ch i51:0.22uF Ch avcc miin Note: output amp is directly (not cap) coupled since vref/cmr is used as the reference Ch fdxi Ch i5:0.1uF i7:7K5 i38:1000pF Ch i57:0.22uF i58:0.22uF agnd i6:7K5 fl i37:0.22uF Ch i4 miin linel liner i55:0.22uF i56:0.22uF Note: rev 4 change tie off unused inputs Mike input is on combo connector on right of this page msi mso swa swb swc swd xo xi Below this line is the analog power/ground domain Note: Care with layout Need single connection point for agnd to gnd AudioGm :'ES888 or ES1887' ES888 isa 2 - i45:8K6 ll 1 ramp i43:330uF ll nc* 203 211 lsig2 lsw2 Stereo line output Cha8 m1 agnd 201 com2 102 rsig1 rsw1 Rhi Ch avccm aol SSM2135 i46:10K Left Jack i47:8K6 Rh Rhi i8:10uF i9:47uF i10:0.1uF Cva4 Cva6 Cv 5 + p2 6 - m2 o2 aold cmr Had 10uF here agnd 7 lamp i48:330uF ro nc* 110 Cha8 lo nc* vee 4 103 111 i50:0.1uF lsig1 lsw1 Stereo headphone output Cv 101 Title: Audio 10 of 16 By: Mark Hayter $Date: 1997/05/17 00:51:49 $ RCS $Revision: 1.32 $ Version: Rev 4 com1 Systems Research Center Palo Alto, CA p5000* u1: l1:5mm,green l2:5mm,yellow LED LED CS8900 isa .sa [] vl.adr[19] 60 .sd [] addr a19 data [0..18] [0..15] sequoia.pc[2] .reset .aen .~memr .~memw .~memcs16 .~refresh .~ior .~iow .~iocs16 .iochrdy .~sbhe 7 75 63 29 28 34 49 61 62 33 64 36 .irq[10] .irq[11] .irq[12] .irq[5] .drq[5] .drq[6] .drq[7] .~dack[5] .~dack[6] .~dack[7] 32 31 30 35 15 13 11 16 14 12 chipsel reset aen memr memw memcs16 refresh ior iow iocs16 iochrdy sbhe lanled linkled bstatus lanled linkled 100 99 78 nc* test res sleep csout elcs 76 nc* eecs eedo eedi eesk 3 irq0 irq1 irq2 irq3 dmarq0 dmarq1 dmarq2 dmack0 dmack1 dmack2 93 77 17 2 5 6 4 x1 x2 97 dop dom dip dim cip cim 83 79 80 81 82 Rh r6:680R lgrn lyel Rh res nc* nc* nc* gnd* r1:4K99 Rhr u2:93C46 microwire SerROM EEPROM cs do di sk 1 4 3 2 The serial eeprom is not populated on the DIGITAL reference design it is shown here for reference only (for example a umi manufacturer may use it) cs do di clk x1 x2 98 84 r5:680R x1:20MHz nc* nc* nc* nc* nc* nc* XTAL2 Xfmrt for 10BaseT Rhi rdm rdp tdm tdp 1:1 rdm rdc rdp 92 91 88 RJ45 for 10BaseT r2:100R tum 1 2 3 rom roc rop 16 rm 6 rip 14 rp 3 rp tom 11 tm 2 tm top 9 tp 1 tp rim rm r3:24R3 87 Rh 1:1.4 c1:68pF tup tdm tdc tdp Cv r4:24R3 6 7 8 Rh tim tic tip c2:0.1uF c3:0.1uF c4:1000pF, 1KV c5:1000pF, 1KV Cv Cv Cvhv Cvhv gnd* Four digital, three analog recomended by Crystal One for serial eeprom, four for audio (sheet 10) p5000* pwr IObypass R2, R3, and R4 are setup for 100 ohm twisted pair. Other values are possible. See CS8900 data sheet, page 123. Note: Changed these caps from 10n to 1n (sheet14) 12x0.1uF Title: Ethernet 11 of 16 By: Hal Murray $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.16 $ Version: Rev 4 Systems Research Center Palo Alto, CA tp22: i26: TP LT1086 p3300* vin i20:'22uF' p2000* vout i23:'121R' adj Cva5 p2000* i22:'22uF' Rv gnd* c11:'0.1uF' c12:'0.1uF' c13:'0.1uF' c14:'0.1uF' c15:'0.1uF' c16:'0.1uF' Cv Cv Cv Cv Cv Cv c01:'1000pF' c02:'1000pF' c03:'1000pF' c04:'1000pF' c05:'1000pF' c06:'1000pF' Cv Cv Cv Cv Cv Cv Cvt6 va2 gnd* gnd* i24:'71R5' p2000* i21:'22uF' Rvi Cva5 gnd* gnd* p5000* i1:'51K' tp21: i36: TP LT1086 p5000* vin Rv T2907A p3300* vout b1 i2:'1K' b2 Rh i10:'22K' i30:'22uF' i33:'121R' adj Cva5 b0 i32:'22uF' Cvt6 Rv T3904 pBat i8:'10K' Rh Rv gnd* va3 pwrgood gnd* i3:'1K' DBAV70 i34:'100R' i11:'10uF' rp1:'TP' i4:'20K' Rv i31:'22uF' Cva4 i7:'BR2032/Keystone 1061' b3 TWOPIN r3 i35:'100R' i5:'0.1uF' i6:'4700pF' Cv Cv rp2:'TP' + Bat Rvi Cva5 rcRst vBat Rv i9:'10uF' TWOPIN Cva4 gnd* Rvi Note: Battery is 3V Li coin cell BR2032 in a smt holder gnd* IDEpwr PwrJack inner p5000* 1 1 2 outer gnd* 2 3 p12000 plugp 3 nc* 4 p5 gnd1 gnd2 p12 nc* gnd* Note: These are the mounting holes, with the two near the connectors grounded they have a .220 diameter pad with a .125 fhs plated hole h0: h3: h6: nc* nc* Hole125 Hole125 Hole125 h1: nc* Hole125 gnd* h2: Hole125 h4: nc* Hole125 nc* h5: Hole125 h7: Hole125 nc* h8: Hole125 12 of 16 Title: Power By: Mark Hayter $Date: 1997/05/14 03:07:47 $ RCS $Revision: 1.28 $ Version: Rev 4 Systems Research Center Palo Alto, CA Note: Sequoia1 gets 0.1uF + 1uF for each of the five power groups plus 1uF extra Note: Sequoia2 gets 0.1uF + 10uF for each of the four power groups pwr c11:'0.1uF' c12:'0.1uF' c13:'0.1uF' c14:'0.1uF' c15:'0.1uF' c16:'0.1uF' c17:'0.1uF' c18:'0.1uF' c19:'0.1uF' Cv Cv Cv Cv Cv Cv Cv Cv Cv c21:'1uF' c22:'1uF' c23:'1uF' c24:'1uF' c25:'1uF' c26:'1uF' Cvt3 Cvt3 Cvt3 Cvt3 Cvt3 Cvt3 c31:'10uF' c32:'10uF' c33:'10uF' c34:'10uF' Cva4 Cva4 Cva4 Cva4 gnd* pwr gnd* pwr gnd* Note: Three 0.1uF for the IDE buffers pwr c41:'0.1uF' c42:'0.1uF' c43:'0.1uF' Cv Cv Cv gnd* Title: Sequoia bypass 13 of 16 By: Mark Hayter $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.8 $ Version: Rev 4 Systems Research Center Palo Alto, CA pwr c:'22uF' Cva5 gnd* pwr c11:'0.1uF' c12:'0.1uF' c13:'0.1uF' c14:'0.1uF' c15:'0.1uF' c16:'0.1uF' Cv Cv Cv Cv Cv Cv c17:'0.1uF' c18:'0.1uF' c19:'0.1uF' c20:'0.1uF' c21:'0.1uF' c22:'0.1uF' Cv Cv Cv Cv Cv Cv gnd* pwr gnd* Title: I/O bypass 14 of 16 By: Mark Hayter $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.8 $ Version: Rev 4 Systems Research Center Palo Alto, CA pwr c:'22uF' Cva5 gnd* pwr c11:'0.1uF' c12:'0.1uF' c13:'0.1uF' c14:'0.1uF' c15:'0.1uF' Cv Cv Cv Cv Cv c01:'1000pF' c02:'1000pF' c03:'1000pF' c04:'1000pF' c05:'1000pF' Cv Cv Cv Cv Cv gnd* pwr gnd* Title: Bypass (5) 15 of 16 By: Hal Murray $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.8 $ Version: Rev 4 Systems Research Center Palo Alto, CA pwr c:'22uF' Cva5 gnd* pwr c11:'0.1uF' c12:'0.1uF' c13:'0.1uF' c14:'0.1uF' c15:'0.1uF' c16:'0.1uF' c17:'0.1uF' c18:'0.1uF' c19:'0.1uF' c20:'0.1uF' Cv Cv Cv Cv Cv Cv Cv Cv Cv Cv c01:'1000pF' c02:'1000pF' c03:'1000pF' c04:'1000pF' c05:'1000pF' c06:'1000pF' c07:'1000pF' c08:'1000pF' c09:'1000pF' c10:'1000pF' Cv Cv Cv Cv Cv Cv Cv Cv Cv Cv gnd* pwr gnd* Title: Bypass (10) 16 of 16 By: Hal Murray $Date: 1997/04/30 09:20:59 $ RCS $Revision: 1.10 $ Version: Rev 4 Systems Research Center Palo Alto, CA