F65550B - Digital Systems Research Center

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

Mark Hayter

RCS $Revision: 1.19 $

Version: Rev 4

clocks

sdctl

vl clocks

sequoia

tvsequoia

clocks

sequoia

clocks

isa

ser1t

ser2t

ir

sequoia

sdctl

cpu

romcard

sequoia

tv

sequoia

clocks

vl

sheet 3, Video controller, VGA and LCD outputs

VIDEO

SDRAM

sheet 2, sdram and address and data buffers

cpu

sdctl

clocks

sequoia

vBat

sequoia.rcrst

sequoia.pBat

sequoia.pwrgood

clocks

sheet 6, SEQUOIA core logic, boot rom and IDE interface

isa

sequoia

vl

SEQUOIA

clocks

clocks isa

AUDIO

sheet 10, audio (mike in, headphone out) and gameport

CLOCKS

sheet 5, clock generation and ROM card interface

romcard

sequoia clocks

vl

PCIUMI

sheet 7, PCI bridge, UMI1 and UMI0

vl

sequoia

clocks

isa

ser1shdn

sequoia

ir

ser2t

ser1t

sheet 9, RS232 interface and IR interface

SERIAL

clocksclocks

vBat

ser1shdn

SUPERIO

sheet 8, super I/O, keyboard/mouse and parallel ports

ser1t

ser2t

ir

sequoia

isa clocks

isa

Sheet 12, power supply and backup battery

Makes p5000*, p3300* and p2000*

rcRst

vBat

pBat

POWER

pwrgood

sheet 11, Ethernet

sequoia

vl

Ether

isa

vl

sequoia

Sheets 13 to 16 show the bypass capacitors and

are included as required by the other sheets

clocks

sequoia

TVOUT

sheet 4, TV output encoder and filter

tv

sequoia

clocks

ser1shdn

isa

sdctl

clocks

romcard vl

cpu

sequoia

CPUPAL

sheet 1, CPU, PAL and 3.3V to 5V buffers isa

NC Reference Design

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/05/16 23:22:15 $ 

Mark Hayter

RCS $Revision: 1.36 $

Version: Rev 4

cpu/pal 1 of 16

[0..7]

[8..15]

[16..23]

[24..31]

vl.data

~sysDen

sysDdir

~sysDen

sysDdir

cpu.d[0..7]

cpu.d[8..15]

cpu.d[16..23]

cpu.d[24..31]

~sysAen

cpu.a[2..9]

cpu.a[10..17]

cpu.a[18..21]

cpu.~be

[2..9]

[10..17]

[18..21]

vl.adr

vl.~be

cpu.a[30]

cpu.a[29]

.~be

.d

.a

nc*

~rw

~mreq

cpu

nwait

nwait .maA

.maB

.muxsel

.~rasA

.~rasB

.~casA

.~casB

.~weB

.~weA

.~cs

Rh

.~ads

.~brdy

.~rdy

.~blast

.~local[0]

.adr[31]

.adr[27]

sysDdir

~sysDen

dbe

dbe [2..4]

[10..12]

.a

~sysAen

.~rdoeba

.rdoeab

sdctl

vl

romcard.wp

.hold

.hlda

vl

LVC04

12

34

56

98

11 10

13 12

vl.hlda abe

vl.sreset ~res

Note: LVC04 is ok with 5V inputs

~res

~fiq

~irq

~irqsequoia.intr

~fiq

gnd*

nc*

gnd*

p3300*

nc*

abe

c0

c1

c2

c3

Rh

c0

c1

c2

c3

Selectively populate res high or low to set core speed

bootmd high on reset

abe

Note: dir is high for a->b

nc*

~rw

sequoia.smi

Rh

p5000*

Note: expected use is smi causes FIQ

pc[4] configured as gpcs3 used to

clocks.cpumclk

nc*

abt

abt gnd*

p3300*

clocks.nmclk

clocks.vlcopy

fiq

i2:1K

i3:1K

i4:1K

i7:1K

i8:1K

i9:1K

i10:1Ki6:1K

i5:1K

i11:1K

i15:33R

i16:33R

i17:33R

i18:33R

i19:33R

i20:33R

u0:

u1:

u2:

u3: u4:

u5:

u6:

u7:

uA

uB

gnd*

Note: If the pulldowns on nwait and dbe

are removed the CPU input pads will

be driven past maximum Vih

i22:1K

p5000*

gnd*

p5000*

ACT00

11

8

6

3

13

12

10

9

5

4

2

1

Rh clocks.clk14m

14.31818MHz

i23:33R

p5000*

clocks.forcpu cclk

cclk

Keep cclk path short

or add terminator

romcard.~oe

romcard.~cs

vl.wnr

i21:1K

R6x33

[23..31]

2

1

43

OSC

outvcc

oe

gnd

nc*

Rhr

Rhi

p3300*

p5000*

b1:

b2:

Note:2 pairs used sheet 2

Note: 2 pairs used sheet 6

.~reset

romcard.~we

.dnc

.mnio

TP

tp2:

t1

TP

tp8:

Bypass

pwr

10 pairs of 0.1uF and 0.001uF

(sheet 16)

Bypass

pwr

10 pairs of 0.1uF and 0.001uF

(sheet 16)

TP

tp23:

TP

tp24:

[2..5]

tp25:

tp26:

[0..3]

[6..9]

tp27:

TP

cpu.a[27]

tp9:

Rhi

.~brdy

Rhi

p5000*

.~rdy

i12:4K7

i13:4K7

.adr[25]

t

TP4

[4]

[]

t

TP4

[4]

[]

t

TP4

[4]

[]

Rh clocks.clk14mb

i24:33R

f0

f2

f1

m0

m1

m2

m3

m4

m5

[26]cpu.a[26]

cpu.a[24]

cpu.a[23]

cpu.a[22]

[24]

[23]

[22]

nc*

cpu.a[27]

71

65

72

121

70

69

138

139

57

68

67

66

56

140

142

130

131

50

52

49

48

51

[]

[0..31]

[]

[0..3]

[]

[2..31]

144

143

141

127

36

122

61

60

62

58

59

124

123

128

SA110

clk

mclk

nmclk

seq

mreq

rw

clf

lock

abort

dbe

wait

reset

fiq

irq

adr

be

data

tms

tdo

tdi

tck

trst

testclk

tck_byp

sna

pwrslp

mse

mccfg0

mccfg1

mccfg2

config

cccfg0

cccfg1

cccfg2

cccfg3

ape

abe

spdf

resetout

24

1

25

48

3V3 or 5V

[]

[8]

[]

[8]

[]

[8]

[]

[8]

3V3 5V

74FCT164245

FT164245

b1

b2

a1

a2

oe1

oe2

dir1

dir2

24

1

25

48

3V3 or 5V

[]

[8]

[]

[8]

[]

[8]

[]

[8]

3V3 5V

74FCT164245

FT164245

b1

b2

a1

a2

oe1

oe2

dir1

dir2

24

1

25

48

3V3 or 5V

[]

[8]

[]

[8]

[]

[8]

[]

[8]

3V3 5V

74FCT164245

FT164245

b1

b2

a1

a2

oe1

oe2

dir1

dir2

24

1

25

48

3V3 or 5V

26

27

29

30

[]

[4]

37

38

40

41

[]

[4]

23

22

20

19

[]

[4]

12

11

9

8

[]

[4]

3V3 5V

74FCT164245

F164245h

b1

b14

b15

b16

b17

b2l

b24

b25

b26

b27

a1

a14

a15

a16

a17

a2l

a24

a25

a26

a27

oe1

oe2

dir1

dir2

sdctl.bootmd

.adr[23]

.adr[22]

TP

tp11:

TP

tp3:

uC

isa.~refresh

R8x33

flashwp

refresh

ba22

ba23

hlda

reset

hold

clk486

romcardwe

romcardoe

romcardcs

vlmnio

vldnc

ba25

ba27

ba31

memldev

blast

rdy

brdy

ads

test2

test1

bootmd

sysddir

sysden

sysaen

ahi

amid

alow

rw

mreq

mclk

cpudbe

rdoeba

rdoeab

cs

web

wea

casb

casa

rasb

rasa

muxsel

malob

maloa

wait

SharkPal

MACH231-6

3V3 world

24

[0..2]

[]

[0..2]

[]

38

28

27

68

66

7

6

[0..7]

[]

70

40

72

65

26

4

[2..4]

[]

[10..12]

[]

[23..31]

[]

either

16

15

17

25

82

52

5V world

9

50

45

49

8

48

46

51

39

69

19

10

18

81

33

13

67

30

23

83

35

clear FIQ

p5000* vl.~loc0or1

vl.~local[1]

vl.~local[0] lor

vl.~boff

Rhi

p5000* i25:1K

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

Mark Hayter

RCS $Revision: 1.23 $

Version: Rev 4

2 of 16

[0..15]

[16..31]

[0..15]

[16..31]

cpu.d[0..15]

sdctl.~rdoeba

sdctl.~weB

sdctl.~casB

sdctl.~rasB

sdctl.~cs[4]

sdctl.~cs[6]

sdctl.~weA

sdctl.~casA

sdctl.~rasA

sdctl.~cs[0]

sdctl.~cs[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

sdctl.maA

sdctl.maB

sdctl.muxsel

cpu.a[13]

cpu.a[14]

cpu.a[15]

cpu.a[16]

cpu.a[18]

cpu.a[19]

cpu.a[17]

cpu.a

[5]

[6]

[7]

[8]

[9]

[22]

[23]

Note: muxsel is high

for RAS, low for CAS

sdctl.muxsel

cpu.~be[0]

cpu.~be[1]

cpu.~be[2]

cpu.~be[3]

cpu.~be[0]

cpu.~be[1]

cpu.~be[2]

cpu.~be[3]

clocks.nmclk

dramData

[21] latA21 latA21

latA21

Note: this latch shuts

when the mux swings to

cas address

SDRAM

sequoia.sda p3300*

sequoia.scl

p3300*

gnd*

sequoia.sda

sequoia.scl

gnd*

latA22

latA23

latA22

latA23

latA22

latA23

Note: sda/scl is I2C made in software through sequoia

and open collector (5V world) buffers

gnd*

u1:

u2:

u3:

gnd*

u4:

u5:

u6:

i3:1K

i4:1K

i5:1K

gnd*

u7:

madr

clocks.sdramA

clocks.sdramB

gnd*

clocks.dbus clocks.dbus

gnd*

cpu.d[16..31]

gnd*

u8:

clocks.dbus clocks.dbus

gnd*

sdctl.rdoeab

Rh

i7:10K

Rh

i8:10K

gnd*

Rh

i9:10K

Rh

i10:10K

gnd*

sdctl.rdoeab

i11:10K

i12:10K gnd*

i13:10K gnd*

i14:10K

Rh

i15:33R

Rh

i16:33R

Rh

i17:33R

Rh

i18:33R

Rh

i19:33R

Rh

i20:33R

Rh

i21:33R

Rh

i22:33R

Rh

i23:33R

Rh

i24:33R

Rh

i25:33R

Rh

i26:33R

Rh

i27:33R

Rh

i28:33R

Rh

i29:33R

Rh

i30:33R ma10apcpu.a[20]

Rhr

Note: Gets two pairs of bypass caps from sheet 1

p3300* Bypass5

pwr

5 pairs of 0.1uF and 0.001uF

(sheet 15)

i31:10K

Rhr

i32:10K

Rhr

i33:10K

Rhr

i34:10K

Rhr

i35:10K

Rhr

i36:10K

Rhr

i37:10K

Rhr

i38:10K

Rhr

p3300*

Note: bootmd is

high (outputs disabled) on reset

latA9

latA8

latA7

latA6

latA5

p3300*

m3

m4

m5

m6

m7

m8

m9

m10

b0

b1

b2

b3

b4

b5

b6

b7

sdbeB[3]

sdbeA[3]

sdbeB[2]

sdbeA[2]

sdbeB[1]

sdbeA[1]

sdbeB[0]

sdbeA[0]

sdbeB

[0]

[1]

[0]

[1]

[2]

[3]

[2]

[3]

sdbeA

[0]

[1]

[0]

[1]

[2]

[3]

[2]

[3]

Note: the slightly perverse assignment of the 32 data bits to the 64 sdram bits

results from the way CS0 and CS2 are connected on the module

g0

g1

g2

g3

g4

g5

g6

g7

Rh

tiehi

11

9

8

7

6

5

4

3

2

1

12

13

14

15

16

17

18

19

3V3 part

74FCT3573

FCT3573i

o0

o1

o2

o3

o4

o5

o6

o7

oe

d0

d1

d2

d3

d4

d5

d6

d7

le

1

13

14

10

11

6

5

3

2

15

12

9

7

4

3V3 part

74LVC257

LVC257

za

zb

zc

zd

oe

a0

a1

b0

b1

c0

c1

d0

d1

s

1

13

14

10

11

6

5

3

2

15

12

9

7

4

3V3 part

74LVC257

LVC257

za

zb

zc

zd

oe

a0

a1

b0

b1

c0

c1

d0

d1

s

63

128

115

111

[]

[0..3]

39

122

129

45

114

30

27

132

126

123

38

[]

[3..9]

[]

[0..2]

167

166

165

83

82

131

130

113

112

47

46

29

28

[]

[16]

[]

[16]

[]

[16]

[]

[16]

SDDIMM

dll

dlh

dhl

dhh

dqmb0

dqmb1

dqmb2

dqmb3

dqmb4

dqmb5

dqmb6

dqmb7

sda

scl

sa0

sa1

sa2

malo

mami

ma10ap

ma11

ma12

ma13

we

s0

s1

s2

s3

ba0

ba1

ck

cas

ras

cke0

cke1

63

128

115

111

[]

[0..3]

39

122

129

45

114

30

27

132

126

123

38

[]

[3..9]

[]

[0..2]

167

166

165

83

82

131

130

113

112

47

46

29

28

[]

[16]

[]

[16]

[]

[16]

[]

[16]

SDDIMM

dll

dlh

dhl

dhh

dqmb0

dqmb1

dqmb2

dqmb3

dqmb4

dqmb5

dqmb6

dqmb7

sda

scl

sa0

sa1

sa2

malo

mami

ma10ap

ma11

ma12

ma13

we

s0

s1

s2

s3

ba0

ba1

ck

cas

ras

cke0

cke1

11

9

8

7

6

5

4

3

2

1

12

13

14

15

16

17

18

19

3V3 part

74FCT3574

FCT3574i

o0

o1

o2

o3

o4

o5

o6

o7

oe

d0

d1

d2

d3

d4

d5

d6

d7

cp

clkab

leab

oeab

clkba

leba

oeba

a17

a16

a

b17

b16

b

FT163501

74FCT163501

3V3 part

[16]

[]

33

31

[16]

[]

24

26

27

28

30

1

2

55

clkab

leab

oeab

clkba

leba

oeba

a17

a16

a

b17

b16

b

FT163501

74FCT163501

3V3 part

[16]

[]

33

31

[16]

[]

24

26

27

28

30

1

2

55

sdctl.bootmd

sdctl.~cs[1]

sdctl.~cs[3]

sdctl.~cs[5]

sdctl.~cs[7]

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/05/12 06:22:39 $ 

Mark Hayter

RCS $Revision: 1.27 $

Video

adra

datab

dataa

datab

nc*

casal

casah

oeab

casbl

casbh

adra

datab

dataa casal

casah

casbl

casbh

.~ads

.mnio

.wnr

.~rdy

.~local[1]

.~be

.adr[2..27]

.data

CvCv

Fb

Cv

Fb

Cv Cv gnd*

pVideo*

Cv Cv gnd* Note: for these power pins

care must be taken with

layout. C&T 65550 data

book section A.10 page A-4

[0] = high VL-bus

[2] = high 1x clock

[5] = low extclk 14.3MHz [5]

[6] = low A26,A27 [6]

[7] = high test disable

[8] = low IVcc = 3.3V

adra

[10] = low EDO

[11] = Panel ID0

[12] = Panel ID1

[13] = Panel ID2

[14] = Panel ID3

[15] = Sw defined

dataa

[2]

[3]

[4]

[5]

[6]

[7]

Rh

p5000*

nc*

[0..7]

[8..15]

adrc[0..7]

Link

enavdd

Note: The LCD section is for experimentation.

The RFI filters suggested by C&T are not fitted

The signals are simply brought out to a connector

Note: This connector has the same pinout

as the C&T development kit connector

nc*

Might want fuse

to +5V on VGA pwr

adrc

Version: Rev 4

3 of 16

vl

.~reset

u1:

u2:

u3:

u4:

i1:1K

i2:33R

i3:33R

i4:33R

i5:33R

i6:33R

i7:33R

i8:33R

i9:33R

i10:33R

i11:33R

i12:33R

i13:33R

i14:33R

u5:

pVideo*i15:10R

i16:0.1uF i17:47uF i18:0.1uF

i19:0.1uF i20:47uF i21:0.1uF

i22:10R

avcc

i22:1000pF

i23:1000pF

i24:560R i25a:37R5 i26a:37R5 i27a:37R5

i28:4.7uH

i29:22uF i30:0.1uF i31:0.047uF

gnd*

i32:4K7

i33:4K7

i34:4K7

i35:4K7

i36:4K7

i37:4K7

i38:4K7

i39:4K7

gnd*

i40:

i41:

i42:

i43:

i44:

i46: i48: i50:

Cv

i53:220pF

i51:220pF

11

12

4

15

5

10

8

7

6

3

2

1

14

13

9

VGAcon

pwr

hsync

vsync

red

green

blue

redrtn

grnrtn

bluertn

syncrtn

grnd

id3

id2

id1

id0

gnd*

hsout

vsout

rout

gout

bout

rasab0a

rasab0b

weaa

weab

rasab1a

rasab1b

weba

webb

plcd

shfclk

flm

lp

m

cvcc0

cvcc1

enavee

.vlbus2

.clk32k

.clk14m

clocks

i52:220pF

Induct

Cva5

Cva6

LcdPwr

1

2

3

5

8

7

10

11

13

[]

[0..7]

[]

[8..15]

[]

[8]

LCDcon

ptop

pmid

plow

shfclk

flm

lp

m

de

enabkl

veesafe

v12000safe

vddsafe

DBAV99DBAV99DBAV99

Rhr

Rhi

p5000* (sheet 16)

10 pairs of 0.1uF and 0.001uF

pwr Bypass

Rh

i54:100K

TP .~local[1]

tp10:

Note: care must be taken with placing these caps

Note: i24, the 560R res on rset must be 1% or better

i25, i26 and i27 pulldowns must be 2% or better

Tried using sequoia.pc[3] for

standby, but chip must be out

of standby during reset or it

does not configure

p5000*

[]

[0..8]

[]

[0..15]

27

13

28

29

14

Dram512kx8

MT16C257

ras

casl

cash

we

oe

data

adr

[]

[0..8]

[]

[0..15]

27

13

28

29

14

Dram512kx8

MT16C257

ras

casl

cash

we

oe

data

adr

[]

[0..8]

[]

[0..15]

27

13

28

29

14

Dram512kx8

MT16C257

ras

casl

cash

we

oe

data

adr

[]

[0..8]

[]

[0..15]

27

13

28

29

14

Dram512kx8

MT16C257

ras

casl

cash

we

oe

data

adr

c0

c1

m0

m1

m2

m3

m4

m5

m6

m7

m8

rs

bo

go

ro

tv.b

Rvi

i25b:37R5

tv.g

Rvi

i26b:37R5

tv.r

Rvi

i27b:37R5 gnd*

Note: If no TV out is needed a and b can

be replaced with a 75R for each of i25-27

Rv Rv Rv

de

tv.h

tv.v

enbk

eeok

v12ok

vddok

181

80

108

142

158

66

42

9

59

56

[]

[0..15]

[]

[0..15]

100

102

103

104

101

[]

[0..8]

124

123

125

126

155

157

159

160

156

[]

[0..8]

99

178

203

154

27

[]

[0..31]

[]

[2..27]

[]

[0..3]

25

24

23

11

31

22

207

55

57

58

60

64

65

208

206

202

205

61

62

69

68

67

70

[]

[0..15]

(VL-bus)

Chips F65550B

CT65550

p

shfclk

flm

lp

m

enavdd

enavee

cvcc0

cgnd0

cvcc1

cgnd1

hsync

vsync

red

green

blue

rset

reset

ads

mnio

wnr

rdyrtn

lrdy

ldev

be

adr

data

lclk

c32khz

xtal1

stndby

href

aa

rasab0

casal

casah

wea

oeab0

casbl

casbh

rasab1

web

ca

rasc

cascl

casch

wec

oec

mad

mbd

agnd

avcc

bvcc0

bvcc1

dvcc

mvcca

mvccb

mvccc

ivcc0

ivcc1

pVideo*

p5000*

bus, memory and digital i/o 5V power

i55:4K7

Rhi

[8]

LINK

p5000*

p3300*

For the latest revision 65550 C&T recomend

that the core only be run at 3.3V. This is a

change from earlier revs, there is at least

one problem (probably timing) so rev 4 has

a link to allow both voltages

NOTE: remove i55 for 5V operation

pwr:

Cv

i58:0.001uF

Cv

i57:0.1uF

Cv

i56:0.1uF

gnd*

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

Mark Hayter

RCS $Revision: 1.10 $

Version: Rev 4

4 of 16TV out

p5000*

f*4

NTSC

clocks.clk14m

p5000*

gnd* Cva4

c4:10uF

Cv

c5:0.1uF

p5000*

gnd*

Cva4

c7:10uF

Cv

c6:0.1uF

Cha8

Rh

r1:75R c1:220uF

Fb

i1:

Cha8

Rh

r2:75R c2:220uF

Fb

i2:

Cha8

Rh

r3:75R c3:220uF

Fb

i3:

RCA

34

21

DIN4

compout

Ch

c10:0.1uF

c9:0.1uF

c8:0.1uF

.r

.g

.b

.h

.v

tv

sequoia.pc[3]

vr

vg

vb

vo

vy

vc

or

yr

cr

oc

yc

cc

yout

cout

dgnd

dpos

fin

stnd

select

encd

vsync

hsync

bin

gin

rin

agnd

apos

crma

luma

cmps

AD724

10

11

9

4

2

6

7

8

16

15

5

12

1

3

14

13

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

Mark Hayter

RCS $Revision: 1.26 $

Version: Rev 4

Clocks 5 of 16

romcard.~oe

romcard.~oe romcard.~cs

romcard.~cs

vl.data[16..23]

vl.data[24..31]

vl.data[8..15]

vl.data[0..7] [0..7]

[16..23]

[24..31]

[8..15]

romData

romAdr

romcard.~cs

romcard.~oe

romcard.wp

[2..5]

[6..9]

[10..13]

[14..17]

gnd*

[2..5]

[6..9]

[10..13]

[14..17]

vl.adr

gnd*

[18..25]

romcard.~we sequoia.smart[3]sequoia.sda

u1:

u2:

u3:

u4:

[18..25]

Cv

p3300*

gnd* p3300*

p3300*

gnd*

ck33 Rh

clocks.sequref

clocks.vlcopy

Rh clocks.cpumclk

nc*

Rh

clocks.sdramA[0]

clocks.sdramA[1]

clocks.sdramA[2]

clocks.sdramA[3]

clocks.sdramB[0]

clocks.sdramB[1]

clocks.sdramB[2]

clocks.sdramB[3]

Rh

Rh clocks.nmclk

clocks.dbus

p5000* nc*

clocks.clk14mb

Rh clocks.clk3m

clk7m

clocks.forcpu

u5:

u6:

i1:10uF i2:0.1uF i3:0.1uF

i4:24R

i5:24R

i6:24R

i7:24R

i8:24R

i9:24R

i10:24R

i11:24R

i12:36R

i13:30R

i14:56R

i15:51R

i16:47R

XTAL

Ch

i18:1M

clocks.clk32k

i19:15pF i20:32.768KHz

gnd*

nc*

gnd*

Note: these are the ISA clock

divided by 4, ie 3.5795MHz ish

sequoia.pBat

p5000*

gnd

7

14

vcc

12

34

56

98

11 10

13 12

C4069

clocks.clk33m

gnd*

p5000*

u7:33.333MHz

Cvr

2

1

43

OSC

outvcc

oe

gnd

Cva4

Note: Clock ordering set for rev.4 layout

Cv

i21:0.1uF

Cv

i22:0.1uF

Cv

i23:0.1uF

Cv

i24:0.1uF

gnd*

p3300*

Recomended bypass caps: one per digital vcc

p5000*

Note: 7 bypass pairs this sheet, 3 for sheet 7.

Bypass

pwr

10 pairs of 0.1uF and 0.001uF

(sheet 16)

Note: think about rom data bus when roms not active

does it need tie offs, or for the PAL to keep it active?

Rhi p5000*

i25:10K

vl.~reset

Rh

i26:47R

~romwe

c1 c2 cx

c3

cb

cc

q5

q4

q3

q2

q1

q0

lf

5

11

7

6

4

18

12

10

9

8

25

2

28

23

21

16

14

26

19

3V3 part

74FCT388915T

F388915t

lock

qq

q0

q1

q2

q3

q4

q5

qd2

vccan

lf

gndan

freqsel

pllen

oenrst

refsel

sync0

sync1

feedback

11

12

10

13

8

9

3

2

4

1

6

5

74ACT74

ACT74

q0

qb0

r0

s0

d0

cp0

q1

qb1

r1

s1

d1

cp1

Rhi

oe4

oe3

oe2

oe1

a4

a3

a2

a1

y4

y3

y2

y1

FCT16244

74FCT16244

5V part

[4]

[]

[4]

[]

[4]

[]

[4]

[]

[4]

[]

[4]

[]

[4]

[]

[4]

[]

1

48

25

24

oe2

oe1

a9

a8

a

y9

y8

y

FCT827

74FCT827

5V part

[8]

[]

15

14

[8]

[]

10

11

1

13

Rh

i17:33R

c33

Rh

i27:51R

ckfb

dir2

dir1

a2

a1

oe2

oe1

b2

b1

FCT16245

74FCT16245

5V part

[8]

[]

[8]

[]

48

25

[8]

[]

[8]

[]

1

24

dir2

dir1

a2

a1

oe2

oe1

b2

b1

FCT16245

74FCT16245

5V part

[8]

[]

[8]

[]

48

25

[8]

[]

[8]

[]

1

24

Note: This is a rev 3 change

it was to gpiob[0], but that was

needed for the smart card detect

31

33

70

55

29

[]

[2..25]

[]

[0..31]

ROMconn

data

adr

ce

oe

wr

wp

reset

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/05/16 00:47:47 $ 

Mark Hayter

RCS $Revision: 1.37 $

Sequoia

nc*

cwe

nc*

.irq[1]

note inverted wrt others!

isa.irq[8]

isa

.aen

.bale

.~dack[0..3]

.~dack[5..7]

.drq[0..3]

.drq[5..7]

.~iochk

.iochrdy

.~iocs16

.~ior

.~iow

.~master

.~memcs16

.~memr

.~memw

.~refresh

.sa[0]

.sa[1]

.~sbhe

.sd

.~smemr

.~smemw

.clk

.tc

.~zws

p5000*

.~memw

.~memr

~romCs

isa.~master

nc*

Version: Rev 4

.adr[2..27]

.adr[31]

.~ads

.~be

.~blast

.~brdy

.dnc

.~eads

nc*

Rh

nc*

Rh

p5000*

p5000* nc*

Rh

p5000*

nc*

.wnr

.~rdy

.mnio

.hlda

.~reset

vl

Rh

p5000*

Rh

p5000*

nc*

.sd[8..15]

ided7

[8..15]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

Rh

gnd*

isa.~ior

.~iocs16

.irq[14]

.iochrdy

Rh

vl.~reset

ideData

~ideCs

~ideCs[1]

.sa[0]

.sa[1]

.sa[2]

.bale

.~iow

.~ior

Note: This IDE interface uses

the ISA command pins directly

therefore if TURBO mode is used

(EIDE) other ISA peripherals may

get confused. This should be tested

and the restriction of only standard

IDE modes may be imposed.

.~reset

nc*

.~brdy

.data

.hlda

.hold

.~lgnt0

.~lreq0

.~local

.~lrdy

.~rdy

saEn

nc*

Rh

gnd*

6 of 16

p5000*

sequoia.pc

gnd*

p5000*

sequoia.gpiob

Rh

p5000*

sequoia.smart[0..3]

gnd*

ma[1]

ma[2]

ma[3]

ma[4]

ma[5]

ma[6]

ma[7]

ma[8]

ma[9]

ma[10]

ma[11]

ma0a

gnd*

p5000*

gnd*

p5000*

gnd*

160/176 package

not DLC processor

reserved

BD delay

other CPU type

reserved

bads,bdev delay

misc config

misc config [2..0] = rev 4

misc config

reserved

internal RTC

See register 100H of Sequoia-1

[2..5]

[6..9]

[10..13]

[14..17]

[2..5]

[6..9]

[10..13]

[14..17]

vl.adr

.sa

[0..18]

.sd[0..7]

[18]

Rh

vl.adr[18]

Note: only loads on adr 18 are ROM and UMI0

sequoia.intr

.sreset [1] gnd*

u1:

i1:10K

i2:10K

i3:10K

i5:10K

i6:100K

i11:100K

i12:100K

i13:100K

i14:100K

i15:100K

i16:100K

i17:100K

i18:100K

i10:100K

i7:100K

i8:100K

i9:100K

i26:100K

i27:100K

i28:100K

i30:100K

i29:4K7

i34:4K7

clocks.clk32k

i31:100K

i32:100K

i33:100K u2:

i35:4K7

i36:100K

sequoia.smart[4..7]

i37:20K

u4:

i38:0R

i39:33R

i40:33R

i41:33R

i42:33R

i43:33R

i44:33R

i45:33R

i46:100K

data

adr

we

oe

ce

Am29F040

22

24

31

[0..18]

[]

[0..7]

[]

u5:

u6:

u7:

u8:

i47:33R

data

ior

iow

balel

hcs

adr

reset

iocs16

irq

iochrdy

IDEcon

27

31

32

1

[0..2]

[]

[0..1]

[]

28

23

25

[0..15]

[]

ideale

~idew

~ider

~hcs

idea

~ideres

sequoia.pwrgood

sequoia.rcrst

nc*

clocks.clk14m

clocks.clk33m

i48:47Rclocks.sequref clko1

Rh

i49:22R

Rh

i50:33R

Rh

i51:33R

clocks.vlbus1

clocks.vlbus2clko1

isa.reset

Rh

Cv

TWOPIN

p5000*

i52:33R

i53:1K i54:0.01uF

gnd*

The ’beep’ speaker gizmo plugs in here

BootROM: Pin out ok for rom/eprom/flash

128kx8, 256kx8, 512kx8

+5V flash may be programmed in system

+12V flash may need adr[18] disconnected

and the pin tied to p5000* (its Vpp)

sequoia.pBat

T3904

p5000*

i25:100K

[0]

[1]

[0]

[1]

[2]

[0]

[1]

~ideCs[0]

.sd

.irq[3..12]

.irq[14..15]

bd

nc*

Rhr

ma

ma0a

ma0b

Rhr

Rhi Rhi

Rhi

Cv

gnd*

bc1:1uF bc2:0.1uF

Note: Bypass caps (0.1uF and 0.001uF each) for

address buffer and bootROM from sheet 1

p5000*

sequoia.nmi

Cvt3

Sqbypass

pwr

9x0.1uF, 5x1uF, 4x10uF for Sequoia

plus 3x0.1uF for IDE buffers

(sheet 13)

TP[1]

tp12:

TP

tp13:

TP

tp16:

saEn

TP

tp17:

TP

tp18:

.~brdy

TP

tp19:

.~rdy

TP

tp20:

.wnr

sp:TP

s0

s1

s2

s5

s6

s7

s8

s9

sa

sb

sd

se

sf

sg

sh

si

sj

sk

sl

sm

sn sp

bads

bdev

bser

fs1xclk

so

~ideBufEn

sequoia.smi

vcccore2

vcccore1

spndrst

rstdrv

rstcpu

rcrst

pwrgood

cpuclko2

cpuclko1

clkin

wbnwt

wnr

stpclk

sreset

smiact

smi

rdy

nmi

mnio

lock

ken

hlda

hitm

flush

eads

dnc

cache

brdy

blast

be

ads

a20m

a31

adr

fs1xclk

bser

bdev

bd

bads

romcs

master

kbrst

kbcs

irq8

acpwr

vlb

lb

swtch

pc

gpiob

gpio

c32kin

css3

tagwe

tagd7

tagd0

sramce

cwe

ca3b

ca3a

mden

ma

ma0b

ma0a

dramwe

SEQUOIA1

PT86C768A2

93

121

120

[1..11]

[]

92

127

128

[0..1]

[]

174

144

136

135

125

57

[0..3]

[]

[0..1]

[]

[0..9]

[]

47

122

123

124

70

68

66

54

69

81

[0..7]

[]

82

83

80

[2..27]

[]

172

162

155

[0..3]

[]

160

153

152

158

161

35

150

163

40

149

159

173

156

37

33

32

38

157

151

59

167

165

55

56

34

65

67

39

148

cpuclk

in14mhz

gpio

rstdrv

deturbo

rdy

nmi

lrdy

local

lreq0

lgnt0

intr

ignne

hold

hlda

hitm

ferr

d

brdy

bint

fs1xclk

bser

bdev

bd

bads

xddir

spkr

saen

turbo

idecs

idebufen

ided7

zws

tc

sysclk

smemw

smemr

sd

sbhe

sa1

sa0

refresh

memw

memr

memcs16

master

irqh

irq

irq1

iow

ior

iocs16

iochrdy

iochk

drq2

drq

dtack

dack

bale

aen

SEQUOIA2

PT86C718A2

115

123

[0..3]

[]

[5..7]

[]

[0..3]

[]

[5..7]

[]

117

118

124

51

50

94

[3..12]

[]

[14..15]

[]

116

111

113

114

121

108

109

110

[0..15]

[]

49

48

122

84

120

135

136

[0..1]

[]

126

127

139

42

144

[0..7]

[]

143

141

146

142

171

[0..31]

[]

166

159

161

162

165

163

4

3

[0..2]

[]

41

160

172

140

119

[4..7]

[]

137

157

oe4

oe3

oe2

oe1

a4

a3

a2

a1

y4

y3

y2

y1

FCT16244

74FCT16244

5V part

[4]

[]

[4]

[]

[4]

[]

[4]

[]

[4]

[]

[4]

[]

[4]

[]

[4]

[]

1

48

25

24

g2

g1

a7

a6

a5

a4

a3

a2

a1

a0

y7

y6

y5

y4

y3

y2

y1

y0

HCT244i

74HCT244

18

16

14

12

9

7

5

3

2

4

6

8

11

13

15

17

1

19

Cv

bc3:0.1uF

p5000*

sequoia.umics

1

19

[]

[8]

[]

[8]

74HCT245

HCT245

ba

g

dir

1

19

9

8

7

6

5

4

3

2

11

12

13

14

15

16

17

18

74HCT245

HCT245i

b0

b1

b2

b3

b4

b5

b6

b7

a0

a1

a2

a3

a4

a5

a6

a7

g

dir

Rh

p5000* i55:4k7 .~lrdy

sequoia.~ferr

sequoia.pc[4]

gnd*

The sequoia burst bus needs pullups on the control lines

if the power-down feature is used the bd data lines also need pullups

p5000*

i24:10K

p5000*

i23:10K

Rhi

bads

bdev

sequoia.pc[0]

s8

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/05/13 18:11:02 $ 

Mark Hayter

RCS $Revision: 1.30 $

Version: Rev 4

Pci and Umis 7 of 16

.~ads

.mnio

.wnr

.dnc

.~be

.adr

.data

.~local[2]

.~rdy

.~lreq0

.~lgnt0

.~blast

.~brdy

.~loc0or1

Rh

p5000* nc*

vl

.~reset

Rh

p5000*

Rh

p5000*

pci.~gnt[1]

pci.~gnt[3]

Configiuration links

Select IRQ14,15 not req/gnt2

Select blast not hiaddr

.~frame

.ad

.~cbe

.~irdy

.~trdy

.~stop

.~devsel

.par

.~perr

.~lock

.~req[0]

.~gnt[0]

.~req[3]

.~gnt[3]

.~inta

.~intb

.~intc

.~intd

.~irdy

.~trdy

.~stop

.~devsel

.~perr

.~serr

.~lock

.~req[3]

.~inta

.~intb

.~intc

.~intd

.~frame

.~req[0]

.~req[1]

p5000*

isa

sequoia.umics

Note: umics may be useful for upper address bit decoding

Note: idsel comes from ad[17]. Don’t care abput loading since there

is only one UMI slot. Additional PCI devices could use ad[18..31]

but then loading might become an issue.

Note: Only config type 0 cycles supported by VIA chip, so no bridges on the UMI

p5000* .~local[2]

Note: pullups for unpopulated bridge

p5000* .~lreq0

vl.adr[19..25]

Note: address lines 19..25 are not used on internal

isa nor by most networking chips, so they come unbuffered

from the vl bus

Rh .drq[0]

Rh .drq[1]

Rh .drq[2]

Rh .drq[3]

Rh .drq[5]

Rh .drq[6]

Rh .drq[7]

Rh

.~iochk

.iochrdy

.~iocs16

.~ior

Rh .~iow

p5000*

gnd*

Rh .irq[1]

Rh .irq[3]

Rh .irq[4]

Rh .irq[5]

Rh .irq[6]

Rh .irq[7]

Rh .irq[9]

gnd*

Rh .irq[10]

Rh .irq[11]

Rh .irq[12]

Rh .irq[14]

Rh .irq[15]

gnd*

Rh

p5000*

Rh

p5000*

Rh

p5000*

Rh

p5000*

Rh

p5000*

.~master

.~memcs16

.~memr

.~memw .~refresh

p5000* Rh .~zws

[15]

nc*

[9..11]

[5]

isa.irq

isa.~iochk

i1:4K7

i2:4K7

i3:4K7

i4:10K

i5:10K

i6:10K

i7:10K

i8:10K

i9:10K

i10:10K

i16:4K7

i15:1K

i41:330R

i11:10K

i12:10K

i43:330R

i44:330R

i13:10K

i14:10K

i40:330R

i21:100K

i22:100K

i23:100K

i24:100K

i25:100K

i26:100K

i27:100K

i28:100K

i29:100K

i30:100K

i31:100K

i32:100K

i42:330R

u1:

i50:2K7

i51:2K7

i52:2K7

i53:2K7

i54:2K7

i55:2K7

i56:2K7

i57:2K7

i58:2K7

i59:2K7

i60:2K7

i61:2K7

i62:2K7

i63:2K7

i64:2K7

i17:4K7

i18:4K7

clocks.vlbus1

.~req[1]

.~gnt[1]

p5000* .sd[8..15]

i37:

p5000* .sd[0..7]

in out

R8x10K

i36:

R8x10Ka

outin

.~inta

.~intb

.~intc

.~intd

.~frame

.~irdy

.~devsel

.~lock

.par

.~trdy

.~stop

.~perr

.~serr

Rh

i67:2K7

p5000* Rh

i68:2K7

p5000*

Rh

gnd*

i69:4k7

i70:4k7

i71:4k7

Note: only use of these adr bits .adr[28]

.adr[29]

.adr[30]

Rhr

Rhi

Rhr

Rhi

Note: 3 pairs of bypass caps from sheet 5

p0

p1

p2

147

102

[]

[9..11]

143

97

136

101

152

96

148

117

116

104

103

105

115

[]

[0..31]

[]

[2..31]

[]

[0..3]

4

3

2

1

149

16

15

99

98

120

159

119

118

128

129

121

5

138

139

141

142

137

160

[]

[0..3]

[]

[0..31]

46

151

VL -- PCI

VT82C505

pclk

frame

ad

cbe

irdy

trdy

stop

devsel

par

perr

serr

lock

req0

req1

gnt0

gnt1

req3

gnt3

inta

intb

intc

intd

cclk

ads

mio

wr

dc

be

ca

cd

ldevo

lrdy

rdyrtn

ldevi

lreqo

lgnti

blast

brdy

reset

wback

eads

iochk

irq5

irq

irq14

irq15

.ad

.~gnt[0]

.~req[0]

.~cbe

vl.~reset

.ad[17]

pci

.aen

.bale

.reset

.~iochk

.iochrdy

.~iocs16

.~ior

.~iow

.tc

.clk

.~zws

.~memr

.~memw

.~memcs16

.~refresh

.~sbhe

.~smemr

.~smemw

.sd

.irq[10]

.irq[11]

.irq[12]

.~dack[3]

.~dack[5]

.~dack[6]

.drq[3]

.drq[5]

.drq[6]

.sa

i72:4K7

p5000* Rhi

227

27

226

26

225

25

224

24

223

23

222

22

221

21

[]

[0..3]

218

118

18

217

117

17

[]

[0..31]

UMIPCI

ad

inta

intb

intc

intd

gnt

req

cbe

clk

frame

irdy

devsel

lock

sdone

sbo

par

rst

idsel

trdy

stop

perr

serr

118

126

124

122

[]

[0..15]

220

20

219

119

19

218

18

217

117

17

216

16

215

115

15

214

114

14

213

113

13

212

112

12

211

[]

[19..25]

[]

[0..18]

UMIISA

sa

sah

upcs

aen

bale

reset

dacka

dackb

dackc

drqa

drqb

drqc

iochk

iochrdy

iocs16

ior

iow

tc

clk

zws

memr

memw

memcs16

refresh

sbhe

smemr

smemw

sd

irqa

irqb

irqc

master

.~master

.~rdy

Note: lreq0 pullup for PCLK=CCLK

Rh

p5000* pci.~gnt[0]

i73:4K7 pclk synchronous

clocks.vlbus1

clocks.vlbus1 This selection makes the UMI slot be PCI config device 6

nc*

These are two holes for standoffs to fix the umi

cards. Basically 0.153 hole with min .180 clearance

mnt1:

mnt2:

Hole153

vl.~boff

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

Mark Hayter

RCS $Revision: 1.28 $

.sa[0..15]

.aen

.sd[0..7]

.~dack[0..3]

.drq[0..3]

.iochrdy

.irq[1]

.irq[3..12]

.~ior

.tc

isa

nc*

.~iow

.~zws

Rh

ppack

ppafd

ppspr

ppbusy

pperr

ppinit

ppd

pppe

ppslct

ppstb

p5000*

ppack

ppafd

ppspr

ppbusy

pperr

ppinit

ppd

pppe

ppslct

ppstb

.out

.in

.rts

.ri

.dtr

.dsr

.dcd

.cts

.out

.in

.rts

.ri

.dtr

.dsr

.dcd

.cts ser2t

Cv

i15:4K7 i16:4K7

gnd*

i17:4K7

p5000*

i18:4K7

TS

p5000*

gnd*

p5000*

~md

~kd

~kc

~mc

xp mkpwr

i19:1000pF

Filter

PTC

~mdata

~mclk

~kdata

~kclock

ser1t

SuperIO

Version: Rev 4

8 of 16

.id0

.rx1

.tx

.id2

.id1

.id3

.irsl2

gpio2

gpio1

nc*

ser1t.out

p5000*

ser2t.rts

ser2t.out

ser2t.dtr

p5000*

ser1t.dtr

ser1t.rts

p5000*ir.irsl2

FDC,KBC,RTC inactive

No X bus

Clock source 32.768kHz

PnP Motherboard, config @015Ch

not NSC test

Note:Internal 30k pulldown

i1:10K

i2:10K

i3:10K

i4:10K

u1:

nc*

Rh

p5000* nc*

Rh

p5000*

Rh

gnd* clocks.clk32k

nc*

i5:10K

i8:1K

i9:10K

i6:

i7:

i10:33R

i11:33R

i12:33R

i14:33R

i20:4K7

i21:4K7

i22:4K7

i23:4K7

i24:4K7

i25:4K7

i26:

i27:4K7

i28:4K7

i29:4K7

i30:680pF

i32:680pF

i31:330pF

i33:

i34:330pF

gnd*

ir

strobe

select

paper

data

init

err

busy

selectpr

afd

ack

PPORT

Parallel

10

14

17

11

15

16

[0..7]

[]

12

13

1

ser1shdn

.reset

vBat

nc*

R8x4k7

88

C8x330

R8x33

8

i13:

ppdx

Fb25

DBAS16

Rhr

Rhi

Rvi Rvi

Chi

Rhi

p5000*

Note: Six of these go to sheet 9

Note: National recommend six 0.1uF bypass caps

IObypass

pwr

12x0.1uF

(sheet14)

gpio1[0]

gpio1[1]

gpio1[2]

gpio1[3]

u2:93C46hostid

p5000*

i35:10K

Rhi

s0 s1

s2

s3

s4

s5

s6

s7

s8

2

3

4

1

EEPROM

microwire

SerROM

cs

do

di

clk

gpio1[4]

gpio1[1]

gpio1[2]

gpio1[3]

u3:93C86

2

3

4

1

EEPROM

microwire

SerROM

cs

do

di

clk

Note: hostid is pre-programmed with a

Digital UID for the network interface

Note: this 16kbit eeprom is nonvolatile storage for the

firmware to keep settings, it is partitioned by Digital, NCI and FirmWorks

u6

u5

u4

u3

u2

u1

l6

l5

l4

l3

l2

l1

DualMD6

dualMDIN6

Lower

1

2

3

4

5

6

Upper

11

12

13

14

15

16

nc*

gnd*

nc*

Rv

p5000*

i36:10K

i37:10Ki38:10K

gnd*

i39:

sequoia.pwrgood

~softres

RviRvi

DBAS16i x2c

x1c

x1

wdo

vcch

vbat

switch

ring

por

onctl

gpio2

gpio1

cs2

cs1

cs0

wp

wgate

wdata

trk0

step

rdata

index

hdsel

dskcng

drate0

dir

densel

zws

wr

tc

rd

mr

irq15

irq14

irq

irq1

iochrdy

drq

dack

data

aen

adr

stb

slct

pe

pd

init

err

busy

astrb

afd_dsrtback

sout1

sin1

rts1

ri1

dtr1

dsr1

dcd1

cts1

sout2

sin2

rts2

ri2

dtr2

dsr2

dcd2

cts2

gpio20

id3

irsl2

irsl1id1

irsl0id2

irtx

irrx1

irrx2id0

p21

p20

p17

p16

p12

kbclk

kbdat

mclk

mdat

PC87307

105

104

103

102

106

107

108

109

110

79

80

81

158

78

77

70

157

141

142

143

144

145

146

147

148

131

132

133

134

135

136

137

138

113

119

118

111

116

117

[0..7]

[]

115

114

112

[0..15]

[]

30

[0..7]

[]

[0..3]

[]

[0..3]

[]

32

36

[3..12]

[]

48

49

51

33

35

34

31

94

90

84

99

92

97

95

91

96

89

93

98

68

71

72

[0..6]

[]

[3..7]

[]

67

159

69

66

64

65

156

50

62

63

.irq[15]

sequoia.~ferr

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/05/12 00:28:29 $ 

Mark Hayter

RCS $Revision: 1.29 $

Serial I/O

gnd*

.dtr

.rts

.cts

.dcd

.ri

.dsr

nc*

ser1t

The IR from the SuperIO supports IRDA and Consumer IR

Only 38kHz consumer IR is provided here

TX frequency is set by software, but receiver module is tuned

Version: Rev 4

9 of 16

p5000*

gnd*

ir

.tx

.rx1

p5000*

gnd*

.id0

.id1

.id2

.id3

Id links for CIR only, don’t do plug’n’play stage 2

Other rx module options are TMFS5nn0

For nn = 30, 33, 36, 37, 38, 40, 56 as the

center frequency in kHz

LED

Rh

LED

Rh

sequoia.pc[5]

sequoia.pc[6]

sequoia.pc[7]

sequoia.pc[8]

sequoia.pc[9] sequoia.scl

sequoia.gpiob[1] sequoia.sda

Note: these are not really sequoia signals

but open collector versions at 3.3V

they are used to make the I2C for SDRAM type detect

gnd*

p5000*

gnd*

nc*

gnd*

Rh

p5000*

Rh

p5000*

Rh

p5000* nc*

nc*

Rh

gnd*

clocks.clk3m

ser2t.out

smin

smin Rh

Rh

ser2t.in

.out

.in

It is in the required 1MHz - 5MHz range

en

r5o

r4o

r3o

r2o

r1o

shdn

r5i

r4i

r3i

r2i

r1i

t4i

t3i

t2i

t1i

t40

t3o

t2o

t1o

c2m

c2p

c1m

c1p

vm

vp

MAX211

13

17

12

14

15

16

2

3

1

28

7

6

20

21

9

4

27

23

18

25

8

5

26

22

19

24

i1:’0.1uF’

i2:’0.1uF’

i3:’0.1uF’

i4:’0.1uF’

i5:’0.1uF’

u1:

u2:

i6:’4K7’

i7:’4K7’

i8:’10K’

i9:’0R’

i10:’0R’

u3:

i11:’4K7’

i12:’4K7’

i13:’4K7’

i14:’4K7’

i15:’4K7’

i16:’4K7’

i17:’4K7’

i18:’4K7’

i27:’14R’

p5000*

i20:’330R’

i21:4.7uF

i19:’15K’

u4: i23:’330R’

i24:’330R’

i25:’330R’

i26:’330R’

i29:’5mm,yellow’

i30:’5mm,green’

ird

3

ELT1MMF

24

1

T2N02

sequoia.smart[4]

sequoia.smart[6..7]

sequoia.smart[1]

sequoia.smart[0]

sequoia.smart[2]

v1p

v1m

v2p

v2m

vp

vm

ser1r.dtr

ser1r.rts

ser1r.out

ser1r.in

ser1r.cts

ser1r.dcd

ser1r.ri

ser1r.dsr

ser1shdngnd*

gnd*

smrst

smclk

smio

virtx

yl

gl

Note: pc[5] and pc[6] can be

programmed to flash leds

Sharp ir options are IS1U60 rx module (38kHz)

and GL560 or GL561 IRled. Note that packages differ!

Note: Use 3.579 MHz clock (cpu core clock) here TSIP5201

Rh

i31:’470R’

smvcc

sequoia.smart[5]

Rh

i32:’10K’

gnd*

Smartcard interface uses Sequoia GPIO bits [0..7]

Smart[0..3] always inputs on reset, [4..7] may be parity

0 - high to power card

1 - high to reset card

2 - card data in

3 - card detect in (low if card)

4 - clock for card

5 - data for card

0 0

0 1

1 0

1 1

data, clock o/c

7 6

3.579MHz clock, gpio data

gpio clock, gpio data

3.579MHz clock, uart

T2907A

Cva4

6

9

1

8

2

3

7

4

5

9pin D

RS232

gnd

dtr

rts

txd

rxd

cts

dcd

ri

dsr

TSIP5201

i22:’14R’

Note: Nat Semi IR front end reference suggests

use of two IR LEDs.

Note: TSSP4400 are similar with light output on side

ir1:

ir2:

Rhr

Rhi

Cv

Cv Cv

Cv

irdr

irir

ACT05

1213

1011

89

65

43

2

1

ACT05

1213

1011

89

65

43

2

1l0

l1

l2

l3

p5000*

1

3

2

TFMS5380

vg

out

vs

gnd*

p5000*

c0

c1

c2

c3

c4

[]

[2]

13

12

11

10

3

4

5

6

15

9

1

7

74F153

F153

ya

ea

yb

eb

i0a

i1a

i2a

i3a

i0b

i1b

i2b

i3b

sel

Alternatively put the IR LEDs in right angle mounts

p5000*

BILED

gnd* Note: These two leds are

only populated on debug or

development boards

Rhi

Hole125

nc*

These holes are for supports for the smartcard reader

when a bare board is used

sm0:

sm1:

Rh

sequoia.gpiob[0]

~cardIns

Note: This is a rev 3 change

gpiob[0] is Wake0 and can trigger a FIQ

both on card insert and card removal

i33:’470R’

Ledlnk gnd*

Note: Either the link wire

or board mounting LED may be used

Onehole

gnd*

This hole sits between the IR LEDs to allow a cable

to be used to bezel mounted LEDs in place of pcb mounted ones

carddet2

carddet1

c8rsvd2

c7io

c6vpp

c5gnd

c4rsvd1

c3clk

c2rst

c1vcc

SMRTPINS

ISO7816

1

3

5

7

2

4

6

8

slot

9

10

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/05/17 00:51:49 $ 

Mark Hayter

RCS $Revision: 1.32 $

Audio

Version: Rev 4

.reset

.~ior

.~iow

.sa[0..11]

.aen

.sd[0..7]

.sd[8..15]

nc*

.drq[5]

.~dack[5]

.drq[0]

.~dack[0]

.drq[1]

.~dack[1]

.drq[3]

.~dack[3]

.irq[9]

.irq[5]

.irq[7]

.irq[10]

.irq[15]

Rh

p5000*

nc*

gnd*

nc*

nc* Note: Slight difference between

888 and 1887 for the DSP serial

port. This arrangement should

be fine for not using the port

Cv

Note: Use xtal

here if the

clk14m is not

accurate enough

Cv Cv Cv

Cv Cv Cv Cv

nc*

Rh

gnd*

Cv

Rh

cmr

Cv

agnd

avcc

Cv

Ch

Ch Ch

Cv

Ch

avcc

nc*

Cv

avcc

agnd

p5000*

Note: Care with layout

Need single connection

point for agnd to gnd Note: output amp is directly

(not cap) coupled since vref/cmr

is used as the reference

Below this line is the analog power/ground domain

10 of 16

isa

clocks.clk14m

i1:1K

i2:

i3:10uF i4:0.1uF

i5:0.1uF

i6:7K5 i7:7K5

i8:10uF i9:47uF i10:0.1uF

Below this line is the analog power/ground domain

gnda

cmr

mic

fdxi

fdxo

auxr

auxl

liner

linel

vdda1

aoutl

aoutr

pcspko

cinr

foutr

cinl

foutl

vref

mute

volup

voldn

pcspki

amode

dackbd

drqd

dackbc

drqc

dackbb

drqb

dackba

drqa

irqe

irqd

irqc

irqb

irqa

xi

xo

datah

datal

aen

adr

iowb

iorb

reset

gpo1

gpo0

mclk

msd

fmsel

dx

dr

dclk

fs

frmstb

fmcsb

td

tc

tb

ta

swd

swc

swb

swa

mso

msi

ES888

56

55

32

31

30

29

28

27

26

25

18

79

80

81

82

83

86

84

85

54

53

78

72

73

[0..11]

[]

9

[0..7]

[]

[8..15]

[]

76

77

71

70

69

68

67

65

66

63

64

61

62

59

60

22

52

19

20

21

44

33

42

34

43

50

49

48

41

46

47

37

38

36

35

39

45

40

i11:2K2

i12:2K2

i13:

i14:2K2 i15:2K2 i16:2K2 i17:2K2

p5000*

i18:150pF

i19:0.01uF i20:0.01uF i21:0.01uF i22:0.01uF

i23:2K2

i24:2K2

i25:2K2

i26:2K2

i27:1M

i28:0.01uF

i29:1M

i30:0.01uF

i31:1M

i32:0.01uF

i33:1M

i34:0.01uF

sa

sb

sc

sd

ta

tb

tc

td

mi

mo moout

miout

pGame

x1

y1

x2

y2

i35:4K7

i36:0.1uF

i37:0.22uF i38:1000pF

i39:0.22uF i40:1000pF

i41:10uF i42:0.1uF

i43:330uF

i44:10K

i45:8K6

i46:10K i47:8K6

i48:330uF

i50:0.1uF

cmr

fr

cir

cil

fl

aor

aol

vref

ramp

lamp

gnd*

7

6

5

4

83

2

1

vee

vcc

-

+

-

+

p1

m1

o1

m2

o2

p2

SSM2135

Fb25

Rhi

Rhr

miin mic

amode fmsel

aold

aord

cmr

Rhr

avccm

Rhr

Rhi

Cha8

Cva6

Cva4

PTC

Rvi Rvi Rvi Rvi

Note: four 0.1uF bypass capacitors (as suggested by ESS) shown on sheet 11

pg

nc*

nc* The frmsrb out from the 888 becomes fsr in on the 1887

The fs in on the 888 becomes fsx in on the 1887

For using the port on both chips these would have to

be linked in the 1887 case and not in the 888 case.

For never using leave unlinked and rely on the internal pulldowns

101

111

103

110

102

Left Jack

201

211

203

210

202

Center Jack

301

311

303

310

302

Right Jack

jacks

3.5mm

three

over

female D

(2 row)

15 pin

4

5

13

11

6

3

14

10

7

2

9

8

1

12

15

GamePort

AudioGm

midii

midio

pwr1

pwr2

pwr3

sw1

sw2

sw3

sw4

x1

y1

x2

y2

gnd1

gnd2

rsig3

rsw3

lsig3

lsw3

com3

rsig2

rsw2

lsig2

lsw2

com2

rsig1

rsw1

lsig1

lsw1

com1

nc*

rl

ll

Ch

i51:0.22uF rl

Ch

i52:0.22uF ll

miin

agnd

nc*

Mike input is on

combo connector

on right of this page

line

output

headphone

output

Stereo

Mono

mike

input

Rhr

ro

lo

agnd

Had 10uF here

:’ES888 or ES1887’

The audio is designed to use either

the ES888 or ES1887 codec

The main difference is that the 1887 includes

FM synth, it is also more expensive (about $3 more)

The 1887 is also slightly more configurable

Software for the 888 should work with the 1887

apart from a few lines of setup code (and the

lack of synth)

Note: rev 4 change

tie off unused inputs

Ch

i53:0.22uF

Ch

i54:0.22uF

Ch

i55:0.22uF

Ch

i56:0.22uF

Ch

i57:0.22uF

Ch

i58:0.22uF

agnd

i0

i1

i2

i3

i4

i5

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

Hal Murray

RCS $Revision: 1.16 $

Version: Rev 4

11 of 16Ethernet

r1:4K99 gnd*

.~memr

.~memw

.~memcs16

.~refresh

.~ior

.~iow

.~iocs16

.iochrdy

.~sbhe

.aen

isa

nc*

.reset

.sa

.sd

.irq[10]

.irq[11]

.irq[12]

.irq[5]

.drq[5]

.drq[6]

.drq[7]

.~dack[5]

.~dack[6]

.~dack[7]

XTAL2

x1:20MHz

Rh

Cv

r2:100R

r3:24R3

r4:24R3

c1:68pF

Cv

c3:0.1uF

8

7

6

9

11

1:1.4

3

2

1

14

16

1:1

for 10BaseT

Xfmrt

rim

rip

rom

roc

rop

tom

top

tim

tic

tip

gnd*

c5:1000pF, 1KVc4:1000pF, 1KV

Cv

c2:0.1uF

r5:680R

R2, R3, and R4 are setup for 100 ohm twisted pair.

Other values are possible. See CS8900 data sheet, page 123.

p5000*

r6:680R

Rhr

Rhi

lanled

linkled

x1

cs

do

disk

x2

1

2

3

6

for 10BaseT

RJ45

rm

rp

tm

tp

rm

rp

tm

tp

rdm

rdc

rdp

tdm

tdp

tdc

Cvhv Cvhv

LEDLED

l1:5mm,green l2:5mm,yellow

Rh

sequoia.pc[2]

vl.adr[19]

Note: Changed these caps from 10n to 1n

p5000*

Four digital, three analog recomended by Crystal

One for serial eeprom, four for audio (sheet 10)

IObypass

pwr

12x0.1uF

(sheet14)

clk

di

do

cs

SerROM

microwire

EEPROM

1

4

3

2

u2:93C46

u1:

tum

tup

res

lgrn

lyel

The serial eeprom is not populated on the DIGITAL reference design

it is shown here for reference only (for example a

umi manufacturer may use it)

12

14

16

11

13

15

35

30

31

32

36

64

33

62

61

49

34

28

29

63

75

7

[]

[0..15]

60

[]

[0..18]

87

88

91

92

82

81

80

79

84

83

98

97

4

6

5

3

2

17

77

93

76

78

99

100

CS8900

lanled

linkled

bstatus

test

res

sleep

csout

elcs

eecs

eedo

eedi

eesk

x1

x2

dop

dom

dip

dim

cip

cim

rdm

rdp

tdm

tdp

addr

a19

data

chipsel

reset

aen

memr

memw

memcs16

refresh

ior

iow

iocs16

iochrdy

sbhe

irq0

irq1

irq2

irq3

dmarq0

dmarq1

dmarq2

dmack0

dmack1

dmack2

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/05/14 03:07:47 $ 

Mark Hayter

RCS $Revision: 1.28 $

Version: Rev 4

12 of 16Power

gnd*

Rv

Cv

p5000*

Rv

pBat

Cv

Rh

i1:’51K’

i2:’1K’

i3:’1K’

i4:’20K’

i5:’0.1uF’ i6:’4700pF’

i7:’BR2032/Keystone 1061’

TWOPIN

i8:’10K’

i9:’10uF’

+

Bat

T3904

rcRst

T2907A

Cva4

p5000* p3300*

gnd* gnd*

i30:’22uF’ i32:’22uF’

i31:’22uF’

i33:’121R’

i34:’100R’

va3

i35:’100R’

gnd*

Rv

Cva5

Cva5 Cvt6

Rv

i36:

p2000*

Cv Cv Cv Cv

c11:’0.1uF’ c12:’0.1uF’ c13:’0.1uF’ c14:’0.1uF’

Cv Cv Cv Cv Cv Cv

c01:’1000pF’ c02:’1000pF’ c03:’1000pF’ c04:’1000pF’ c05:’1000pF’ c06:’1000pF’

gnd*

p2000*

Cv

c15:’0.1uF’

Cv

c16:’0.1uF’

p3300* p2000*

gnd* gnd*

i20:’22uF’ i22:’22uF’

i21:’22uF’

i23:’121R’

i24:’71R5’

va2

gnd*

Rv

Cva5

Cva5 Cvt6

i26:

p5000*

vBat

DBAV70

Hole125

nc*

Hole125

nc*

Hole125

nc*

Hole125

nc*

Hole125

nc*

Hole125

nc*

Hole125

gnd*

Hole125

gnd*

Hole125

nc* h0:

h1:

h2:

h3:

h4:

h5: h8:

h7:

h6:

Note: Battery is 3V Li coin cell BR2032

in a smt holder

p12000

gnd*

Rh

Rvi

Rv

i11:’10uF’

i10:’22K’

Cva4

TWOPIN

pwrgood

TP

tp21:

TP

tp22:

rp2:’TP’

rp1:’TP’

LT1086

vin

adj

vout

LT1086

vin

adj

vout

b0

b1 b2

r3 b3

p12

gnd2

gnd1

p5

IDEpwr

1

2

3

4

Note: These are the mounting holes, with the two near the connectors grounded

they have a .220 diameter pad with a .125 fhs plated hole

plugp

outer

inner

PwrJack

1

2

3nc*

Cv Cv Cv Cv Cv

c11:’0.1uF’ c12:’0.1uF’ c13:’0.1uF’ c14:’0.1uF’ c15:’0.1uF’

c21:’1uF’ c22:’1uF’ c23:’1uF’ c24:’1uF’ c25:’1uF’

pwr

gnd*

c31:’10uF’

pwr

gnd*

Cv Cv Cv Cv

c16:’0.1uF’ c17:’0.1uF’ c18:’0.1uF’ c19:’0.1uF’

c26:’1uF’

Cva4

c32:’10uF’

Cva4

c33:’10uF’

Cva4

c34:’10uF’

Cva4

Note: Sequoia1 gets 0.1uF + 1uF for each of the five power groups plus 1uF extra

Note: Sequoia2 gets 0.1uF + 10uF for each of the four power groups

Note: Three 0.1uF for the IDE buffers

Cv Cv Cv

c41:’0.1uF’ c42:’0.1uF’ c43:’0.1uF’

pwr

gnd*

Cvt3 Cvt3 Cvt3 Cvt3 Cvt3 Cvt3

Sequoia bypass 13 of 16

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

Mark Hayter

RCS $Revision: 1.8 $

Version: Rev 4

Cv Cv Cv Cv Cv Cv

Cv Cv

c11:’0.1uF’ c12:’0.1uF’ c13:’0.1uF’ c14:’0.1uF’ c15:’0.1uF’ c16:’0.1uF’

c17:’0.1uF’ c18:’0.1uF’

Cv Cv

c19:’0.1uF’ c20:’0.1uF’

pwr

gnd*

c:’22uF’

pwr

gnd*

Cva5

Cv Cv

c21:’0.1uF’ c22:’0.1uF’

pwr

gnd*

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

Mark Hayter

RCS $Revision: 1.8 $

Version: Rev 4

I/O bypass 14 of 16

Cv Cv Cv Cv Cv

c11:’0.1uF’ c12:’0.1uF’ c13:’0.1uF’ c14:’0.1uF’ c15:’0.1uF’

Cv Cv Cv Cv Cv

c01:’1000pF’ c02:’1000pF’ c03:’1000pF’ c04:’1000pF’ c05:’1000pF’

pwr

gnd*

c:’22uF’

pwr

gnd*

Cva5

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

RCS $Revision: 1.8 $

Version: Rev 4

Bypass (5) 15 of 16

Hal Murray

Cv Cv Cv Cv Cv Cv Cv Cv

c11:’0.1uF’ c12:’0.1uF’ c13:’0.1uF’ c14:’0.1uF’ c15:’0.1uF’ c16:’0.1uF’ c17:’0.1uF’ c18:’0.1uF’

Cv Cv Cv Cv Cv Cv Cv Cv

c01:’1000pF’ c02:’1000pF’ c03:’1000pF’ c04:’1000pF’ c05:’1000pF’ c06:’1000pF’ c07:’1000pF’ c08:’1000pF’

Cv Cv

c19:’0.1uF’ c20:’0.1uF’

Cv Cv

c09:’1000pF’ c10:’1000pF’

pwr

gnd*

c:’22uF’

pwr

gnd*

Cva5

Systems Research Center

Palo Alto, CA

Title:

By:

$Date: 1997/04/30 09:20:59 $ 

RCS $Revision: 1.10 $

Version: Rev 4

Hal Murray 16 of 16Bypass (10)

gnd*