G5SB-14 12DC - OMRON - Datasheet.Global

 2014-2017 Microchip Technology Inc. DS60001290E-page 1

PIC32MX1XX/2XX/5XX 64/100-PIN

Operating Conditions

• 2.3V to 3.6V, -40ºC to +105ºC (DC to 40 MHz),

-40ºC to +85ºC (DC to 50 MHz)

Core: 50 MHz/83 DMIPS MIPS32

M4K

•MIPS16e

mode for up to 40% smaller code size

• Code-efficient (C and Assembly) architecture

• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply

Clock Management

• 0.9% internal oscillator

• Programmable PLLs and oscillator clock sources

• Fail-Safe Clock Monitor (FSCM)

• Independent Watchdog Timer

• Fast wake-up and start-up

Power Management

• Low-power management modes (Sleep and Idle)

• Integrated Power-on Reset, Brown-out Reset, and High

Voltage Detect

• 0.5 mA/MHz dynamic current (typical)

•44 μA I

current (typical)

Audio/Graphics/ Touch HMI Features

• External graphics interface with up to 34 PMP pins

• Audio data communication: I

S, LJ, RJ, USB

• Audio data control interface: SPI and I

• Audio data master clock:

- Generation of fractional clock frequencies

- Can be synchronized with USB clock

- Can be tuned in run-time

• Charge Time Measurement Unit (CTMU):

- Supports mTouch

capacitive touch sensing

- Provides high-resolution time measurement (1 ns)

Advanced Analog Features

• ADC Module:

- 10-bit 1 Msps rate with one Sample and Hold (S&H)

- Up to 48 analog inputs

- Can operate during Sleep mode

• Flexible and independent ADC trigger sources

• On-chip temperature measurement capability

• Comparators:

- Three dual-input Comparator modules

- Programmable reference with 32 voltage points

Timers/Output Compare/Input Capture

• Five General Purpose Timers:

- Five 16-bit and up to two 32-bit Timers/Counters

• Five Output Compare (OC) modules

• Five Input Capture (IC) modules

• Peripheral Pin Select (PPS) to allow function remap

• Real-Time Clock and Calendar (RTCC) module

Communication Interf aces

• USB 2.0-compliant Full-speed OTG controller

• Up to five UART modules (12.5 Mbps):

- LIN 1.2 protocols and IrDA

support

• Four 4-wire SPI modules (25 Mbps)

•Two I

C modules (up to 1 Mbaud) with SMBus support

• PPS to allow function remap

• Parallel Master Port (PMP) with dual read/write buffers

• Controller Area Network (CAN) 2.0B Compliant with

DeviceNet™ addressing support

Direct Memory Access (DMA)

• Four channels of hardware DMA with automatic data

size detection

• 32-bit Programmable Cyclic Redundancy Check (CRC)

• Two additional channels dedicated to USB

• Two additional channels dedicated to CAN

Input/Output

• 10 mA or 15 mA source/sink for standard V

and

up to 22 mA for non-standard V

• 5V-tolerant pins

• Selectable open drain, pull-ups, and pull-downs

• External interrupts on all I/O pins

Qualification and Class B Support

• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC)

• Class B Safety Library, IEC 60730

Debugger Development Support

• In-circuit and in-application programming

•4-wire MIPS

Enhanced JTAG interface

• Unlimited program and six complex data breakpoints

• IEEE 1149.2-compatible (JTAG) boundary scan

Packages

Type QFN TQFP TFBGA (see Note 1)

Pin Count 64 64 100 100 100

I/O Pins (up to) 53 53 85 85 85

Contact/Lead Pitch 0.50 mm 0.50 mm 0.40 mm 0.50 mm 0.65 mm

Dimensions 9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 7x7x1.2 mm

Note 1: Please contact your local Microchip Sales Office for information regarding the availability of devices in the 100-pin TFBGA package.

32-bit Micr ocontr ollers (up to 512 KB Flash and 64 KB SRAM) with

Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 2  2014-2017 Microchip Technology Inc.

TABLE 1: PIC32MX1XX/2XX/5XX 64/100-PIN CONTROLLER FAMILY FEATURES

Device

Pins

Packages

(4)

Program Memory (KB)

(1)

Data Memory (KB)

Remappable Periphe rals

10-bit 1 Msps ADC (Channels)

Analog Comparators

USB On-The-Go (OTG)

CAN

CTMU

PMP

RTCC

DMA Channels (Programmable/Dedicated)

I/O Pins

JTAG

Remappable Pins

Timers/Capture/Compare

(2)

UART

SPI/I

External Interrupts

(3)

PIC32MX120F064H 64 QFN,

TQFP 64+3 8 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y

PIC32MX130F128H 64 QFN,

TQFP 128+3 16 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y

PIC32MX130F128L 100 TQFP 128+3 16 54 5/5/5 5 4 5 48 3 N 0 Y 2 Y Y 4/0 85 Y

100 TFBGA

PIC32MX230F128H 64 QFN,

TQFP 128+3 16 37 5/5/5 4 3 5 28 3 Y 0 Y 2 Y Y 4/2 49 Y

PIC32MX230F128L 100 TQFP 128+3 16 54 5/5/5 5 4 5 48 3 Y 0 Y 2 Y Y 4/2 81 Y

100 TFBGA

PIC32MX530F128H 64 QFN,

TQFP 128+3 16 37 5/5/5 4 3 5 28 3 Y 1 Y 2 Y Y 4/4 49 Y

PIC32MX530F128L 100 TQFP 128+3 16 54 5/5/5 5 4 5 48 3 Y 1 Y 2 Y Y 4/4 81 Y

100 TFBGA

PIC32MX150F256H 64 QFN,

TQFP 256+3 32 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y

PIC32MX150F256L 100 TQFP 256+3 32 54 5/5/5 5 4 5 48 3 N 0 Y 2 Y Y 4/0 85 Y

100 TFBGA

PIC32MX250F256H 64 QFN,

TQFP 256+3 32 37 5/5/5 4 3 5 28 3 Y 0 Y 2 Y Y 4/2 49 Y

PIC32MX250F256L 100 TQFP 256+3 32 54 5/5/5 5 4 5 48 3 Y 0 Y 2 Y Y 4/2 81 Y

100 TFBGA

PIC32MX550F256H 64 QFN,

TQFP 256+3 32 37 5/5/5 4 3 5 28 3 Y 1 Y 2 Y Y 4/4 49 Y

PIC32MX550F256L 100 TQFP 256+3 32 54 5/5/5 5 4 5 48 3 Y 1 Y 2 Y Y 4/4 81 Y

100 TFBGA

PIC32MX170F512H 64 QFN,

TQFP 512+3 64 37 5/5/5 4 3 5 28 3 N 0 Y 2 Y Y 4/0 53 Y

PIC32MX170F512L 100 TQFP 512+3 64 54 5/5/5 5 4 5 48 3 N 0 Y 2 Y Y 4/0 85 Y

100 TFBGA

PIC32MX270F512H 64 QFN,

TQFP 512+3 64 37 5/5/5 4 3 5 28 3 Y 0 Y 2 Y Y 4/2 49 Y

PIC32MX270F512L 100 TQFP 512+3 64 54 5/5/5 5 4 5 48 3 Y 0 Y 2 Y Y 4/2 81 Y

100 TFBGA

PIC32MX570F512H 64 QFN,

TQFP 512+3 64 37 5/5/5 4 3 5 28 3 Y 1 Y 2 Y Y 4/4 49 Y

PIC32MX570F512L 100 TQFP 512+3 64 54 5/5/5 5 4 5 48 3 Y 1 Y 2 Y Y 4/4 81 Y

100 TFBGA

Note 1: All devices feature 3 KB of Boot Flash memory.

2: Four out of five timers are remappable.

3: Four out of five external interrupts are remappable.

4: Please contact your local Microchip Sales Office for information regarding the availability of devices in the 100-pin TFBGA package.

 2014-2017 Microchip Technology Inc. DS60001290E-page 3

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Device Pin Tables

TABLE 2: PIN NAMES FOR 64-PIN GENERAL PURPOSE DEVICES

Pin # Full Pin Name Pin # Full Pin Name

1AN22/RPE5/PMD5/RE5 33 RPF3/RF3

2AN23/PMD6/RE6 34 RPF2/RF2

3AN27/PMD7/RE7 35 RPF6/SCK1/INT0/RF6

4AN16/C1IND/RPG6/SCK2/PMA5/RG6 36 SDA1/RG3

5AN17/C1INC/RPG7/PMA4/RG7 37 SCL1/RG2

6AN18/C2IND/RPG8/PMA3/RG8 38 V

7MCLR 39 OSC1/CLKI/RC12

8AN19/C2INC/RPG9/PMA2/RG9 40 OSC2/CLKO/RC15

9 V

41 V

10 V

42 RPD8/RTCC/RD8

11 AN5/C1INA/RPB5/RB5 43 RPD9/RD9

12 AN4/C1INB/RB4 44 RPD10/PMA15/RD10

13 PGED3/AN3/C2INA/RPB3/RB3 45 RPD11/PMA14/RD11

14 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 46 RPD0/RD0

15 PGEC1/V

REF

-/AN1/RPB1/CTED12/RB1 47 SOSCI/RPC13/RC13

16 PGED1/V

REF

+/AN0/RPB0/PMA6/RB0 48 SOSCO/RPC14/T1CK/RC14

17 PGEC2/AN6/RPB6/RB6 49 AN24/RPD1/RD1

18 PGED2/AN7/RPB7/CTED3/RB7 50 AN25/RPD2/RD2

19 AV

51 AN26/C3IND/RPD3/RD3

20 AV

52 RPD4/PMWR/RD4

21 AN8/RPB8/CTED10/RB8 53 RPD5/PMRD/RD5

22 AN9/RPB9/CTED4/PMA7/RB9 54 C3INC/RD6

23 TMS/CV

REFOUT

/AN10/RPB10/CTED11/PMA13/RB10 55 C3INB/RD7

24 TDO/AN11/PMA12/ RB11 56 V

CAP

25 V

57 V

26 V

58 C3INA/RPF0/RF0

27 TCK/AN12/PMA11/RB12 59 RPF1/RF1

28 TDI/AN13/PMA10/RB13 60 PMD0/RE0

29 AN14/RPB14/SCK3/CTED5/PMA1/RB14 61 PMD1/RE1

30 AN15/RPB15/OCFB/CTED6/PMA0/RB15 62 AN20/PMD2/RE2

31 RPF4/SDA2/PMA9/RF4 63 RPE3/CTPLS/PMD3/RE3

32 RPF5/SCL2/PMA8/RF5 64 AN21/PMD4/RE4

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.

2: Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 1 1.0 “I/O Ports” for more information.

3: Shaded pins are 5V tolerant.

4: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V

externally.

64-PIN QF N

(4)

AND TQFP (TOP VIEW)

PIC32MX120F064H

PIC32MX130F128H

PIC32MX150F256H

64 1

TQFP

QFN

(4)

PIC32MX170F512H

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 4  2014-2017 Microchip Technology Inc.

TABLE 3: PIN NAMES FOR 64-PIN USB DEVICES

Pin # Full Pin Name Pin # Full Pin Name

1AN22/RPE5/PMD5/RE5 33 USBID/RPF3/RF3

2AN23/PMD6/RE6 34 V

BUS

3AN27/PMD7/RE7 35 V

USB

4AN16/C1IND/RPG6/SCK2/PMA5/RG6 36 D-

5AN17/C1INC/RPG7/PMA4/RG7 37 D+

6AN18/C2IND/RPG8/PMA3/RG8 38 V

7MCLR 39 OSC1/CLKI/RC12

8AN19/C2INC/RPG9/PMA2/RG9 40 OSC2/CLKO/RC15

9 V

41 V

10 V

42 RPD8/RTCC/RD8

11 AN5/C1INA/RPB5/V

BUSON

/RB5 43 RPD9/SDA1/RD9

12 AN4/C1INB/RB4 44 RPD10/SCL1/PMA15/RD10

13 PGED3/AN3/C2INA/RPB3/RB3 45 RPD11/PMA14/RD11

14 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 46 RPD0/INT0/RD0

15 PGEC1/V

REF

-/AN1/RPB1/CTED12/RB1 47 SOSCI/RPC13/RC13

16 PGED1/V

REF

+/AN0/RPB0/PMA6/RB0 48 SOSCO/RPC14/T1CK/RC14

17 PGEC2/AN6/RPB6/RB6 49 AN24/RPD1/RD1

18 PGED2/AN7/RPB7/CTED3/RB7 50 AN25/RPD2/SCK1/RD2

19 AV

51 AN26/C3IND/RPD3/RD3

20 AV

52 RPD4/PMWR/RD4

21 AN8/RPB8/CTED10/RB8 53 RPD5/PMRD/RD5

22 AN9/RPB9/CTED4/PMA7/RB9 54 C3INC/RD6

23 TMS/CV

REFOUT

/AN10/RPB10/CTED11/PMA13/RB10 55 C3INB/RD7

24 TDO/AN11/PMA12/ RB11 56 V

CAP

25 V

57 V

26 V

58 C3INA/RPF0/RF0

27 TCK/AN12/PMA11/RB12 59 RPF1/RF1

28 TDI/AN13/PMA10/RB13 60 PMD0/RE0

29 AN14/RPB14/SCK3/CTED5/PMA1/RB14 61 PMD1/RE1

30 AN15/RPB15/OCFB/CTED6/PMA0/RB15 62 AN20/PMD2/RE2

31 RPF4/SDA2/PMA9/RF4 63 RPE3/CTPLS/PMD3/RE3

32 RPF5/SCL2/PMA8/RF5 64 AN21/PMD4/RE4

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.

2: Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 1 1.0 “I/O Ports” for more information.

3: Shaded pins are 5V tolerant.

4: The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to V

externally.

64-PIN QF N

(4)

AND TQFP (TOP VIEW)

PIC32MX530F128H

PIC32MX250F256H

PIC32MX270F512H

64 1

TQFP

QFN

(4)

PIC32MX550F256H

PIC32MX570F512H

PIC32MX230F128H

 2014-2017 Microchip Technology Inc. DS60001290E-page 5

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 4: PIN NAMES FOR 100-PIN GENERAL PURPOSE DEVICES

Pin # Full Pin Name Pin # Full Pin Name

1AN28/RG15 36 V

37 V

3AN22/RPE5/PMD5/RE5 38 TCK/CTED2/RA1

4 AN23/PMD6/RE6 39 AN34/RPF13/SCK3/RF13

5AN27/PMD7/RE7 40 AN35/RPF12/RF12

6 AN29/RPC1/RC1 41 AN12/PMA11/RB12

7AN30/RPC2/RC2 42 AN13/PMA10/RB13

8 AN31/RPC3/RC3 43 AN14/RPB14/CTED5/PMA1/RB14

9 RPC4/CTED7/RC4 44 AN15/RPB15/OCFB/CTED6/PMA0/RB15

10 AN16/C1IND/RPG6/SCK2/PMA5/RG6 45 V

11 AN17/C1INC/RPG7/PMA4/RG7 46 V

12 AN18/C2IND/RPG8/PMA3/RG8 47 AN36/RPD14/RD14

13 MCLR 48 AN37/RPD15/SCK4/RD15

14 AN19/C2INC/RPG9/PMA2/RG9 49 RPF4/PMA9/RF4

15 V

50 RPF5/PMA8/RF5

16 V

51 RPF3/RF3

17 TMS/CTED1/RA0 52 AN38/RPF2/RF2

18 AN32/RPE8/RE8 53 AN39/RPF8/RF8

19 AN33/RPE9/RE9 54 RPF7/RF7

20 AN5/C1INA/RPB5/RB5 55 RPF6/SCK1/INT0/RF6

21 AN4/C1INB/RB4 56 SDA1/RG3

22 PGED3/AN3/C2INA/RPB3/RB3 57 SCL1/RG2

23 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 58 SCL2/RA2

24 PGEC1/AN1/RPB1/CTED12/RB1 59 SDA2/RA3

25 PGED1/AN0/RPB0/RB0 60 TDI/CTED9/RA4

26 PGEC2/AN6/RPB6/RB6 61 TDO/RA5

27 PGED2/AN7/RPB7/CTED3/RB7 62 V

28 V

REF

-/PMA7/RA9 63 OSC1/CLKI/RC12

29 V

REF

+/PMA6/RA10 64 OSC2/CLKO/RC15

30 AV

65 V

31 AV

66 RPA14/RA14

32 AN8/RPB8/CTED10/RB8 67 RPA15/RA15

33 AN9/RPB9/CTED4/RB9 68 RPD8/RTCC/RD8

34 CV

REFOUT

/AN10/RPB10/CTED11/PMA13/RB10 69 RPD9/RD9

35 AN11/PMA12/RB11 70 RPD10/PMA15/RD10

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.

2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more

information.

3: Shaded pins are 5V tolerant.

100

100-PIN TQFP (TOP VIEW)

PIC32MX130F128L

PIC32MX170F512L

PIC32MX150F256L

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 6  2014-2017 Microchip Technology Inc.

71 RPD11/PMA14/RD11 86 V

72 RPD0/RD0 87 AN44/C3INA/RPF0/PMD11/RF0

73 SOSCI/RPC13/RC13 88 AN45/RPF1/PMD10/RF1

74 SOSCO/RPC14/T1CK/RC14 89 RPG1/PMD9/RG1

75 V

90 RPG0/PMD8/RG0

76 AN24/RPD1/RD1 91 RA6

77 AN25/RPD2/RD2 92 CTED8/RA7

78 AN26/C3IND/RPD3/RD3 93 AN46/PMD0/RE0

79 AN40/RPD12/PMD12/RD12 94 AN47/PMD1/RE1

80 AN41/PMD13/RD13 95 RG14

81 RPD4/PMWR/RD4 96 RG12

82 RPD5/PMRD/RD5 97 RG13

83 AN42/C3INC/PMD14/RD6 98 AN20/PMD2/RE2

84 AN43/C3INB/PMD15/RD7 99 RPE3/CTPLS/PMD3/RE3

85 V

CAP

100 AN21/PMD4/RE4

TABLE 4: PIN NAMES FOR 100-PIN GENERAL PURPOSE DEVICES (CONTINUED)

Pin # Full Pin Name Pin # Full Pin Name

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.

2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more

information.

3: Shaded pins are 5V tolerant.

100

100-PIN TQFP (TOP VIEW)

PIC32MX130F128L

PIC32MX170F512L

PIC32MX150F256L

 2014-2017 Microchip Technology Inc. DS60001290E-page 7

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 5: PIN NAMES FOR 100-PIN USB DEVICES

Pin # Full Pin Name Pin # Full Pin Name

1AN28/RG15 36 V

37 V

3AN22/RPE5/PMD5/RE5 38 TCK/CTED2/RA1

4 AN23/PMD6/RE6 39 AN34/RPF13/SCK3/RF13

5AN27/PMD7/RE7 40 AN35/RPF12/RF12

6 AN29/RPC1/RC1 41 AN12/PMA11/RB12

7AN30/RPC2/RC2 42 AN13/PMA10/RB13

8 AN31/RPC3/RC3 43 AN14/RPB14/CTED5/PMA1/RB14

9 RPC4/CTED7/RC4 44 AN15/RPB15/OCFB/CTED6/PMA0/RB15

10 AN16/C1IND/RPG6/SCK2/PMA5/RG6 45 V

11 AN17/C1INC/RPG7/PMA4/RG7 46 V

12 AN18/C2IND/RPG8/PMA3/RG8 47 AN36/RPD14/RD14

13 MCLR 48 AN37/RPD15/SCK4/RD15

14 AN19/C2INC/RPG9/PMA2/RG9 49 RPF4/PMA9/RF4

15 V

50 RPF5/PMA8/RF5

16 V

51 USBID/RPF3/RF3

17 TMS/CTED1/RA0 52 AN38/RPF2/RF2

18 AN32/RPE8/RE8 53 AN39/RPF8/RF8

19 AN33/RPE9/RE9 54 V

BUS

20 AN5/C1INA/RPB5/V

BUSON

/RB5 55 V

USB

21 AN4/C1INB/RB4 56 D-

22 PGED3/AN3/C2INA/RPB3/RB3 57 D+

23 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 58 SCL2/RA2

24 PGEC1/AN1/RPB1/CTED12/RB1 59 SDA2/RA3

25 PGED1/AN0/RPB0/RB0 60 TDI/CTED9/RA4

26 PGEC2/AN6/RPB6/RB6 61 TDO/RA5

27 PGED2/AN7/RPB7/CTED3/RB7 62 V

28 V

REF

-/PMA7/RA9 63 OSC1/CLKI/RC12

29 V

REF

+/PMA6/RA10 64 OSC2/CLKO/RC15

30 AV

65 V

31 AV

66 RPA14/SCL1/RA14

32 AN8/RPB8/CTED10/RB8 67 RPA15/SDA1/RA15

33 AN9/RPB9/CTED4/RB9 68 RPD8/RTCC/RD8

34 CV

REFOUT

/AN10/RPB10/CTED11/PMA13/RB10 69 RPD9/RD9

35 AN11/PMA12/RB11 70 RPD10/SCK1/PMA15/RD10

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.

2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more

information.

3: Shaded pins are 5V tolerant.

100

100-PIN TQFP (TOP VIEW)

PIC32MX530F128L

PIC32MX250F256L

PIC32MX270F512L

PIC32MX550F256L

PIC32MX570F512L

PIC32MX230F128L

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 8  2014-2017 Microchip Technology Inc.

71 RPD11/PMA14/RD11 86 V

72 RPD0/INT0/RD0 87 AN44/C3INA/RPF0/PMD11/RF0

73 SOSCI/RPC13/RC13 88 AN45/RPF1/PMD10/RF1

74 SOSCO/RPC14/T1CK/RC14 89 RPG1/PMD9/RG1

75 V

90 RPG0/PMD8/RG0

76 AN24/RPD1/RD1 91 RA6

77 AN25/RPD2/RD2 92 CTED8/RA7

78 AN26/C3IND/RPD3/RD3 93 AN46/PMD0/RE0

79 AN40/RPD12/PMD12/RD12 94 AN47/PMD1/RE1

80 AN41/PMD13/RD13 95 RG14

81 RPD4/PMWR/RD4 96 RG12

82 RPD5/PMRD/RD5 97 RG13

83 AN42/C3INC/PMD14/RD6 98 AN20/PMD2/RE2

84 AN43/C3INB/PMD15/RD7 99 RPE3/CTPLS/PMD3/RE3

85 V

CAP

100 AN21/PMD4/RE4

TABLE 5: PIN NAMES FOR 100-PIN USB DEVICES (CONTINUED)

Pin # Full Pin Name Pin # Full Pin Name

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin

Select” for restrictions.

2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more

information.

3: Shaded pins are 5V tolerant.

100

100-PIN TQFP (TOP VIEW)

PIC32MX530F128L

PIC32MX250F256L

PIC32MX270F512L

PIC32MX550F256L

PIC32MX570F512L

PIC32MX230F128L

 2014-2017 Microchip Technology Inc. DS60001290E-page  9
PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
Table of Contents
0 Device Overview ........................................................................................................................................................................ 13
0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 25
0 CPU............................................................................................................................................................................................ 35
0 Memory Organization ................................................................................................................................................................. 39
0 Interrupt Controller ..................................................................................................................................................................... 53
0 Flash Program Memory.............................................................................................................................................................. 63
0 Resets ........................................................................................................................................................................................ 69
0 Oscillator Configuration.............................................................................................................................................................. 73
0 Direct Memory Access (DMA) Controller ................................................................................................................................... 85
0 USB On-The-Go (OTG)............................................................................................................................................................ 105
0 I/O Ports ................................................................................................................................................................................... 129
0 Timer1 ...................................................................................................................................................................................... 159
0 Timer2/3, Timer4/5 ................................................................................................................................................................... 163
0 Watchdog Timer (WDT) ........................................................................................................................................................... 169
0 Input Capture............................................................................................................................................................................ 173
0 Output Compare....................................................................................................................................................................... 177
0 Serial Peripheral Interface (SPI)............................................................................................................................................... 181
0 Inter-Integrated Circuit (I
2
C) ..................................................................................................................................................... 191
0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 199
0 Parallel Master Port (PMP)....................................................................................................................................................... 207
0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 221
0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 231
0 Controller Area Network (CAN) ................................................................................................................................................ 243
0 Comparator .............................................................................................................................................................................. 271
0 Comparator Voltage Reference (CV
REF
) ................................................................................................................................. 275
0 Charge Time Measurement Unit (CTMU)  ............................................................................................................................... 279
0 Power-Saving Features ........................................................................................................................................................... 285
0 Special Features ...................................................................................................................................................................... 291
0 Instruction Set .......................................................................................................................................................................... 303
0 Development Support............................................................................................................................................................... 305
0 40 MHz Electrical Characteristics............................................................................................................................................. 309
0 50 MHz Electrical Characteristics............................................................................................................................................. 353
0 DC and AC Device Characteristics Graphs.............................................................................................................................. 359
0 Packaging Information.............................................................................................................................................................. 361
The Microchip Web Site..................................................................................................................................................................... 379
Customer Change Notification Service .............................................................................................................................................. 379
Customer Support .............................................................................................................................................................................. 379
Product Identification System ............................................................................................................................................................ 380

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 10  2014-2017 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

 2014-2017 Microchip Technology Inc. DS60001290E-page 11

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Referenced Sources

This device data sheet is based on the following

individual sections of the “PIC32 Family Reference

Manual”. These documents should be considered as

the general reference for the operation of a particular

module or device feature.

•Section 1. “Introduction” (DS60001127)

•Section 2. “CPU” (DS60001113)

•Section 3. “Memory Organization” (DS60001115)

•Section 5. “Flash Pr ogram Memor y ” (DS60001121)

•Section 6. “Oscillator Configuration” (DS60001112)

•Section 7. “Resets” (DS60001118)

•Section 8. “Interrupt Controller” (DS60001108)

•Section 9. “Watchdog Timer a nd Pow er- up T i me r” (DS60001114)

•Section 10. “Powe r-Saving Features” (DS60001130)

•Section 12. “I/O Ports” (DS60001120)

•Section 13. “Parallel Master Port (PMP)” (DS60001128)

•Section 14. “ Timers ” (DS60001105)

•Section 15. “Input Capture” (DS60001122)

•Section 16. “Output Compare” (DS60001111)

•Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104)

•Section 19. “Comparator” (DS60001110)

•Section 20. “Comparator Voltage Reference (CV

REF

)” (DS60001109)

•Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)

•Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)

•Section 24. “Inter-Integrated Circuit (I

C)” (DS60001116)

•Section 27. “USB On-The-Go (OTG)” (DS60001126)

•Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)

•Section 31. “Direc t Memory Access (D MA) Controller ” (DS60001117)

•Section 32. “Configuration” (DS60001124)

•Section 33. “ Pr o gram m ing and D i ag nos tic s” (DS60001129)

•Section 34. “Co ntrol ler Area Network (CAN)” (DS60001123)

•Section 37. “Charge Time Measurement Unit (CTMU)” (DS60001167)

Note: To access the documents listed below,

browse to the documentation section of

the Microchip web site

(www.microchip.com).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 12  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 13

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for

PIC32MX1XX/2XX/5XX 64/100-pin devices.

Figure 1-1 illustrates a general block diagram of the

core and peripheral modules in the PIC32MX1XX/2XX/

5XX 64/100-pin family of devices.

Table 1-1 lists the functions of the various pins shown

in the pinout diagrams.

FIGURE 1-1: PIC32M X1 XX /2XX/5XX 64/100-PIN BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-

pin family of devices. It is not intended to

be a comprehensive reference source.

To complement the information in this

data sheet, refer to the related section of

the “PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32).

Note: Not all features are available on all devices. Refer to TABLE 1: “PIC32MX1XX/2XX/5XX 64/100-pin Controller

Family Features” for the list of features by device.

UART1-5

Comparators

PORTA/CNA

PORTD/CND

PORTE/CNE

PORTF/CNF

PORTG/CNG

PORTB/CNB

JTAG

Priority

DMAC ICD

MIPS32

M4K

CPU Core

IS DS

EJTAG INT

Bus Matrix

Data RAM Peripheral Bridge

32-bit wide Flash

32 32

Peripheral Bus Clocked by PBCLK

Program Flash

Memory Controller

32 32

Interrupt

Controller

BSCAN

PORTC/CNC

PMP

I2C1,2

SPI1-4

IC1-5

PWM

OC1-5

OSC1/CLKI

OSC2/CLKO

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

CAP

OSC/S

OSC

Oscillators

PLL

DIVIDERS

SYSCLK

PBCLK

Peripheral Bus Clocked by SYSCLK

USB

PLL-USB

USBCLK

RTCC

10-bit ADC

Timer1-5

Remappable

Pins

CTMU

1-3

CAN

 2014-2017 Microchip Technology Inc. DS60001290E-page 14

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 1-1: PINOUT I/O DESCRI PTIONS

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

AN0 16 25 I Analog

Analog input channels.

AN1 15 24 I Analog

AN2 14 23 I Analog

AN3 13 22 I Analog

AN4 12 21 I Analog

AN5 11 20 I Analog

AN6 17 26 I Analog

AN7 18 27 I Analog

AN8 21 32 I Analog

AN9 22 33 I Analog

AN10 23 34 I Analog

AN11 24 35 I Analog

AN12 27 41 I Analog

AN13 28 42 I Analog

AN14 29 43 I Analog

AN15 30 44 I Analog

AN16 4 10 I Analog

AN17 5 11 I Analog

AN18 6 12 I Analog

AN19 8 14 I Analog

AN20 62 98 I Analog

AN21 64 100 I Analog

AN22 1 3 I Analog

AN23 2 4 I Analog

AN24 49 76 I Analog

AN25 50 77 I Analog

AN26 51 78 I Analog

AN27 3 5 I Analog

AN28 — 1 I Analog

AN29 — 6 I Analog

AN30 — 7 I Analog

AN31 — 8 I Analog

AN32 — 18 I Analog

AN33 — 19 I Analog

AN34 — 39 I Analog

AN35 — 40 I Analog

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 15

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

AN36 — 47 I Analog

Analog input channels.

AN37 — 48 I Analog

AN38 — 52 I Analog

AN39 — 53 I Analog

AN40 — 79 I Analog

AN41 — 80 I Analog

AN42 — 83 I Analog

AN43 — 84 I Analog

AN44 — 87 I Analog

AN45 — 88 I Analog

AN46 — 93 I Analog

AN47 — 94 I Analog

CLKI 39 63 I ST/CMOS External clock source input. Always associated with OSC1 pin

function.

CLKO 40 64 O —

Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode. Optionally functions as CLKO in RC

and EC modes. Always associated with the OSC2 pin

function.

OSC1 39 63 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC

mode; CMOS otherwise.

OSC2 40 64 O —

Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode. Optionally functions as CLKO in RC

and EC modes.

SOSCI 47 73 I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS

otherwise.

SOSCO 48 74 O — 32.768 kHz low-power oscillator crystal output.

IC1 PPS PPS I ST

Capture Input 1-5

IC2 PPS PPS I ST

IC3 PPS PPS I ST

IC4 PPS PPS I ST

IC5 PPS PPS I ST

OC1 PPS PPS O ST Output Compare Output 1

OC2 PPS PPS O ST Output Compare Output 2

OC3 PPS PPS O ST Output Compare Output 3

OC4 PPS PPS O ST Output Compare Output 4

OC5 PPS PPS O ST Output Compare Output 5

OCFA PPS PPS I ST Output Compare Fault A Input

OCFB 30 44 I ST Output Compare Fault B Input

TABLE 1-1: PINOUT I/O DESCRI PTIONS (CONTINUED)

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 16

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

INT0 35

(1)

, 46

(2)

(1)

, 72

(2)

I ST External Interrupt 0

INT1 PPS PPS I ST External Interrupt 1

INT2 PPS PPS I ST External Interrupt 2

INT3 PPS PPS I ST External Interrupt 3

INT4 PPS PPS I ST External Interrupt 4

RA0 — 17 I/O ST

PORTA is a bidirectional I/O port

RA1 — 38 I/O ST

RA2 — 58 I/O ST

RA3 — 59 I/O ST

RA4 — 60 I/O ST

RA5 — 61 I/O ST

RA6 — 91 I/O ST

RA7 — 92 I/O ST

RA9 — 28 I/O ST

RA10 — 29 I/O ST

RA14 — 66 I/O ST

RA15 — 67 I/O ST

RB0 16 25 I/O ST

PORTB is a bidirectional I/O port

RB1 15 24 I/O ST

RB2 14 23 I/O ST

RB3 13 22 I/O ST

RB4 12 21 I/O ST

RB5 11 20 I/O ST

RB6 17 26 I/O ST

RB7 18 27 I/O ST

RB8 21 32 I/O ST

RB9 22 33 I/O ST

RB10 23 34 I/O ST

RB11 24 35 I/O ST

RB12 27 41 I/O ST

RB13 28 42 I/O ST

RB14 29 43 I/O ST

RB15 30 44 I/O ST

TABLE 1-1: PINOUT I/O DESCRI PTIONS (CONTINUED)

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 17

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

RC1 — 6 I/O ST

PORTC is a bidirectional I/O port

RC2 — 7 I/O ST

RC3 — 8 I/O ST

RC4 — 9 I/O ST

RC12 39 63 I/O ST

RC13 47 73 I/O ST

RC14 48 74 I/O ST

RC15 40 64 I/O ST

RD0 46 72 I/O ST

PORTD is a bidirectional I/O port

RD1 49 76 I/O ST

RD2 50 77 I/O ST

RD3 51 78 I/O ST

RD4 52 81 I/O ST

RD5 53 82 I/O ST

RD6 54 83 I/O ST

RD7 55 84 I/O ST

RD8 42 68 I/O ST

RD9 43 69 I/O ST

RD10 44 70 I/O ST

RD11 45 71 I/O ST

RD12 — 79 I/O ST

RD13 — 80 I/O ST

RD14 — 47 I/O ST

RD15 — 48 I/O ST

RE0 60 93 I/O ST

PORTE is a bidirectional I/O port

RE1 61 94 I/O ST

RE2 62 98 I/O ST

RE3 63 99 I/O ST

RE4 64 100 I/O ST

RE5 1 3 I/O ST

RE6 2 4 I/O ST

RE7 3 5 I/O ST

RE8 — 18 I/O ST

RE9 — 19 I/O ST

TABLE 1-1: PINOUT I/O DESCRI PTIONS (CONTINUED)

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 18

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

RF0 58 87 I/O ST

PORTF is a bidirectional I/O port

RF1 59 88 I/O ST

RF2 34

(3)

52 I/O ST

RF3 33 51 I/O ST

RF4 31 49 I/O ST

RF5 32 50 I/O ST

RF6 35

(1)

I/O ST

RF7 — 54

(4)

I/O ST

RF8 — 53 I/O ST

RF12 — 40 I/O ST

RF13 — 39 I/O ST

RG0 — 90 I/O ST

PORTG is a bidirectional I/O port

RG1 — 89 I/O ST

RG2 37

(1)

I/O ST

RG3 36

(1)

I/O ST

RG6 4 10 I/O ST

RG7 5 11 I/O ST

RG8 6 12 I/O ST

RG9 8 14 I/O ST

RG12 — 96 I/O ST

RG13 — 97 I/O ST

RG14 — 95 I/O ST

RG15 — 1 I/O ST

T1CK 48 74 I ST Timer1 External Clock Input

T2CK PPS PPS I ST Timer2 External Clock Input

T3CK PPS PPS I ST Timer3 External Clock Input

T4CK PPS PPS I ST Timer4 External Clock Input

T5CK PPS PPS I ST Timer5 External Clock Input

U1CTS PPS PPS I ST UART1 Clear to Send

U1RTS PPS PPS O — UART1 Ready to Send

U1RX PPS PPS I ST UART1 Receive

U1TX PPS PPS O — UART1 Transmit

U2CTS PPS PPS I ST UART2 Clear to Send

U2RTS PPS PPS O — UART2 Ready to Send

U2RX PPS PPS I ST UART2 Receive

U2TX PPS PPS O — UART2 Transmit

TABLE 1-1: PINOUT I/O DESCRI PTIONS (CONTINUED)

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 19

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

U3CTS PPS PPS I ST UART3 Clear to Send

U3RTS PPS PPS O — UART3 Ready to Send

U3RX PPS PPS I ST UART3 Receive

U3TX PPS PPS O — UART3 Transmit

U4CTS PPS PPS I ST UART4 Clear to Send

U4RTS PPS PPS O — UART4 Ready to Send

U4RX PPS PPS I ST UART4 Receive

U4TX PPS PPS O — UART4 Transmit

U5CTS — PPS I ST UART5 Clear to Send

U5RTS — PPS O — UART5 Ready to Send

U5RX — PPS I ST UART5 Receive

U5TX — PPS O — UART5 Transmit

SCK1 35

(1)

, 50

(2)

(1)

, 70

(2)

I/O ST Synchronous Serial Clock Input/Output for SPI1

SDI1 PPS PPS I — SPI1 Data In

SDO1 PPS PPS O ST SPI1 Data Out

SS1 PPS PPS I/O — SPI1 Slave Synchronization for Frame Pulse I/O

SCK2 4 10 I/O ST Synchronous Serial Clock Input/Output for SPI2

SDI2 PPS PPS I — SPI2 Data In

SDO2 PPS PPS O ST SPI2 Data Out

SS2 PPS PPS I/O — SPI2 Slave Synchronization for Frame Pulse I/O

SCK3 29 39 I/O ST Synchronous Serial Clock Input/Output for SPI3

SDI3 PPS PPS I — SPI3 Data In

SDO3 PPS PPS O ST SPI3 Data Out

SS3 PPS PPS I/O — SPI3 Slave Synchronization for Frame Pulse I/O

SCK4 — 48 I/O ST Synchronous Serial Clock Input/Output for SPI4

SDI4 — PPS I — SPI4 Data In

SDO4 — PPS O ST SPI4 Data Out

SS4 — PPS I/O — SPI4 Slave Synchronization for Frame Pulse I/O

SCL1 37

(1)

, 44

(2)

(1)

, 66

(2)

I/O ST Synchronous Serial Clock Input/Output for I2C1

SDA1 36

(1)

, 43

(2)

(1)

, 67

(2)

I/O ST Synchronous Serial Data Input/Output for I2C1

SCL2 32 58 I/O ST Synchronous Serial Clock Input/Output for I2C2

SDA2 31 59 I/O ST Synchronous Serial Data Input/Output for I2C2

TMS 23 17 I ST JTAG Test Mode Select Pin

TCK 27 38 I ST JTAG Test Clock Input Pin

TDI 28 60 I — JTAG Test Clock Input Pin

TDO 24 61 O — JTAG Test Clock Output Pin

TABLE 1-1: PINOUT I/O DESCRI PTIONS (CONTINUED)

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 20

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

RTCC 42 68 O — Real-Time Clock Alarm Output

REFOUT

23 34 O Analog Comparator Voltage Reference (Output)

C1INA 11 20 I Analog

Comparator 1 Inputs

C1INB 12 21 I Analog

C1INC 5 11 I Analog

C1IND 4 10 I Analog

C2INA 13 22 I Analog

Comparator 2 Inputs

C2INB 14 23 I Analog

C2INC 8 14 I Analog

C2IND 6 12 I Analog

C3INA 58 87 I Analog

Comparator 3 Inputs

C3INB 55 84 I Analog

C3INC 54 83 I Analog

C3IND 51 78 I Analog

C1OUT PPS PPS O — Comparator 1 Output

C2OUT PPS PPS O — Comparator 2 Output

C3OUT PPS PPS O — Comparator 3 Output

PMALL 30 44 O TTL/ST Parallel Master Port Address Latch Enable Low Byte

PMALH 29 43 O TTL/ST Parallel Master Port Address Latch Enable High Byte

PMA0 30 44 O TTL/ST Parallel Master Port Address bit 0 Input (Buffered Slave

modes) and Output (Master modes)

PMA1 29 43 O TTL/ST Parallel Master Port Address bit 0 Input (Buffered Slave

modes) and Output (Master modes)

TABLE 1-1: PINOUT I/O DESCRI PTIONS (CONTINUED)

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 21

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

PMA2 8 14 O TTL/ST

Parallel Master Port data (Demultiplexed Master mode) or

Address/Data (Multiplexed Master modes)

PMA3 6 12 O TTL/ST

PMA4 5 11 O TTL/ST

PMA5 4 10 O TTL/ST

PMA6 16 29 O TTL/ST

PMA7 22 28 O TTL/ST

PMA8 32 50 O TTL/ST

PMA9 31 49 O TTL/ST

PMA10 28 42 O TTL/ST

PMA11 27 41 O TTL/ST

PMA12 24 35 O TTL/ST

PMA13 23 34 O TTL/ST

PMA14 45 71 O TTL/ST

PMA15 44 70 O TTL/ST

PMCS1 45 71 O TTL/ST

Parallel Master Port data (Demultiplexed Master mode) or

Address/Data (Multiplexed Master modes)

PMCS2 44 70 O TTL/ST

PMD0 60 93 I/O TTL/ST

PMD1 61 94 I/O TTL/ST

PMD2 62 98 I/O TTL/ST

PMD3 63 99 I/O TTL/ST

PMD4 64 100 I/O TTL/ST

PMD5 1 3 I/O TTL/ST

PMD6 2 4 I/O TTL/ST

PMD7 3 5 I/O TTL/ST

PMD8 — 90 I/O TTL/ST

PMD9 — 89 I/O TTL/ST

PMD10 — 88 I/O TTL/ST

PMD11 — 87 I/O TTL/ST

PMD12 — 79 I/O TTL/ST

PMD13 — 80 I/O TTL/ST

PMD14 — 83 I/O TTL/ST

PMD15 — 84 I/O TTL/ST

PMRD 53 82 O — Parallel Master Port Read Strobe

PMWR 52 81 O — Parallel Master Port Write Strobe

BUS(2)

34 54 I Analog USB Bus Power Monitor

TABLE 1-1: PINOUT I/O DESCRI PTIONS (CONTINUED)

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 22

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

USB

(2)

35 55 P — USB internal transceiver supply. If the USB module is not

used, this pin must be connected to V

BUSON(2)

11 20 O — USB Host and OTG bus power control Output

D+

(2)

37 57 I/O Analog USB D+

D-

(2)

36 56 I/O Analog USB D-

USBID

(2)

33 51 I ST USB OTG ID Detect

PGED1 16 25 I/O ST Data I/O pin for Programming/Debugging Communication

Channel 1

PGEC1 15 24 I ST Clock Input pin for Programming/Debugging Communication

Channel 1

PGED2 18 27 I/O ST Data I/O Pin for Programming/Debugging Communication

Channel 2

PGEC2 17 26 I ST Clock Input Pin for Programming/Debugging Communication

Channel 2

PGED3 13 22 I/O ST Data I/O Pin for Programming/Debugging Communication

Channel 3

PGEC3 14 23 I ST Clock Input Pin for Programming/Debugging Communication

Channel 3

CTED1 — 17 I ST CTMU External Edge Input 1

CTED2 — 38 I ST CTMU External Edge Input 2

CTED3 18 27 I ST CTMU External Edge Input 3

CTED4 22 33 I ST CTMU External Edge Input 4

CTED5 29 43 I ST CTMU External Edge Input 5

CTED6 30 44 I ST CTMU External Edge Input 6

CTED7 — 9 I ST CTMU External Edge Input 7

CTED8 — 92 I ST CTMU External Edge Input 8

CTED9 — 60 I ST CTMU External Edge Input 9

CTED10 21 32 I ST CTMU External Edge Input 10

CTED11 23 34 I ST CTMU External Edge Input 11

CTED12 15 24 I ST CTMU External Edge Input 12

CTED13 14 23 I ST CTMU External Edge Input 13

C1RX PPS PPS I ST Enhanced CAN Receive

C1TX PPS PPS O ST Enhanced CAN Transmit

TABLE 1-1: PINOUT I/O DESCRI PTIONS (CONTINUED)

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 23

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

MCLR 713IST

Master Clear (Reset) input. This pin is an active-low Reset to

the device.

19 30 P P Positive supply for analog modules. This pin must be

connected at all times.

20 31 P P Ground reference for analog modules

10, 26, 38,

2, 16, 37,

46, 62, 86 P — Positive supply for peripheral logic and I/O pins

CAP

56 85 P — Capacitor for Internal Voltage Regulator

9, 25, 41 15, 36, 45,

65, 75 P — Ground reference for logic and I/O pins

REF

+ 16 29 P Analog Analog Voltage Reference (High) Input

REF

- 15 28 P Analog Analog Voltage Reference (Low) Input

TABLE 1-1: PINOUT I/O DESCRI PTIONS (CONTINUED)

Pin Name

Pin Number

Type Buffer

Type Description

64-pin

QFN/

TQFP

100-pin

TQFP

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input O = Output

ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer P = Power

Note 1: This pin is only available on devices without a USB module.

2: This pin is only available on devices with a USB module.

3: This pin is not available on 64-pin devices with a USB module.

4: This pin is only available on 100-pin devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 24

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page  25
PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
2.0 GUIDELINES FOR GETTING 
STARTED WITH 32-BIT MCUS
2.1 Basic Connection Requirements
Getting started with the PIC32MX1XX/2XX/5XX 64/
100-pin family of 32-bit Microcontrollers (MCUs) 
requires attention to a minimal set of device pin 
connections before proceeding with development. The 
following is a list of pin names, which must always be 
connected:
•All V
DD
 and V
SS
 pins (see 2.2 “Decoupling 
Capacitors”)
•All AV
DD
 and AV
SS
 pins, even if the ADC module is 
not used (see 2.2 “Decoupling Ca pac itors”)
•V
CAP
 pin (see 2.3 “Capacitor on Internal Voltage 
Regulator (V
CAP
)”) 
•MCLR pin (see 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins, used for In-Circuit Serial 
Programming (ICSP™) and debugging purposes 
(see 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator 
source is used (see 2.7 “External O scilla tor Pins”)
The following pins may be required:
V
REF
+/V
REF
- pins, used when external voltage 
reference for the ADC module is implemented.
2.2 Decoupling Capacitors
The use of decoupling capacitors on power supply 
pins, such as V
DD
, V
SS
, AV
DD
 and AV
SS
 is required. 
See Figure 2-1.
Consider the following criteria when using decoupling 
capacitors:
•Value and type of capacitor: A value of 0.1 µF 
(100 nF), 10-20V is recommended. The capacitor 
should be a low Equivalent Series Resistance 
(low-ESR) capacitor and have resonance 
frequency in the range of 20 MHz and higher. It is 
further recommended that ceramic capacitors be 
used.
•Placement on the printed circuit board: The 
decoupling capacitors should be placed as close 
to the pins as possible. It is recommended that 
the capacitors be placed on the same side of the 
board as the device. If space is constricted, the 
capacitor can be placed on another layer on the 
PCB using a via; however, ensure that the trace 
length from the pin to the capacitor is within one-
quarter inch (6 mm) in length.
•Handling hi gh frequency nois e: If the board is 
experiencing high frequency noise, upward of 
tens of MHz, add a second ceramic-type capacitor 
in parallel to the above described decoupling 
capacitor. The value of the second capacitor can 
be in the range of 0.01 µF to 0.001 µF. Place this 
second capacitor next to the primary decoupling 
capacitor. In high-speed circuit designs, consider 
implementing a decade pair of capacitances as 
close to the power and ground pins as possible. 
For example, 0.1 µF in parallel with 0.001 µF.
•Maximiz ing perform anc e: On the board layout 
from the power supply circuit, run the power and 
return traces to the decoupling capacitors first, 
and then to the device pins. This ensures that the 
decoupling capacitors are first in the power chain. 
Equally important is to keep the trace length 
between the capacitor and the power pins to a 
minimum thereby reducing PCB track inductance.
Note: This data sheet summarizes the features 
of the PIC32MX1XX/2XX/5XX 64/100-pin 
family of devices. It is not intended to be a 
comprehensive reference source. To 
complement the information in this data 
sheet, refer to the related section of the 
“PI C32 Fa mily R efere nce Ma nual” , which 
is available from the Microchip web site 
(www.microchip.com/PIC32).
Note: The AV
DD
 and AV
SS
 pins must be 
connected, regardless of ADC use and 
the ADC voltage reference source.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 26  2014-2017 Microchip Technology Inc.

FIGURE 2-1: RECOMME NDED

MINIMUM CONNECTION

2.2.1 BULK CAPACITORS

The use of a bulk capacitor is recommended to improve

power supply stability. Typical values range from 4.7 µF

to 47 µF. This capacitor should be located as close to

the device as possible.

2.3 Capacit or on Internal Voltage

Regulator (V

CAP

)

2.3.1 INTERNAL REGULATOR MODE

A low-ESR (3 ohm) capacitor is required on the V

CAP

pin, which is used to stabilize the internal voltage regu-

lator output. The V

CAP

pin must not be connected to

, and must have a C

EFC

capacitor, with at least a

6V rating, connected to ground. The type can be

ceramic or tantalum. Refer to Section 31.0 “40 MHz

Electrical Characteristics” for additional information

on C

EFC

specifications.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions:

• Device Reset

• Device programming and debugging

Pulling The MCLR pin low generates a device Reset.

Figure 2-2 illustrates a typical MCLR circuit. During

device programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (V

and V

) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R and C will need to be adjusted based on the

application and PCB requirements.

For example, as illustrated in Figure 2-2, it is

recommended that the capacitor C, be isolated from

the MCLR pin during programming and debugging

operations.

Place the components illustrated in Figure 2-2 within

one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

PIC32

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

10K

MCLR

0.1 µF

Ceramic

(2)

Note 1:

If the USB module is not used, this pin must be

connected to V

As an option, instead of a hard-wired connection, an

inductor (L1) can be substituted between V

and

to improve ADC noise rejection. The inductor

impedance should be less than 3



and the inductor

capacity greater than 10 mA.



Where:

CNV

--------------

2LC

-----------------------

2fC

----------------------





(i.e., ADC conversion rate/2)

Connect

(2)

USB

(1)

CAP

Tantalum or

ceramic 10 µF

ESR  3

(3)

Aluminum or electrolytic capacitors should not be

used. ESR





from -40ºC to 125ºC @ SYSCLK

frequency (i.e., MIPS).

0.1 µF

Note 1:

470









will limit any current flowing into

MCLR from the external capacitor C, in the event of

MCLR pin breakdown, due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS). Ensure that the

MCLR pin V

and V

specifications are met without

interfering with the Debug/Programmer tools.

The capacitor can be sized to prevent unintentional

Resets from brief glitches or to extend the device

Reset period during POR.

No pull-ups or bypass capacitors are allowed on

active debug/program PGECx/PGEDx pins.

(1)

10k

MCLR

PIC32

1 k



0.1 µF

(2)

PGECx

(3)

PGEDx

(3)

ICSP™

 2014-2017 Microchip Technology Inc. DS60001290E-page 27

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming™ (ICSP™) and debugging pur-

poses. It is recommended to keep the trace length

between the ICSP connector and the ICSP pins on the

device as short as possible. If the ICSP connector is

expected to experience an ESD event, a series resistor

is recommended, with the value in the range of a few

tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin input voltage high

) and input voltage low (V

) requirements.

Ensure that the “Communication Channel Select” (i.e.,

PGECx/PGEDx pins) programmed into the device

matches the physical connections for the ICSP to

MPLAB

ICD 3 or MPLAB REAL ICE™.

For more information on MPLAB ICD 3 and MPLAB

REAL ICE connection requirements, refer to the follow-

ing documents that are available on the Microchip web

site.

•“Using MPLAB

ICD 3” (poster) DS50001765

•“MPLAB

ICD 3 Design Advi sory” DS50001764

•“MPLAB

REAL ICE™ In-Circuit Debugger

User’s Guide” DS50001616

•“Using MPLAB

REAL ICE™ Emulator” (poster)

DS50001749

2.6 JTAG

The TMS, TDO, TDI and TCK pins are used for testing

and debugging according to the Joint Test Action

Group (JTAG) standard. It is recommended to keep the

trace length between the JTAG connector and the

JTAG pins on the device as short as possible. If the

JTAG connector is expected to experience an ESD

event, a series resistor is recommended, with the value

in the range of a few tens of Ohms, not to exceed 100

Ohms.

Pull-up resistors, series diodes and capacitors on the

TMS, TDO, TDI and TCK pins are not recommended

as they will interfere with the programmer or debugger

communications to the device. If such discrete

components are an application requirement, they

should be removed from the circuit during

programming and debugging. Alternatively, refer to the

AC/DC characteristics and timing requirements

information in the respective device Flash

programming specification for information on

capacitive loading limits and pin input voltage high (V

)

and input voltage low (V

) requirements

2.7 External Oscillator Pins

Many MCUs have options for at least two oscillators: a

high-frequency primary oscillator and a low-frequency

secondary oscillator (refer to Section 8.0 “Oscillator

Configuration” for details).

The oscillator circuit should be placed on the same side

of the board as the device. Also, place the oscillator cir-

cuit close to the respective oscillator pins, not exceed-

ing one-half inch (12 mm) distance between them. The

load capacitors should be placed next to the oscillator,

on the same side of the board. Use a grounded copper

pour around the oscillator circuit to isolate them from

surrounding circuits. The grounded copper pour should

be routed directly to the MCU ground. Do not run any

signal traces or power traces inside the ground pour.

Also, if using a two-sided board, avoid any traces on

the other side of the board where the crystal is placed.

A suggested layout is illustrated in Figure 2-3.

FIGURE 2-3: SUGGESTED OSCILLATOR

CIRCUIT PLACEMENT

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 28  2014-2017 Microchip Technology Inc.

2.7.1 CRYSTAL OSCILLATOR DESIGN

CONSIDERATION

The following examples are used to calculate the

Primary Oscillator loading capacitor values:

•C

= PIC32_OSC2_Pin Capacitance = ~4-5 pF

•C

OUT

= PIC32_OSC1_Pin Capacitance = ~4-5 pF

• C1 and C2 = XTAL manufacturing recommended

loading capacitance

• Estimated PCB stray capacitance, (i.e.,12 mm

length) = 2.5 pF

EXAMPLE 2-1: CRYSTAL LOAD CAPAC ITOR

CALCULATION

The following tips are used to increase oscillator gain,

(i.e., to increase peak-to-peak oscillator signal):

• Select a crystal with a lower “minimum” power drive

rating

• Select an crystal oscillator with a lower XTAL

manufacturing “ESR” rating.

• Add a parallel resistor across the crystal. The smaller

the resistor value the greater the gain. It is recom-

mended to stay in the range of 600k to 1M

• C1 and C2 values also affect the gain of the oscillator.

The lower the values, the higher the gain.

• C2/C1 ratio also affects gain. To increase the gain,

make C1 slightly smaller than C2, which will also help

start-up performance.

2.7.1.1 Additional Microchip References

• AN588 “PICmicro

Microcon trol le r Osc ill ato r

Design Guide”

• AN826 “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro

Device s”

• AN849 “Basic PICmicro

Oscillator Design”

FIGURE 2-4: PRIMARY CRYSTAL

OSCILLATOR CIRCUIT

RECOMMENDATIONS

Note: Do not add excessive gain such that the

oscillator signal is clipped, flat on top of

the sine wave. If so, you need to reduce

the gain or add a series resistor, RS, as

shown in circuit “C” in Figure 2-4. Failure

to do so will stress and age the crystal,

which can result in an early failure. Adjust

the gain to trim the max peak-to-peak to

-0.6V. When measuring the oscilla-

tor signal you must use a FET scope

probe or a probe with  1.5 pF or the

scope probe itself will unduly change the

gain and peak-to-peak levels.

Crystal manufacturer recommended:

= 15

Therefore:

LOAD

= {( [

] * [

OUT

] ) / [

OUT

] }

estimated oscillator PCB stray capacitance

= {( [5 + 15][5 + 15] ) / [5 + 15 + 15 + 5] } + 2.5

= {( [20][20]) / [40] } + 2.5

= 10 + 2.5 = 12.5

Rounded to the nearest standard value or 13 pF in this example for

Primary Oscillator crystals “C1” and “C2”.

OSC2 OSC1

Typical XT

(4-10 MHz)

Circuit A

OSC2 OSC1

Typical HS

(10-25 MHz)

Circuit B

OSC2 OSC1

Typical XT/HS

(4-25 MHz)

Circuit C

OSC2 OSC1

Not Recommended

Circuit D

Not Recommended

OSC2 OSC1

Circuit E

 2014-2017 Microchip Technology Inc. DS60001290E-page 29

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

2.8 Unused I/Os

Unused I/O pins should not be allowed to float as

inputs. They can be configured as outputs and driven

to a logic-low state.

Alternatively, inputs can be reserved by connecting the

pin to V

through a 1k to 10k resistor and configuring

the pin as an input.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 30  2014-2017 Microchip Technology Inc.

2.9 Considerations When Interfacing

to Remotely Powered Circuits

2.9.1 NON-5V TOLERANT INPUT PINS

A quick review of the absolute maximum rating section

in 31.0 “40 MHz Elect rical Charac teris tics” will indi-

cate that the voltage on any non-5v tolerant pin may not

exceed AV

+ 0.3V. Figure 2-5 shows an exam-

ple of a remote circuit using an independent power

source, which is powered while connected to a PIC32

non-5V tolerant circuit that is not powered.

FIGURE 2-5: PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE

Current Flow

CPU LOGIC

TRIS

ANSEL

I/O IN

I/O OUT

VSS

PIC32

AN2/RB0

On/Off

PIC32

POWER

SUPPLY

Non-5V Tolerant

Pin Architecture

VDD

Remote

0.3V dVIH d3.6V

Remote

GND

Note: When V

power is OFF.

 2014-2017 Microchip Technology Inc. DS60001290E-page 31

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Without proper signal isolation, on non-5V tolerant

pins, the remote signal can power the PIC32 device

through the high side ESD protection diodes.

Besides violating the absolute maximum rating

specification when V

of the PIC32 device is

restored and ramping up or ramping down, it can

also negatively affect the internal Power-on Reset

(POR) and Brown-out Reset (BOR) circuits, which

can lead to improper initialization of internal PIC32

logic circuits. In these cases, it is recommended to

implement digital or analog signal isolation as

depicted in Figure 2-6, as appropriate. This is

indicative of all industry microcontrollers and not just

Microchip products.

TABLE 2-1: EXAMPLES OF DIGITAL/

ANALOG ISOLATORS WITH

OPTIONAL LEVEL

TRANSLATION

FIGURE 2-6: DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS

Example Digital/Analog

Signal Isolation Circuits

Inductive Coupling

Capacitive Coupling

Opto Coupling

Analog/Digital Switch

ADuM7241 / 40 ARZ (1 Mbps) X — — —

ADuM7241 / 40 CRZ (25 Mbps) X — — —

ISO721 — X — —

LTV-829S (2 Channel) — — X —

LTV-849S (4 Channel) — — X —

FSA266 / NC7WB66 — — — X

External VDD PIC32

PIC32 VDD

Opto Digital

ISOLATOR IN1

VSS

REMOTE_IN

Digital Isolator PIC32 VDD

VSS

PIC32

Conn

IN1

OUT1

REMOTE_IN

REMOTE_OUT

External VDD

REMOTE_IN

External VDD

PIC32

PIC32 VDD

VSS

Digital Isolator

Analog_IN1

Analog_OUT2

External_VDD1

PIC32 VDD

VSS

PIC32

Conn Analog_IN2

Analog Switch

Analog / Digital Isolator

ENB

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 32  2014-2017 Microchip Technology Inc.

2.9.2 5V TOLERANT INPUT PINS

The internal high side diode on 5V tolerant pins are

bussed to an internal floating node, rather than being

connected to V

, as shown in Figure 2-7. Voltages

on these pins, if V

< 2.3V, should not exceed

roughly 3.2V relative to V

of the PIC32 device.

Voltage of 3.6V or higher will violate the absolute

maximum specification, and will stress the oxide

layer separating the high side floating node, which

impacts device reliability. If a remotely powered

“digital-only” signal can be guaranteed to always be

 3.2V relative to Vss on the PIC32 device side, a

5V tolerant pin could be used without the need for a

digital isolator. This is assuming there is not a

ground loop issue, logic ground of the two circuits

not at the same absolute level, and a remote logic

low input is not less than V

- 0.3V.

FIGURE 2-7: PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE

CPU LOGIC

TRIS

ANSEL

I/O IN

I/O OUT

VSS

PIC32

RG10

On/Off

PIC32

POWER

SUPPLY

5V Tolerant Pin

Architecture

VDD

Remote

VIH = 2.5V

Remote

GND

Floating Bus

Oxide BV = 3.6V

if VDD < 2.3V

OXIDE

 2014-2017 Microchip Technology Inc. DS60001290E-page 33

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

2.10 Typical Application Connection

Examples

Examples of typical application connections are shown

in Figure 2-8, Figure 2-9, and Figure 2-10.

FIGURE 2-8: CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION

FIGURE 2-9: AUDIO PLAYBACK APPLICATION

CTMU

Current Source

ADC

Microchip

mTouch

Library

User

Application

Microchip

Graphics

Library

Read the Touch Sensors

Process Samples

Display Data

Parallel

Master

Port

LCD Controller

Frame

Buffer

Display

Controller

PMD<7:0>

LCD

Panel

PIC32MX1XX/2XX/5XX

To AN6 To AN7 To AN8 To AN11

R1 R1 R1

AN0

AN1

AN11

To A N 0

To A N1

To A N 5

AN9

PMWR

To AN9

Audio

Codec

Display

PMP

SPI

USB

PMD<7:0>

Stereo Headphones

Speaker

PIC32MX1XX/2XX/5XX

Host

PMWR

MMC SD

SDI

REFCLKO

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 34  2014-2017 Microchip Technology Inc.

FIGURE 2-10: LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH

PROJECTED CAPACITIVE TOUCH

LCD Display

PIC32MX1XX/2XX/5XX

SRAM

CTMU

Microchip mTouch

DMA PMP

ADC

Projected Capacitive

Touch Overlay

GFX Libraries

External Frame Buffer

ANx

 2014-2017 Microchip Technology Inc. DS60001290E-page 35

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

3.0 CPU

The the MIPS32

M4K

Processor Core is the heart of

the PIC32MX1XX/2XX/5XX 64/100-pin device proces-

sor. The CPU fetches instructions, decodes each

instruction, fetches source operands, executes each

instruction and writes the results of instruction

execution to the proper destinations.

3.1 Features

• 5-stage pipeline

• 32-bit address and data paths

• MIPS32

Enhanced Architecture (Release 2):

- Multiply-accumulate and multiply-subtract

instructions

- Targeted multiply instruction

- Zero/One detect instructions

-WAIT instruction

- Conditional move instructions (MOVN, MOVZ)

- Vectored interrupts

- Programmable exception vector base

- Atomic interrupt enable/disable

- Bit field manipulation instructions

• MIPS16e

Code Compression:

- 16-bit encoding of 32-bit instructions to

improve code density

- Special PC-relative instructions for efficient

loading of addresses and constants

-SAVE and RESTORE macro instructions for

setting up and tearing down stack frames

within subroutines

- Improved support for handling 8 and 16-bit

data types

• Simple Fixed Mapping Translation (FMT)

Mechanism:

• Simple Dual Bus Interface:

- Independent 32-bit address and data buses

- Transactions can be aborted to improve

interrupt latency

• Autonomous Multiply/Divide Unit (MDU):

- Maximum issue rate of one 32x16 multiply

per clock

- Maximum issue rate of one 32x32 multiply

every other clock

- Early-in iterative divide. Minimum 11 and

maximum 33 clock latency (dividend (rs) sign

extension-dependent)

• Power Control:

- Minimum frequency: 0 MHz

- Low-Power mode (triggered by WAIT instruction)

- Extensive use of local gated clocks

• EJTAG Debug:

- Support for single stepping

- Virtual instruction and data address/value

-Breakpoints

FIGURE 3-1: MIPS32

M4K

PROCESSOR CORE

BLOC K DI AGRAM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 2. “CPU”

(DS60001113) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32). Resources

for the MIPS32

M4K

Processor Core

are available at http://www.imgtec.com.

CPU

MDU

Execution Core

(RF/ALU/Shift) FMT

TAP

EJTAG

Bus Interface

Power

Management

System

Co-processor

Off-chip Debug Interface

Bus Matrix

Dual Bus Interface

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 36  2014-2017 Microchip Technology Inc.

3.2 Architectur e Overview

The MIPS32

M4K

processor core contains several

logic blocks working together in parallel, providing an

efficient high-performance computing engine. The

following blocks are included with the core:

• Execution Unit

• Multiply/Divide Unit (MDU)

• System Control Coprocessor (CP0)

• Fixed Mapping Translation (FMT)

• Dual Internal Bus interfaces

• Power Management

• MIPS16e

Support

• Enhanced JTAG (EJTAG) Controller

3.2.1 EXECUTION UNIT

The MIPS32

M4K

processor core execution unit

implements a load/store architecture with single-cycle

ALU operations (logical, shift, add, subtract) and an

autonomous multiply/divide unit. The core contains

thirty-two 32-bit General Purpose Registers (GPRs)

used for integer operations and address calculation.

The execution unit includes:

• 32-bit adder used for calculating the data address

• Address unit for calculating the next instruction

address

• Logic for branch determination and branch target

address calculation

• Load aligner

• Bypass multiplexers used to avoid stalls when

executing instruction streams where data

producing instructions are followed closely by

consumers of their results

• Leading Zero/One detect unit for implementing

the CLZ and CLO instructions

• Arithmetic Logic Unit (ALU) for performing bitwise

logical operations

• Shifter and store aligner

3.2.2 MULTIPLY/DIVIDE UNIT (MDU)

The MIPS32

M4K

processor core includes a Multi-

ply/Divide Unit (MDU) that contains a separate pipeline

for multiply and divide operations. This pipeline oper-

ates in parallel with the Integer Unit (IU) pipeline and

does not stall when the IU pipeline stalls. This allows

MDU operations to be partially masked by system stalls

and/or other integer unit instructions.

The high-performance MDU consists of a 32x16 booth

recoded multiplier, result/accumulation registers (HI

and LO), a divide state machine, and the necessary

multiplexers and control logic. The first number shown

(‘32’ of 32x16) represents the rs operand. The second

number (‘16’ of 32x16) represents the rt operand. The

PIC32 core only checks the value of the latter (rt) oper-

and to determine how many times the operation must

pass through the multiplier. The 16x16 and 32x16

operations pass through the multiplier once. A 32x32

operation passes through the multiplier twice.

The MDU supports execution of one 16x16 or 32x16

multiply operation every clock cycle; 32x32 multiply

operations can be issued every other clock cycle.

Appropriate interlocks are implemented to stall the

issuance of back-to-back 32x32 multiply operations.

The multiply operand size is automatically determined

by logic built into the MDU.

Divide operations are implemented with a simple 1 bit

per clock iterative algorithm. An early-in detection

checks the sign extension of the dividend (rs) operand.

If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit

wide rs, 15 iterations are skipped and for a 24-bit wide

rs, 7 iterations are skipped. Any attempt to issue a sub-

sequent MDU instruction while a divide is still active

causes an IU pipeline stall until the divide operation is

completed.

Table 3-1 lists the repeat rate (peak issue rate of cycles

until the operation can be reissued) and latency (num-

ber of cycles until a result is available) for the PIC32

core multiply and divide instructions. The approximate

latency and repeat rates are listed in terms of pipeline

clocks.

TABLE 3- 1: MIPS32

M4K

PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/

DIVIDE UNIT LATENCIES AND REPEAT RATES

Op code Operand Size (mul rt) (div rs)Latency Repeat Rate

MULT/MULTU, MADD/MADDU,

MSUB/MSUBU 16 bits 1 1

32 bits 2 2

MUL 16 bits 2 1

32 bits 3 2

DIV/DIVU 8 bits 12 11

16 bits 19 18

24 bits 26 25

32 bits 33 32

 2014-2017 Microchip Technology Inc. DS60001290E-page 37

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

The MIPS architecture defines that the result of a

multiply or divide operation be placed in the HI and LO

registers. Using the Move-From-HI (MFHI) and Move-

From-LO (MFLO) instructions, these values can be

transferred to the General Purpose Register file.

In addition to the HI/LO targeted operations, the

MIPS32

architecture also defines a multiply instruction,

MUL, which places the least significant results in the pri-

mary register file instead of the HI/LO register pair. By

avoiding the explicit MFLO instruction required when

using the LO register, and by supporting multiple desti-

nation registers, the throughput of multiply-intensive

operations is increased.

Two other instructions, Multiply-Add (MADD) and

Multiply-Subtract (MSUB), are used to perform the

multiply-accumulate and multiply-subtract operations.

The MADD instruction multiplies two numbers and then

adds the product to the current contents of the HI and

LO registers. Similarly, the MSUB instruction multiplies

two operands and then subtracts the product from the

HI and LO registers. The MADD and MSUB operations

are commonly used in DSP algorithms.

3.2.3 SYSTEM CONTROL 

COPROCESSOR (CP0)

In the MIPS architecture, CP0 is responsible for the

virtual-to-physical address translation, the exception

control system, the processor’s diagnostics capability,

the operating modes (Kernel, User and Debug) and

whether interrupts are enabled or disabled. Configura-

tion information, such as presence of options like

MIPS16e

, is also available by accessing the CP0

registers, listed in Tabl e 3-2.

TABLE 3-2: COPROCESSOR 0 REGISTERS

Number Register

Name Function

0-6 Reserved Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core.

7HWREna Enables access via the RDHWR instruction to selected hardware registers.

8BadVAddr

(1)

Reports the address for the most recent address-related exception.

9Count

(1)

Processor cycle count.

10 Reserved Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core.

11 Compare

(1)

Timer interrupt control.

12 Status

(1)

Processor status and control.

12 IntCtl

(1)

Interrupt system status and control.

13 Cause

(1)

Cause of last general exception.

14 EPC

(1)

Program counter at last exception.

15 PRId Processor identification and revision.

15 EBASE Exception vector base register.

16 Config Configuration register.

16 Config1 Configuration register 1.

16 Config2 Configuration register 2.

16 Config3 Configuration register 3.

17-22 Reserved Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core.

23 Debug

(2)

Debug control and exception status.

24 DEPC

(2)

Program counter at last debug exception.

25-29 Reserved Reserved in the PIC32MX1XX/2XX/5XX 64/100-pin family core.

30 ErrorEPC

(1)

Program counter at last error.

31 DESAVE

(2)

Debug handler scratchpad register.

Note 1: Registers used in exception processing.

2: Registers used during debug.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 38  2014-2017 Microchip Technology Inc.

Coprocessor 0 also contains the logic for identifying

and managing exceptions. Exceptions can be caused

by a variety of sources, including alignment errors in

data, external events or program errors. Ta b l e 3-3 lists

the exception types in order of priority.

TABLE 3- 3: MIPS32

M4K

PROCESSOR CORE EXCEPTION TYPES

3.3 Power Management

The MIPS

M4K

processor core offers a number of

power management features, including low-power

design, active power management and power-down

modes of operation. The core is a static design that

supports slowing or Halting the clocks, which reduces

system power consumption during Idle periods.

3.3.1 INSTRUCTION-CONTROLLED

POWER MANAGEMENT

The mechanism for invoking Power-Down mode is

through execution of the WAIT instruction. For more

information on power management, see Section 27.0

“Power-Saving Fea tures ”.

3.3.2 LOCAL CLOCK GATING

The majority of the power consumed by the PIC32MX-

1XX/2XX/5XX 64/100-pin family core is in the clock

tree and clocking registers. The PIC32MX family uses

extensive use of local gated-clocks to reduce this

dynamic power consumption.

3.4 EJTAG Debug Support

The MIPS

M4K

processor core provides for an

Enhanced JTAG (EJTAG) interface for use in the soft-

ware debug of application and kernel code. In addition

to standard User mode and Kernel modes of operation,

the M4K

core provides a Debug mode that is entered

after a debug exception (derived from a hardware

breakpoint, single-step exception, etc.) is taken and

continues until a Debug Exception Return (DERET)

instruction is executed. During this time, the processor

executes the debug exception handler routine.

The EJTAG interface operates through the Test Access

Port (TAP), a serial communication port used for trans-

ferring test data in and out of the core. In addition to the

standard JTAG instructions, special instructions

defined in the EJTAG specification define which

registers are selected and how they are used.

Exception Description

Reset Assertion MCLR or a Power-on Reset (POR).

DSS EJTAG debug single step.

DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the

EjtagBrk bit in the ECR register.

NMI Assertion of NMI signal.

Interrupt Assertion of unmasked hardware or software interrupt signal.

DIB EJTAG debug hardware instruction break matched.

AdEL Fetch address alignment error. Fetch reference to protected address.

IBE Instruction fetch bus error.

DBp EJTAG breakpoint (execution of SDBBP instruction).

Sys Execution of SYSCALL instruction.

Bp Execution of BREAK instruction.

RI Execution of a reserved instruction.

CpU Execution of a coprocessor instruction for a coprocessor that is not enabled.

CEU Execution of a CorExtend instruction when CorExtend is not enabled.

Ov Execution of an arithmetic instruction that overflowed.

Tr Execution of a trap (when trap condition is true).

DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).

AdEL Load address alignment error. Load reference to protected address.

AdES Store address alignment error. Store to protected address.

DBE Load or store bus error.

DDBL EJTAG data hardware breakpoint matched in load data compare.

 2014-2017 Microchip Technology Inc. DS60001290E-page 39

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

4.0 MEMORY ORGANIZATION

PIC32MX1XX/2XX/5XX 64/100-pin microcontrollers

provide 4 GB of unified virtual memory address space.

All memory regions, including program, data memory,

SFRs and Configuration registers, reside in this

address space at their respective unique addresses.

The program and data memories can be optionally par-

titioned into user and kernel memories. In addition, the

data memory can be made executable, allowing

PIC32MX1XX/2XX/5XX 64/100-pin devices to execute

from data memory.

The key features include:

• 32-bit native data width

• Separate User (KUSEG) and Kernel (KSEG0/

KSEG1) mode address space

• Flexible program Flash memory partitioning

• Flexible data RAM partitioning for data and

program space

• Separate boot Flash memory for protected code

• Robust bus exception handling to intercept 

runaway code

• Simple memory mapping with Fixed Mapping

Translation (FMT) unit

4.1 Memory Layout

PIC32MX1XX/2XX/5XX 64/100-pin microcontrollers

implement two address schemes: virtual and physical.

All hardware resources, such as program memory,

data memory and peripherals, are located at their

respective physical addresses. Virtual addresses are

exclusively used by the CPU to fetch and execute

instructions as well as access peripherals. Physical

addresses are used by bus master peripherals, such as

DMA and the Flash controller, that access memory

independently of the CPU.

The memory maps for the PIC32MX1XX/2XX/5XX 64/

100-pin devices are illustrated in Figure 4-1 through

Figure 4-4.

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be a

comprehensive reference source.For

detailed information, refer to Section 3.

“Memory Organization” (DS60001115)

in the “PIC 32 Famil y Refe rence M anual” ,

which is available from the Microchip

web site (www.microchip.com/PIC32).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 40  2014-2017 Microchip Technology Inc.

FIGURE 4-1: MEMORY MAP FOR DEVICES WITH 64 KB OF PROGRAM MEMORY + 8 KB RAM

Virtual

Memory Map

(1)

Physical

Memory Map

(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD010000

0xBD00FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0002000

0xA0001FFF

RAM

(2)

0xA0000000 0x1FC00C00

Reserved Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D010000 0x1F800000

0x9D00FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D010000

Reserved Program Flash

(2)

0x1D00FFFF

0x80002000

0x80001FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00002000

Reserved RAM

(2)

0x00001FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-

tion code provided by end-user development tools (refer to the specific development tool

documentation for information).

KSEG1KSEG0

 2014-2017 Microchip Technology Inc. DS60001290E-page 41

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 4-2: MEMORY MAP FOR DEVICES WITH 128 KB OF PROGRAM MEMORY + 16 KB RAM

Virtual

Memory Map

(1)

Physical

Memory Map

(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD020000

0xBD01FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0004000

0xA0003FFF

RAM

(2)

0xA0000000 0x1FC00C00

Reserved Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D020000 0x1F800000

0x9D01FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D020000

Reserved Program Flash

(2)

0x1D01FFFF

0x80004000

0x80003FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00004000

Reserved RAM

(2)

0x00003FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-

tion code provided by end-user development tools (refer to the specific development tool

documentation for information).

KSEG1KSEG0

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 42  2014-2017 Microchip Technology Inc.

FIGURE 4-3: MEMORY MAP FOR DEVICES WITH 256 KB OF PROGRAM MEMORY + 32 KB RAM

Virtual

Memory Map

(1)

Physical

Memory Map

(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD040000

0xBD03FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF

RAM

(2)

0xA0000000 0x1FC00C00

Reserved Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D040000 0x1F800000

0x9D03FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D040000

Reserved Program Flash

(2)

0x1D03FFFF

0x80008000

0x80007FFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM

(2)

0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-

tion code provided by end-user development tools (refer to the specific development tool

documentation for information).

KSEG1KSEG0

 2014-2017 Microchip Technology Inc. DS60001290E-page 43

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 4-4: MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY + 64 KB RAM

Virtual

Memory Map

(1)

Physical

Memory Map

(1)

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD080000

0xBD07FFFF

Program Flash

(2)

0xBD000000

Reserved

0xA0010000

0xA000FFFF

RAM

(2)

0xA0000000 0x1FC00C00

Reserved Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D080000 0x1F800000

0x9D07FFFF

Program Flash

(2)

Reserved

0x9D000000 0x1D080000

Reserved Program Flash

(2)

0x1D07FFFF

0x80010000

0x8000FFFF

RAM

(2)

0x1D000000

Reserved

0x80000000 0x00010000

Reserved RAM

(2)

0x0000FFFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-

tion code provided by end-user development tools (refer to the specific development tool

documentation for information).

KSEG1KSEG0

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TABLE 4-1: SFR MEMORY MAP

Peripheral V irtual Address

Base Offset Start

Interrupt Controller

0xBF88

0x1000

Bus Matrix 0x2000

DMA 0x3000

USB 0x5000

PORTA-PORTG 0x6000

CAN1 0xB000

Watchdog Timer

0xBF80

0x0000

RTCC 0x0200

Timer1-Timer5 0x0600

IC1-IC5 0x2000

OC1-OC5 0x3000

I2C1-I2C2 0x5000

SPI1-SPI4 0x5800

UART1-UART5 0x6000

PMP 0x7000

ADC1 0x9000

DAC 0x9800

Comparator 1, 2, 3 0xA000

Oscillator 0xF000

Device and Revision ID 0xF200

Flash Controller 0xF400

PPS 0xFA00

Configuration 0xBFC0 0x0BF0

 2014-2017 Microchip Technology Inc. DS60001290E-page 45

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

4.2 Special Function Register Maps

TABLE 4-2: BUS MATRIX REGISTER MAP

Virt ual Addr ess

(BF88_#)

Name

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

2000 BMXCON

(1)

31:16 — — — — — BMXCHEDMA — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 041F

15:0 — — — — — — — — — BMXWSDRM — — — BMXARB<2:0> 0047

2010 BMXDKPBA

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDKPBA<15:0> 0000

2020 BMXDUDBA

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUDBA<15:0> 0000

2030 BMXDUPBA

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUPBA<15:0> 0000

2040 BMXDRMSZ 31:16 BMXDRMSZ<31:0> xxxx

15:0 xxxx

2050 BMXPUPBA

(1)

31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000

15:0 BMXPUPBA<15:0> 0000

2060 BMXPFMSZ 31:16 BMXPFMSZ<31:0> xxxx

15:0 xxxx

2070 BMXBOOTSZ 31:16 BMXBOOTSZ<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Register s” for more information.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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4.3 Control Registers

the RAM and Flash memory partitions for data and

code.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — BMX

ERRIXI

BMX

ERRICD

BMX

ERRDMA

BMX

ERRDS

BMX

ERRIS

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1

—BMX

WSDRM — — — BMXARB<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 31-21 Unimplemented: Read as ‘0’

bit 20 BMXERRIXI: Enable Bus Error from IXI bit

1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus

0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus

bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit

1 = Enable bus error exceptions for unmapped address accesses initiated from ICD

0 = Disable bus error exceptions for unmapped address accesses initiated from ICD

bit 18 BMXERRDMA: Bus Error from DMA bit

1 = Enable bus error exceptions for unmapped address accesses initiated from DMA

0 = Disable bus error exceptions for unmapped address accesses initiated from DMA

bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)

1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access

0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access

bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)

1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access

0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access

bit 15-7 Unimplemented: Read as ‘0’

bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit

1 = Data RAM accesses from CPU have one wait state for address setup

0 = Data RAM accesses from CPU have zero wait states for address setup

bit 5-3 Unimplemented: Read as ‘0’

bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits

111 = Reserved (using these configuration modes will produce undefined behavior)

•

011 = Reserved (using these configuration modes will produce undefined behavior)

010 = Arbitration Mode 2

001 = Arbitration Mode 1 (default)

000 = Arbitration Mode 0

 2014-2017 Microchip Technology Inc. DS60001290E-page 47

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

BMXDKPBA<15:8>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDKPBA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits

When non-zero, this value selects the relative base address for kernel program space in RAM

bit 9-0 BMXDKPBA<9:0>: Read-Only bits

Value is always ‘0’, which forces 1 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel

mode data usage.

2: The value in this register must be less than or equal to BMXDRMSZ.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

BMXDUDBA<15:8>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDUDBA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits

When non-zero, the value selects the relative base address for User mode data space in RAM, the value

must be greater than BMXDKPBA.

bit 9-0 BMXDUDBA<9:0>: Read-Only bits

Value is always ‘0’, which forces 1 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel

mode data usage.

2: The value in this register must be less than or equal to BMXDRMSZ.

 2014-2017 Microchip Technology Inc. DS60001290E-page 49

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

BMXDUPBA<15:8>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDUPBA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits

When non-zero, the value selects the relative base address for User mode program space in RAM,

BMXDUPBA must be greater than BMXDUDBA.

bit 9-0 BMXDUPBA<9:0>: Read-Only bits

Value is always ‘0’, which forces 1 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel

mode data usage.

2: The value in this register must be less than or equal to BMXDRMSZ.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 50  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

RRRRR R R R

BMXDRMSZ<31:24>

23:16

RRRRR R R R

BMXDRMSZ<23:16>

15:8

RRRRR R R R

BMXDRMSZ<15:8>

7:0

RRRRR R R R

BMXDRMSZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits

Static value that indicates the size of the Data RAM in bytes:

0x00002000 = Device has 8 KB RAM

0x00004000 = Device has 16 KB RAM

0x00008000 = Device has 32 KB RAM

0x00010000 = Device has 64 KB RAM

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — BMXPUPBA<19:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXPUPBA<15:8>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXPUPBA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-20 Unimplemented: Read as ‘0’

bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits

bit 10-0 BMXPUPBA<10:0>: Read-Only bits

Value is always ‘0’, which forces 2 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel

mode data usage.

2: The value in this register must be less than or equal to BMXPFMSZ.

 2014-2017 Microchip Technology Inc. DS60001290E-page 51

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

RRRRR R R R

BMXPFMSZ<31:24>

23:16

RRRRR R R R

BMXPFMSZ<23:16>

15:8

RRRRR R R R

BMXPFMSZ<15:8>

7:0

RRRRR R R R

BMXPFMSZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits

Static value that indicates the size of the PFM in bytes:

0x00010000 = Device has 64 KB Flash

0x00020000 = Device has 128 KB Flash

0x00040000 = Device has 256 KB Flash

0x00080000 = Device has 512 KB Flash

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R R R R R R R R

BMXBOOTSZ<31:24>

23:16

R R R R R R R R

BMXBOOTSZ<23:16>

15:8

R R R R R R R R

BMXBOOTSZ<15:8>

7:0

R R R R R R R R

BMXBOOTSZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits

Static value that indicates the size of the Boot PFM in bytes:

0x00000C00 = Device has 3 KB Boot Flash

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 52  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 53

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

5.0 INTERRUPT CONTROLLER

PIC32MX1XX/2XX/5XX 64/100-pin devices generate

interrupt requests in response to interrupt events from

peripheral modules. The interrupt control module exists

externally to the CPU logic and prioritizes the interrupt

events before presenting them to the CPU.

The PIC32MX1XX/2XX/5XX 64/100-pin interrupt

module includes the following features:

• Up to 76 interrupt sources

• Up to 46 interrupt vectors

• Single and multi-vector mode operations

• Five external interrupts with edge polarity control

• Interrupt proximity timer

• Seven user-selectable priority levels for each

vector

• Four user-selectable subpriority levels within each

priority

• Software can generate any interrupt

• User-configurable interrupt vector table location

• User-configurable interrupt vector spacing

FIGURE 5-1: INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 8. “Interrupt

Controller” (DS60001108) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32).

Note: The dedicated shadow register set is not

available on these devices.

Interrupt Controller

Interrupt Requests

Vector Number

CPU Core

Priority Level

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 54  2014-2017 Microchip Technology Inc.

TABLE 5-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION

Interrupt Source

(1)

IRQ # Vector

Interrupt Bit Location Persistent

Interrupt

Flag Enable Priority Sub-priority

Highest Natural Order Priority

CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No

CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No

CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No

INT0 – External Interrupt 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> No

T1 – Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> No

IC1E – Input Capture 1 Error 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> Yes

IC1 – Input Capture 1 6 5 IFS0<6> IEC0<6> IPC1<12:10> IPC1<9:8> Yes

OC1 – Output Compare 1 7 6 IFS0<7> IEC0<7> IPC1<20:18> IPC1<17:16> No

INT1 – External Interrupt 1 8 7 IFS0<8> IEC0<8> IPC1<28:26> IPC1<25:24> No

T2 – Timer2 9 8 IFS0<9> IEC0<9> IPC2<4:2> IPC2<1:0> No

IC2E – Input Capture 2 10 9 IFS0<10> IEC0<10> IPC2<12:10> IPC2<9:8> Yes

IC2 – Input Capture 2 11 9 IFS0<11> IEC0<11> IPC2<12:10> IPC2<9:8> Yes

OC2 – Output Compare 2 12 10 IFS0<12> IEC0<12> IPC2<20:18> IPC2<17:16> No

INT2 – External Interrupt 2 13 11 IFS0<13> IEC0<13> IPC2<28:26> IPC2<25:24> No

T3 – Timer3 14 12 IFS0<14> IEC0<14> IPC3<4:2> IPC3<1:0> No

IC3E – Input Capture 3 15 13 IFS0<15> IEC0<15> IPC3<12:10> IPC3<9:8> Yes

IC3 – Input Capture 3 16 13 IFS0<16> IEC0<16> IPC3<12:10> IPC3<9:8> Yes

OC3 – Output Compare 3 17 14 IFS0<17> IEC0<17> IPC3<20:18> IPC3<17:16> No

INT3 – External Interrupt 3 18 15 IFS0<18> IEC0<18> IPC3<28:26> IPC3<25:24> No

T4 – Timer4 19 16 IFS0<19> IEC0<19> IPC4<4:2> IPC4<1:0> No

IC4E – Input Capture 4 Error 20 17 IFS0<20> IEC0<20> IPC4<12:10> IPC4<9:8> Yes

IC4 – Input Capture 4 21 17 IFS0<21> IEC0<21> IPC4<12:10> IPC4<9:8> Yes

OC4 – Output Compare 4 22 18 IFS0<22> IEC0<22> IPC4<20:18> IPC4<17:16> No

INT4 – External Interrupt 4 23 19 IFS0<23> IEC0<23> IPC4<28:26> IPC4<25:24> No

T5 – Timer5 24 20 IFS0<24> IEC0<24> IPC5<4:2> IPC5<1:0> No

IC5E – Input Capture 5 Error 25 21 IFS0<25> IEC0<25> IPC5<12:10> IPC5<9:8> Yes

IC5 – Input Capture 5 26 21 IFS0<26> IEC0<26> IPC5<12:10> IPC5<9:8> Yes

OC5 – Output Compare 5 27 22 IFS0<27> IEC0<27> IPC5<20:18> IPC5<17:16> No

AD1 – ADC1 Convert done 28 23 IFS0<28> IEC0<28> IPC5<28:26> IPC5<25:24> Yes

FSCM – Fail-Safe Clock Monitor 29 24 IFS0<29> IEC0<29> IPC6<4:2> IPC6<1:0> No

RTCC – Real-Time Clock and Calendar 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8> No

FCE – Flash Control Event 31 26 IFS0<31> IEC0<31> IPC6<20:18> IPC6<17:16> No

CMP1 – Comparator Interrupt 32 27 IFS1<0> IEC1<0> IPC6<28:26> IPC6<25:24> No

CMP2 – Comparator Interrupt 33 28 IFS1<1> IEC1<1> IPC7<4:2> IPC7<1:0> No

USB – USB Interrupts 34 29 IFS1<2> IEC1<2> IPC7<12:10> IPC7<9:8> Yes

SPI1E – SPI1 Fault 35 30 IFS1<3> IEC1<3> IPC7<20:18> IPC7<17:16> Yes

SPI1RX – SPI1 Receive Done 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> Yes

SPI1TX – SPI1 Transfer Done 37 30 IFS1<5> IEC1<5> IPC7<20:18> IPC7<17:16> Yes

U1E – UART1 Fault 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> Yes

U1RX – UART1 Receive Done 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24> Yes

U1TX – UART1 Transfer Done 40 31 IFS1<8> IEC1<8> IPC7<28:26> IPC7<25:24> Yes

I2C1B – I2C1 Bus Collision Event 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> Yes

I2C1S – I2C1 Slave Event 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0> Yes

I2C1M – I2C1 Master Event 43 32 IFS1<11> IEC1<11> IPC8<4:2> IPC8<1:0> Yes

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX 1XX/2XX/5XX 64/100-pin Contro ller

Family Features” for the list of available peripherals.

2: This interrupt source is not available on 64-pin devices.

 2014-2017 Microchip Technology Inc. DS60001290E-page 55

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

CNA – PORTA Input Change Interrupt 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8> Yes

CNB – PORTB Input Change Interrupt 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8> Yes

CNC – PORTC Input Change Interrupt 46 33 IFS1<14> IEC1<14> IPC8<12:10> IPC8<9:8> Yes

CND – PORTD Input Change Interrupt 47 33 IFS1<15> IEC1<15> IPC8<12:10> IPC8<9:8> Yes

CNE – PORTE Input Change Interrupt 48 33 IFS1<16> IEC1<16> IPC8<12:10> IPC8<9:8> Yes

CNF – PORTF Input Change Interrupt 49 33 IFS1<17> IEC1<17> IPC8<12:10> IPC8<9:8> Yes

CNG – PORTG Input Change Interrupt 50 33 IFS1<18> IEC1<18> IPC8<12:10> IPC8<9:8> Yes

PMP – Parallel Master Port 51 34 IFS1<19> IEC1<19> IPC8<20:18> IPC8<17:16> Yes

PMPE – Parallel Master Port Error 52 34 IFS1<20> IEC1<20> IPC8<20:18> IPC8<17:16> Yes

SPI2E – SPI2 Fault 53 35 IFS1<21> IEC1<21> IPC8<28:26> IPC8<25:24> Yes

SPI2RX – SPI2 Receive Done 54 35 IFS1<22> IEC1<22> IPC8<28:26> IPC8<25:24> Yes

SPI2TX – SPI2 Transfer Done 55 35 IFS1<23> IEC1<23> IPC8<28:26> IPC8<25:24> Yes

U2E – UART2 Error 56 36 IFS1<24> IEC1<24> IPC9<4:2> IPC9<1:0> Yes

U2RX – UART2 Receiver 57 36 IFS1<25> IEC1<25> IPC9<4:2> IPC9<1:0> Yes

U2TX – UART2 Transmitter 58 36 IFS1<26> IEC1<26> IPC9<4:2> IPC9<1:0> Yes

I2C2B – I2C2 Bus Collision Event 59 37 IFS1<27> IEC1<27> IPC9<12:10> IPC9<9:8> Yes

I2C2S – I2C2 Slave Event 60 37 IFS1<28> IEC1<28> IPC9<12:10> IPC9<9:8> Yes

I2C2M – I2C2 Master Event 61 37 IFS1<29> IEC1<29> IPC9<12:10> IPC9<9:8> Yes

U3E – UART3 Error 62 38 IFS1<30> IEC1<30> IPC9<20:18> IPC9<17:16> Yes

U3RX – UART3 Receiver 63 38 IFS1<31> IEC1<31> IPC9<20:18> IPC9<17:16> Yes

U3TX – UART3 Transmitter 64 38 IFS2<0> IEC2<0> IPC9<20:18> IPC9<17:16> Yes

U4E – UART4 Error 65 39 IFS2<1> IEC2<1> IPC9<28:26> IPC9<25:24> Yes

U4RX – UART4 Receiver 66 39 IFS2<2> IEC2<2> IPC9<28:26> IPC9<25:24> Yes

U4TX – UART4 Transmitter 67 39 IFS2<3> IEC2<3> IPC9<28:26> IPC9<25:24> Yes

U5E – UART5 Error

(2)

68 40 IFS2<4> IEC2<4> IPC10<4:2> IPC10<1:0> Yes

U5RX – UART5 Receiver

(2)

69 40 IFS2<5> IEC2<5> IPC10<4:2> IPC10<1:0> Yes

U5TX – UART5 Transmitter

(2)

70 40 IFS2<6> IEC2<6> IPC10<4:2> IPC10<1:0> Yes

CTMU – CTMU Event

(2)

71 41 IFS2<7> IEC2<7> IPC10<12:10> IPC10<9:8> Yes

DMA0 – DMA Channel 0 72 42 IFS2<8> IEC2<8> IPC10<20:18> IPC10<17:16> No

DMA1 – DMA Channel 1 73 43 IFS2<9> IEC2<9> IPC10<28:26> IPC10<25:24> No

DMA2 – DMA Channel 2 74 44 IFS2<10> IEC2<10> IPC11<4:2> IPC11<1:0> No

DMA3 – DMA Channel 3 75 45 IFS2<11> IEC2<11> IPC11<12:10> IPC11<9:8> No

CMP3 – Comparator 3 Interrupt 76 46 IFS2<12> IEC2<12> IPC11<20:18> IPC11<17:16> No

CAN1 – CAN1 Event 77 47 IFS2<13> IEC2<13> IPC11<28:26> IPC11<25:24> Yes

SPI3E – SPI3 Fault 78 48 IFS2<14> IEC2<14> IPC12<4:2> IPC12<1:0> Yes

SPI3RX – SPI3 Receive Done 79 48 IFS2<15> IEC2<15> IPC12<4:2> IPC12<1:0> Yes

SPI3TX – SPI3 Transfer Done 80 48 IFS2<16> IEC2<16> IPC12<4:2> IPC12<1:0> Yes

SPI4E – SPI4 Fault

(2)

81 49 IFS2<17> IEC2<17> IPC12<12:10> IPC12<9:8> Yes

SPI4RX – SPI4 Receive Done

(2)

82 49 IFS2<18> IEC2<18> IPC12<12:10> IPC12<9:8> Yes

SPI4TX – SPI4 Transfer Done

(2)

83 49 IFS2<19> IEC2<19> IPC12<12:10> IPC12<9:8> Yes

Lowest Natural Order Priority

TABLE 5-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source

(1)

IRQ # Vector

Interrupt Bit Location Persistent

Interrupt

Flag Enable Priority Sub-priority

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX 1XX/2XX/5XX 64/100-pin Contro ller

Family Features” for the list of available peripherals.

2: This interrupt source is not available on 64-pin devices.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 56  2014-2017 Microchip Technology Inc.

5.1 Interrupts Control Registers

TABLE 5-2: INTERRUPT REGISTER MAP

Virtua l Ad dress

(BF88_#)

Name

(3)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

1000 INTCON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — MVEC —TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

1010 INTSTAT

(4)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000

1020 IPTMR 31:16 IPTMR<31:0> 0000

15:0 0000

1030 IFS0 31:16 FCEIF RTCCIF FSCMIF AD1IF OC5IF IC5IF IC5EIF T5IF INT4IF OC4IF IC4IF IC4EIF T4IF INT3IF OC3IF IC3IF 0000

15:0 IC3EIF T3IF INT2IF OC2IF IC2IF IC2EIF T2IF INT1IF OC1IF IC1IF IC1EIF T1IF INT0IF CS1IF CS0IF CTIF 0000

1040 IFS1 31:16 U3RXIF U3EIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF CNGIF CNFIF CNEIF 0000

15:0 CNDIF CNCIF CNBIF CNAIF I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF USBIF

(2)

CMP2IF CMP1IF 0000

1050 IFS2 31:16 — — — — — — — — — — — — SPI4TXIF

(1)

SPI4RXIF

(1)

SPI4EIF

(1)

SPI3TXIF 0000

15:0 SPI3RXIF SPI3EIF CANIF CMP3IF DMA3IF DMA2IF DMA1IF DMA0IF CTMUIF U5TXIF

(1)

U5RXIF

(1)

U5EIF

(1)

U4TXIF U4RXIF U4EIF U3TXIF 0000

1060 IEC0 31:16 FCEIE RTCCIE FSCMIE AD1IE OC5IE IC5IE IC5EIE T5IE INT4IE OC4IE IC4IE IC4EIE T4IE INT3IE OC3IE IC3IE 0000

15:0 IC3EIE T3IE INT2IE OC2IE IC2IE IC2EIE T2IE INT1IE OC1IE IC1IE IC1EIE T1IE INT0IE CS1IE CS0IE CTIE 0000

1070 IEC1 31:16 U3RXIE U3EIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE CNGIE CNFIE CNEIE 0000

15:0 CNDIE CNCIE CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE USBIE

(2)

CMP2IE CMP1IE 0000

1080 IEC2 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — DMA3IE DMA2IE DMA1IE DMA0IE CTMUIE U5TXIE

(1)

U5RXIE

(1)

U5EIE

(1)

U4TXIE U4RXIE U4EIE U3TXIE 0000

1090 IPC0 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000

15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000

10A0 IPC1 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000

15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000

10B0 IPC2 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000

15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000

10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000

15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000

10D0 IPC4 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This bit is only available on 100-pin devices.

2: This bit is only implemented on devices with a USB module.

3: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR,

SET, and INV Registers” for more information.

4: This register does not have associated CLR, SET, and INV registers.

5: This bit is only implemented on devices with a CAN module.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

10E0 IPC5 31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000

15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000

10F0 IPC6 31:16 — — — CMP1IP<2:0> CMP1IS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000

15:0 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000

1100 IPC7 31:16 — — — U1IP<2:0> U1IS<1:0> — — — SPI1IP<2:0> SPI1IS<1:0> 0000

15:0 — — — USBIP<2:0>

(2)

USBIS<1:0>

(2)

— — — CMP2IP<2:0> CMP2IS<1:0> 0000

1110 IPC8 31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000

15:0 — — — CNIP<2:0> CNIS<1:0> — — — I2C1IP<2:0> I2C1IS<1:0> 0000

1120 IPC9 31:16 — — — U4IP<2:0> U4IS<1:0> — — — U3IP<2:0> U3IS<1:0> 0000

15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0> 0000

1130 IPC10 31:16 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000

15:0 — — — CTMUIP<2:0> CTMUIS<1:0> — — — U5IP<2:0> U5IS<1:0> 0000

1140 IPC11 31:16 — — — CANIP<2:0>

(5)

CANIS<1:0>

(5)

— — — CMP3IP<2:0> CMP3IS<1:0> 0000

15:0 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000

1150 IPC12 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — SPI4P<2:0>

(1)

SPI4S<1:0>

(1)

— — — SPI3P<2:0> SPI3S<1:0> 0000

TABLE 5-2: INTERRUPT REGISTER MAP (CONTINUED)

Virtual Address

(BF88_#)

Name

(3)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This bit is only available on 100-pin devices.

2: This bit is only implemented on devices with a USB module.

SET, and INV Registers” for more information.

4: This register does not have associated CLR, SET, and INV registers.

5: This bit is only implemented on devices with a CAN module.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

— — — MVEC —TPC<2:0>

7:0

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT4EP INT3EP INT2EP INT1EP INT0EP

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as ‘0’

bit 12 MVEC: Multi Vector Configuration bit

1 = Interrupt controller configured for multi vectored mode

0 = Interrupt controller configured for single vectored mode

bit 11 Unimplemented: Read as ‘0’

bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits

111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer

110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer

101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer

100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer

011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer

010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer

001 = Interrupts of group priority 1 start the Interrupt Proximity timer

000 = Disables Interrupt Proximity timer

bit 7-5 Unimplemented: Read as ‘0’

bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — —SRIPL<2:0>

(1)

7:0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

——VEC<5:0>

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-11 Unimplemented: Read as ‘0’

bit 10-8 SRIPL<2:0>: Requested Priority Level bits

(1)

111-000 = The priority level of the latest interrupt presented to the CPU

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 VEC<5:0>: Interrupt Vector bits

(1)

11111-00000 = The interrupt vector that is presented to the CPU

Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IPTMR<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IPTMR<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IPTMR<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IPTMR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits

Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by

an interrupt event.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS31 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS9 IFS8

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS7 IFS6 IFS5 IFS4 IFS3 IFS2 IFS1 IFS0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IFS31-IFS0: Interrupt Flag Status bits

1 = Interrupt request has occurred

0 = No interrupt request has occurred

Note: This register represents a generic definition of the IFSx register. Refer to Table 5-1 for the exact bit

definitions.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC23 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC16

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC9 IEC8

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC7 IEC6 IEC5 IEC4 IEC3 IEC2 IEC1 IEC0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IEC31-IEC0: Interrupt Enable bits

1 = Interrupt is enabled

0 = Interrupt is disabled

Note: This register represents a generic definition of the IECx register. Refer to Table 5-1 for the exact bit

definitions.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — IP3<2:0> IS3<1:0>

23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — IP2<2:0> IS2<1:0>

15:8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — IP1<2:0> IS1<1:0>

7:0

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — IP0<2:0> IS0<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-26 IP3<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 25-24 IS3<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

bit 23-21 Unimplemented: Read as ‘0’

bit 20-18 IP2<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 17-16 IS2<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

bit 15-13 Unimplemented: Read as ‘0’

bit 12-10 IP1<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

Note: This register represents a generic definition of the IPCx register. Refer to Table 5-1 for the exact bit

definitions.

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bit 9-8 IS1<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

bit 7-5 Unimplemented: Read as ‘0’

bit 4-2 IP0<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 1-0 IS0<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

Note: This register represents a generic definition of the IPCx register. Refer to Table 5-1 for the exact bit

definitions.

 2014-2017 Microchip Technology Inc. DS60001290E-page 63

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

6.0 FLASH PROGRAM MEMORY

PIC32MX1XX/2XX/5XX 64/100-pin devices contain an

internal Flash program memory for executing user

code. There are three methods by which the user can

program this memory:

• Run-Time Self-Programming (RTSP)

• EJTAG Programming

• In-Circuit Serial Programming™ (ICSP™)

RTSP is performed by software executing from either

Flash or RAM memory. Information about RTSP

techniques is available in Section 5. “Flash Program

Memory” (DS60001121) in the “PIC32 Family

Reference Manual”.

EJTAG is performed using the EJTAG port of the

device and an EJTAG capable programmer.

ICSP is performed using a serial data connection to the

device and allows much faster programming times than

RTSP.

The EJTAG and ICSP methods are described in the

“PIC32 Flash Programming Specification”

(DS60001145), which can be downloaded from the

Microchip web site.

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 5. “Flash

Program Memory” (DS60001121) in the

“PI C32 Fami ly Re ferenc e Manua l” , which

is available from the Microchip web site

(www.microchip.com/PIC32).

Note: On PIC32MX1XX/2XX/5XX 64/100-pin

devices, the Flash page size is 1 KB and

the row size is 128 bytes (256 IW and

32 IW, respectively).

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6.1 Control Registers

TABLE 6-1: FLASH CONTROLLER REGISTER MAP

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

F400 NVMCON

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 WR WREN WRERR LVDERR LVDSTAT ——————— NVMOP<3:0> 0000

F410 NVMKEY 31:16 NVMKEY<31:0> 0000

15:0 0000

F420

NVMADDR

(1)

31:16 NVMADDR<31:0> 0000

15:0 0000

F430 NVMDATA 31:16 NVMDATA<31:0> 0000

15:0 0000

F440 NVMSRC

ADDR

31:16 NVMSRCADDR<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for more

information.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R-0 R-0 R-0 U-0 U-0 U-0

WR WREN

(1)

WRERR

(2)

LVDERR

(2)

LVDSTAT

(2)

— — —

7:0

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

————NVMOP<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 WR: Write Control bit

This bit is writable when WREN = 1 and the unlock sequence is followed.

1 = Initiate a Flash operation. Hardware clears this bit when the operation completes

0 = Flash operation complete or inactive

bit 14 WREN: Write Enable bit

(1)

1 = Enable writes to WR bit and enables LVD circuit

0 = Disable writes to WR bit and disables LVD circuit

This is the only bit in this register reset by a device Reset.

bit 13 WRERR: Write Error bit

(2)

This bit is read-only and is automatically set by hardware.

1 = Program or erase sequence did not complete successfully

0 = Program or erase sequence completed normally

bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)

(2)

This bit is read-only and is automatically set by hardware.

1 = Low-voltage detected (possible data corruption, if WRERR is set)

0 = Voltage level is acceptable for programming

bit 11 LVDSTA T: Low-Voltage Detect Status bit (LVD circuit must be enabled)

(2)

This bit is read-only and is automatically set, and cleared, by hardware.

1 = Low-voltage event active

0 = Low-voltage event NOT active

bit 10-4 Unimplemented: Read as ‘0’

bit 3-0 NVMOP<3:0>: NVM Operation bits

These bits are writable when WREN = 0.

1111 =Reserved

•

0111 = Reserved

0110 =No operation

0101 =Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected

0100 =Page erase operation: erases page selected by NVMADDR, if it is not write-protected

0011 =Row program operation: programs row selected by NVMADDR, if it is not write-protected

0010 =No operation

0001 =Word program operation: programs word selected by NVMADDR, if it is not write-protected

0000 = No operation

Note 1: This bit is cleared by any reset (i.e., POR, BOR, WDT, MCLR, SWR).

2: This bit is only cleared by setting NVMOP = 0000, and initiating a Flash WR operation or a POR. Any

other kind of reset (i.e., BOR, WDT, MCLR) does not clear this bit.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<31:24>

23:16

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<23:16>

15:8

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<15:8>

7:0

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMKEY<31:0>: Unlock Register bits

These bits are write-only, and read as ‘0’ on any read.

Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMADDR<31:0>: Flash Address bits

Bulk/Chip/PFM Erase: Address is ignored

Page Erase: Address identifies the page to erase

Row Program: Address identifies the row to program

Word Program: Address identifies the word to program

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMDATA<31:0>: Flash Programming Data bits

Note: The bits in this register are only reset by a Power-on Reset (POR).

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits

The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits

(NVMCON<3:0>) are set to perform row programming.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 68  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 69

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

7.0 RESETS

The Reset module combines all Reset sources and

controls the device Master Reset signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

•MCLR: Master Clear Reset pin

• SWR: Software Reset

• WDTR: Watchdog Timer Reset

• BOR: Brown-out Reset

• CMR: Configuration Mismatch Reset

• HVDR: High Voltage Detect Reset

A simplified block diagram of the Reset module is

illustrated in Figure 7-1.

FIGURE 7-1: SYSTEM RESET BLOCK DIAGRAM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 7. “Resets”

(DS60001118) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

MCLR

Rise

Detect

POR

Sleep or Idle

Brown-out

Reset

WDT

Time-out

Glitch Filter

BOR

Configuration

SYSRST

Software Reset

Power-up

Timer

Voltage

Enabled

Reset

WDTR

SWR

CMR

MCLR

Mismatch

Regulator

Brown-out

Reset

HVDR

CAP

HVD Detect

and Reset

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 70  2014-2017 Microchip Technology Inc.

7.1 Control Registers

TABLE 7-1: RESET SFR SUMMARY

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

F600 RCON 31:16 — — HVDR —————————————0000

15:0 ——————CMR VREGS EXTR SWR —WDTO SLEEP IDLE BOR POR xxxx

(1)

F610 RSWRST 31:16 ————————————————0000

15:0 ———————————————SWRST 0000

Legend: — = unimplemented, read as ‘0’. Address offset values are shown in hexadecimal.

Note 1:

The Reset value is dependent on the DEVCFGx Configuration bits and the type of reset.

 2014-2017 Microchip Technology Inc. DS60001290E-page 71

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0

——HVDR— — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0

— — — — — — CMR VREGS

7:0

R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS

EXTR SWR — WDTO SLEEP IDLE BOR

(1)

POR

(1)

Legend: HS = Set by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29 HVDR: High Voltage Detect Reset Flag bit

1 = High Voltage Detect (HVD) Reset has occurred, voltage on V

CAP

> 2.5V

0 = HVD Reset has not occurred

bit 28-10 Unimplemented: Read as ‘0’

bit 9 CMR: Configuration Mismatch Reset Flag bit

1 = Configuration mismatch Reset has occurred

0 = Configuration mismatch Reset has not occurred

bit 8 VREGS: Voltage Regulator Standby Enable bit

1 = Regulator is enabled and is on during Sleep mode

0 = Regulator is disabled and is off during Sleep mode

bit 7 EXTR: External Reset (MCLR) Pin Flag bit

1 = Master Clear (pin) Reset has occurred

0 = Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset Flag bit

1 = Software Reset was executed

0 = Software Reset as not executed

bit 5 Unimplemented: Read as ‘0’

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT Time-out has occurred

0 = WDT Time-out has not occurred

bit 3 SLEEP: Wake From Sleep Flag bit

1 = Device was in Sleep mode

0 = Device was not in Sleep mode

bit 2 IDLE: Wake From Idle Flag bit

1 = Device was in Idle mode

0 = Device was not in Idle mode

bit 1 BOR: Brown-out Reset Flag bit

(1)

1 = Brown-out Reset has occurred

0 = Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

(1)

1 = Power-on Reset has occurred

0 = Power-on Reset has not occurred

Note 1: User software must clear this bit to view next detection.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 72  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC

— — — — — — —SWRST

(1)

Legend: HC = Cleared by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-1 Unimplemented: Read as ‘0’

bit 0 SWRST: Software Reset Trigger bit

(1)

1 = Enable software Reset event

0 = No effect

Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section

6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.

 2014-2017 Microchip Technology Inc. DS60001290E-page 73

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

8.0 OSCILLATOR

CONFIGURATION

The PIC32MX1XX/2XX/5XX 64/100-pin oscillator

system has the following modules and features:

• A Total of four external and internal oscillator

options as clock sources

• On-Chip PLL with user-selectable input divider,

multiplier and output divider to boost operating

frequency on select internal and external

oscillator sources

• On-Chip user-selectable divisor postscaler on

select oscillator sources

• Software-controllable switching between 

various clock sources

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and permits safe application recovery

or shutdown

• Dedicated On-Chip PLL for USB peripheral

A block diagram of the oscillator system is provided in

Figure 8-1.

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 6. “Oscillator

Configuration” (DS60001112) in the

“PI C32 Fami ly Re ferenc e Manua l” , which

is available from the Microchip web site

(www.microchip.com/PIC32).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 74  2014-2017 Microchip Technology Inc.

FIGURE 8-1: PIC32MX1 XX/2XX/5XX 64/ 100-PIN FAMILY CLOCK DIAGRAM

Notes: 1.

A series resistor, R

, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain,

add a parallel resistor, R

, with a value of 1 M



The internal feedback resistor, R

, is typically in the range of 2 M



to 10 M



Refer to

Section 6. “Oscillator Configuration”

(DS60001112) in the “

PIC32 Family Reference Manual

” for determining the best

oscillator components.

PBCLK out is available on the OSC2 pin in certain clock modes.

USB PLL is available on PIC32MX2XX/5XX devices only.

Timer1, RTCC

Clock Control Logic

Fail-Safe

Clock

Monitor

FSCM INT

FSCM Event

COSC<2:0>

NOSC<2:0>

OSWEN

FSCMEN<1:0>

PLL

Secondary Osc illator (S

OSC

)

SOSCEN and FSOSCEN

SOSCO

SOSCI

Primary Oscillator

OSC

(XT, HS, EC)

CPU and Select Peripherals

Peripherals

FRCDIV<2:0>

WDT, PWRT

8 MHz typical

FRC

31.25 kHz typical

FRC

Oscillator

LPRC

Oscillator

OSC

LPRC

FRCDIV

TUN<5:0>

div 16

Postscaler

FPLLIDIV<2:0>

PBDIV<1:0>

FRC/16

Postscaler

COSC<2:0>

div x

div y

PLLODIV<2:0>

div x

32.768 kHz

PLLMULT<2:0>

PBCLK (T

)



4 MHz

PLL x24

USB Clock (48 MHz)

div 2

UPLLEN

UFRCEN

div x

UPLLIDIV<2:0>

4 MHz



5 MHz

(3)

XTAL

(1)

Enable

OSC2

(4)

OSC1

(2)

To Internal

Logic

USB PLL

(5)

OSC

)

div 2

To A D C

SYSCLK

REFCLKI

REFCLKO

To S P I

ROSEL<3:0>

OSC

FRC

LPRC

OSC

PBCLK

SYSCLK

XTPLL, HSPLL,

ECPLL, FRCPLL

System PLL

512

----------+







RODIV<14:0>

(N)

ROTRIM<8:0>

(M)

(1)



96 MHz

 2014-2017 Microchip Technology Inc. DS60001290E-page 75

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 8-2: PIC32MX1XX/2XX/5XX PLL B LOCK D IAGRAM

FPLLIDIV XVCO FPLLODIV SYSCLK

FPLLMULT

FIN:

(1)

3.92 MHz FIN z FSYS:

(1)

60 MHz FSYS z

SYSCLK:

(1)

234,375 Hz SYSCLK

 50 MHz

Divide By:

1,2,3,4,5,6,10,12

Multiply By:

15,16,17,18,19,

20,21,22,23,24

Divide By:

1,2,4,8,16,32,64,256

(Crystal, External Clock

Or Internal RC)

Note 1: This frequency range must be satisfied at all times if the PLL is enabled and software is updating the

corresponding bits in the OSCON register.

 2014-2017 Microchip Technology Inc. DS60001290E-page 76

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

8.1 Control Registers

TABLE 8-1: OSCILLATOR CONFIGURATION REGISTER MAP

Virt ual Addres s

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

F000 OSCCON 31:16 — — PLLODIV<2:0> FRCDIV<2:0> —SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0> x1xx

(2)

15:0 —COSC<2:0> —NOSC<2:0> CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN

(3)

SOSCEN OSWEN xxxx

(2)

F010 OSCTUN 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — TUN<5:0> 0000

F020 REFOCON 31:16 —RODIV<14:0> 0000

15:0 ON —SIDL OE RSLP —DIVSWEN ACTIVE — — — — ROSEL<3:0> 0000

F030 REFOTRIM 31:16 ROTRIM<8:0> — — — — — — — 0000

15:0 — — — — — — — — —— — — — — — — 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2

“CLR, SET, and INV Registers” for more information.

2: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.

3: This bit is only available on devices with a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 77

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 R/W-y R/W-y R/W-y R/W-0 R/W-0 R/W-1

—— PLLODIV<2:0> FRCDIV<2:0>

23:16

U-0 R-0 R-1 R/W-y R/W-y R/W-y R/W-y R/W-y

— SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0>

15:8

U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y

— COSC<2:0> —NOSC<2:0>

7:0

R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-y R/W-0

CLKLOCK ULOCK

(1)

SLOCK SLPEN CF UFRCEN

(1)

SOSCEN OSWEN

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29-27 PLLODIV<2:0>: Output Divider for PLL

111 = PLL output divided by 256

110 = PLL output divided by 64

101 = PLL output divided by 32

100 = PLL output divided by 16

011 = PLL output divided by 8

010 = PLL output divided by 4

001 = PLL output divided by 2

000 = PLL output divided by 1

bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits

111 = FRC divided by 256

110 = FRC divided by 64

101 = FRC divided by 32

100 = FRC divided by 16

011 = FRC divided by 8

010 = FRC divided by 4

001 = FRC divided by 2 (default setting)

000 = FRC divided by 1

bit 23 Unimplemented: Read as ‘0’

bit 22 SOSCRDY: Secondary Oscillator (S

OSC

) Ready Indicator bit

1 = Indicates that the Secondary Oscillator is running and is stable

0 = Secondary Oscillator is still warming up or is turned off

bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit

1 = PBDIV<1:0> bits can be written

0 = PBDIV<1:0> bits cannot be written

bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits

11 = PBCLK is SYSCLK divided by 8 (default)

10 = PBCLK is SYSCLK divided by 4

01 = PBCLK is SYSCLK divided by 2

00 = PBCLK is SYSCLK divided by 1

Note 1: This bit is available on PIC32MX2XX/5XX devices only.

Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the

“PIC32 Family Reference Manual” for details.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 78  2014-2017 Microchip Technology Inc.

bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits

111 = Clock is multiplied by 24

110 = Clock is multiplied by 21

101 = Clock is multiplied by 20

100 = Clock is multiplied by 19

011 = Clock is multiplied by 18

010 = Clock is multiplied by 17

001 = Clock is multiplied by 16

000 = Clock is multiplied by 15

bit 15 Unimplemented: Read as ‘0’

bit 14-12 COSC<2:0>: Current Oscillator Selection bits

111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits

110 = Internal Fast RC (FRC) Oscillator divided by 16

101 = Internal Low-Power RC (LPRC) Oscillator

100 = Secondary Oscillator (S

OSC

)

011 = Primary Oscillator (P

OSC

) with PLL module (XTPLL, HSPLL or ECPLL)

010 = Primary Oscillator (P

OSC

) (XT, HS or EC)

001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)

000 = Internal Fast RC (FRC) Oscillator

bit 11 Unimplemented: Read as ‘0’

bit 10-8 N OSC<2:0>: New Oscillator Selection bits

111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits

110 = Internal Fast RC Oscillator (FRC) divided by 16

101 = Internal Low-Power RC (LPRC) Oscillator

100 = Secondary Oscillator (S

OSC

)

011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)

010 = Primary Oscillator (XT, HS or EC)

001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)

000 = Internal Fast Internal RC Oscillator (FRC)

On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).

bit 7 CLKLOCK: Clock Selection Lock Enable bit

If clock switching and monitoring is disabled (FCKSM<1:0> = 1x):

1 = Clock and PLL selections are locked

0 = Clock and PLL selections are not locked and may be modified

If clock switching and monitoring is enabled (FCKSM<1:0> = 0x):

Clock and PLL selections are never locked and may be modified.

bit 6 ULOCK: USB PLL Lock Status bit

(1)

1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied

0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or

USB PLL is disabled

bit 5 SLOCK: PLL Lock Status bit

1 = PLL module is in lock or PLL module start-up timer is satisfied

0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4 SLPEN: Sleep Mode Enable bit

1 = Device will enter Sleep mode when a WAIT instruction is executed

0 = Device will enter Idle mode when a WAIT instruction is executed

bit 3 CF: Clock Fail Detect bit

1 = FSCM has detected a clock failure

0 = No clock failure has been detected

Note 1: This bit is available on PIC32MX2XX/5XX devices only.

Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the

“PIC32 Family Reference Manual” for details.

 2014-2017 Microchip Technology Inc. DS60001290E-page 79

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 2 UFRCEN: USB FRC Clock Enable bit

(1)

1 = Enable FRC as the clock source for the USB clock source

0 = Use the Primary Oscillator or USB PLL as the USB clock source

bit 1 SOSCEN: Secondary Oscillator (S

OSC

) Enable bit

1 = Enable Secondary Oscillator

0 = Disable Secondary Oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits

0 = Oscillator switch is complete

Note 1: This bit is available on PIC32MX2XX/5XX devices only.

Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the

“PIC32 Family Reference Manual” for details.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 80  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8

U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— TUN<5:0>

(1)

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits

(1)

100000 = Center frequency -12.5%

100001 =

•

111111 =

000000 = Center frequency. Oscillator runs at minimal frequency (8 MHz)

000001 =

•

011110 =

011111 = Center frequency +12.5%

Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the

FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither

characterized, nor tested.

Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the

“PIC32 Family Reference Manual” for details.

 2014-2017 Microchip Technology Inc. DS60001290E-page 81

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—RODIV<14:8>

(1)

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RODIV<7:0>

(3)

15:8

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC

ON —SIDLOE

RSLP

(2)

— DIVSWEN ACTIVE

7:0

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — ROSEL<3:0>

(1)

Legend: HC = Hardware Clearable HS = Hardware Settable

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Unimplemented: Read as ‘0’

bit 30-16 RODIV<14:0>: Reference Clock Divider bits

(1)

This value selects the Reference Clock Divider bits. See Figure 8-1 for more information.

bit 15 ON: Output Enable bit

1 = Reference Oscillator Module enabled

0 = Reference Oscillator Module disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Peripheral Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 OE: Reference Clock Output Enable bit

1 = Reference clock is driven out on REFCLKO pin

0 = Reference clock is not driven out on REFCLKO pin

bit 11 RSLP: Reference Oscillator Module Run in Sleep bit

(2)

1 = Reference Oscillator Module output continues to run in Sleep

0 = Reference Oscillator Module output is disabled in Sleep

bit 10 Unimplemented: Read as ‘0’

bit 9 DIVSWEN: Divider Switch Enable bit

1 = Divider switch is in progress

0 = Divider switch is complete

bit 8 ACTIVE: Reference Clock Request Status bit

1 = Reference clock request is active

0 = Reference clock request is not active

bit 7-4 Unimplemented: Read as ‘0’

Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may

result.

2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.

3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ‘1’.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits

(1)

1111 = Reserved; do not use

•

1001 = Reserved; do not use

1000 =REFCLKI

0111 = System PLL output

0110 = USB PLL output

0101 =S

OSC

0100 =LPRC

0011 =FRC

0010 =P

OSC

0001 = PBCLK

0000 = SYSCLK

Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may

result.

2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.

3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ‘1’.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ROTRIM<8:1>

23:16

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

ROTRIM<0> — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits

111111111 = 511/512 divisor added to RODIV value

111111110 = 510/512 divisor added to RODIV value

•

100000000 = 256/512 divisor added to RODIV value

•

000000010 = 2/512 divisor added to RODIV value

000000001 = 1/512 divisor added to RODIV value

000000000 = 0/512 divisor added to RODIV value

bit 22-0 Unimplemented: Read as ‘0’

Note: While the ON bit (REFOCON<15>) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is

also set to ‘1’.

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NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 85

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

9.0 DIRECT MEMORY ACCESS

(DMA) CONTROLLER

The PIC32 Direct Memory Access (DMA) controller is a

bus master module useful for data transfers between

different devices without CPU intervention. The source

and destination of a DMA transfer can be any of the

memory mapped modules existent in the PIC32 (such

as Peripheral Bus (PBUS) devices: SPI, UART, PMP,

etc.) or memory itself.

The following are some of the key features of the DMA

controller module:

• Four identical channels, each featuring:

- Auto-increment source and destination

address registers

- Source and destination pointers

- Memory to memory and memory to

peripheral transfers

• Automatic word-size detection:

- Transfer granularity, down to byte level

- Bytes need not be word-aligned at source

and destination

• Fixed priority channel arbitration

• Flexible DMA channel operating modes:

- Manual (software) or automatic (interrupt)

DMA requests

- One-Shot or Auto-Repeat Block Transfer

modes

- Channel-to-channel chaining

• Flexible DMA requests:

- A DMA request can be selected from any of

the peripheral interrupt sources

- Each channel can select any (appropriate)

observable interrupt as its DMA request

source

- A DMA transfer abort can be selected from

any of the peripheral interrupt sources

- Pattern (data) match transfer termination

• Multiple DMA channel status interrupts:

- DMA channel block transfer complete

- Source empty or half empty

- Destination full or half full

- DMA transfer aborted due to an external

event

- Invalid DMA address generated

• DMA debug support features:

- Most recent address accessed by a DMA

channel

- Most recent DMA channel to transfer data

• CRC Generation module:

- CRC module can be assigned to any of the

available channels

- CRC module is highly configurable

FIGU RE 9-1 : DMA BLOCK DIAG R AM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 31. “Direct

Memory Access (DMA) Controller”

(DS60001117) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

Address Decoder Channel 0 Control

Channel 1 Control

Channel n Control

Global Control

(DMACON)

Bus Interface

Channel Priority

Arbitration

SEL

System IRQINT Controller

Device Bus + Bus Arbitration

Peripheral Bus

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9.1 Control Registers

TABLE 9-1: DMA GLOBAL REGISTER MAP

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

3000 DMACON 31:16 ——— — — ———————————0000

15:0 ON — — SUSPEND DMABUSY ———————————0000

3010 DMASTAT 31:16 ——— — — ———————————0000

15:0 — — — — — — — — — — — — RDWR DMACH<2:0> 0000

3020 DMAADDR 31:16 DMAADDR<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for

more information.

TABLE 9-2: DMA CRC REGISTER MAP

Virt ua l Ad dr es s

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

3030 DCRCCON 31:16 — — BYTO<1:0> WBO — — BITO ————————0000

15:0 ——— PLEN<4:0> CRCEN CRCAPP CRCTYP — — CRCCH<2:0> 0000

3040 DCRCDATA 31:16 DCRCDATA<31:0> 0000

15:0 0000

3050 DCRCXOR 31:16 DCRCXOR<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 87

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TABLE 9-3: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP

Virt ual Addres s

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

3060 DCH0CON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

3070 DCH0ECON 31:16 — — — — — — — — CHAIRQ<7:0> 00FF

15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FFF8

3080 DCH0INT 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

3090 DCH0SSA 31:16 CHSSA<31:0> 0000

15:0 0000

30A0 DCH0DSA 31:16 CHDSA<31:0> 0000

15:0 0000

30B0 DCH0SSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHSSIZ<15:0> 0000

30C0 DCH0DSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHDSIZ<15:0> 0000

30D0 DCH0SPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHSPTR<15:0> 0000

30E0 DCH0DPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHDPTR<15:0> 0000

30F0 DCH0CSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHCSIZ<15:0> 0000

3100 DCH0CPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHCPTR<15:0> 0000

3110 DCH0DAT 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — CHPDAT<7:0> 0000

3120 DCH1CON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

3130 DCH1ECON 31:16 — — — — — — — — CHAIRQ<7:0> 00FF

15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FFF8

3140 DCH1INT 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

3150 DCH1SSA 31:16 CHSSA<31:0> 0000

15:0 0000

3160 DCH1DSA 31:16 CHDSA<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

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3170 DCH1SSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHSSIZ<15:0> 0000

3180 DCH1DSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHDSIZ<15:0> 0000

3190 DCH1SPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHSPTR<15:0> 0000

31A0 DCH1DPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHDPTR<15:0> 0000

31B0 DCH1CSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHCSIZ<15:0> 0000

31C0 DCH1CPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHCPTR<15:0> 0000

31D0 DCH1DAT 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — CHPDAT<7:0> 0000

31E0 DCH2CON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

31F0 DCH2ECON 31:16 — — — — — — — — CHAIRQ<7:0> 00FF

15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FFF8

3200 DCH2INT 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

3210 DCH2SSA 31:16 CHSSA<31:0> 0000

15:0 0000

3220 DCH2DSA 31:16 CHDSA<31:0> 0000

15:0 0000

3230 DCH2SSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHSSIZ<15:0> 0000

3240 DCH2DSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHDSIZ<15:0> 0000

3250 DCH2SPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHSPTR<15:0> 0000

3260 DCH2DPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHDPTR<15:0> 0000

3270 DCH2CSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHCSIZ<15:0> 0000

TABLE 9-3: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED)

Virt ual Addres s

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 89

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

3280 DCH2CPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHCPTR<15:0> 0000

3290 DCH2DAT 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — CHPDAT<7:0> 0000

32A0 DCH3CON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

32B0 DCH3ECON 31:16 — — — — — — — — CHAIRQ<7:0> 00FF

15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FFF8

32C0 DCH3INT 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

32D0 DCH3SSA 31:16 CHSSA<31:0> 0000

15:0 0000

32E0 DCH3DSA 31:16 CHDSA<31:0> 0000

15:0 0000

32F0 DCH3SSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHSSIZ<15:0> 0000

3300 DCH3DSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHDSIZ<15:0> 0000

3310 DCH3SPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHSPTR<15:0> 0000

3320 DCH3DPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHDPTR<15:0> 0000

3330 DCH3CSIZ 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHCSIZ<15:0> 0000

3340 DCH3CPTR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CHCPTR<15:0> 0000

3350 DCH3DAT 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — CHPDAT<7:0> 0000

TABLE 9-3: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED)

Virt ual Addres s

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0

(1)

—— SUSPEND DMABUSY

(1)

— — —

7:0

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: DMA On bit

(1)

1 = DMA module is enabled

0 = DMA module is disabled

bit 14-13 Unimplemented: Read as ‘0’

bit 12 SUSPEND: DMA Suspend bit

1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus

0 = DMA operates normally

bit 11 DMABUSY: DMA Module Busy bit

(1)

1 = DMA module is active

0 = DMA module is disabled and not actively transferring data

bit 10-0 Unimplemented: Read as ‘0’

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — RDWR DMACH<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3 RDWR: Read/Write Status bit

1 = Last DMA bus access was a read

0 = Last DMA bus access was a write

bit 2-0 DMACH<2:0>: DMA Channel bits

These bits contain the value of the most recent active DMA channel.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<31:24>

23:16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<23:16>

15:8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<15:8>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DMAADDR<31:0>: DMA Module Address bits

These bits contain the address of the most recent DMA access.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 92  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0

—— BYTO<1:0> WBO

(1)

——BITO

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — PLEN<4:0>

7:0

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

CRCEN CRCAPP

(1)

CRCTYP —— CRCCH<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits

11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order

per half-word)

10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per

half-word)

01 = Endian byte swap on word boundaries (i.e., reverse source byte order)

00 = No swapping (i.e., source byte order)

bit 27 WBO: CRC Write Byte Order Selection bit

(1)

1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>

0 = Source data is written to the destination unaltered

bit 26-25 Unimplemented: Read as ‘0’

bit 24 BITO: CRC Bit Order Selection bit

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)

0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)

0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)

bit 23-13 Unimplemented: Read as ‘0’

bit 12-8 PLEN<4:0>: Polynomial Length bits

(1)

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

These bits are unused.

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

Denotes the length of the polynomial – 1.

bit 7 CRCEN: CRC Enable bit

1 = CRC module is enabled and channel transfers are routed through the CRC module

0 = CRC module is disabled and channel transfers proceed normally

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

 2014-2017 Microchip Technology Inc. DS60001290E-page 93

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 6 CRCAPP: CRC Append Mode bit

(1)

1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer

completes the DMA writes the calculated CRC value to the location given by CHxDSA

0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the

destination

bit 5 CRCTYP: CRC Type Selection bit

1 = The CRC module will calculate an IP header checksum

0 = The CRC module will calculate a LFSR CRC

bit 4-3 Unimplemented: Read as ‘0’

bit 2-0 CRCCH<2:0>: CRC Channel Select bits

111 = CRC is assigned to Channel 7

110 = CRC is assigned to Channel 6

101 = CRC is assigned to Channel 5

100 = CRC is assigned to Channel 4

011 = CRC is assigned to Channel 3

010 = CRC is assigned to Channel 2

001 = CRC is assigned to Channel 1

000 = CRC is assigned to Channel 0

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DCRCDATA<31:0>: CRC Data Register bits

Writing to this register will seed the CRC generator. Reading from this register will return the current value of

the CRC. Bits greater than PLEN will return ‘0’ on any read.

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written

to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

Bits greater than PLEN will return ‘0’ on any read.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

This register is unused.

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = Enable the XOR input to the Shift register

0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in

the register

 2014-2017 Microchip Technology Inc. DS60001290E-page 95

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

CHBUSY — — — — — — CHCHNS

(1)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0

CHEN

(2)

CHAED CHCHN CHAEN — CHEDET CHPRI<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 CHBUSY: Channel Busy bit

1 = Channel is active or has been enabled

0 = Channel is inactive or has been disabled

bit 14-9 Unimplemented: Read as ‘0’

bit 8 CHCHNS: Chain Channel Selection bit

(1)

1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)

0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)

bit 7 CHEN: Channel Enable bit

(2)

1 = Channel is enabled

0 = Channel is disabled

bit 6 CHAED: Channel Allow Events If Disabled bit

1 = Channel start/abort events will be registered, even if the channel is disabled

0 = Channel start/abort events will be ignored if the channel is disabled

bit CHCHN: Channel Chain Enable bit

1 = Allow channel to be chained

0 = Do not allow channel to be chained

bit 4 CHAEN: Channel Automatic Enable bit

1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete

0 = Channel is disabled on block transfer complete

bit 3 Unimplemented: Read as ‘0’

bit 2 CHEDET: Channel Event Detected bit

1 = An event has been detected

0 = No events have been detected

bit 1-0 CHPRI<1:0>: Channel Priority bits

11 = Channel has priority 3 (highest)

10 = Channel has priority 2

01 = Channel has priority 1

00 = Channel has priority 0

Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).

2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if

available on the device variant) to see when the channel is suspended, as it may take some clock cycles

to complete a current transaction before the channel is suspended.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 96  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

CHAIRQ<7:0>

(1)

15:8

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

CHSIRQ<7:0>

(1)

7:0

S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

CFORCE CABORT PATEN SIRQEN AIRQEN — — —

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits

(1)

11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag

•

00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag

00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag

bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits

(1)

11111111 = Interrupt 255 will initiate a DMA transfer

•

00000001 = Interrupt 1 will initiate a DMA transfer

00000000 = Interrupt 0 will initiate a DMA transfer

bit 7 CFORCE: DMA Forced Transfer bit

1 = A DMA transfer is forced to begin when this bit is written to a ‘1’

0 = This bit always reads ‘0’

bit 6 CABORT: DMA Abort Transfer bit

1 = A DMA transfer is aborted when this bit is written to a ‘1’

0 = This bit always reads ‘0’

bit 5 PATEN: Channel Pattern Match Abort Enable bit

1 = Abort transfer and clear CHEN on pattern match

0 = Pattern match is disabled

bit 4 SIRQEN: Channel Start IRQ Enable bit

1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs

0 = Interrupt number CHSIRQ is ignored and does not start a transfer

bit 3 AIRQEN: Channel Abort IRQ Enable bit

1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs

0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer

bit 2-0 Unimplemented: Read as ‘0’

Note 1: See Table 5-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.

 2014-2017 Microchip Technology Inc. DS60001290E-page 97

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23 CHSDIE: Channel Source Done Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 16 CHERIE: Channel Address Error Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 15-8 Unimplemented: Read as ‘0’

bit 7 CHSDIF: Channel Source Done Interrupt Flag bit

1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)

0 = No interrupt is pending

bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit

1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)

0 = No interrupt is pending

bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit

1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)

0 = No interrupt is pending

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 98  2014-2017 Microchip Technology Inc.

bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit

1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)

0 = No interrupt is pending

bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit

1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a

pattern match event occurs

0 = No interrupt is pending

bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit

1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)

0 = No interrupt is pending

bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit

1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted

0 = No interrupt is pending

bit 0 CHERIF: Channel Address Error Interrupt Flag bit

1 = A channel address error has been detected 

Either the source or the destination address is invalid.

0 = No interrupt is pending

 2014-2017 Microchip Technology Inc. DS60001290E-page 99

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSA<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSA<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSA<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHSSA<31:0> Channel Source Start Address bits

Channel source start address.

Note: This must be the physical address of the source.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits

Channel destination start address.

Note: This must be the physical address of the destination.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 100  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSIZ<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSIZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHSSIZ<15:0>: Channel Source Size bits

1111111111111111 = 65,535 byte source size

•

0000000000000010 = 2 byte source size

0000000000000001 = 1 byte source size

0000000000000000 = 65,536 byte source size

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSIZ<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSIZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits

1111111111111111 = 65,535 byte destination size

•

0000000000000010 = 2 byte destination size

0000000000000001 = 1 byte destination size

0000000000000000 = 65,536 byte destination size

 2014-2017 Microchip Technology Inc. DS60001290E-page 101

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHSPTR<15:8>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHSPTR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits

1111111111111111 = Points to byte 65,535 of the source

•

0000000000000001 = Points to byte 1 of the source

0000000000000000 = Points to byte 0 of the source

Note: When in Pattern Detect mode, this register is reset on a pattern detect.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHDPTR<15:8>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHDPTR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits

1111111111111111 = Points to byte 65,535 of the destination

•

0000000000000001 = Points to byte 1 of the destination

0000000000000000 = Points to byte 0 of the destination

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHCSIZ<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHCSIZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits

1111111111111111 = 65,535 bytes transferred on an event

•

0000000000000010 = 2 bytes transferred on an event

0000000000000001= 1 byte transferred on an event

0000000000000000 = 65,536 bytes transferred on an event

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHCPTR<15:8>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHCPTR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits

1111111111111111 = 65,535 bytes have been transferred since the last event

•

0000000000000001 = 1 byte has been transferred since the last event

0000000000000000 = 0 bytes have been transferred since the last event

Note: When in Pattern Detect mode, this register is reset on a pattern detect.

 2014-2017 Microchip Technology Inc. DS60001290E-page 103

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHPDAT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 CHPDAT<7:0>: Channel Data Register bits

Pattern Terminate mode:

Data to be matched must be stored in this register to allow terminate on match.

All other modes:

Unused.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 104  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 105

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

10.0 USB ON-THE-GO (OTG)

The Universal Serial Bus (USB) module contains

analog and digital components to provide a USB 2.0

full-speed and low-speed embedded host, full-speed

device or OTG implementation with a minimum of

external components. This module in Host mode is

intended for use as an embedded host and therefore

does not implement a UHCI or OHCI controller.

The USB module consists of the clock generator, the

USB voltage comparators, the transceiver, the Serial

Interface Engine (SIE), a dedicated USB DMA control-

ler, pull-up and pull-down resistors, and the register

interface. A block diagram of the PIC32 USB OTG

module is presented in Figure 10-1.

The clock generator provides the 48 MHz clock

required for USB full-speed and low-speed communi-

cation. The voltage comparators monitor the voltage on

the V

BUS

pin to determine the state of the bus. The

transceiver provides the analog translation between

the USB bus and the digital logic. The SIE is a state

machine that transfers data to and from the endpoint

buffers and generates the hardware protocol for data

transfers. The USB DMA controller transfers data

between the data buffers in RAM and the SIE. The inte-

grated pull-up and pull-down resistors eliminate the

need for external signaling components. The register

interface allows the CPU to configure and

communicate with the module.

The PIC32 USB module includes the following

features:

• USB Full-speed support for host and device

• Low-speed host support

• USB OTG support

• Integrated signaling resistors

• Integrated analog comparators for V

BUS

monitoring

• Integrated USB transceiver

• Transaction handshaking performed by hardware

• Endpoint buffering anywhere in system RAM

• Integrated DMA to access system RAM and Flash

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 27. “USB On-

The-Go (OTG)” (DS60001126) in the

“PI C32 Fami ly Re ferenc e Manua l” , which

is available from the Microchip web site

(www.microchip.com/PIC32).

Note: The implementation and use of the USB

specifications, and other third party

specifications or technologies, may

require licensing; including, but not limited

to, USB Implementers Forum, Inc. (also

referred to as USB-IF). The user is fully

responsible for investigating and

satisfying any applicable licensing

obligations.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 106  2014-2017 Microchip Technology Inc.

FIGURE 10-1: PIC32MX1XX/2XX/5XX USB I NTERFACE DIAGRAM

OSC1

OSC2

Primary Oscillator

8MHzTypical

FRC

Oscillator

TUN<5:0>

(3)

PLL

48 MHz USB Clock

(6)

Div x

UPLLEN

(5)

(PB Out)

(1)

UFRCEN

(2)

OSC

)

UPLLIDIV

(5)

IN(4)

Div 2

USB

D+

D-

USBID

(7)

BUS

Transceiver

SIE

BUSON(7)

Comparators

USB

SRP Charge

SRP Discharge

Registers

and

Control

Interface

Transceiver Power 3.3V

To Clock Generator for Core and Peripherals

Sleep or Idle

Sleep

USBEN

USB Suspend

CPU Clock Not P

OSC

USB Module

Voltage

System

RAM

USB Suspend

Full Speed Pull-up

Host Pull-down

Low Speed Pull-up

Host Pull-down

ID Pull-up

DMA

Note 1: PB clock is only available on this pin for select EC modes.

2: This bit field is contained in the OSCCON register.

3: This bit field is contained in the OSCTRM register.

4: USB PLL U

requirements: 4 MHz.

5: This bit field is contained in the DEVCFG2 register.

6: A 48 MHz clock is required for proper USB operation.

7: Pins can be used as GPIO when the USB module is disabled or if the USB is enabled but

DEVCFG3<31:30> = ‘0b00.

Nominal +5V

 2014-2017 Microchip Technology Inc. DS60001290E-page 107

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

10.1 Control Registers

TABLE 10-1: USB REGISTER MAP

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

5040 U1OTGIR

(2)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF —VBUSVDIF 0000

5050 U1OTGIE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE —VBUSVDIE 0000

5060 U1OTGSTAT

(3)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— ID —LSTATE —SESVD SESEND —VBUSVD 0000

5070 U1OTGCON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000

5080 U1PWRC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————UACTPND

(4)

— — USLPGRD USBBUSY —USUSPEND USBPWR 0000

5200 U1IR

(2)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF 0000

DETACHIF 0000

5210 U1IE

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE 0000

DETACHIE 0000

5220 U1EIR

(2)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0000

EOFEF 0000

5230 U1EIE

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0000

EOFEE 0000

5240 U1STAT

(3)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— ENDPT<3:0> DIR PPBI — — 0000

5250 U1CON

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————JSTATE SE0 PKTDIS USBRST HOSTEN RESUME PPBRST USBEN 0000

TOKBUSY SOFEN 0000

5260 U1ADDR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————LSPDEN DEVADDR<6:0> 0000

5270 U1BDTP1 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— BDTPTRL<15:9> —0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See

Section 11.2 “CLR, SET, and INV Registe rs” for more information.

2: This register does not have associated SET and INV registers.

3: This register does not have associated CLR, SET and INV registers.

4: Reset value for this bit is undefined.

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DS60001290E-page 108  2014-2017 Microchip Technology Inc.

5280 U1FRML

(3)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— FRML<7:0> 0000

5290 U1FRMH

(3)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — — FRMH<2:0> 0000

52A0 U1TOK 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— PID<3:0> EP<3:0> 0000

52B0 U1SOF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— CNT<7:0> 0000

52C0 U1BDTP2 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— BDTPTRH<23:16> 0000

52D0 U1BDTP3 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— BDTPTRU<31:24> 0000

52E0 U1CNFG1 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————UTEYE — — USBSIDL LSDEV — — UASUSPND 0000

5300 U1EP0 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————— LSPD RETRYDIS —EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5310 U1EP1 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5320 U1EP2 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5330 U1EP3 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5340 U1EP4 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5350 U1EP5 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5360 U1EP6 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5370 U1EP7 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5380 U1EP8 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

TABLE 10-1: USB REGISTER MAP (CONTINUED)

Virt ual Addres s

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Sectio n 11.2 “CLR, SET, an d INV Regis te rs” for more information.

2: This register does not have associated SET and INV registers.

3: This register does not have associated CLR, SET and INV registers.

4: Reset value for this bit is undefined.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

5390 U1EP9 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53A0 U1EP10 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53B0 U1EP11 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53C0 U1EP12 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53D0 U1EP13 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53E0 U1EP14 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53F0 U1EP15 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

TABLE 10-1: USB REGISTER MAP (CONTINUED)

Virt ual Addres s

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Sectio n 11.2 “CLR, SET, an d INV Regis te rs” for more information.

2: This register does not have associated SET and INV registers.

3: This register does not have associated CLR, SET and INV registers.

4: Reset value for this bit is undefined.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0

R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS

IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF

Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 IDIF: ID State Change Indicator bit

1 = Change in ID state detected

0 = No change in ID state detected

bit 6 T1MSECIF: 1 Millisecond Timer bit

1 = 1 millisecond timer has expired

0 = 1 millisecond timer has not expired

bit 5 LSTATEIF: Line State Stable Indicator bit

1 = USB line state has been stable for 1millisecond, but different from last time

0 = USB line state has not been stable for 1 millisecond

bit 4 ACTVIF: Bus Activity Indicator bit

1 = Activity on the D+, D-, ID or V

BUS

pins has caused the device to wake-up

0 = Activity has not been detected

bit 3 SESVDIF: Session Valid Change Indicator bit

1 =V

BUS

voltage has dropped below the session end level

0 =V

BUS

voltage has not dropped below the session end level

bit 2 SESENDIF: B-Device V

BUS

Change Indicator bit

1 = A change on the session end input was detected

0 = No change on the session end input was detected

bit 1 Unimplemented: Read as ‘0’

bit 0 VBUSVDIF: A-Device V

BUS

Change Indicator bit

1 = Change on the session valid input detected

0 = No change on the session valid input detected

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 IDIE: ID Interrupt Enable bit

1 = ID interrupt enabled

0 = ID interrupt disabled

bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit

1 = 1 millisecond timer interrupt enabled

0 = 1 millisecond timer interrupt disabled

bit 5 LSTATEIE: Line State Interrupt Enable bit

1 = Line state interrupt enabled

0 = Line state interrupt disabled

bit 4 ACTVIE: Bus Activity Interrupt Enable bit

1 = ACTIVITY interrupt enabled

0 = ACTIVITY interrupt disabled

bit 3 SESVDIE: Session Valid Interrupt Enable bit

1 = Session valid interrupt enabled

0 = Session valid interrupt disabled

bit 2 SESENDIE: B-Session End Interrupt Enable bit

1 = B-session end interrupt enabled

0 = B-session end interrupt disabled

bit 1 Unimplemented: Read as ‘0’

bit 0 VBUSVDIE: A-V

BUS

Valid Interrupt Enable bit

1 =A-V

BUS

valid interrupt enabled

0 =A-V

BUS

valid interrupt disabled

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 112  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0

ID —LSTATE— SESVD SESEND — VBUSVD

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 ID: ID Pin State Indicator bit

1 = No cable is attached or a Type-B cable has been plugged into the USB receptacle

0 = A Type-A cable has been plugged into the USB receptacle

bit 6 Unimplemented: Read as ‘0’

bit 5 LSTATE: Line State Stable Indicator bit

1 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has been stable for the previous 1 ms

0 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has not been stable for the previous 1 ms

bit 4 Unimplemented: Read as ‘0’

bit 3 SESVD: Session Valid Indicator bit

1 =V

BUS

voltage is above Session Valid on the A or B device

0 =V

BUS

voltage is below Session Valid on the A or B device

bit 2 SESEND: B-Device Session End Indicator bit

1 =V

BUS

voltage is below Session Valid on the B device

0 =V

BUS

voltage is above Session Valid on the B device

bit 1 Unimplemented: Read as ‘0’

bit 0 VBUSVD: A-Device V

BUS

Valid Indicator bit

1 =V

BUS

voltage is above Session Valid on the A device

0 =V

BUS

voltage is below Session Valid on the A device

 2014-2017 Microchip Technology Inc. DS60001290E-page 113

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 DPPULUP: D+ Pull-Up Enable bit

1 = D+ data line pull-up resistor is enabled

0 = D+ data line pull-up resistor is disabled

bit 6 DMPULUP: D- Pull-Up Enable bit

1 = D- data line pull-up resistor is enabled

0 = D- data line pull-up resistor is disabled

bit 5 DPPULDWN: D+ Pull-Down Enable bit

1 = D+ data line pull-down resistor is enabled

0 = D+ data line pull-down resistor is disabled

bit 4 DMPULDWN: D- Pull-Down Enable bit

1 = D- data line pull-down resistor is enabled

0 = D- data line pull-down resistor is disabled

bit 3 VBUSON: V

BUS

Power-on bit

1 =V

BUS

line is powered

0 =V

BUS

line is not powered

bit 2 OTGEN: OTG Functionality Enable bit

1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control

0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control

bit 1 VBUSCHG: V

BUS

Charge Enable bit

1 =V

BUS

line is charged through a pull-up resistor

0 =V

BUS

line is not charged through a resistor

bit 0 VBUSDIS: V

BUS

Discharge Enable bit

1 =V

BUS

line is discharged through a pull-down resistor

0 =V

BUS

line is not discharged through a resistor

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

UACTPND —— USLPGRD USBBUSY — USUSPEND USBPWR

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 UACTPND: USB Activity Pending bit

1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet

0 = An interrupt is not pending

bit 6-5 Unimplemented: Read as ‘0’

bit 4 USLPGRD: USB Sleep Entry Guard bit

1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending

0 = USB module does not block Sleep entry

bit 3 USBBUSY: USB Module Busy bit

(1)

1 = USB module is active or disabled, but not ready to be enabled

0 = USB module is not active and is ready to be enabled

Note: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all

USB module registers produce undefined results.

bit 2 Unimplemented: Read as ‘0’

bit 1 USUSPEND: USB Suspend Mode bit

1 = USB module is placed in Suspend mode

(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)

0 = USB module operates normally

bit 0 USBPWR: USB Operation Enable bit

1 = USB module is turned on

0 = USB module is disabled

(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power

consumption.)

 2014-2017 Microchip Technology Inc. DS60001290E-page 115

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 R/WC-0, HS

STALLIF ATTACHIF

(1)

RESUMEIF

(2)

IDLEIF TRNIF

(3)

SOFIF UERRIF

(4)

URSTIF

(5)

DETACHIF

(6)

Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 STALLIF: STALL Handshake Interrupt bit

1 = In Host mode, a STALL handshake was received during the handshake phase of the transaction

In Device mode, a STALL handshake was transmitted during the handshake phase of the transaction

0 = STALL handshake has not been sent

bit 6 ATTACHIF: Peripheral Attach Interrupt bit

(1)

1 = Peripheral attachment was detected by the USB module

0 = Peripheral attachment was not detected

bit 5 RESUMEIF: Resume Interrupt bit

(2)

1 = K-State is observed on the D+ or D- pin for 2.5 µs

0 = K-State is not observed

bit 4 IDLEIF: Idle Detect Interrupt bit

1 = Idle condition detected (constant Idle state of 3 ms or more)

0 = No Idle condition detected

bit 3 TRNIF: Token Processing Complete Interrupt bit

(3)

1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information

0 = Processing of current token not complete

bit 2 SOFIF: SOF Token Interrupt bit

1 = SOF token received by the peripheral or the SOF threshold reached by the host

0 = SOF token was not received nor threshold reached

bit 1 UERRIF: USB Error Condition Interrupt bit

(4)

1 = Unmasked error condition has occurred

0 = Unmasked error condition has not occurred

bit 0 URSTIF: USB Reset Interrupt bit (Device mode)

(5)

1 = Valid USB Reset has occurred

0 = No USB Reset has occurred

bit 0 DETACHIF: USB Detach Interrupt bit (Host mode)

(6)

1 = Peripheral detachment was detected by the USB module

0 = Peripheral detachment was not detected

Note 1: This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for

2.5 µs, and the current bus state is not SE0.

2: When not in Suspend mode, this interrupt should be disabled.

3: Clearing this bit will cause the STAT FIFO to advance.

4: Only error conditions enabled through the U1EIE register will set this bit.

5: Device mode.

6: Host mode.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 116  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

——————— —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

——————— —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

——————— —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE

(1)

URSTIE

(2)

DETACHIE

(3)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 STALLIE: STALL Handshake Interrupt Enable bit

1 = STALL interrupt enabled

0 = STALL interrupt disabled

bit 6 ATTACHIE: ATTACH Interrupt Enable bit

1 = ATTACH interrupt enabled

0 = ATTACH interrupt disabled

bit 5 RESUMEIE: RESUME Interrupt Enable bit

1 = RESUME interrupt enabled

0 = RESUME interrupt disabled

bit 4 IDLEIE: Idle Detect Interrupt Enable bit

1 = Idle interrupt enabled

0 = Idle interrupt disabled

bit 3 TRNIE: Token Processing Complete Interrupt Enable bit

1 = TRNIF interrupt enabled

0 = TRNIF interrupt disabled

bit 2 SOFIE: SOF Token Interrupt Enable bit

1 = SOFIF interrupt enabled

0 = SOFIF interrupt disabled

bit 1 UERRIE: USB Error Interrupt Enable bit

(1)

1 = USB Error interrupt enabled

0 = USB Error interrupt disabled

bit 0 URSTIE: USB Reset Interrupt Enable bit

(2)

1 = URSTIF interrupt enabled

0 = URSTIF interrupt disabled

DETACHIE: USB Detach Interrupt Enable bit

(3)

1 = DATTCHIF interrupt enabled

0 = DATTCHIF interrupt disabled

Note 1: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.

2: Device mode.

3: Host mode.

 2014-2017 Microchip Technology Inc. DS60001290E-page 117

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS

BTSEF BMXEF DMAEF

(1)

BTOEF

(2)

DFN8EF CRC16EF

CRC5EF

(4)

PIDEF

EOFEF

(3,5)

Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 BTSEF: Bit Stuff Error Flag bit

1 = Packet rejected due to bit stuff error

0 = Packet accepted

bit 6 BMXEF: Bus Matrix Error Flag bit

1 = The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, is invalid.

0 = No address error

bit 5 DMAEF: DMA Error Flag bit

(1)

1 = USB DMA error condition detected

0 = No DMA error

bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit

(2)

1 = Bus turnaround time-out has occurred

0 = No bus turnaround time-out

bit 3 DFN8EF: Data Field Size Error Flag bit

1 = Data field received is not an integral number of bytes

0 = Data field received is an integral number of bytes

bit 2 CRC16EF: CRC16 Failure Flag bit

1 = Data packet rejected due to CRC16 error

0 = Data packet accepted

Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the

module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer

size is not sufficient to store the received data packet causing it to be truncated.

2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)

has elapsed.

3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has

reached zero.

4: Device mode.

5: Host mode.

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bit 1 CRC5EF: CRC5 Host Error Flag bit

(4)

1 = Token packet rejected due to CRC5 error

0 = Token packet accepted

EOFEF: EOF Error Flag bit

(3,5)

1 = EOF error condition detected

0 = No EOF error condition

bit 0 PIDEF: PID Check Failure Flag bit

1 = PID check failed

0 = PID check passed

Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the

module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer

size is not sufficient to store the received data packet causing it to be truncated.

2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)

has elapsed.

3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has

reached zero.

4: Device mode.

5: Host mode.

 2014-2017 Microchip Technology Inc. DS60001290E-page 119

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE

(1)

PIDEE

EOFEE

(2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit

1 = BTSEF interrupt enabled

0 = BTSEF interrupt disabled

bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit

1 = BMXEF interrupt enabled

0 = BMXEF interrupt disabled

bit 5 DMAEE: DMA Error Interrupt Enable bit

1 = DMAEF interrupt enabled

0 = DMAEF interrupt disabled

bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit

1 = BTOEF interrupt enabled

0 = BTOEF interrupt disabled

bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit

1 = DFN8EF interrupt enabled

0 = DFN8EF interrupt disabled

bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit

1 = CRC16EF interrupt enabled

0 = CRC16EF interrupt disabled

bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit

(1)

1 = CRC5EF interrupt enabled

0 = CRC5EF interrupt disabled

EOFEE: EOF Error Interrupt Enable bit

(2)

1 = EOF interrupt enabled

0 = EOF interrupt disabled

bit 0 PIDEE: PID Check Failure Interrupt Enable bit

1 = PIDEF interrupt enabled

0 = PIDEF interrupt disabled

Note 1: Device mode.

2: Host mode.

Note: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R-x R-x R-x R-x R-x R-x U-0 U-0

ENDPT<3:0> DIR PPBI — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits

(Represents the number of the BDT, updated by the last USB transfer.)

1111 = Endpoint 15

1110 = Endpoint 14

•

0001 = Endpoint 1

0000 = Endpoint 0

bit 3 DIR: Last BD Direction Indicator bit

1 = Last transaction was a transmit transfer (TX)

0 = Last transaction was a receive transfer (RX)

bit 2 PPBI: Ping-Pong BD Pointer Indicator bit

1 = The last transaction was to the ODD BD bank

0 = The last transaction was to the EVEN BD bank

bit 1-0 Unimplemented: Read as ‘0’

Note: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only

valid when the TRNIF bit (U1IR<3>) is active. Clearing the TRNIF bit advances the FIFO. Data in register

is invalid when the TRNIF bit = 0.

 2014-2017 Microchip Technology Inc. DS60001290E-page 121

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

JSTATE SE0 PKTDIS

(4)

USBRST HOSTEN

(2)

RESUME

(3)

PPBRST USBEN

(4)

TOKBUSY

(1,5)

SOFEN

(5)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 JSTA TE: Live Differential Receiver JSTATE flag bit

1 = JSTATE detected on the USB

0 = No JSTATE detected

bit 6 SE0: Live Single-Ended Zero flag bit

1 = Single Ended Zero detected on the USB

0 = No Single Ended Zero detected

bit 5 PKTDIS: Packet Transfer Disable bit

(4)

1 = Token and packet processing disabled (set upon SETUP token received)

0 = Token and packet processing enabled

TOKBUSY: Token Busy Indicator bit

(1,5)

1 = Token being executed by the USB module

0 = No token being executed

bit 4 USBRST: Module Reset bit

(5)

1 = USB reset generated

0 = USB reset terminated

bit 3 HOSTEN: Host Mode Enable bit

(2)

1 = USB host capability enabled

0 = USB host capability disabled

bit 2 RESUME: RESUME Signaling Enable bit

(3)

1 = RESUME signaling activated

0 = RESUME signaling disabled

Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see

2: All host control logic is reset any time that the value of this bit is toggled.

3: Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and

then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to

the RESUME signaling when this bit is cleared.

4: Device mode.

5: Host mode.

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bit 1 PPBRST: Ping-Pong Buffers Reset bit

1 = Reset all Even/Odd buffer pointers to the EVEN BD banks

0 = Even/Odd buffer pointers not being Reset

bit 0 USBEN: USB Module Enable bit

(4)

1 = USB module and supporting circuitry enabled

0 = USB module and supporting circuitry disabled

SOFEN: SOF Enable bit

(5)

1 = SOF token sent every 1 ms

0 = SOF token disabled

Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see

2: All host control logic is reset any time that the value of this bit is toggled.

3: Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and

then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to

the RESUME signaling when this bit is cleared.

4: Device mode.

5: Host mode.

 2014-2017 Microchip Technology Inc. DS60001290E-page 123

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LSPDEN DEVADDR<6:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 LSPDEN: Low Speed Enable Indicator bit

1 = Next token command to be executed at Low Speed

0 = Next token command to be executed at Full Speed

bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FRML<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 FRML<7:0>: The 11-bit Frame Number Lower bits

The register bits are updated with the current frame number whenever a SOF TOKEN is received.

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DS60001290E-page 124  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — — FRMH<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-3 Unimplemented: Read as ‘0’

bit 2-0 FRMH<2:0>: The Upper 3 bits of the Frame Numbers bits

The register bits are updated with the current frame number whenever a SOF TOKEN is received.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PID<3:0>

(1)

EP<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-4 PID<3:0>: Token Type Indicator bits

(1)

0001 = OUT (TX) token type transaction

1001 = IN (RX) token type transaction

1101 = SETUP (TX) token type transaction

Note: All other values are reserved and must not be used.

bit 3-0 EP<3:0>: Token Command Endpoint Address bits

The four bit value must specify a valid endpoint.

Note 1: All other values are reserved and must not be used.

 2014-2017 Microchip Technology Inc. DS60001290E-page 125

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 CNT<7:0>: SOF Threshold Value bits

Typical values of the threshold are:

01001010 = 64-byte packet

00101010 = 32-byte packet

00011010 =16-byte packet

00010010 =8-byte packet

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

BDTPTRL<15:9> —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-1 BDTPTRL<15:9>: BDT Base Address bits

This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting

location of the BDT in system memory.

The 32-bit BDT base address is 512-byte aligned.

bit 0 Unimplemented: Read as ‘0’

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BDTPTRH<23:16>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 BDTPTRH<23:16>: BDT Base Address bits

This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting

location of the BDT in system memory.

The 32-bit BDT base address is 512-byte aligned.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BDTPTRU<31:24>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 BDTPTRU<31:24>: BDT Base Address bits

This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location

of the BDT in system memory.

The 32-bit BDT base address is 512-byte aligned.

 2014-2017 Microchip Technology Inc. DS60001290E-page 127

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0

UTEYE — — USBSIDL USBSIDL ——UASUSPND

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 UTEYE: USB Eye-Pattern Test Enable bit

1 = Eye-Pattern Test enabled

0 = Eye-Pattern Test disabled

bit 6-5 Unimplemented: Read as ‘0’

bit 4 USBSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 3 LSDEV: Low-Speed Device Enable bit

1 = USB module operates in Low-Speed Device mode only

0 = USB module operates in OTG, Host, or Full-Speed Device mode

bit 2-1 Unimplemented: Read as ‘0’

bit 0 UASUSPND: Automatic Suspend Enable bit

1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit

(U1PWRC<1>) in Register 10-5.

0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the

USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)

1 = Direct connection to a low-speed device enabled

0 = Direct connection to a low-speed device disabled; hub required with PRE_PID

bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)

1 = Retry NAKed transactions disabled

0 = Retry NAKed transactions enabled; retry done in hardware

bit 5 Unimplemented: Read as ‘0’

bit 4 EPCONDIS: Bidirectional Endpoint Control bit

If EPTXEN = 1 and EPRXEN = 1:

1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed

0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed

Otherwise, this bit is ignored.

bit 3 EPRXEN: Endpoint Receive Enable bit

1 = Endpoint n receive enabled

0 = Endpoint n receive disabled

bit 2 EPTXEN: Endpoint Transmit Enable bit

1 = Endpoint n transmit enabled

0 = Endpoint n transmit disabled

bit 1 EPSTALL: Endpoint Stall Status bit

1 = Endpoint n was stalled

0 = Endpoint n was not stalled

bit 0 EPHSHK: Endpoint Handshake Enable bit

1 = Endpoint Handshake enabled

0 = Endpoint Handshake disabled (typically used for isochronous endpoints)

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

11.0 I/O PORTS

General purpose I/O pins are the simplest of peripher-

als. They allow the PIC

MCU to monitor and control

other devices. To add flexibility and functionality, some

pins are multiplexed with alternate functions. These

functions depend on which peripheral features are on

the device. In general, when a peripheral is functioning,

that pin may not be used as a general purpose I/O pin.

The following are the key features of this module:

• Individual output pin open-drain enable or disable

• Individual input pin weak pull-up and pull-down

• Monitor selective inputs and generate interrupt

when change in pin state is detected

• Operation during CPU Sleep and Idle modes

• Fast bit manipulation using CLR, SET and INV

registers

Figure 11-1 illustrates a block diagram of a typical

multiplexed I/O port.

FIGURE 11-1: BLOCK DIAGRAM OF A TYPIC AL MU LTIPLEXED PORT STRUCTURE

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 12. “I/O Ports”

(DS60001120) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

Peripheral Output Data

Peripheral Module

Peripheral Output Enable

PIO Module

Peripheral Module Enable

WR LAT

I/O Pin

WR PORT

Data Bus

RD LAT

RD PORT

RD TRIS

WR TRIS

RD ODC

SYSCLK

EN Q

SYSCLK

WR ODC

ODC

TRIS

LAT

Sleep

Output Multip le xer s

I/O Cell

Synchronization

Peripheral Input

Legend:

R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.

Note:

This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure

for any specific port/peripheral combination may be different than shown here.

Peripheral Input Buffer

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11 .1 Pa ra llel I/ O (P IO) Po rt s

All port pins have ten registers directly associated with

their operation as digital I/O. The data direction register

(TRISx) determines whether the pin is an input or an

output. If the data direction bit is a ‘1’, then the pin is an

input. All port pins are defined as inputs after a Reset.

Reads from the latch (LATx) read the latch. Writes to

the latch write the latch. Reads from the port (PORTx)

read the port pins, while writes to the port pins write the

latch.

11.1.1 OPEN-DRAIN CONFIGURATION

In addition to the PORTx, LATx, and TRISx registers for

data control, some port pins can also be individually

configured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits

configures the corresponding pin, regardless of the out-

put function including PPS remapped output functions

to act as an open-drain output. The only exception is

the I

C pins that are open drain by default.

The open-drain feature allows the presence of outputs

higher than V

(e.g., 5V) on any desired 5V-tolerant

pins by using external pull-up resistors. The maximum

open-drain voltage allowed is the same as the

maximum V

specification.

See the “Device Pin Tables” section for the available

pins and their functionality.

11.1.2 CONFIGURING ANALOG AND

DIGITAL PORT PINS

The ANSELx register controls the operation of the

analog port pins. The port pins that are to function as

analog inputs must have their corresponding ANSEL

and TRIS bits set. In order to use port pins for I/O

functionality with digital modules, such as Timers,

UARTs, etc., the corresponding ANSELx bit must be

cleared.

The ANSELx register has a default value of 0xFFFF;

therefore, all pins that share analog functions are

analog (not digital) by default. The ANSELx register bit,

when cleared, disables the corresponding digital input

buffer pin(s).

If the TRIS bit is cleared (output) while the ANSELx bit

is set, the digital output level (V

or V

) is converted

by an analog peripheral, such as the ADC module or

Comparator module. The TRISx bits only control the

corresponding digital output buffer pin(s).

When the PORT register is read, all pins configured as

analog input channels are read as cleared (a low level;

i.e., when ANSELx = 1; TRISx = x).

Analog levels on any pin defined as a digital input

(including the ANx pins) can cause the input buffer to

consume current that exceeds the device

specifications.

11.1.3 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be an NOP.

11.1.4 INPUT CHANGE NOTIFICATION

The input Change Notification (CN) function of the I/O

ports allows the PIC32MX1XX/2XX/5XX 64/100-pin

devices to generate interrupt requests to the processor

in response to a change-of-state on selected input pins.

This feature can detect input change-of-states even in

Sleep mode, when the clocks are disabled. Every I/O

port pin can be selected (enabled) for generating an

interrupt request on a change-of-state.

Five control registers are associated with the CN func-

tionality of each I/O port. The CNENx registers contain

the CN interrupt enable control bits for each of the input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

The CNSTATx register indicates whether a change

occurred on the corresponding pin since the last read

of the PORTx bit.

11.1.5 INTERNALLY SELECTABLE PULL-

UPS AND PULL-DOWNS

Each I/O pin also has a weak pull-up and every I/O

pin has a weak pull-down connected to it, which are

independent of any other I/O pin functionality (i.e.,

PPS, Open Drain, or CN). The pull-ups act as a

current source or sink source connected to the pin,

and eliminate the need for external resistors when

push-button or keypad devices are connected. The

pull-ups and pull-downs are enabled separately using

the CNPUx and the CNPDx registers, which contain

the control bits for each of the pins. Setting any of the

control bits enables the weak pull-ups and/or pull-

downs for the corresponding pins.

An additional control register (CNCONx) is shown in

11 .2 CL R , SE T, a n d INV Reg is ters

Every I/O module register has a corresponding CLR

(clear), SET (set) and INV (invert) register designed to

provide fast atomic bit manipulations. As the name of

the register implies, a value written to a SET, CLR or

INV register effectively performs the implied operation,

but only on the corresponding base register and only

bits specified as ‘1’ are modified. Bits specified as ‘0’

are not modified.

Reading SET, CLR and INV registers returns undefined

values. To see the affects of a write operation to a SET,

CLR or INV register, the base register must be read.

Note: Pull-ups and pull-downs on change notifi-

cation pins should always be disabled

when the port pin is configured as a digital

output. They should also be disabled on

5V tolerant pins when the pin voltage can

exceed V

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

11.3 Peripheral Pin Select

A major challenge in general purpose devices is provid-

ing the largest possible set of peripheral features while

minimizing the conflict of features on I/O pins. The chal-

lenge is even greater on low pin count devices. In an

application where more than one peripheral needs to

be assigned to a single pin, inconvenient workarounds

in application code or a complete redesign may be the

only options.

Peripheral pin select configuration provides an

alternative to these choices by enabling peripheral set

selection and their placement on a wide range of I/O

pins. By increasing the pinout options available on a

particular device, users can better tailor the device to

their entire application, rather than trimming the

application to fit the device.

The peripheral pin select configuration feature

operates over a fixed subset of digital I/O pins. Users

may independently map the input and/or output of most

digital peripherals to these I/O pins. Peripheral pin

select is performed in software and generally does not

require the device to be reprogrammed. Hardware

safeguards are included that prevent accidental or

spurious changes to the peripheral mapping once it has

been established.

11.3.1 AVAILABLE PINS

The number of available pins is dependent on the

particular device and its pin count. Pins that support the

peripheral pin select feature include the designation

“RPn” in their full pin designation, where “RP”

designates a remappable peripheral and “n” is the

remappable port number.

11.3.2 AVAILABLE PERIPHERALS

The peripherals managed by the peripheral pin select

are all digital-only peripherals. These include general

serial communications (UART and SPI), general pur-

pose timer clock inputs, timer-related peripherals (input

capture and output compare) and interrupt-on-change

inputs.

In comparison, some digital-only peripheral modules

are never included in the peripheral pin select feature.

This is because the peripheral’s function requires spe-

cial I/O circuitry on a specific port and cannot be easily

connected to multiple pins. These modules include I

among others. A similar requirement excludes all mod-

ules with analog inputs, such as the Analog-to-Digital

Converter (ADC).

A key difference between remappable and non-remap-

pable peripherals is that remappable peripherals are

not associated with a default I/O pin. The peripheral

must always be assigned to a specific I/O pin before it

can be used. In contrast, non-remappable peripherals

are always available on a default pin, assuming that the

peripheral is active and not conflicting with another

peripheral.

When a remappable peripheral is active on a given I/O

pin, it takes priority over all other digital I/O and digital

communication peripherals associated with the pin.

Priority is given regardless of the type of peripheral that

is mapped. Remappable peripherals never take priority

over any analog functions associated with the pin.

11.3.3 CONTROLLING PERIPHERAL PIN

SELECT

Peripheral pin select features are controlled through

two sets of SFRs: one to map peripheral inputs, and

one to map outputs. Because they are separately

controlled, a particular peripheral’s input and output (if

the peripheral has both) can be placed on any

selectable function pin without constraint.

The association of a peripheral to a peripheral-select-

able pin is handled in two different ways, depending on

whether an input or output is being mapped.

11.3.4 INPUT MAPPING

The inputs of the peripheral pin select options are

mapped on the basis of the peripheral. That is, a control

will be mapped to. The [pin name]R registers, where [pin

name] refers to the peripheral pins listed in Ta b le 11-1,

are used to configure peripheral input mapping (see

fields. Programming these bit fields with an appropriate

value maps the RPn pin with the corresponding value to

that peripheral. For any given device, the valid range of

values for any bit field is shown in Table 11-1.

For example, Figure 11-2 illustrates the remappable

pin selection for the U1RX input.

FIGURE 11-2: REMAPPABLE INPUT

EXAMPLE FOR U1RX

RPA2

RPB6

RPA4

2U1RX input

U1RXR<3:0>

to peripheral

RPn

Note: For input only, peripheral pin select functionality

does not have priority over TRISx settings.

Therefore, when configuring RPn pin for input,

the corresponding bit in the TRISx register must

also be configured for input (set to ‘1’).

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TABLE 11-1: INPUT PIN SELECTION

Peripheral Pin [pin na me]R SFR [pin name]R bits [pin name]R Value to

RPn Pin Selection

INT3 INT3R INT3R<3:0> 0000 = RPD2

0001 = RPG8

0010 = RPF4

0011 = RPD10

0100 = RPF1

0101 = RPB9

0110 = RPB10

0111 = RPC14

1000 = RPB5

(7)

1001 = Reserved

1010 = RPC1

(3)

1011 = RPD14

(3)

1100 = RPG1

(3)

1101 = RPA14

(3)

1110 = Reserved

1111 = RPF2

(1)

T2CK T2CKR T2CKR<3:0>

IC3 IC3R IC3R<3:0>

U1RX U1RXR U1RXR<3:0>

U2RX U2RXR U2RXR<3:0>

U5CTS

(3)

U5CTSR U5CTSR<3:0>

SDI3 SDI3R SDI3R<3:0>

SDI4

(3)

SDI4R SDI4R<3:0>

REFCLKI REFCLKIR REFCLKIR<3:0>

INT4 INT4R INT4R<3:0> 0000 = RPD3

0001 = RPG7

0010 = RPF5

0011 = RPD11

0100 = RPF0

0101 = RPB1

0110 = RPE5

0111 = RPC13

1000 = RPB3

1001 = RPF12

(3)

1010 = RPC4

(3)

1011 = RPD15

(3)

1100 = RPG0

(3)

1101 = RPA15

(3)

1110 = RPF2

(1)

1111 = RPF7

(2)

T5CK T5CKR T5CKR<3:0>

IC4 IC4R IC4R<3:0>

U3RX U3RXR U3RXR<3:0>

U4CTS U4CTSR U4CTSR<3:0>

SDI1 SDI1R SDI1R<3:0>

SDI2 SDI2R SDI2R<3:0>

C1RX

(5)

C1RXR

(5)

C1RXR<3:0>

(5)

INT2 INT2R INT2R<3:0> 0000 = RPD9

0001 = RPG6

0010 = RPB8

0011 = RPB15

0100 = RPD4

0101 = RPB0

0110 = RPE3

0111 = RPB7

1000 = Reserved

1001 = RPF12

(3)

1010 = RPD12

(3)

1011 = RPF8

(3)

1100 = RPC3

(3)

1101 = RPE9

(3)

1110 = RPD14

(3)

1111 = RPB2

T4CK T4CKR T4CKR<3:0>

IC2 IC2R IC2R<3:0>

IC5 IC5R IC5R<3:0>

U1CTS U1CTSR U1CTSR<3:0>

U2CTS U2CTSR U2CTSR<3:0>

SS1 SS1R SS1R<3:0>

SS3 SS3R SS1R<3:0>

SS4

(3)

SS3R SS3R<3:0>

Note 1: This selection is not available on 64-pin USB devices.

2: This selection is only available on 100-pin General Purpose devices.

3: This selection is not available on 64-pin devices.

4: This selection is not available when USBID functionality is used on USB devices.

5: This selection is not available on devices without a CAN module.

6: This selection is not available on USB devices.

7: This selection is not available when V

BUSON

functionality is used on USB devices.

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INT1 INT1R INT1R<3:0> 0000 = RPD1

0001 = RPG9

0010 = RPB14

0011 = RPD0

0100 = RPD8

0101 = RPB6

0110 = RPD5

0111 = RPB2

1000 = RPF3

(4)

1001 = RPF13

(3)

1010 = Reserved

1011 = RPF2

(1)

1100 = RPC2

(3)

1101 = RPE8

(3)

1110 = Reserved

1111 = Reserved

T3CK T3CKR T3CKR<3:0>

IC1 IC1R IC1R<3:0>

U3CTS U3CTSR U3CTSR<3:0>

U4RX U4RXR U4RXR<3:0>

U5RX U5RXR U5RXR<3:0>

SS2 SS2R SS2R<3:0>

OCFA OCFAR OCFAR<3:0>

TABLE 11-1: INPUT PIN SELECTION (CONTINUED)

Peripheral Pin [pin nam e]R SFR [pin na me]R bits [pin name]R Value to

RPn Pin Selection

Note 1: This selection is not available on 64-pin USB devices.

2: This selection is only available on 100-pin General Purpose devices.

3: This selection is not available on 64-pin devices.

4: This selection is not available when USBID functionality is used on USB devices.

5: This selection is not available on devices without a CAN module.

6: This selection is not available on USB devices.

7: This selection is not available when V

BUSON

functionality is used on USB devices.

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11.3.5 OUTPUT MAPPING

In contrast to inputs, the outputs of the peripheral pin

select options are mapped on the basis of the pin. In

this case, a control register associated with a

particular pin dictates the peripheral output to be

mapped. The RPnR registers (Register 11-2) are

used to control output mapping. Like the [pin name]R

registers, each register contains sets of 4 bit fields.

The value of the bit field corresponds to one of the

peripherals, and that peripheral’s output is mapped

to the pin (see Tabl e 11-2 and Figure 11-3).

A null output is associated with the output register reset

value of ‘0’. This is done to ensure that remappable

outputs remain disconnected from all output pins by

default.

FIGURE 11-3: EXAMPLE OF

MULTIPLEXING OF

REMAPPABLE OUTPUT

FOR RPA0

11.3.6 CONTROLLING CONFIGURATION

CHANGES

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. PIC32 devices include two features to

prevent alterations to the peripheral map:

• Control register lock sequence

• Configuration bit select lock

11.3.6.1 Control Register Lock

Under normal operation, writes to the RPnR and [pin

name]R registers are not allowed. Attempted writes

appear to execute normally, but the contents of the

registers remain unchanged. To change these regis-

ters, they must be unlocked in hardware. The regis-

ter lock is controlled by the IOLOCK Configuration bit

(CFGCON<13>). Setting IOLOCK prevents writes to

the control registers; clearing IOLOCK allows writes.

To set or clear the IOLOCK bit, an unlock sequence

must be executed. Refer to Section 6. “Oscillator”

(DS60001112) in the “PIC32 Family Reference

Manual” for details.

11.3.6.2 Configuration Bit Select Lock

As an additional level of safety, the device can be

configured to prevent more than one write session to

the RPnR and [pin name]R registers. The IOL1WAY

Configuration bit (DEVCFG3<29>) blocks the IOLOCK

bit from being cleared after it has been set once. If

IOLOCK remains set, the register unlock procedure

does not execute, and the peripheral pin select control

registers cannot be written to. The only way to clear the

bit and re-enable peripheral remapping is to perform a

device Reset.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session.

RPA0R<3:0>

Default

U1TX Output

U1RTS Output 2

Output Data

RPA0

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TABLE 11-2: OUTPUT PIN SELECTION

RPn Port Pin RPnR SFR RPnR bits RPnR Value to Peripheral

Selection

RPD2 RPD2R RPD2R<3:0> 0000 = No Connect

0001 = U3TX

0010 = U4RTS

0011 = Reserved

0100 = Reserved

0101 = Reserved

0110 = SDO2

0111 = Reserved

1000 = Reserved

1001 = Reserved

1010 = Reserved

1011 = OC3

1100 = C1TX

(5)

1101 = C2OUT

1110 = SDO3

1111 = SDO4

(3)

RPG8 RPG8R RPG8R<3:0>

RPF4 RPF4R RPF4R<3:0>

RPD10 RPD10R RPD10R<3:0>

RPF1 RPF1R RPF1R<3:0>

RPB9 RPB9R RPB9R<3:0>

RPB10 RPB10R RPB10R<3:0>

RPC14 RPC14R RPC14R<3:0>

RPB5

(7)

RPB5R RPB5R<3:0>

RPC1

(3)

RPC1R RPC1R<3:0>

RPD14

(3)

RPD14R RPD14R<3:0>

RPG1

(3)

RPG1R RPG1R<3:0>

RPA14

(3)

RPA14R RPA14R<3:0>

RPD3 RPD3R RPD3R<3:0> 0000 = No Connect

0001 = U2TX

0010 = Reserved

0011 = U1TX

0100 = U5RTS

(3)

0101 = Reserved

0110 = SDO2

0111 = Reserved

1000 = SDO1

1001 = Reserved

1010 = Reserved

1011 = OC4

1100 = Reserved

1101 = C3OUT

1110 = SDO3

1111 = SDO4

(3)

RPG7 RPG7R RPG7R<3:0>

RPF5 RPF5R RPF5R<3:0>

RPD11 RPD11R RPD11R<3:0>

RPF0 RPF0R RPF0R<3:0>

RPB1 RPB1R RPB1R<3:0>

RPE5 RPE5R RPE5R<3:0>

RPC13 RPC13R RPC13R<3:0>

RPB3 RPB3R RPB3R<3:0>

RPF3

(4)

RPF3R RPF3R<3:0>

RPC4

(3)

RPC4R RPC4R<3:0>

RPD15

(3)

RPD15R RPD15R<3:0>

RPG0

(3)

RPG0R RPG0R<3:0>

RPA15

(3)

RPA15R RPA15R<3:0>

Note 1: This selection is not available on 64-pin USB devices.

2: This selection is only available on 100-pin General Purpose devices.

3: This selection is not available on 64-pin devices.

4: This selection is not available when USBID functionality is used on USB devices.

5: This selection is not available on devices without a CAN module.

6: This selection is not available on USB devices.

7: This selection is not available when V

BUSON

functionality is used on USB devices.

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RPD9 RPD9R RPD9R<3:0> 0000 = No Connect

0001 = U3RTS

0010 = U4TX

0011 = REFCLKO

0100 = U5TX

(3)

0101 = Reserved

0110 = Reserved

0111 = SS1

1000 = SDO1

1001 = Reserved

1010 = Reserved

1011 = OC5

1100 = Reserved

1101 = C1OUT

1110 = SS3

1111 = SS4

(3)

RPG6 RPG6R RPG6R<3:0>

RPB8 RPB8R RPB8R<3:0>

RPB15 RPB15R RPB15R<3:0>

RPD4 RPD4R RPD4R<3:0>

RPB0 RPB0R RPB0R<3:0>

RPE3 RPE3R RPE3R<3:0>

RPB7 RPB7R RPB7R<3:0>

RPB2 RPB2R RPB2R<3:0>

RPF12

(3)

RPF12R RPF12R<3:0>

RPD12

(3)

RPD12R RPD12R<3:0>

RPF8

(3)

RPF8R RPF8R<3:0>

RPC3

(3)

RPC3R RPC3R<3:0>

RPE9

(3)

RPE9R RPE9R<3:0>

RPD1 RPD1R RPD1R<3:0> 0000 = No Connect

0001 = U2RTS

0010 = Reserved

0011 = U1RTS

0100 = U5TX

(3)

0101 = Reserved

0110 = SS2

0111 = Reserved

1000 = SDO1

1001 = Reserved

1010 = Reserved

1011 = OC2

1100 = OC1

1101 = Reserved

1110 = Reserved

1111 = Reserved

RPG9 RPG9R RPG9R<3:0>

RPB14 RPB14R RPB14R<3:0>

RPD0 RPD0R RPD0R<3:0>

RPD8 RPD8R RPD8R<3:0>

RPB6 RPB6R RPB6R<3:0>

RPD5 RPD5R RPD5R<3:0>

RPF3

(1)

RPF3R RPF3R<3:0>

RPF6

(2)

RPF6R RPF6R<3:0>

RPF13

(3)

RPF13R RPF13R<3:0>

RPC2

(3)

RPC2R RPC2R<3:0>

RPE8

(3)

RPE8R RPE8R<3:0>

RPF2

(1)

RPF2R RPF2R<3:0>

TABLE 11-2: OUTPUT PIN SELECTION (CONTINUED)

RPn Port Pin RPnR SFR RPnR bits RPnR Value to Peripheral

Selection

Note 1: This selection is not available on 64-pin USB devices.

2: This selection is only available on 100-pin General Purpose devices.

3: This selection is not available on 64-pin devices.

4: This selection is not available when USBID functionality is used on USB devices.

5: This selection is not available on devices without a CAN module.

6: This selection is not available on USB devices.

7: This selection is not available when V

BUSON

functionality is used on USB devices.

 2014-2017 Microchip Technology Inc. DS60001290E-page 137

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

11.4 Control Registers

TABLE 11-3: PORTA REGISTER MAP 100-PIN DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6000 ANSELA 31:16 ————— — ——————————0000

15:0 —————ANSELA10 ANSELA9 —————————0060

6010 TRISA 31:16 ————— — ——————————0000

15:0 TRISA15 TRISA14 ———TRISA10 TRISA9 —TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF

6020 PORTA 31:16 ————— — ——————————0000

15:0 RA15 RA14 ———RA10 RA9 —RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx

6030 LATA 31:16 ————— — ——————————0000

15:0 LATA15 LATA14 ———LATA10 LATA9 —LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx

6040 ODCA 31:16 ————— — ——————————0000

15:0 ODCA15 ODCA14 ———ODCA10 ODCA9 —ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000

6050 CNPUA 31:16 ————— — ——————————0000

15:0 CNPUA15 CNPUA14 ———CNPUA10 CNPUA9 —CNPUA7 CNPUA6 CNPUA5 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000

6060 CNPDA 31:16 ————— — ——————————0000

15:0 CNPDA15 CNPDA14 ———CNPDA10 CNPDA9 —CNPDA7 CNPDA6 CNPDA5 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000

6070 CNCONA 31:16 ————— — ——————————0000

15:0 ON —SIDL —— — ——————————0000

6080 CNENA 31:16 ————— — ——————————0000

15:0 CNIEA15 CNIEA14 ———CNIEA10 CNIEA9 —CNIEA7 CNIEA6 CNIEA5 CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000

6090 CNSTATA

31:16 ————— — ——————————0000

15:0 CN

STATA15

STATA14 ———CN

STATA10

STATA9 —CN

STATA7

STATA6

STATA5

STATA4

STATA3

STATA2

STATA1

STATA0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 138  2014-2017 Microchip Technology Inc.

TABLE 11-4: PORTB REGISTER MAP

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6100 ANSELB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ANSELB15 ANSELB14 ANSELB13 ANSELB12 ANSELB11 ANSELB10 ANSELB9 ANSELB8 ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 FFFF

6110 TRISB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF

6120 PORTB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx

6130 LATB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx

6140 ODCB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000

6150 CNPUB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000

6160 CNPDB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000

6170 CNCONB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6180 CNENB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000

6190 CNSTATB

31:16 — — — — — — — — — — — — — — — — 0000

15:0 CN

STATB15

STATB14

STATB13

STATB12

STATB11

STATB10

STATB9

STATB8

STATB7

STATB6

STATB5

STATB4

STATB3

STATB2

STATB1

STATB0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 139

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 11-5: PORTC REGISTER MAP FOR 100-PIN DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6200 ANSELC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — ANSELC3 ANSELC2 ANSELC1 —000E

6210 TRISC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 —FFFF

6220 PORTC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 RC15 RC14 RC13 RC12 — — — — — — — RC4 RC3 RC2 RC1 —xxxx

6230 LATC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 —xxxx

6240 ODCC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — ODCC4 ODCC3 ODCC2 ODCC1 —0000

6250 CNPUC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPUC15 CNPUC14 CNPUC13 CNPUC12 — — — — — — — CNPUC4 CNPUC3 CNPUC2 CNPUC1 —0000

6260 CNPDC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPDC15 CNPDC14 CNPDC13 CNPDC12 — — — — — — — CNPDC4 CNPDC3 CNPDC2 CNPDC1 —0000

6270 CNCONC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6280 CNENC 31:16 — — — — — — — — — — — — — — — 0000

15:0 CNIEC15 CNIEC14 CNIEC13 CNIEC12 — — — — — — — CNIEC4 CNIEC3 CNIEC2 CNIEC1 —0000

6290 CNSTATC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12 — — — — — — — CNSTATC4 CNSTATC3 CNSTATC2 CNSTATC1 —0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 140  2014-2017 Microchip Technology Inc.

TABLE 11-6: PORTC REGISTER MAP FOR 64-PIN DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6200 ANSELC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — ANSELC3 ANSELC2 ANSELC1 —000E

6210 TRISC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — — — — — — F000

6220 PORTC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 RC15 RC14 RC13 RC12 — — — — — — — — — — — — xxxx

6230 LATC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — — — — — — xxxx

6240 ODCC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — — — — — — 0000

6250 CNPUC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPUC15 CNPUC14 CNPUC13 CNPUC12 — — — — — — — — — — — — 0000

6260 CNPDC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPDC15 CNPDC14 CNPDC13 CNPDC12 — — — — — — — — — — — — 0000

6270 CNCONC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6280 CNENC 31:16 — — — — — — — — — — — — — — — 0000

15:0 CNIEC15 CNIEC14 CNIEC13 CNIEC12 — — — — — — — — — — — — 0000

6290 CNSTATC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12 — — — — — — — — — — — — 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 141

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 11-7: PORTD REGISTER MAP FOR 100-PIN DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6300 ANSELD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ANSELD15 ANSELD14 ANSELD13 ANSELD12 — — — — ANSELD7 ANSELD6 — — ANSELD3 ANSELD2 ANSELD1 —F0CE

6310 TRISD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF

5320 PORTD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx

6330 LATD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx

6340 ODCD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000

6350 CNPUD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000

6360 CNPDD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000

6370 CNCOND 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6380 CNEND 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNIED15 CNIED14 CNIED13 CNIED12 CNIED11 CNIED10 CNIED9 CNIED8 CNIED7 CNIED6 CNIED5 CNIED4 CNIED3 CNIED2 CNIED1 CNIED0 0000

6390 CNSTATD

31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNS

TATD15

STATD14

STATD13

STATD12

STATD11

STATD10

STATD9

STATD8

STATD7

STATD6

STATD5

STATD4

STATD3

STATD2

STATD1

STATD0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 142  2014-2017 Microchip Technology Inc.

TABLE 11-8: PORTD REGISTER MAP FOR 64-PIN DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6300 ANSELD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — ANSELD3 ANSELD2 ANSELD1 —000E

6310 TRISD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0FFF

5320 PORTD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx

6330 LATD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx

6340 ODCD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000

6350 CNPUD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000

6360 CNPDD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000

6370 CNCOND 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6380 CNEND 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — CNIED11 CNIED10 CNIED9 CNIED8 CNIED7 CNIED6 CNIED5 CNIED4 CNIED3 CNIED2 CNIED1 CNIED0 0000

6390 CNSTATD

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — CN

STATD11

STATD10

STATD9

STATD8

STATD7

STATD6

STATD5

STATD4

STATD3

STATD2

STATD1

STATD0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 143

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 11-9: PORTE REGISTER MAP FOR 100-PIN DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6400 ANSELE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — ANSELE9 ANSELE8 ANSELE7 ANSELE6 ANSELE5 ANSELE4 —ANSELE2 ANSELE1 ANSELE0 03F7

6410 TRISE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF

6420 PORTE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx

6440 LATE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx

6440 ODCE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — ODCE9 ODCE8 ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000

6450 CNPUE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPDE3 CNPUE2 CNPUE1 CNPUE0 0000

6460 CNPDE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — CNPDE9 CNPDE8 CNPDE7 CNPDE6 CNPDE5 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000

6470 CNCONE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6480 CNENE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — CNIEE9 CNIEE8 CNIEE7 CNIEE6 CNIEE5 CNIEE4 CNIEE3 CNIEE2 CNIEE1 CNIEE0 0000

6490 CNSTATE

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — CN

STATE9

STATE8

STATE7

STATE6

STATE5

STATE4

STATE3

STATE2

STATE1

STATE0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 144  2014-2017 Microchip Technology Inc.

TABLE 11-10: PORTE REGISTER MAP FOR 64-PIN DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6400 ANSELE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————ANSELE7 ANSELE6 ANSELE5 ANSELE4 —ANSELE2 — — 03F4

6410 TRISE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF

6420 PORTE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx

6440 LATE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx

6440 ODCE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000

6450 CNPUE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPDE3 CNPUE2 CNPUE1 CNPUE0 0000

6460 CNPDE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————CNPDE7 CNPDE6 CNPDE5 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000

6470 CNCONE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6480 CNENE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————CNIEE7 CNIEE6 CNIEE5 CNIEE4 CNIEE3 CNIEE2 CNIEE1 CNIEE0 0000

6490 CNSTATE

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————CN

STATE7

STATE6

STATE5

STATE4

STATE3

STATE2

STATE1

STATE0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 145

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 11-11: PORTF REGISTER MAP FOR PIC32MX130F128L, PIC32MX150F256L, AND PIC32MX170F512L DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6500 ANSELF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — ANSELE13 ANSELE12 ———ANSELE8 — — — — — ANSELE2 ANSELE1 ANSELE0 3107

6510 TRISF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — TRISF13 TRISF12 ———TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31FF

6520 PORTF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — RF13 RF12 ———RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx

6530 LATF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — LATF13 LATF12 ———LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx

6540 ODCF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — ODCF13 ODCF12 ———ODCF8 ODCF7 ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000

6550 CNPUF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — CNPUF13 CNPUF12 ———CNPUF8 CNPUF7 CNPUF6 CNPUF5 CNPUF4 CNPDF3 CNPUF2 CNPUF1 CNPUF0 0000

6560 CNPDF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — CNPDF13 CNPDF12 ———CNPDF8 CNPDF7 CNPDF6 CNPDF5 CNPDF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 0000

6570 CNCONF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6580 CNENF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — CNIEF13 CNIEF12 ———CNIEF8 CNIEF7 CNIEF6 CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 0000

6590 CNSTATF

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——CN

STATF13

STATF12 ———CN

STATF8

STATF7

STATF6

STATF5

STATF4

STATF3

STATF2

STATF1

STATF0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 146  2014-2017 Microchip Technology Inc.

TABLE 11-12: PORTF REGISTER MAP FOR PIC32MX230F128L, PIC32MX530F128L, PIC32MX250F256L, PIC32MX550F256L,

PIC32MX270F512L, AND PIC32MX570F512L DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6500 ANSELF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — ANSELE13 ANSELE12 ———ANSELE8 — — — — — ANSELE2 ANSELE1 ANSELE0 3107

6510 TRISF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — TRISF13 TRISF12 ———TRISF8 — — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F

6520 PORTF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — RF13 RF12 ———RF8 — — RF5 RF4 RF3 RF2 RF1 RF0 xxxx

6530 LATF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — LATF13 LATF12 ———LATF8 — — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx

6540 ODCF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — ODCF13 ODCF12 ———ODCF8 — — ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000

6550 CNPUF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — CNPUF13 CNPUF12 ———CNPUF8 — — CNPUF5 CNPUF4 CNPDF3 CNPUF2 CNPUF1 CNPUF0 0000

6560 CNPDF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — CNPDF13 CNPDF12 ———CNPDF8 — — CNPDF5 CNPFF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 0000

6570 CNCONF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6580 CNENF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — CNIEF13 CNIEF12 ———CNIEF8 — — CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 0000

6590 CNSTATF

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — CN

STATF13

STATF12 ———CN

STATF8 — — CN

STATF5

STATF4

STATF3

STATF2

STATF1

STATF0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 147

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 11-13: PORTF REGISTER MAP FOR PIC32MX120F064H, PIC32MX130F128H, PIC32MX150F256H, AND

PIC32MX170F512H DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6510 TRISF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————————TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 007F

6520 PORTF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————————RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx

6530 LATF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————————LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx

6540 ODCF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————————ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000

6550 CNPUF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————————CNPUF6 CNPUF5 CNPUF4 CNPUF3 CNPUF2 CNPUF1 CNPUF0 0000

6560 CNPDF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————————CNPDF6 CNPDF5 CNPDF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 0000

6570 CNCONF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6580 CNENF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————————CNIEF6 CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 0000

6590 CNSTATF

31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————————CN

STATF6

STATF5

STATF4

STATF3

STATF2

STATF1

STATF0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 148  2014-2017 Microchip Technology Inc.

TABLE 11-14: PORTF REGISTER MAP FOR PIC32MX230F128H, PIC32MX530F128H, PIC32MX250F256H, PIC32MX550F256H,

PIC32MX270F512H, AND PIC32MX570F512H DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6510 TRISF 31:16 ————————————————0000

15:0 — — — — — — — — — — TRISF5 TRISF4 TRISF3 —TRISF1 TRISF0 003B

6520 PORTF 31:16 ————————————————0000

15:0 — — — — — — — — — — RF5 RF4 RF3 —RF1 RF0 xxxx

6530 LATF 31:16 ————————————————0000

15:0 — — — — — — — — — — LATF5 LATF4 LATF3 —LATF1 LATF0 xxxx

6540 ODCF 31:16 ————————————————0000

15:0 — — — — — — — — — — ODCF5 ODCF4 ODCF3 —ODCF1 ODCF0 0000

6550 CNPUF 31:16 ————————————————0000

15:0 — — — — — — — — — — CNPUF5 CNPUF4 CNPUF3 —CNPUF1 CNPUF0 0000

6560 CNPDF 31:16 ————————————————0000

15:0 — — — — — — — — — — CNPDF5 CNPDF4 CNPDF3 —CNPDF1 CNPDF0 0000

6570 CNCONF 31:16 ————————————————0000

15:0 ON —SIDL —————————————0000

6580 CNENF 31:16 ————————————————0000

15:0 — — — — — — — — — — CNIEF5 CNIEF4 CNIEF3 —CNIEF1 CNIEF0 0000

6590 CNSTATF

31:16 ————————————————0000

15:0 — — — — — — — — — — CN

STATF5

STATF4

STATF3 —CN

STATF1

STATF0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 149

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 11-15: PORTG REGISTER MAP FOR 100-PIN DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6600 ANSELG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ANSELG15 — — — — — ANSELG9 ANSELG8 ANSELG7 ANSELG6 — — — — — — 83C0

6610 TRISG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF

6620 PORTG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3

(2)

RG2

(2)

RG1 RG0 xxxx

6630 LATG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx

6640 ODCG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ODCG15 ODCG14 ODCG13 ODCG12 — — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 ODCG1 ODCG0 0000

6650 CNPUG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPUG15 CNPUG14 CNPUG13 CNPUG12 — — CNPUG9 CNPUG8 CNPUG7 CNPUG6 — — CNPUG3 CNPUG2 CNPUG1 CNPUG0 0000

6660 CNPDG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPDG15 CNPDG14 CNPDG13 CNPDG12 — — CNPDG9 CNPDG8 CNPDG7 CNPDG6 — — CNPDG3 CNPDG2 CNPDG1 CNPDG0 0000

6670 CNCONG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6680 CNENG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNIEG15 CNIEG14 CNIEG13 CNIEG12 — — CNIEG9 CNIEG8 CNIEG7 CNIEG6 — — CNIEG3 CNIEG2 CNIEG1 CNIEG0 0000

6690 CNSTATG

31:16 — — — — — — — — — — — — — — — — 0000

15:0 CN

STATG15

STATG14

STATG13

STATG12 — — CN

STATG9

STATG8

STATG7

STATG6 — — CN

STATG3

STATG2

STATG1

STATG0 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

2: This bit is only available on devices without a USB module.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 150  2014-2017 Microchip Technology Inc.

TABLE 11-16: PORTG REGISTER MAP FOR 64-PIN DEVICES ONLY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6600 ANSELG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————ANSELG9 ANSELG8 ANSELG7 ANSELG6 — — — — — — 03C0

6610 TRISG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 — — 03CC

6620 PORTG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————RG9 RG8 RG7 RG6 — — RG3

(2)

RG2

(2)

— — xxxx

6630 LATG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 — — xxxx

6640 ODCG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 — — 0000

6650 CNPUG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————CNPUG9 CNPUG8 CNPUG7 CNPUG6 — — CNPUG3 CNPUG2 — — 0000

6660 CNPDG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————CNPDG9 CNPDG8 CNPDG7 CNPDG6 — — CNPDG3 CNPDG2 — — 0000

6670 CNCONG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6680 CNENG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————CNIEG9 CNIEG8 CNIEG7 CNIEG6 — — CNIEG3 CNIEG2 — — 0000

6690 CNSTATG

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————CN

STATG9

STATG8

STATG7

STATG6 — — CN

STATG3

STATG2 — — 0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.

more information.

2: This bit is only available on devices without a USB module.

 2014-2017 Microchip Technology Inc. DS60001290E-page 151

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 11-17: PERIPHERAL PIN SELECT INPUT REGISTER MAP

Virt ua l Ad dr es s

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

FA04 INT1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————INT1R<3:0>0000

FA08 INT2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————INT2R<3:0>0000

FA0C INT3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————INT3R<3:0>0000

FA10 INT4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————INT4R<3:0>0000

FA18 T2CKR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————T2CKR<3:0>0000

FA1C T3CKR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————T3CKR<3:0>0000

FA20 T4CKR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————T4CKR<3:0>0000

FA24 T5CKR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————T5CKR<3:0>0000

FA28 IC1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— IC1R<3:0> 0000

FA2C IC2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— IC2R<3:0> 0000

FA30 IC3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— IC3R<3:0> 0000

FA34 IC4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— IC4R<3:0> 0000

FA38 IC5R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— IC5R<3:0> 0000

FA48 OCFAR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————OCFAR<3:0>0000

FA50 U1RXR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————U1RXR<3:0>0000

FA54 U1CTSR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— U1CTSR<3:0> 0000

FA58 U2RXR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————U2RXR<3:0>0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 152  2014-2017 Microchip Technology Inc.

FA5C U2CTSR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— U2CTSR<3:0> 0000

FA60 U3RXR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————U3RXR<3:0>0000

FA64 U3CTSR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— U3CTSR<3:0> 0000

FA68 U4RXR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————U4RXR<3:0>0000

FA6C U4CTSR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— U4CTSR<3:0> 0000

FA70 U5RXR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————U5RXR<3:0>0000

FA74 U5CTSR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— U5CTSR<3:0> 0000

FA84 SDI1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————SDI1R<3:0>0000

FA88 SS1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— SS1R<3:0> 0000

FA90 SDI2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————SDI2R<3:0>0000

FA94 SS2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— SS2R<3:0> 0000

FA9C SDI3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————SDI3R<3:0>0000

FAA0 SS3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————SS3R<3:0>0000

FAA8 SDI4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————SDI4R<3:0>0000

FAAC SS4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————SS4R<3:0>0000

FAC8 C1RXR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————————————C1RXR<3:0>0000

FAD0 REFCLKIR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ———————————— REFCLKIR<3:0> 0000

TABLE 11-17: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

 2014-2017 Microchip Technology Inc. DS60001290E-page 153

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 11-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP

Virt ua l Ad dr es s

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

FB38 RPA14R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —RPA14<3:0>0000

FB3C RPA15R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —RPA15<3:0>0000

FB40 RPB0R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB0<3:0> 0000

FB44 RPB1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB1<3:0> 0000

FB48 RPB2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB2<3:0> 0000

FB4C RPB3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB3<3:0> 0000

FB54 RPB5R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB5<3:0> 0000

FB58 RPB6R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB6<3:0> 0000

FB5C RPB7R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB7<3:0> 0000

FB60 RPB8R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB8<3:0> 0000

FB64 RPB9R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB9<3:0> 0000

FB68 RPB10R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB10<3:0> 0000

FB78 RPB14R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB14<3:0> 0000

FB7C RPB15R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB15<3:0> 0000

FB84 RPC1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC1<3:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register is not available if the associated RPx function is not present on the device. Refer to the pin table for the specific device to determine availability.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 154  2014-2017 Microchip Technology Inc.

FB88 RPC2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC2<3:0> 0000

FB8C RPC3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC3<3:0> 0000

FB90 RPC4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC4<3:0> 0000

FBB4 RPC13R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC13<3:0> 0000

FBB8 RPC14R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC14<3:0> 0000

FBC0 RPD0R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD0<3:0> 0000

FBC4 RPD1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD1<3:0> 0000

FBC8 RPD2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD2<3:0> 0000

FBCC RPD3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD3<3:0> 0000

FBD0 RPD4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD4<3:0> 0000

FBD4 RPD5R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD5<3:0> 0000

FBE0 RPD8R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD8<3:0> 0000

FBE4 RPD9R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD9<3:0> 0000

FBE8 RPD10R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD10<3:0> 0000

FBEC RPD11R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —RPD11<3:0>0000

FBF0 RPD12R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD12<3:0> 0000

FBF8 RPD14R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD14<3:0> 0000

TABLE 11-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register is not available if the associated RPx function is not present on the device. Refer to the pin table for the specific device to determine availability.

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FBFC RPD15R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPD15<3:0> 0000

FC0C RPE3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPE3<3:0> 0000

FC14 RPE5R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPE5<3:0> 0000

FC20 RPE8R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPE8<3:0> 0000

FC24 RPE9R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPE9<3:0> 0000

FC40 RPF0R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPF0<3:0> 0000

FC44 RPF1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPF1<3:0> 0000

FC48 RPF2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPF2<3:0> 0000

FC4C RPF3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPF3<3:0> 0000

FC50 RPF4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPF4<3:0> 0000

FC54 RPF5R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPF5<3:0> 0000

FC58 RPF6R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPF6<3:0> 0000

FC5C RPF7R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPF6<3:0> 0000

FC60 RPF8R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPF7<3:0> 0000

FC70 RPF12R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —RPF12<3:0>0000

FC74 RPF13R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —RPF13<3:0>0000

FC80 RPG0R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPG0<3:0> 0000

TABLE 11-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register is not available if the associated RPx function is not present on the device. Refer to the pin table for the specific device to determine availability.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

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FC84 RPG1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPG1<3:0> 0000

FC98 RPG6R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPG6<3:0> 0000

FC9C RPG7R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPG7<3:0> 0000

FCA0 RPG8R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPG8<3:0> 0000

FCA4 RPG9R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPG9<3:0> 0000

TABLE 11-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register is not available if the associated RPx function is not present on the device. Refer to the pin table for the specific device to determine availability.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

————[pin name]R<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3-0 [pin name]R<3:0>: Peripheral Pin Select Input bits

Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Ta bl e 11 - 1 for

input pin selection values.

Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

———— RPnR<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3-0 RPnR<3:0>: Peripheral Pin Select Output bits

See Tabl e 11 -2 for output pin selection values.

Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

ON —SIDL— — — — —

7:0

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Change Notice (CN) Control ON bit

1 = CN is enabled

0 = CN is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Control bit

1 = CPU Idle Mode halts CN operation

0 = CPU Idle does not affect CN operation

bit 12-0 Unimplemented: Read as ‘0’

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

12.0 TIMER1

This family of PIC32 devices features one synchronous/

asynchronous 16-bit timer that can operate as a free-

running interval timer for various timing applications and

counting external events. This timer can also be used

with the Low-Power Secondary Oscillator (S

OSC

) for

Real-Time Clock (RTC) applications. The following

modes are supported:

• Synchronous Internal Timer

• Synchronous Internal Gated Timer

• Synchronous External Timer

• Asynchronous External Timer

12.1 Additional Supported Features

• Selectable clock prescaler

• Timer operation during CPU Idle and Sleep mode

• Fast bit manipulation using CLR, SET and INV

registers

• Asynchronous mode can be used with the S

OSC

to function as a Real-Time Clock (RTC)

FIGURE 12-1: TIMER1 BLOCK DIAGRAM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 14. “Timers”

(DS60001105) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

Sync

SOSCI

SOSCO/T1CK

TMR1

T1IF

Equal 16-bit Comparator

PR1

Reset

SOSCEN

Event Flag

TSYNC

TGATE

PBCLK

TCS

Gate

Sync

TCKPS<1:0>

Prescaler

1, 8, 64, 256

x 1

1 0

0 0

Note: The default state of the SOSCEN (OSCCON<1>) bit during a device Reset is controlled by the FSOSCEN

bit in Configuration Word, DEVCFG1.

Data Bus<31:0>

<15:0>

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12.2 Control Registers

TABLE 12-1: TIMER1 REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

0600 T1CON 31:16 ————————————————0000

15:0 ON —SIDL TWDIS TWIP — — — TGATE —TCKPS<1:0> —TSYNC TCS —0000

0610 TMR1 31:16 ————————————————0000

15:0 TMR1<15:0> 0000

0620 PR1 31:16 ————————————————0000

15:0 PR1<15:0> FFFF

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0

(1)

— SIDL TWDIS TWIP — — —

7:0

R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

TGATE — TCKPS<1:0> — TSYNC TCS —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Timer On bit

(1)

1 = Timer is enabled

0 = Timer is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when device enters Idle mode

0 = Continue operation even in Idle mode

bit 12 TWDIS: Asynchronous Timer Write Disable bit

1 = Writes to TMR1 are ignored until pending write operation completes

0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)

bit 11 TWIP: Asynchronous Timer Write in Progress bit

In Asynchronous Timer mode:

1 = Asynchronous write to TMR1 register in progress

0 = Asynchronous write to TMR1 register complete

In Synchronous Timer mode:

This bit is read as ‘0’.

bit 10-8 Unimplemented: Read as ‘0’

bit 7 TGATE: Timer Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation is enabled

0 = Gated time accumulation is disabled

bit 6 Unimplemented: Read as ‘0’

bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits

11 = 1:256 prescale value

10 = 1:64 prescale value

01 = 1:8 prescale value

00 = 1:1 prescale value

bit 3 Unimplemented: Read as ‘0’

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit

When TCS = 1:

1 = External clock input is synchronized

0 = External clock input is not synchronized

When TCS = 0:

This bit is ignored.

bit 1 TCS: Timer Clock Source Select bit

1 = External clock from TxCKI pin

0 = Internal peripheral clock

bit 0 Unimplemented: Read as ‘0’

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

13.0 TIMER2/3, TIMER4/5

This family of PIC32 devices features four synchronous

16-bit timers (default) that can operate as a free-

running interval timer for various timing applications

and counting external events. The following modes are

supported:

• Synchronous internal 16-bit timer

• Synchronous internal 16-bit gated timer

• Synchronous external 16-bit timer

Two 32-bit synchronous timers are available by

combining Timer2 with Timer3 and Timer4 with Timer5.

The 32-bit timers can operate in three modes:

• Synchronous internal 32-bit timer

• Synchronous internal 32-bit gated timer

• Synchronous external 32-bit timer

13.1 Additional Supported Features

• Selectable clock prescaler

• Timers operational during CPU idle

• Time base for Input Capture and Output Compare

modules (Timer2 and Timer3 only)

• ADC event trigger (Timer3 in 16-bit mode, Timer2/

3 in 32-bit mode)

• Fast bit manipulation using CLR, SET and INV

registers

FIGURE 13-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 14. “Timers”

(DS60001105) of the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

Note: In this chapter, references to registers,

TxCON, TMRx and PRx, use ‘x’ to

represent Timer2 through 5 in 16-bit

modes. In 32-bit modes, ‘x’ represents

Timer2 or 4; ‘y’ represents Timer3 or 5.

Sync

PRx

TxIF

Equal Comparator x 16

TMRx

Reset

Event Flag

TGATE

Gate

TxCK

Sync

TGATE

TCS

TCKPS

Prescaler

1, 2, 4, 8, 16,

32, 64, 256

x 1

1 0

0 0

PBCLK

Trigger

(1)

ADC Event

Note 1:

ADC event trigger is available on Timer3 only.

Data Bus<31:0>

<15:0>

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FIGURE 13-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)

(1)

TMRy

(1)

TMRx

(1)

TyIF Event

Equal 32-bit Comparator

PRy

PRx

Reset

LS Half Word

MS Half Word

Flag

Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the

use of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.

2: ADC event trigger is available only on the Timer2/3 pair.

TGATE

PBCLK

Gate

TxCK

Sync

ADC Event

Trigger

(2)

TGATE

TCS

TCKPS

Prescaler

1, 2, 4, 8, 16,

32, 64, 256

1 0

0 0

x 1

Data Bus<31:0>

<31:0>

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13.2 Control Registers

TABLE 13-1: TIMER2 THROUGH TIMER5 REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

0800 T2CON 31:16 ————————————————0000

15:0 ON —SIDL —————TGATE TCKPS<2:0> T32 —TCS —0000

0810 TMR2 31:16 ————————————————0000

15:0 TMR2<15:0> 0000

0820 PR2 31:16 ————————————————0000

15:0 PR2<15:0> FFFF

0A00 T3CON 31:16 ————————————————0000

15:0 ON —SIDL —————TGATE TCKPS<2:0> — — TCS —0000

0A10 TMR3 31:16 ————————————————0000

15:0 TMR3<15:0> 0000

0A20 PR3 31:16 ————————————————0000

15:0 PR3<15:0> FFFF

0C00 T4CON 31:16 ————————————————0000

15:0 ON —SIDL —————TGATE TCKPS<2:0> T32 —TCS —0000

0C10 TMR4 31:16 ————————————————0000

15:0 TMR4<15:0> 0000

0C20 PR4 31:16 ————————————————0000

15:0 PR4<15:0> FFFF

0E00 T5CON 31:16 ————————————————0000

15:0 ON —SIDL —————TGATE TCKPS<2:0> — — TCS —0000

0E10 TMR5 31:16 ————————————————0000

15:0 TMR5<15:0> 0000

0E20 PR5 31:16 ————————————————0000

15:0 PR5<15:0> FFFF

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

(1,3)

—SIDL

(4)

— — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

TGATE

(3)

TCKPS<2:0>

(3)

T32

(2)

—TCS

(3)

—

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Timer On bit

(1,3)

1 = Module is enabled

0 = Module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

(4)

1 = Discontinue operation when device enters Idle mode

0 = Continue operation even in Idle mode

bit 12-8 Unimplemented: Read as ‘0’

bit 7 TGATE: Timer Gated Time Accumulation Enable bit

(3)

When TCS = 1:

This bit is ignored and is read as ‘0’.

When TCS = 0:

1 = Gated time accumulation is enabled

0 = Gated time accumulation is disabled

bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits

(3)

111 = 1:256 prescale value

110 = 1:64 prescale value

101 = 1:32 prescale value

100 = 1:16 prescale value

011 = 1:8 prescale value

010 = 1:4 prescale value

001 = 1:2 prescale value

000 = 1:1 prescale value

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit is available only on even numbered timers (Timer2 and Timer4).

3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3 and Timer5). All

timer functions are set through the even numbered timers.

4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer

in Idle mode.

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bit 3 T32: 32-Bit Timer Mode Select bit

(2)

1 = Odd numbered and even numbered timers form a 32-bit timer

0 = Odd numbered and even numbered timers form a separate 16-bit timer

bit 2 Unimplemented: Read as ‘0’

bit 1 TCS: Timer Clock Source Select bit

(3)

1 = External clock from TxCK pin

0 = Internal peripheral clock

bit 0 Unimplemented: Read as ‘0’

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit is available only on even numbered timers (Timer2 and Timer4).

3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3 and Timer5). All

timer functions are set through the even numbered timers.

4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer

in Idle mode.

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NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 169

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

14.0 WATCHDOG TIMER (WDT)

The Watchdog Timer (WDT), when enabled, operates

from the internal Low-Power Oscillator (LPRC) clock

source and can be used to detect system software mal-

functions by resetting the device if the WDT is not

cleared periodically in software. Various WDT time-out

periods can be selected using the WDT postscaler. The

WDT can also be used to wake the device from Sleep

or Idle mode.

The following are some of the key features of the WDT

module:

• Configuration or software controlled

• User-configurable time-out period

• Can wake the device from Sleep or Idle

FIGURE 14-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM

Note: This data sheet summarizes the

features of the PIC32MX1XX/2XX/5XX

64/100-pin Family family of devices. It is

not intended to be a comprehensive

reference source. To complement the

information in this data sheet, refer to

Section 9. “Watchdog, Deadman, and

Power-up Timers” (DS60001114) in the

“PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32).

Wake

WDTCLR = 1

WDT Enable

LPRC

Power Save

25-bit Counter

PWRT Enable

WDT Enable

LPRC

WDT Counter Reset

Control

Oscillator

Device Reset

NMI (Wake-up)

PWRT

PWRT Enable

FWDTPS<4:0> (DEVCFG1<20:16>)

Clock

Decoder

1:64 Output

WDT Enable

Reset Event

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TABLE 14-1: WATCHDOG TIMER REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

0000 WDTCON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON — — — — — — — — SWDTPS<4:0> WDTWINEN WDTCLR 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

 2014-2017 Microchip Technology Inc. DS60001290E-page 171

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

(1,2)

— — — — — — —

7:0

U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0

— SWDTPS<4:0> WDTWINEN WDTCLR

Legend: y = Values set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Watchdog Timer Enable bit

(1,2)

1 = Enables the WDT if it is not enabled by the device configuration

0 = Disable the WDT if it was enabled in software

bit 14-7 Unimplemented: Read as ‘0’

bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits

On reset, these bits are set to the values of the WDTPS <4:0> of Configuration bits.

bit 1 WDTWINEN: Watchdog Timer Window Enable bit

1 = Enable windowed Watchdog Timer

0 = Disable windowed Watchdog Timer

bit 0 WDTCLR: Watchdog Timer Reset bit

1 = Writing a ‘1’ will clear the WDT

0 = Software cannot force this bit to a ‘0’

Note 1: A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.

2: When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 172  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 173

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

15.0 INPUT CAPTURE

The Input Capture module is useful in applications

requiring frequency (period) and pulse measurement.

The Input Capture module captures the 16-bit or 32-bit

value of the selected Time Base registers when an

event occurs at the ICx pin. The following events cause

capture events:

• Simple capture event modes:

- Capture timer value on every falling edge of

input at ICx pin

- Capture timer value on every rising edge of

input at ICx pin

- Capture timer value on every edge (rising

and falling)

- Capture timer value on every edge (rising

and falling), specified edge first.

• Prescaler capture event modes:

- Capture timer value on every 4th rising edge of

input at ICx pin

- Capture timer value on every 16th rising edge of

input at ICx pin

Each input capture channel can select between one of

two 16-bit timers (Timer2 or Timer3) for the time base,

or two 16-bit timers (Timer2 and Timer3) together to

form a 32-bit timer. The selected timer can use either

an internal or external clock.

The other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

• Interrupt on input capture event

• 4-word FIFO buffer for capture values

Interrupt optionally generated after 1, 2, 3, or 4

buffer locations are filled

• Input capture can also be used to provide

additional sources of external interrupts

FIGU RE 15-1: INPUT C AP TU RE BL O CK DI AGR AM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 15. “Input

Capture” (DS60001122) of the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32).

Note:

An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

FIFO CONTROL

ICxBUF

TMR2 TMR3

CaptureEvent

FIFO

ICI<1:0>

ICM<2:0>

101

100

011

010

001

111

To CPU

Set Flag ICxIF

(In IFSx Register)

Rising Edge Mode

Prescaler Mode

(4th Rising Edge)

Falling Edge Mode

Edge Detection

Prescaler Mode

(16th Rising Edge)

Sleep/Idle

Wake-up Mode

C32 | ICTMR

ICx pin

Mode

110

Specified/Every

Edge Mode

FEDGE

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15.1 Control Registers

TABLE 15-1: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 5 REGISTER MAP

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

2000 IC1CON

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL ———FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2010 IC1BUF 31:16 IC1BUF<31:0> xxxx

15:0 xxxx

2200 IC2CON

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL ———FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2210 IC2BUF 31:16 IC2BUF<31:0> xxxx

15:0 xxxx

2400 IC3CON

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL ———FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2410 IC3BUF 31:16 IC3BUF<31:0> xxxx

15:0 xxxx

2600 IC4CON

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL ———FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2610 IC4BUF 31:16 IC4BUF<31:0> xxxx

15:0 xxxx

2800 IC5CON

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL ———FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2810 IC5BUF 31:16 IC5BUF<31:0> xxxx

15:0 xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 175

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

CON: INPUT CAPTURE ‘

’ CONTROL REGISTER (‘x’ = 1 THROUGH 5)

Bit Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

(1)

—SIDL— — —FEDGEC32

7:0

R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit

-n = Bit Value at POR: (‘0’, ‘1’, x = unknown) P = Programmable bit r = Reserved bit

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Input Capture Module Enable bit

(1)

1 = Module enabled

0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Control bit

1 = Halt in CPU Idle mode

0 = Continue to operate in CPU Idle mode

bit 12-10 Unimplemented: Read as ‘0’

bit 9 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)

1 = Capture rising edge first

0 = Capture falling edge first

bit 8 C32: 32-bit Capture Select bit

1 = 32-bit timer resource capture

0 = 16-bit timer resource capture

bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)

0 = Timer3 is the counter source for capture

1 = Timer2 is the counter source for capture

bit 6-5 ICI<1:0>: Interrupt Control bits

11 = Interrupt on every fourth capture event

10 = Interrupt on every third capture event

01 = Interrupt on every second capture event

00 = Interrupt on every capture event

bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)

1 = Input capture overflow occurred

0 = No input capture overflow occurred

bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only)

1 = Input capture buffer is not empty; at least one more capture value can be read

0 = Input capture buffer is empty

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 176  2014-2017 Microchip Technology Inc.

bit 2-0 ICM<2:0>: Input Capture Mode Select bits

111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)

110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter

101 = Prescaled Capture Event mode – every sixteenth rising edge

100 = Prescaled Capture Event mode – every fourth rising edge

011 = Simple Capture Event mode – every rising edge

010 = Simple Capture Event mode – every falling edge

001 = Edge Detect mode – every edge (rising and falling)

000 = Input Capture module is disabled

CON: INPUT CAPTURE ‘

’ CONTROL REGISTER (CONTINUED)(‘x’ = 1

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

 2014-2017 Microchip Technology Inc. DS60001290E-page 177

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

16. 0 OU T P UT COMPAR E

The Output Compare module is used to generate a

single pulse or a train of pulses in response to selected

time base events. For all modes of operation, the

Output Compare module compares the values stored

in the OCxR and/or the OCxRS registers to the value in

the selected timer. When a match occurs, the Output

Compare module generates an event based on the

selected mode of operation.

The following are the key features of this module:

• Multiple Output Compare modules in a device

• Programmable interrupt generation on compare

event

• Single and Dual Compare modes

• Single and continuous output pulse generation

• Pulse-Width Modulation (PWM) mode

• Hardware-based PWM Fault detection and

automatic output disable

• Can operate from either of two available 16-bit

time bases or a single 32-bit time base

FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 16. “Output

Compare” (DS60001111) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32).

OCxR

(1)

Comparator

Output

Logic

OCM<2:0>

Output Enable

OCx

(1)

Set Flag bit

OCxIF

(1)

OCxRS

(1)

Mode Select

Note 1:Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,

1 through 5.

2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.

OCTSEL

OCFA or OCFB

(2)

Timer2 Timer2 Timer3

Logic

Output

Enable

Timer3

Rollover Rollover

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DS60001290E-page 178  2014-2017 Microchip Technology Inc.

16.1 Control Registers

TABLE 16-1: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 5 REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

3000 OC1CON 31:16 ————————————————0000

15:0 ON —SIDL ———————OC32 OCFLT OCTSEL OCM<2:0> 0000

3010 OC1R 31:16 OC1R<31:0> xxxx

15:0 xxxx

3020 OC1RS 31:16 OC1RS<31:0> xxxx

15:0 xxxx

3200 OC2CON 31:16 ————————————————0000

15:0 ON —SIDL ———————OC32 OCFLT OCTSEL OCM<2:0> 0000

3210 OC2R 31:16 OC2R<31:0> xxxx

15:0 xxxx

3220 OC2RS 31:16 OC2RS<31:0> xxxx

15:0 xxxx

3400 OC3CON 31:16 ————————————————0000

15:0 ON —SIDL ———————OC32 OCFLT OCTSEL OCM<2:0> 0000

3410 OC3R 31:16 OC3R<31:0> xxxx

15:0 xxxx

3420 OC3RS 31:16

15:0 OC3RS<31:0> xxxx

xxxx

3600 OC4CON 31:16 ————————————————0000

15:0 ON —SIDL ———————OC32 OCFLT OCTSEL OCM<2:0> 0000

3610 OC4R 31:16 OC4R<31:0> xxxx

15:0 xxxx

3620 OC4RS 31:16

15:0 OC4RS<31:0> xxxx

xxxx

3800 OC5CON 31:16 ————————————————0000

15:0 ON —SIDL ———————OC32 OCFLT OCTSEL OCM<2:0> 0000

3810 OC5R 31:16 OC5R<31:0> xxxx

15:0 xxxx

3820 OC5RS 31:16 OC5RS<31:0> xxxx

15:0 xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 179

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

(1)

—SIDL— — — — —

7:0

U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

—— OC32 OCFLT

(2)

OCTSEL OCM<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Output Compare Peripheral On bit

(1)

1 = Output Compare peripheral is enabled

0 = Output Compare peripheral is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when CPU enters Idle mode

0 = Continue operation in Idle mode

bit 12-6 Unimplemented: Read as ‘0’

bit 5 OC32: 32-bit Compare Mode bit

1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisons to the 32-bit timer source

0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source

bit 4 OCFLT: PWM Fault Condition Status bit

(2)

1 = PWM Fault condition has occurred (cleared in HW only)

0 = No PWM Fault condition has occurred

bit 3 OCTSEL: Output Compare Timer Select bit

1 = Timer3 is the clock source for this Output Compare module

0 = Timer2 is the clock source for this Output Compare module

bit 2-0 OCM<2:0>: Output Compare Mode Select bits

111 = PWM mode on OCx; Fault pin enabled

110 = PWM mode on OCx; Fault pin disabled

101 = Initialize OCx pin low; generate continuous output pulses on OCx pin

100 = Initialize OCx pin low; generate single output pulse on OCx pin

011 = Compare event toggles OCx pin

010 = Initialize OCx pin high; compare event forces OCx pin low

001 = Initialize OCx pin low; compare event forces OCx pin high

000 = Output compare peripheral is disabled but continues to draw current

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit is only used when OCM<2:0> = ‘111’. It is read as ‘0’ in all other modes.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 180  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 181

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

17.0 SERIAL PERIPHERAL

INTERFACE (SPI)

The SPI module is a synchronous serial interface that

is useful for communicating with external peripherals

and other microcontroller devices. These peripheral

devices may be Serial EEPROMs, Shift registers, dis-

play drivers, Analog-to-Digital Converters (ADC), etc.

The PIC32 SPI module is compatible with Motorola

SPI and SIOP interfaces.

Some of the key features of the SPI module are:

• Master and Slave modes support

• Four different clock formats

• Enhanced Framed SPI protocol support

• User-configurable 8-bit, 16-bit and 32-bit data width

• Separate SPI FIFO buffers for receive and transmit

- FIFO buffers act as 4/8/16-level deep FIFOs

based on 32/16/8-bit data width

• Programmable interrupt event on every 8-bit, 

16-bit and 32-bit data transfer

• Operation during CPU Sleep and Idle mode

• Audio Codec Support:

-I

S protocol

- Left-justified

- Right-justified

-PCM

FIGU RE 17 -1 : SPI MODU LE BLOC K DI AG R AM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 23. “Serial

Peripheral Interface (SPI)”

(DS60001106) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

Internal

Data Bus

SDIx

SDOx

SSx/F

SYNC

SCKx

SPIxSR

bit 0

Shift

Control

Edge

Select

MSTEN

Baud Rate

Slave Select

Sync Control

Clock

Control

Transmit

Receive

and Frame

Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.

FIFOs Share Address SPIxBUF

SPIxBUF

Generator

PBCLK

WriteRead

SPIxTXB FIFO

SPIxRXB FIFO

REFCLK

MCLKSEL

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

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17.1 Control Registers

TABLE 17-1: SPI1 THR OUGH SPI4 REGISTER MAP

Virt ual Ad dress

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

5800 SPI1CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF 0000

15:0 ON —SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000

5810 SPI1STAT 31:16 — — — RXBUFELM<4:0> ——— TXBUFELM<4:0> 0000

15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE —SPITBE —SPITBF SPIRBF 19EB

5820 SPI1BUF 31:16 DATA<31:0> 0000

15:0 0000

5830 SPI1BRG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — BRG<8:0> 0000

5840 SPI1CON2

31:16 — — — — — — — — — — — — — — — — 0000

15:0 SPI

SGNEXT — — FRM

ERREN

SPI

ROVEN

SPI

TUREN IGNROV IGNTUR AUDEN ———AUD

MONO —AUDMOD<1:0> 0000

5A00 SPI2CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF 0000

15:0 ON —SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000

5A10 SPI2STAT 31:16 — — — RXBUFELM<4:0> ——— TXBUFELM<4:0> 0000

15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE —SPITBE —SPITBF SPIRBF 19EB

5A20 SPI2BUF 31:16 DATA<31:0> 0000

15:0 0000

5A30 SPI2BRG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — BRG<8:0> 0000

5A40 SPI2CON2

31:16 — — — — — — — — — — — — — — — — 0000

15:0 SPI

SGNEXT — — FRM

ERREN

SPI

ROVEN

SPI

TUREN IGNROV IGNTUR AUDEN ———AUD

MONO —AUDMOD<1:0> 0000

5C00 SPI3CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF 0000

15:0 ON —SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000

5C10 SPI3STAT 31:16 — — — RXBUFELM<4:0> ——— TXBUFELM<4:0> 0000

15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE —SPITBE —SPITBF SPIRBF 19EB

5C20 SPI3BUF 31:16 DATA<31:0> 0000

15:0 0000

5C30 SPI3BRG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — BRG<8:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 1 1.2 “CLR, SET, and INV

Registers” for more information.

2: This register is only available on 100-pin devices.

 2014-2017 Microchip Technology Inc. DS60001290E-page 183

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

5C40 SPI3CON2

31:16 — — — — — — — — — — — — — — — — 0000

15:0 SPI

SGNEXT — — FRM

ERREN

SPI

ROVEN

SPI

TUREN IGNROV IGNTUR AUDEN ———AUD

MONO —AUDMOD<1:0> 0000

5E00 SPI4CON

(2)

31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF 0000

15:0 ON —SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000

5E10 SPI4STAT

(2)

31:16 — — — RXBUFELM<4:0> ——— TXBUFELM<4:0> 0000

15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE —SPITBE —SPITBF SPIRBF 19EB

5E20 SPI4BUF

(2)

31:16 DATA<31:0> 0000

15:0 0000

5E30 SPI4BRG

(2)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — BRG<8:0> 0000

5E40 SPI4CON2

(2)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 SPI

SGNEXT — — FRM

ERREN

SPI

ROVEN

SPI

TUREN IGNROV IGNTUR AUDEN ———AUD

MONO —AUDMOD<1:0> 0000

TABLE 17-1: SPI1 THROUGH SPI4 REGISTER MAP (CONTINUED)

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Registers” for more information.

2: This register is only available on 100-pin devices.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0>

23:16

R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

MCLKSEL

(2)

— — — — — SPIFE ENHBUF

(2)

15:8

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

— SIDL DISSDO MODE32 MODE16 SMP CKE

(3)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSEN CKP

(4)

MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FRMEN: Framed SPI Support bit

1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)

0 = Framed SPI support is disabled

bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)

1 = Frame sync pulse input (Slave mode)

0 = Frame sync pulse output (Master mode)

bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)

1 = Frame pulse is active-high

0 = Frame pulse is active-low

bit 28 MSSEN: Master Mode Slave Select Enable bit

1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in 

Master mode. Polarity is determined by the FRMPOL bit.

0 = Slave select SPI support is disabled.

bit 27 FRMSYPW: Frame Sync Pulse Width bit

1 = Frame sync pulse is one character wide

0 = Frame sync pulse is one clock wide

bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per

pulse. This bit is only valid in FRAMED_SYNC mode.

111 = Reserved; do not use

110 = Reserved; do not use

101 = Generate a frame sync pulse on every 32 data characters

100 = Generate a frame sync pulse on every 16 data characters

011 = Generate a frame sync pulse on every 8 data characters

010 = Generate a frame sync pulse on every 4 data characters

001 = Generate a frame sync pulse on every 2 data characters

000 = Generate a frame sync pulse on every data character

bit 23 MCLKSEL: Master Clock Enable bit

(2)

1 = REFCLK is used by the Baud Rate Generator

0 = PBCLK is used by the Baud Rate Generator

bit 22-18 Unimplemented: Read as ‘0’

Note 1: When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit can only be written when the ON bit = 0.

3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value

of CKP.

 2014-2017 Microchip Technology Inc. DS60001290E-page 185

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)

1 = Frame synchronization pulse coincides with the first bit clock

0 = Frame synchronization pulse precedes the first bit clock

bit 16 ENHBUF: Enhanced Buffer Enable bit

(2)

1 = Enhanced Buffer mode is enabled

0 = Enhanced Buffer mode is disabled

bit 15 ON: SPI Peripheral On bit

(1)

1 = SPI Peripheral is enabled

0 = SPI Peripheral is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when CPU enters in Idle mode

0 = Continue operation in Idle mode

bit 12 DISSDO: Disable SDOx pin bit

1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register

0 = SDOx pin is controlled by the module

bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits

When AUDEN = 1:

MODE32 MODE16 Communication

11 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame

10 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame

01 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame

00 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame

When AUDEN = 0:

MODE32 MODE16 Communication

1x 32-bit

01 16-bit

00 8-bit

bit 9 SMP: SPI Data Input Sample Phase bit

Master mode (MSTEN = 1):

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

Slave mode (MSTEN = 0):

SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.

bit 8 CKE: SPI Clock Edge Select bit

(3)

1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)

0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)

bit 7 SSEN: Slave Select Enable (Slave mode) bit

1 = SSx pin used for Slave mode

0 = SSx pin not used for Slave mode, pin controlled by port function.

bit 6 CKP: Clock Polarity Select bit

(4)

1 = Idle state for clock is a high level; active state is a low level

0 = Idle state for clock is a low level; active state is a high level

bit 5 MSTEN: Master Mode Enable bit

1 = Master mode

0 =Slave mode

Note 1: When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit can only be written when the ON bit = 0.

3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value

of CKP.

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bit 4 DISSDI: Disable SDI bit

1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)

0 = SDI pin is controlled by the SPI module

bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits

11 = Interrupt is generated when the buffer is not full (has one or more empty elements)

10 = Interrupt is generated when the buffer is empty by one-half or more

01 = Interrupt is generated when the buffer is completely empty

00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are 

complete

bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits

11 = Interrupt is generated when the buffer is full

10 = Interrupt is generated when the buffer is full by one-half or more

01 = Interrupt is generated when the buffer is not empty

00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)

Note 1: When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit can only be written when the ON bit = 0.

3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value

of CKP.

 2014-2017 Microchip Technology Inc. DS60001290E-page 187

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SPISGNEXT —— FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR

7:0

R/W-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0

AUDEN

(1)

— — — AUDMONO

(1,2)

— AUDMOD<1:0>

(1,2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit

1 = Data from RX FIFO is sign extended

0 = Data from RX FIFO is not sign extened

bit 14-13 Unimplemented: Read as ‘0’

bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit

1 = Frame Error overflow generates error events

0 = Frame Error does not generate error events

bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit

1 = Receive overflow generates error events

0 = Receive overflow does not generate error events

bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit

1 = Transmit Underrun Generates Error Events

0 = Transmit Underrun Does Not Generates Error Events

bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)

1 = A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data

0 = A ROV is a critical error which stop SPI operation

bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)

1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty

0 = A TUR is a critical error which stop SPI operation

bit 7 AUDEN: Enable Audio CODEC Support bit

(1)

1 = Audio protocol enabled

0 = Audio protocol disabled

bit 6-5 Unimplemented: Read as ‘0’

bit 3 AUDMONO: Transmit Audio Data Format bit

(1,2)

1 = Audio data is mono (Each data word is transmitted on both left and right channels)

0 = Audio data is stereo

bit 2 Unimplemented: Read as ‘0’

bit 1-0 AUDMOD<1:0>: Audio Protocol Mode bit

(1,2)

11 = PCM/DSP mode

10 = Right Justified mode

01 = Left Justified mode

00 = I

S mode

Note 1: This bit can only be written when the ON bit = 0.

2: This bit is only valid for AUDEN = 1.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — RXBUFELM<4:0>

23:16

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — TXBUFELM<4:0>

15:8

U-0 U-0 U-0 R/C-0, HS R-0 U-0 U-0 R-0

— — — FRMERR SPIBUSY — — SPITUR

7:0

R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0

SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF

Legend: C = Clearable bit HS = Set in hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)

bit 23-21 Unimplemented: Read as ‘0’

bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)

bit 15-13 Unimplemented: Read as ‘0’

bit 12 FRMERR: SPI Frame Error status bit

1 = Frame error detected

0 = No Frame error detected

This bit is only valid when FRMEN = 1.

bit 11 SPIBUSY: SPI Activity Status bit

1 = SPI peripheral is currently busy with some transactions

0 = SPI peripheral is currently idle

bit 10-9 Unimplemented: Read as ‘0’

bit 8 SPITUR: Transmit Under Run bit

1 = Transmit buffer has encountered an underrun condition

0 = Transmit buffer has no underrun condition

This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling (ON bit = 0)

and re-enabling (ON bit = 1) the module, or writing a ‘0’ to SPITUR.

bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)

1 = When SPI module shift register is empty

0 = When SPI module shift register is not empty

bit 6 SPIROV: Receive Overflow Flag bit

1 = A new data is completely received and discarded. The user software has not read the previous data in

the SPIxBUF register.

0 = No overflow has occurred

This bit is set in hardware; can bit only be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the

module, or by writing a ‘0’ to SPIROV.

bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)

1 = RX FIFO is empty (CRPTR = SWPTR)

0 = RX FIFO is not empty (CRPTR



SWPTR)

bit 4 Unimplemented: Read as ‘0’

 2014-2017 Microchip Technology Inc. DS60001290E-page 189

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 3 SPITBE: SPI Transmit Buffer Empty Status bit

1 = Transmit buffer, SPIxTXB is empty

0 = Transmit buffer, SPIxTXB is not empty

Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.

Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.

bit 2 Unimplemented: Read as ‘0’

bit 1 SPITBF: SPI Transmit Buffer Full Status bit

1 = Transmit not yet started, SPITXB is full

0 = Transmit buffer is not full

Standard Buffer Mode:

Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.

Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.

Enhanced Buffer Mode:

Set when CWPTR + 1 = SRPTR; cleared otherwise

bit 0 SPIRBF: SPI Receive Buffer Full Status bit

1 = Receive buffer, SPIxRXB is full

0 = Receive buffer, SPIxRXB is not full

Standard Buffer Mode:

Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.

Enhanced Buffer Mode:

Set when SWPTR + 1 = CRPTR; cleared otherwise

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 190  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 191

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

18.0 INTER-INTEGRATED CIRCUIT

The I

C module provides complete hardware support

for both Slave and Multi-Master modes of the I

C serial

communication standard. Figure 18-1 illustrates the

C module block diagram.

Each I

C module has a 2-pin interface: the SCLx pin is

clock and the SDAx pin is data.

Each I

C module offers the following key features:

•I

C interface supporting both master and slave

operation

•I

C Slave mode supports 7-bit and 10-bit addressing

•I

C Master mode supports 7-bit and 10-bit

addressing

•I

C port allows bidirectional transfers between

master and slaves

• Serial clock synchronization for the I

C port can

be used as a handshake mechanism to suspend

and resume serial transfer (SCLREL control)

•I

C supports multi-master operation; detects bus

collision and arbitrates accordingly

• Provides support for address bit masking

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 24. “Inter-

Integrated Circuit (I

C)” (DS60001116)

in the “PIC 32 Famil y Refer ence Man ual” ,

which is available from the Microchip

web site (www.microchip.com/PIC32).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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FIGURE 18-1: I

C BLOCK DIAGRAM

Internal

Data Bus

SCLx

SDAx

Shift

Match Detect

I2CxADD

Start and Stop

Bit Detect

Clock

Address Match

Clock

Stretching

I2CxTRN

LSB

Shift Clock

BRG Down Counter

Reload

Control

PBCLK

Start and Stop

Bit Generation

Acknowledge

Generation

Collision

Detect

I2CxCON

I2CxSTAT

Control Logic

Read

LSB

Write

Read

I2CxBRG

I2CxRSR

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

I2CxMSK

I2CxRCV

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18.1 Control Registers

TABLE 18-1: I2C1 AND I2C2 REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

5000 I2C1CON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN BFFF

5010 I2C1STAT 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000

5020 I2C1ADD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — Address Register 0000

5030 I2C1MSK 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — Address Mask Register 0000

5040 I2C1BRG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — Baud Rate Generator Register 0000

5050 I2C1TRN 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — Transmit Register 0000

5060 I2C1RCV 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — Receive Register 0000

5100 I2C2CON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN BFFF

5110 I2C2STAT 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000

5120 I2C2ADD 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — Address Register 0000

5130 I2C2MSK 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — Address Mask Register 0000

5140 I2C2BRG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — Baud Rate Generator Register 0000

5150 I2C2TRN 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — Transmit Register 0000

5160 I2C2RCV 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — Receive Register 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and

INV Registers” for more information.

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CON: I

C ‘x’ CONTROL REGISTER (‘x’ = 1 AND 2)

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0

(1)

— SIDL SCLREL STRICT A10M DISSLW SMEN

7:0

R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

Legend: HC = Cleared in Hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: I

C Enable bit

(1)

1 = Enables the I

C module and configures the SDA and SCL pins as serial port pins

0 = Disables the I

C module; all I

C pins are controlled by PORT functions

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 SCLREL: SCLx Release Control bit (when operating as I

C slave)

1 = Release SCLx clock

0 = Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at

beginning of slave transmission. Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave

transmission.

bit 11 STRICT: Strict I

C Reserved Address Rule Enable bit

1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate

addresses in reserved address space.

0 = Strict I

C Reserved Address Rule not enabled

bit 10 A10M: 10-bit Slave Address bit

1 = I2CxADD is a 10-bit slave address

0 = I2CxADD is a 7-bit slave address

bit 9 DISSLW: Disable Slew Rate Control bit

1 = Slew rate control disabled

0 = Slew rate control enabled

bit 8 SMEN: SMBus Input Levels bit

1 = Enable I/O pin thresholds compliant with SMBus specification

0 = Disable SMBus input thresholds

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 7 GCEN: General Call Enable bit (when operating as I

C slave)

1 = Enable interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

0 = General call address disabled

bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I

C slave)

Used in conjunction with SCLREL bit.

1 = Enable software or receive clock stretching

0 = Disable software or receive clock stretching

bit 5 ACKDT: Acknowledge Data bit (when operating as I

C master, applicable during master receive)

Value that is transmitted when the software initiates an Acknowledge sequence.

1 = Send NACK during Acknowledge

0 = Send ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit 

(when operating as I

C master, applicable during master receive)

1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. 

Hardware clear at end of master Acknowledge sequence.

0 = Acknowledge sequence not in progress

bit 3 RCEN: Receive Enable bit (when operating as I

C master)

1 = Enables Receive mode for I

C. Hardware clear at end of eighth bit of master receive data byte.

0 = Receive sequence not in progress

bit 2 PEN: Stop Condition Enable bit (when operating as I

C master)

1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

0 = Stop condition not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I

C master)

1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of 

master Repeated Start sequence.

0 = Repeated Start condition not in progress

bit 0 SEN: Start Condition Enable bit (when operating as I

C master)

1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

0 = Start condition not in progress

CON: I

C ‘x’ CONTROL REGISTER (CONTINUED)(‘x’ = 1 AND 2)

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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STAT: I

C STATUS REGISTER

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC

ACKSTAT TRSTAT — — — BCL GCSTAT ADD10

7:0

R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC

IWCOL I2COV D_A P S R_W RBF TBF

Legend: HS = Set in hardware HSC = Hardware set/cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ACKSTAT: Acknowledge Status bit 

(when operating as I

C master, applicable to master transmit operation)

1 = Acknowledge was not received from slave

0 = Acknowledge was received from slave

Hardware set or clear at end of slave Acknowledge.

bit 14 TRSTAT: Transmit Status bit (when operating as I

C master, applicable to master transmit operation)

1 = Master transmit is in progress (8 bits + ACK)

0 = Master transmit is not in progress

Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.

bit 13-11 Unimplemented: Read as ‘0’

bit 10 BCL: Master Bus Collision Detect bit

1 = A bus collision has been detected during a master operation

0 = No collision

Hardware set at detection of bus collision. This condition can only be cleared by disabling (ON bit = 0) and

re-enabling (ON bit = 1) the module.

bit 9 GCSTAT: General Call Status bit

1 = General call address was received

0 = General call address was not received

Hardware set when address matches general call address. Hardware clear at Stop detection.

bit 8 ADD10: 10-bit Address Status bit

1 = 10-bit address was matched

0 = 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.

bit 7 IWCOL: Write Collision Detect bit

1 = An attempt to write the I2CxTRN register failed because the I

C module is busy

0 = No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

bit 6 I2COV: Receive Overflow Flag bit

1 = A byte was received while the I2CxRCV register is still holding the previous byte

0 = No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

bit 5 D_A: Data/Address bit (when operating as I

C slave)

1 = Indicates that the last byte received was data

0 = Indicates that the last byte received was device address

Hardware clear at device address match. Hardware set by reception of slave byte.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 4 P: Stop bit

1 = Indicates that a Stop bit has been detected last

0 = Stop bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

bit 3 S: Start bit

1 = Indicates that a Start (or Repeated Start) bit has been detected last

0 = Start bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

bit 2 R_W: Read/Write Information bit (when operating as I

C slave)

1 = Read – indicates data transfer is output from slave

0 = Write – indicates data transfer is input to slave

Hardware set or clear after reception of I

C device address byte.

bit 1 RBF: Receive Buffer Full Status bit

1 = Receive complete, I2CxRCV is full

0 = Receive not complete, I2CxRCV is empty

Hardware set when I2CxRCV is written with received byte. Hardware clear when software 

reads I2CxRCV.

bit 0 TBF: Transmit Buffer Full Status bit

1 = Transmit in progress, I2CxTRN is full

0 = Transmit complete, I2CxTRN is empty

Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

STAT: I

C STATUS REGISTER (CONTINUED)

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 198  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 199

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

19.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTE R

(UART)

The UART module is one of the serial I/O modules

available in PIC32MX1XX/2XX/5XX 64/100-pin family

devices. The UART is a full-duplex, asynchronous

communication channel that communicates with

peripheral devices and personal computers through

protocols, such as RS-232, RS-485, LIN and IrDA

The module also supports the hardware flow control

option, with UxCTS and UxRTS pins, and also includes

an IrDA encoder and decoder.

The primary features of the UART module are:

• Full-duplex, 8-bit or 9-bit data transmission

• Even, odd or no parity options (for 8-bit data)

• One or two Stop bits

• Hardware auto-baud feature

• Hardware flow control option

• Fully integrated Baud Rate Generator (BRG) with

16-bit prescaler

• Baud rates ranging from 38 bps to 12.5 Mbps at

50 MHz

• 8-level deep First-In-First-Out (FIFO) transmit

data buffer

• 8-level deep FIFO receive data buffer

• Parity, framing and buffer overrun error detection

• Support for interrupt-only on address detect 

bit = 1)

• Separate transmit and receive interrupts

• Loopback mode for diagnostic support

• LIN Protocol support

• IrDA encoder and decoder with 16x baud clock

output for external IrDA encoder/decoder support

Figure 19-1 illustrates a simplified block diagram of the

UART.

FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 21. “Universal

Asynchronous Receiver Transmitter

(UART)” (DS60001107) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32).

Baud Rate Generator

UxRX

Hardware Flow Control

UARTx Receiver

UARTx Transmitter UxTX

UxCTS

UxRTS/BCLKx

IrDA

Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.

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19.1 Control Registers

TABLE 19-1: UART1 THROUGH UART5 REGISTER MAP

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6000 U1MODE

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL IREN RTSMD —UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000

6010 U1STA

(1)

31:16 — — — — — — — ADM_EN ADDR<7:0> 0000

15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA FFFF

6020 U1TXREG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — TX8 Transmit Register 0000

6030 U1RXREG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — RX8 Receive Register 0000

6040 U1BRG

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 Baud Rate Generator Prescaler 0000

6200 U2MODE

(1)

31:16

15:0

— — — — — — — — — — — — — — — — 0000

ON —SIDL IREN RTSMD —UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000

6210 U2STA

(1)

31:16 — — — — — — — ADM_EN ADDR<7:0> 0000

15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA FFFF

6220 U2TXREG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — TX8 Transmit Register 0000

6230 U2RXREG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — RX8 Receive Register 0000

6240 U2BRG

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 Baud Rate Generator Prescaler 0000

6400 U3MODE

(1)

31:16

15:0

— — — — — — — — — — — — — — — — 0000

ON —SIDL IREN RTSMD —UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000

6410 U3STA

(1)

31:16 — — — — — — — ADM_EN ADDR<7:0> 0000

15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA FFFF

6420 U3TXREG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — TX8 Transmit Register 0000

6430 U3RXREG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — RX8 Receive Register 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

information.

2: This register is only available on 100-pin devices.

 2014-2017 Microchip Technology Inc. DS60001290E-page 201

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

6440 U3BRG

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 Baud Rate Generator Prescaler 0000

6600 U4MODE

(1)

31:16

15:0

— — — — — — — — — — — — — — — — 0000

ON —SIDL IREN RTSMD —UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000

6610 U4STA

(1)

31:16 — — — — — — — ADM_EN ADDR<7:0> 0000

15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA FFFF

6620 U4TXREG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — TX8 Transmit Register 0000

6630 U4RXREG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — RX8 Receive Register 0000

6640 U4BRG

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 Baud Rate Generator Prescaler 0000

6800 U5MODE

(1,2)

31:16

15:0

— — — — — — — — — — — — — — — — 0000

ON —SIDL IREN RTSMD —UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000

6810 U5STA

(1,2)

31:16 — — — — — — — ADM_EN ADDR<7:0> 0000

15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA FFFF

6820 U5TXREG

(1,2)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — TX8 Transmit Register 0000

6830 U5RXREG

(1,2)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — RX8 Receive Register 0000

6840 U5BRG

(1,2)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 Baud Rate Generator Prescaler 0000

TABLE 19-1: UART1 THROUGH UART5 REGISTER MAP (CONTINUED)

Virt ual Addres s

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

information.

2: This register is only available on 100-pin devices.

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DS60001290E-page 202  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

(1)

—SIDLIRENRTSMD—UEN<1:0>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: UARTx Enable bit

(1)

1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN 

control bits

0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx

registers; UARTx power consumption is minimal

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when device enters Idle mode

0 = Continue operation in Idle mode

bit 12 IREN: IrDA Encoder and Decoder Enable bit

1 = IrDA is enabled

0 = IrDA is disabled

bit 11 RTSMD: Mode Selection for UxRTS Pin bit

1 = UxRTS pin is in Simplex mode

0 = UxRTS pin is in Flow Control mode

bit 10 Unimplemented: Read as ‘0’

bit 9-8 UEN<1:0>: UARTx Enable bits

11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits

in the PORTx register

10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits

in the PORTx register

00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by

corresponding bits in the PORTx register

bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit

1 = Wake-up enabled

0 = Wake-up disabled

bit 6 LPBACK: UARTx Loopback Mode Select bit

1 = Loopback mode is enabled

0 = Loopback mode is disabled

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 5 ABAUD: Auto-Baud Enable bit

1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55);

cleared by hardware upon completion

0 = Baud rate measurement disabled or completed

bit 4 RXINV: Receive Polarity Inversion bit

1 = UxRX Idle state is ‘0’

0 = UxRX Idle state is ‘1’

bit 3 BRGH: High Baud Rate Enable bit

1 = High-Speed mode – 4x baud clock enabled

0 = Standard Speed mode – 16x baud clock enabled

bit 2-1 PDSEL<1:0>: Parity and Data Selection bits

11 = 9-bit data, no parity

10 = 8-bit data, odd parity

01 = 8-bit data, even parity

00 = 8-bit data, no parity

bit 0 STSEL: Stop Selection bit

1 = 2 Stop bits

0 = 1 Stop bit

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —ADM_EN

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADDR<7:0>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1

UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT

7:0

R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/W-0 R-0

URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-25 Unimplemented: Read as ‘0’

bit 24 ADM_EN: Automatic Address Detect Mode Enable bit

1 = Automatic Address Detect mode is enabled

0 = Automatic Address Detect mode is disabled

bit 23-16 ADDR<7:0>: Automatic Address Mask bits

When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address

detection.

bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits

11 = Reserved, do not use

10 = Interrupt is generated and asserted while the transmit buffer is empty

01 = Interrupt is generated and asserted when all characters have been transmitted

00 =Interrupt is generated and asserted while the transmit buffer contains at least one empty space

bit 13 UTXINV: Transmit Polarity Inversion bit

If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is ‘0’):

1 = UxTX Idle state is ‘0’

0 = UxTX Idle state is ‘1’

If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’):

1 = IrDA encoded UxTX Idle state is ‘1’

0 = IrDA encoded UxTX Idle state is ‘0’

bit 12 URXEN: Receiver Enable bit

1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)

0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by the

port.

bit 11 UTXBRK: Transmit Break bit

1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by

hardware upon completion

0 = Break transmission is disabled or completed

bit 10 UTXEN: Transmit Enable bit

1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)

0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is

controlled by the port.

bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)

1 = Transmit buffer is full

0 = Transmit buffer is not full, at least one more character can be written

 2014-2017 Microchip Technology Inc. DS60001290E-page 205

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 8 TRMT: Transmit Shift Register is Empty bit (read-only)

1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)

0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer

bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit

11 = Reserved; do not use

10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters)

01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters)

00 =Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect

0 = Address Detect mode is disabled

bit 4 RIDLE: Receiver Idle bit (read-only)

1 = Receiver is Idle

0 = Data is being received

bit 3 PERR: Parity Error Status bit (read-only)

1 = Parity error has been detected for the current character

0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (read-only)

1 = Framing error has been detected for the current character

0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit.

This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit

resets the receiver buffer and RSR to empty state.

1 = Receive buffer has overflowed

0 = Receive buffer has not overflowed

bit 0 URXDA: Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read

0 = Receive buffer is empty

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 206  2014-2017 Microchip Technology Inc.

19.2 Timing Diagrams

Figure 19-2 and Figure 19-3 illustrate typical receive

and transmit timing for the UART module.

FIGU RE 19 -2 : UART R E CEPT I O N

FIGURE 19-3: TRANSMISSION (8-BIT OR 9-BIT DATA)

Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13

Read to

UxRXREG

UxRX

RIDLE

OERR

UxRXIF

URXISEL = 00

UxRXIF

URXISEL = 01

UxRXIF

URXISEL = 10

Char 1 Char 2-4 Char 5-10 Char 11-13

Cleared by

Software

Cleared by

Software

Cleared by

Software

StartStart Bit 0 Bit 1 Stop

Write to

TSR

BCLK/16

(Shift Clock)

UxTX

UxTXIF

UTXISEL = 00

Bit 1

UxTXREG

UTXISEL = 01

UxTXIF

UTXISEL = 10

8 into TxBUF

Pull from Buffer

 2014-2017 Microchip Technology Inc. DS60001290E-page 207

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

20.0 PARALLEL MASTER PORT

(PMP)

The PMP is a parallel 8-bit or 16-bit input/output mod-

ule specifically designed to communicate with a wide

variety of parallel devices, such as communications

peripherals, LCDs, external memory devices and

microcontrollers. Because the interface to parallel

peripherals varies significantly, the PMP module is

highly configurable.

The following are the key features of the PMP module:

• 8-bit,16-bit interface

• Up to 16 programmable address lines

• Up to two Chip Select lines

• Programmable strobe options:

- Individual read and write strobes, or

- Read/write strobe with enable strobe

- Selectable polarity

• Address auto-increment/auto-decrement

• Programmable address/data multiplexing

• Programmable polarity on control signals

• Parallel Slave Port support:

- Legacy addressable

- Address support

• Read and Write 4-byte deep auto-incrementing buffer

• Programmable Wait states

• Operate during CPU Sleep and Idle modes

• Fast bit manipulation using CLR, SET and INV

registers

• Freeze option for in-circuit debugging

FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 13. “Parallel

Master Port (PMP)” (DS60001128) in

the “PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32).

Note: On 64-pin devices, data pins PMD<15:8>

are not available in 16-bit Master modes.

PMA<0>

PMA<14>

PMRD

PMWR

PMENB

PMRD/PMWR

PMCS1

PMA<1>

PMA<13:2>

PMALL

PMALH

Flash

Address Bus

Data Bus

Control Lines

LCD FIFO

Microcontroller

8-bit/16-bit Data (with or without multiplexed addressing)

Up to 16-bit Address

Parallel

Buffer

PMD<7:0>

Master Port

EEPROM

SRAM

Note: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes.

PMD<15:8>

(1)

PMA<15>

PMCS2

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

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20.1 Control Registers

TABLE 20-1: PARALLEL MASTER PORT REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

7000 PMCON 31:16 ————————RDSTART — — — — — DUALBUF —0000

15:0 ON —SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP CS2P CS1P —WRSP RDSP 0000

7010 PMMODE 31:16 ————————————————0000

15:0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000

7020 PMADDR

31:16 ————————————————0000

15:0

CS2 CS1

ADDR<13:0> 0000

ADDR15 ADDR14

0000

7030 PMDOUT 31:16 ————————————————0000

15:0 DATAOUT<15:0> 0000

7040 PMDIN 31:16 ————————————————0000

15:0 DATAIN<15:0> 0000

7050 PMAEN 31:16 ————————————————0000

15:0 PTEN<15:0> 0000

7060 PMSTAT 31:16 ————————————————0000

15:0 IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E BFBF

7070 PMWADDR

31:16 ————————————————0000

15:0

WCS2 WCS1

——————————————0000

WADDR15 WADDR14

WADDR<13:0> 0000

7080 PMRADDR

31:16 ————————————————0000

15:0

RCS2 RCS1

——————————————0000

RADDR15 RADDR14

RADDR<13:0> 0000

7090 PMRDIN 31:16 31:16 ———————————————0000

15:0 15:0 RDATAIN<15:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 209

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

R/W-0, HC U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

RDSTART ————— DUALBUF —

15:8

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

—SIDL

ADRMUX<1:0>

PMPTTL PTWREN PTRDEN

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

CSF<1:0>

(2)

ALP

(2)

CS2P

(2)

CS1P

(2)

— WRSP RDSP

Legend: HC = Hardware cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23 RDSTART: Start a Read on the PMP Bus bit

(3)

1 = Start a read cycle on the PMP bus

0 = No effect

This bit is cleared by hardware at the end of the read cycle when the BUSY bit (PMMODE<15>) = 0.

bit 22-18 Unimplemented: Read as ‘0’

bit 17 DUALBUF: Parallel Master Port Dual Read/Write Buffer Enable bit

This bit is only valid in Master mode.

1 = PMP uses separate registers for reads and writes

Reads: PMRADDR and PMRDIN

Writes: PMRWADDR and PMDOUT

0 = PMP uses legacy registers for reads and writes

Reads/Writes: PMADDR and PMRDIN

bit 16 Unimplemented: Read as ‘0’

bit 15 ON: Parallel Master Port Enable bit

(1)

1 = PMP enabled

0 = PMP disabled, no off-chip access performed

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits

11 = Lower 8 bits of address are multiplexed on PMD<15:0> pins

10 = All 16 bits of address are multiplexed on PMD<7:0> pins

01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<15:8>

00 = Address and data appear on separate pins

bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit

1 = PMP module uses TTL input buffers

0 = PMP module uses Schmitt Trigger input buffer

bit 9 PTWREN: Write Enable Strobe Port Enable bit

1 = PMWR/PMENB port enabled

0 = PMWR/PMENB port disabled

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.

2: These bits have no effect when their corresponding pins are used as address lines.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 210  2014-2017 Microchip Technology Inc.

bit 8 PTRDEN: Read/Write Strobe Port Enable bit

1 = PMRD/PMWR port enabled

0 = PMRD/PMWR port disabled

bit 7-6 CSF<1:0>: Chip Select Function bits

(2)

11 = Reserved

10 = PMCS1 and PMCS2 function as Chip Select

01 = PMCS1 functions as address bit 14; PMCS2 functions as Chip Select

00 = PMCS1 and PMCS2 function as address bits 14 and 15, respectively

bit 5 ALP: Address Latch Polarity bit

(2)

1 = Active-high (PMALL and PMALH)

0 = Active-low (PMALL and PMALH)

bit 4 CS2P: Chip Select 0 Polarity bit

(2)

1 = Active-high (PMCS2)

0 =Active-low (PMCS2

)

bit 3 CS1P: Chip Select 0 Polarity bit

(2)

1 = Active-high (PMCS1)

0 =Active-low (PMCS1

)

bit 2 Unimplemented: Read as ‘0’

bit 1 WRSP: Write Strobe Polarity bit

For Slave Modes and Master mode 2 (MODE<1:0> = 00,01,10):

1 = Write strobe active-high (PMWR)

0 = Write strobe active-low (PMWR)

For Master mode 1 (MODE<1:0> = 11):

1 = Enable strobe active-high (PMENB)

0 = Enable strobe active-low (PMENB)

bit 0 RDSP: Read Strobe Polarity bit

For Slave modes and Master mode 2 (MODE<1:0> = 00,01,10):

1 = Read Strobe active-high (PMRD)

0 = Read Strobe active-low (PMRD)

For Master mode 1 (MODE<1:0> = 11):

1 = Read/write strobe active-high (PMRD/PMWR)

0 = Read/write strobe active-low (PMRD/PMWR)

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.

2: These bits have no effect when their corresponding pins are used as address lines.

 2014-2017 Microchip Technology Inc. DS60001290E-page 211

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAITB<1:0>

(1)

WAITM<3:0>

(1)

WAITE<1:0>

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 BUSY: Busy bit (Master mode only)

1 = Port is busy

0 = Port is not busy

bit 14-13 IRQM<1:0>: Interrupt Request Mode bits

11 = Reserved, do not use

10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)

or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only)

01 = Interrupt generated at the end of the read/write cycle

00 = No Interrupt generated

bit 12-11 INCM<1:0>: Increment Mode bits

11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only)

10 = Decrement ADDR<15:0> by 1 every read/write cycle

(2)

01 = Increment ADDR<15:0> by 1 every read/write cycle

(2)

00 = No increment or decrement of address

bit 10 MODE16: 8/16-bit Mode bit

1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer

0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer

bit 9-8 MODE<1:0>: Parallel Port Mode Select bits

11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<7:0> and PMD<8:15>

(3)

)

10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<7:0> and PMD<8:15>

(3)

)

01 = Enhanced Slave mode, control signals (

PMRD

PMWR

PMCS

, PMD<7:0> and PMA<1:0>)

00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)

bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits

(1)

11 = Data wait of 4 T

; multiplexed address phase of 4 T

10 = Data wait of 3 T

; multiplexed address phase of 3 T

01 = Data wait of 2 T

; multiplexed address phase of 2 T

00 = Data wait of 1 T

; multiplexed address phase of 1 T

(default)

Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 T

PBCLK

cycle for a

write operation; WAITB = 1 T

PBCLK

cycle, WAITE = 0 T

PBCLK

cycles for a read operation.

2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select

CS2 and CS1.

3: These pins are active when MODE16 = 1 (16-bit mode).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 212  2014-2017 Microchip Technology Inc.

bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits

(1)

1111 = Wait of 16 T

•

0001 = Wait of 2 T

0000 = Wait of 1 T

(default)

bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits

(1)

11 = Wait of 4 T

10 = Wait of 3 T

01 = Wait of 2 T

00 = Wait of 1 T

(default)

For Read operations:

11 = Wait of 3 T

10 = Wait of 2 T

01 = Wait of 1 T

00 = Wait of 0 T

(default)

Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 T

PBCLK

cycle for a

write operation; WAITB = 1 T

PBCLK

cycle, WAITE = 0 T

PBCLK

cycles for a read operation.

2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select

CS2 and CS1.

3: These pins are active when MODE16 = 1 (16-bit mode).

 2014-2017 Microchip Technology Inc. DS60001290E-page 213

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CS2

(1)

CS1

(3)

ADDR<13:8>

ADDR15

(2)

ADDR14

(4)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 CS2: Chip Select 2 bit

(1)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive

bit 15 ADDR<15>: Target Address bit 15

(2)

bit 14 CS1: Chip Select 1 bit

(3)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive

bit 14 ADDR<14>: Target Address bit 14

(4)

bit 13-0 ADDR<13:0>: Address bits

Note 1: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01.

2: When the CSF<1:0> bits (PMCON<7:6>) = 00.

3: When the CSF<1:0> bits (PMCON<7:6>) = 10.

4: When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01.

Note: If the DUALBUF bit (PMCON<17>) = 0, the bits in this register control both read and write target

addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the

PMRADDR register for Read operations and the PMWADDR register for Write operations.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 214  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAOUT<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAOUT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 DATAOUT<15:0>: Port Data Output bits

This register is used for Read operations in the Enhanced Parallel Slave mode and Write operations for Dual

Buffer Master mode.

In Dual Buffer Master mode, the DUALBUF bit (PMPCON<17>) = 1, a write to the MSB triggers the trans-

action on the PMP port. When MODE16 = 1, MSB = DATAOUT<15:8>. When MODE16 = 0,

MSB = DATAOUT<7:0>.

Note: In Master mode, a read will return the last value written to the register. In Slave mode, a read will return

indeterminate results.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAIN<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAIN<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 DATAIN<15:0>: Port Data Input bits

This register is used for both Parallel Master Port mode and Enhanced Parallel Slave mode.

In Parallel Master mode, a write to the MSB triggers the write transaction on the PMP port. Similarly, a read

to the MSB triggers the read transaction on the PMP port.

When MODE16 = 1, MSB = DATAIN<15:8>. When MODE16 = 0, MSB = DATAIN<7:0>.

Note: This register is not used in Dual Buffer Master mode (i.e., DUALBUF bit (PMPCON<17>) = 1).

 2014-2017 Microchip Technology Inc. DS60001290E-page 215

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN<15:14>

(1)

PTEN<13:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN<7:2> PTEN<1:0>

(2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Write ‘0’; ignore read

bit 15-14 PTEN<15:14>: PMCSx Address Port Enable bits

1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1

(1)

0 = PMA15 and PMA14 function as port I/O

bit 13-2 PTEN<13:2>: PMP Address Port Enable bits

1 = PMA<13:2> function as PMP address lines

0 = PMA<13:2> function as port I/O

bit 1-0 PTEN<1:0>: PMALH/PMALL Address Port Enable bits

1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL

(2)

0 = PMA1 and PMA0 pads function as port I/O

Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>).

2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode

selected by the ADRMUX<1:0> bits in the PMCON register.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 216  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8

R-0 R/W-0, HSC U-0 U-0 R-0 R-0 R-0 R-0

IBF IBOV — — IB3F IB2F IB1F IB0F

7:0

R-1 R/W-0, HSC U-0 U-0 R-1 R-1 R-1 R-1

OBE OBUF —— OB3E OB2E OB1E OB0E

Legend: HSC = Set by Hardware; Cleared by Software

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 IBF: Input Buffer Full Status bit

1 = All writable input buffer registers are full

0 = Some or all of the writable input buffer registers are empty

bit 14 IBOV: Input Buffer Overflow Status bit

1 = A write attempt to a full input byte buffer occurred (must be cleared in software)

0 = No overflow occurred

bit 13-12 Unimplemented: Read as ‘0’

bit 11-8 IBxF: Input Buffer ‘x’ Status Full bits

1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)

0 = Input Buffer does not contain any unread data

bit 7 OBE: Output Buffer Empty Status bit

1 = All readable output buffer registers are empty

0 = Some or all of the readable output buffer registers are full

bit 6 OBUF: Output Buffer Underflow Status bit

1 = A read occurred from an empty output byte buffer (must be cleared in software)

0 = No underflow occurred

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 OBxE: Output Buffer ‘x’ Status Empty bits

1 = Output buffer is empty (writing data to the buffer will clear this bit)

0 = Output buffer contains data that has not been transmitted

 2014-2017 Microchip Technology Inc. DS60001290E-page 217

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCS2

(1)

WCS1

(3)

WADDR<13:8>

WADDR15

(2)

WADDR14

(4)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 WCS2: Chip Select 2 bit

(1)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive

bit 15 WADDR<15>: Target Address bit 15

(2)

bit 14 WCS1: Chip Select 1 bit

(3)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive

bit 14 WADDR<14>: Target Address bit 14

(4)

bit 13-0 WADDR<13:0>: Address bits

Note 1: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01.

2: When the CSF<1:0> bits (PMCON<7:6>) = 00.

3: When the CSF<1:0> bits (PMCON<7:6>) = 10.

4: When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01.

Note: This register is only used when the DUALBUF bit (PMCON<17>) is set to ‘1’.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 218  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RCS2

(1)

RCS1

(3)

RADDR<13:8>

RADDR15

(2)

RADDR14

(4)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 RCS2: Chip Select 2 bit

(1)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive (RADDR15 function is selected)

bit 15 RADDR<15>: Target Address bit 15

(2)

bit 14 RCS1: Chip Select 1 bit

(3)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive (RADDR14 function is selected)

bit 14 RADDR<14>: Target Address bit 14

(4)

bit 13-0 RADDR<13:0>: Address bits

Note 1: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01.

2: When the CSF<1:0> bits (PMCON<7:6>) = 00.

3: When the CSF<1:0> bits (PMCON<7:6>) = 10.

4: When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01.

Note: This register is only used when the DUALBUF bit (PMCON<17>) is set to ‘1’.

 2014-2017 Microchip Technology Inc. DS60001290E-page 219

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RDATAIN<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RDATAIN<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 RDATAIN<15:0>: Port Read Input Data bits

Note: This register is only used when the DUALBUF bit (PMCON<17>) is set to ‘1’ and exclusively for reads. If the

DUALBUF bit is ‘0’, the PMDIN register (Register 20-5) is used for reads instead of PMRDIN.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 220  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 221

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

21.0 REAL-TIME CLOCK AND

CALENDAR (RTCC)

The PIC32 RTCC module is intended for applications in

which accurate time must be maintained for extended

periods of time with minimal or no CPU intervention.

Low-power optimization provides extended battery

lifetime while keeping track of time.

The following are the key features of this module:

• Time: hours, minutes and seconds

• 24-hour format (military time)

• Visibility of one-half second period

• Provides calendar: Weekday, date, month and

year

• Alarm intervals are configurable for half of a

second, one second, 10 seconds, one minute, 10

minutes, one hour, one day, one week, one month

and one year

• Alarm repeat with decrementing counter

• Alarm with indefinite repeat: Chime

• Year range: 2000 to 2099

• Leap year correction

• BCD format for smaller firmware overhead

• Optimized for long-term battery operation

• Fractional second synchronization

• User calibration of the clock crystal frequency with

auto-adjust

• Calibration range: 0.66 seconds error per month

• Calibrates up to 260 ppm of crystal error

• Requirements: External 32.768 kHz clock crystal

• Alarm pulse or seconds clock output on 

RTCC pin

FIGU RE 21 -1 : RTCC BLO C K DI AG R AM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 29. “Real-Time

Clock and Calendar (RTCC)”

(DS60001125) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

RTCC Prescalers

RTCC Timer

Comparator

Compare Registers

Repeat Counter

ALRMTIME

HR, MIN, SEC

ALRMDATE

with Masks

RTCC Interrupt Logic

Alarm

Event

32.768 kHz Input

from Secondary

0.5s

Alarm Pulse

Set RTCC Flag

RTCVAL

ALRMVAL

RTCC

RTCOE

Oscillator (S

OSC

)

CAL<9:0>

MONTH, DAY, WDAY

RTCTIME

HR, MIN, SEC

RTCDATE

YEAR, MONTH, DAY, WDAY

Seconds Pulse

RTSECSEL

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DS60001290E-page 222  2014-2017 Microchip Technology Inc.

21.1 Control Registers

TABLE 21-1: RTCC REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

0200 RTCCON 31:16 — — — — — — CAL<9:0> 0000

15:0 ON —SIDL — — — — — RTSECSEL RTCCLKON — — RTCWREN RTCSYNC HALFSEC RTCOE 0000

0210 RTCALRM 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ALRMEN CHIME PIV ALRMSYNC AMASK<3:0> ARPT<7:0> 0000

0220 RTCTIME 31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx

15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00

0230 RTCDATE 31:16 YEAR10<3:0> YEAR01<3:0> MONTH10<3:0> MONTH01<3:0> xxxx

15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx00

0240 ALRMTIME 31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx

15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00

0250 ALRMDATE 31:16 — — — — — — — — MONTH10<3:0> MONTH01<3:0> 00xx

15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx0x

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 223

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — —CAL<9:8>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CAL<7:0>

15:8

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

(1,2)

—SIDL— — — — —

7:0

R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0

RTSECSEL

(3)

RTCCLKON ——RTCWREN

(4)

RTCSYNC HALFSEC

(5)

RTCOE

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-26 Unimplemented: Read as ‘0’

bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value

0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute

•

0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute

0000000000 = No adjustment

1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute

•

1000000000 = Maximum negative adjustment, subtracts 512 clock pulses every one minute

bit 15 ON: RTCC On bit

(1,2)

1 = RTCC module is enabled

0 = RTCC module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode

0 = Continue normal operation in Idle mode

bit 12-8 Unimplemented: Read as ‘0’

bit 7 RTSECSEL: RTCC Seconds Clock Output Select bit

(3)

1 = RTCC Seconds Clock is selected for the RTCC pin

0 = RTCC Alarm Pulse is selected for the RTCC pin

bit 6 RTCCLKON: RTCC Clock Enable Status bit

1 = RTCC Clock is actively running

0 = RTCC Clock is not running

bit 5-4 Unimplemented: Read as ‘0’

Note 1: The ON bit is only writable when RTCWREN = 1.

2: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.

4: The RTCWREN bit can be set only when the write sequence is enabled.

5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).

Note: This register is reset only on a Power-on Reset (POR).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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bit 3 RTCWREN: RTC Value Registers Write Enable bit

(4)

1 = RTC Value registers can be written to by the user

0 = RTC Value registers are locked out from being written to by the user

bit 2 RTCSYNC: RTCC Value Registers Read Synchronization bit

1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read

If the register is read twice and results in the same data, the data can be assumed to be valid

0 = RTC Value registers can be read without concern about a rollover ripple

bit 1 HALFSEC: Half-Second Status bit

(5)

1 = Second half period of a second

0 = First half period of a second

bit 0 RTCOE: RTCC Output Enable bit

1 = RTCC clock output enabled – clock presented onto an I/O

0 = RTCC clock output disabled

Note 1: The ON bit is only writable when RTCWREN = 1.

2: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.

4: The RTCWREN bit can be set only when the write sequence is enabled.

5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).

Note: This register is reset only on a Power-on Reset (POR).

 2014-2017 Microchip Technology Inc. DS60001290E-page 225

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

ALRMEN

(1,2)

CHIME

(2)

PIV

(2)

ALRMSYNC

(3)

AMASK<3:0>

(3)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ARPT<7:0>

(3)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ALRMEN: Alarm Enable bit

(1,2)

1 = Alarm is enabled

0 = Alarm is disabled

bit 14 CHIME: Chime Enable bit

(2)

1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF

0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00

bit 13 PIV: Alarm Pulse Initial Value bit

(2)

When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.

When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.

bit 12 ALRMSYNC: Alarm Sync bit

(3)

1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read. 

The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple

bits may be changing, which are then synchronized to the PB clock domain

0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC

clocks away from a half-second rollover

bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits

(3)

0000 = Every half-second

0001 = Every second

0010 = Every 10 seconds

0011 = Every minute

0100 = Every 10 minutes

0101 = Every hour

0110 = Once a day

0111 = Once a week

1000 = Once a month

1001 = Once a year (except when configured for February 29, once every four years)

1010 = Reserved; do not use

1011 = Reserved; do not use

11xx = Reserved; do not use

Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and

CHIME = 0.

2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.

3: This assumes a CPU read will execute in less than 32 PBCLKs.

Note: This register is reset only on a Power-on Reset (POR).

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bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits

(3)

11111111 =Alarm will trigger 256 times

•

00000000 =Alarm will trigger one time

The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.

Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and

CHIME = 0.

2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.

3: This assumes a CPU read will execute in less than 32 PBCLKs.

Note: This register is reset only on a Power-on Reset (POR).

 2014-2017 Microchip Technology Inc. DS60001290E-page 227

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

HR10<3:0> HR01<3:0>

23:16

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

MIN10<3:0> MIN01<3:0>

15:8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SEC10<3:0> SEC01<3:0>

7:0

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10s place digits; contains a value from 0 to 2

bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1s place digit; contains a value from 0 to 9

bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10s place digits; contains a value from 0 to 5

bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1s place digit; contains a value from 0 to 9

bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10s place digits; contains a value from 0 to 5

bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1s place digit; contains a value from 0 to 9

bit 7-0 Unimplemented: Read as ‘0’

Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 228  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

YEAR10<3:0> YEAR01<3:0>

23:16

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

MONTH10<3:0> MONTH01<3:0>

15:8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DAY10<3:0> DAY01<3:0>

7:0

U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x

— — — — WDAY01<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10s place digits

bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1s place digit

bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10s place digits; contains a value of 0 or 1

bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1s place digit; contains a value from 0 to 9

bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10s place digits; contains a value from 0 to 3

bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1s place digit; contains a value from 0 to 9

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1s place digit; contains a value from 0 to 6

Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).

 2014-2017 Microchip Technology Inc. DS60001290E-page 229

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

HR10<3:0> HR01<3:0>

23:16

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

MIN10<3:0> MIN01<3:0>

15:8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SEC10<3:0> SEC01<3:0>

7:0

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10s place digits; contains a value from 0 to 2

bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1s place digit; contains a value from 0 to 9

bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10s place digits; contains a value from 0 to 5

bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1s place digit; contains a value from 0 to 9

bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10s place digits; contains a value from 0 to 5

bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1s place digit; contains a value from 0 to 9

bit 7-0 Unimplemented: Read as ‘0’

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

MONTH10<3:0> MONTH01<3:0>

15:8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DAY10<1:0> DAY01<3:0>

7:0

U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x

— — — — WDAY01<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10s place digits; contains a value of 0 or 1

bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1s place digit; contains a value from 0 to 9

bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10s place digits; contains a value from 0 to 3

bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1s place digit; contains a value from 0 to 9

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1s place digit; contains a value from 0 to 6

 2014-2017 Microchip Technology Inc. DS60001290E-page 231

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

22.0 10-BIT ANALOG-TO-DIGITAL

CONVERTER (ADC)

The 10-bit Analog-to-Digital Converter (ADC) includes

the following features:

• Successive Approximation Register (SAR)

conversion

• Up to 1 Msps conversion speed

• Up to 48 analog input pins

• External voltage reference input pins

• One unipolar, differential Sample and Hold

Amplifier (SHA)

• Automatic Channel Scan mode

• Selectable conversion trigger source

• 16-word conversion result buffer

• Selectable buffer fill modes

• Eight conversion result format options

• Operation during CPU Sleep and Idle modes

A block diagram of the 10-bit ADC is illustrated in

Figure 22-1. The 10-bit ADC has up to 28 analog input

pins, designated AN0-AN27. In addition, there are two

analog input pins for external voltage reference

connections. These voltage reference inputs may be

shared with other analog input pins and may be

common to other analog module references.

FIGU RE 22-1: ADC1 MO D ULE BLO CK DI AGRA M

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 17. “10-bit

Analog-to-Digital Converter (ADC)”

(DS60001104) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

SAR ADC

S&H

ADC1BUF0

ADC1BUF1

ADC1BUF2

ADC1BUFF

ADC1BUFE

REF(3)

CTMUT

(2)

AN1

REFL

CH0SB<5:0>

CH0NA CH0NB

CH0SA<5:0>

Channel

Scan

CSCNA

Alternate

REF

(1)

REF

(1)

Note 1: V

REF

+ and V

REF

- inputs can be multiplexed with other analog inputs.

2: Connected to the CTMU temperature reference diode. See Section 26.0 “Charge Time Measurement Unit

(CTMU)” for more information.

3: Internal precision 1.2V reference. See Section 24.0 “Comparator” for more information.

4: This selection is only used with CTMU capacitive and time measurement.

Input Selection

REFH

REFL

VCFG<2:0>

AN47

AN0

Open

(4)

CTMUI

(3)

ALTS (AD1CON2<0>)

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 232  2014-2017 Microchip Technology Inc.

FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

Div 2

PB(2)

ADC Conversion

Clock Multiplier

2, 4,..., 512

ADRC

ADCS<7:0>

FRC

(1)

Note 1: See Section 31.0 “40 MHz Electrical Characterist ics” for the exact FRC clock value.

2: Refer to Figure 8-1 in Section 8.0 “Oscillator Configuration” for more information.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 233  2014-2017 Microchip Technology Inc.

22.1 Control Registers

TABLE 22-1: ADC REGISTER MAP

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

9000 AD1CON1

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — FORM<2:0> SSRC<2:0> CLRASAM —ASAM SAMP DONE 0000

9010 AD1CON2

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 VCFG<2:0> OFFCAL —CSCNA — — BUFS —SMPI<3:0> BUFM ALTS 0000

9020 AD1CON3

(1)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 ADRC — — SAMC<4:0> ADCS<7:0> 0000

9040 AD1CHS

(1)

31:16 CH0NB —CH0SB<5:0>

(2)

CH0NA —CH0SA<5:0>

(2)

0000

15:0 — — — — — — — — — — — — — — — — 0000

9050 AD1CSSL

(1,3)

31:16 CSSL31 CSSL30 CSSL29 CSSL28 CSSL27 CSSL26 CSSL25 CSSL24 CSSL23 CSSL22 CSSL21 CSSL20 CSSL19 CSSL18 CSSL17 CSSL16 0000

15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000

9060 AD1CSSL2

(1)

31:16 —————————————CSSL50 CSSL49 CSSL48 0000

15:0 CSSL47 CSSL46 CSSL45 CSSL44 CSSL43 CSSL42 CSSL41 CSSL40 CSSL39 CSSL38 CSSL37 CSSL36 CSSL35 CSSL34 CSSL33 CSSL32 0000

9070 ADC1BUF0 31:16 ADC Result Word 0 (ADC1BUF0<31:0>) 0000

15:0 0000

9080 ADC1BUF1 31:16 ADC Result Word 1 (ADC1BUF1<31:0>) 0000

15:0 0000

9090 ADC1BUF2 31:16 ADC Result Word 2 (ADC1BUF2<31:0>) 0000

15:0 0000

90A0 ADC1BUF3 31:16 ADC Result Word 3 (ADC1BUF3<31:0>) 0000

15:0 0000

90B0 ADC1BUF4 31:16 ADC Result Word 4 (ADC1BUF4<31:0>) 0000

15:0 0000

90C0 ADC1BUF5 31:16 ADC Result Word 5 (ADC1BUF5<31:0>) 0000

15:0 0000

90D0 ADC1BUF6 31:16 ADC Result Word 6 (ADC1BUF6<31:0>) 0000

15:0 0000

90E0 ADC1BUF7 31:16 ADC Result Word 7 (ADC1BUF7<31:0>) 0000

15:0 0000

90F0 ADC1BUF8 31:16 ADC Result Word 8 (ADC1BUF8<31:0>) 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

2: For 64-pin devices, the MSB of these bits is not available.

3: For 64-pin devices, only the CSSL30:CSSL0 bits are available.

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

DS60001290E-page 234  2014-2017 Microchip Technology Inc.

9100 ADC1BUF9 31:16 ADC Result Word 9 (ADC1BUF9<31:0>) 0000

15:0 0000

9110 ADC1BUFA 31:16 ADC Result Word A (ADC1BUFA<31:0>) 0000

15:0 0000

9120 ADC1BUFB 31:16 ADC Result Word B (ADC1BUFB<31:0>) 0000

15:0 0000

9130 ADC1BUFC 31:16 ADC Result Word C (ADC1BUFC<31:0>) 0000

15:0 0000

9140 ADC1BUFD 31:16 ADC Result Word D (ADC1BUFD<31:0>) 0000

15:0 0000

9150 ADC1BUFE 31:16 ADC Result Word E (ADC1BUFE<31:0>) 0000

15:0 0000

9160 ADC1BUFF 31:16 ADC Result Word F (ADC1BUFF<31:0>) 0000

15:0 0000

TABLE 22-1: ADC REGISTER MAP (CONTINUED)

Virt ual Addres s

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

2: For 64-pin devices, the MSB of these bits is not available.

3: For 64-pin devices, only the CSSL30:CSSL0 bits are available.

 2014-2017 Microchip Technology Inc. DS60001290E-page 235

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

(1)

—SIDL——FORM<2:0>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC

SSRC<2:0> CLRASAM — ASAM SAMP

(2)

DONE

(3)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: ADC Operating Mode bit

(1)

1 = ADC module is operating

0 = ADC module is not operating

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-11 Unimplemented: Read as ‘0’

bit 10-8 FORM<2:0>: Data Output Format bits

011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)

010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)

001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)

000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)

111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)

110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)

101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)

100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)

bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits

111 = Internal counter ends sampling and starts conversion (auto convert)

110 = Reserved

101 = Reserved

100 = Reserved

011 = CTMU ends sampling and starts conversion

010 = Timer 3 period match ends sampling and starts conversion

001 = Active transition on INT0 pin ends sampling and starts conversion

000 = Clearing SAMP bit ends sampling and starts conversion

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if

ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC



0, this

bit is automatically cleared by hardware to end sampling and start conversion.

3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can

write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation

already in progress. This bit is automatically cleared by hardware at the start of a new conversion.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 236  2014-2017 Microchip Technology Inc.

bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated)

1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the

ADC interrupt is generated.

0 = Normal operation, buffer contents will be overwritten by the next conversion sequence

bit 3 Unimplemented: Read as ‘0’

bit 2 ASAM: ADC Sample Auto-Start bit

1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set.

0 = Sampling begins when SAMP bit is set

bit 1 SAMP: ADC Sample Enable bit

(2)

1 = The ADC sample and hold amplifier is sampling

0 = The ADC sample/hold amplifier is holding

When ASAM = 0, writing ‘1’ to this bit starts sampling.

When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion.

bit 0 DONE: Analog-to-Digital Conversion Status bit

(3)

1 = Analog-to-digital conversion is done

0 = Analog-to-digital conversion is not done or has not started

Clearing this bit will not affect any operation in progress.

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if

ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC



0, this

bit is automatically cleared by hardware to end sampling and start conversion.

3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can

write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation

already in progress. This bit is automatically cleared by hardware at the start of a new conversion.

 2014-2017 Microchip Technology Inc. DS60001290E-page 237

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0

VCFG<2:0> OFFCAL — CSCNA — —

7:0

R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS — SMPI<3:0> BUFM ALTS

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits

REFH

REFL

000 AV

AVss

001 External V

REF

+ pin AV

010 AV

External V

REF

- pin

011 External V

REF

+ pin External V

REF

- pin

1xx AV

bit 12 OFFCAL: Input Offset Calibration Mode Select bit

1 = Enable Offset Calibration mode

Positive and negative inputs of the sample and hold amplifier are connected to V

REFL

0 = Disable Offset Calibration mode

The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL

bit 11 Unimplemented: Read as ‘0’

bit 10 CSCNA: Input Scan Select bit

1 = Scan inputs

0 = Do not scan inputs

bit 9-8 Unimplemented: Read as ‘0’

bit 7 BUFS: Buffer Fill Status bit

Only valid when BUFM = 1.

1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7

0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF

bit 6 Unimplemented: Read as ‘0’

bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits

1111 = Interrupts at the completion of conversion for each 16

sample/convert sequence

1110 = Interrupts at the completion of conversion for each 15

sample/convert sequence

•

0001 = Interrupts at the completion of conversion for each 2

sample/convert sequence

0000 = Interrupts at the completion of conversion for each sample/convert sequence

bit 1 BUFM: ADC Result Buffer Mode Select bit

1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8

0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0

bit 0 ALTS: Alternate Input Sample Mode Select bit

1 = Uses Sample A input multiplexer settings for first sample, then alternates between Sample B and 

Sample A input multiplexer settings for all subsequent samples

0 = Always use Sample A input multiplexer settings

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 238  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADRC —— SAMC<4:0>

(1)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W R/W-0

ADCS<7:0>

(2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ADRC: ADC Conversion Clock Source bit

1 = Clock derived from FRC

0 = Clock derived from Peripheral Bus Clock (PBCLK)

bit 14-13 Unimplemented: Read as ‘0’

bit 12-8 SAMC<4:0>: Auto-Sample Time bits

(1)

11111 = 31 T

•

00001 = 1 T

00000 = 0 T

(Not allowed)

bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits

(2)

11111111 =T

• 2 • (ADCS<7:0> + 1) = 512 • T

= T

•

00000001 =T

• 2 • (ADCS<7:0> + 1) = 4 • T

= T

00000000 =T

• 2 • (ADCS<7:0> + 1) = 2 • T

= T

Note 1: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111.

2: This bit is not used if the ADRC bit (AD1CON3<15>) = 1.

 2014-2017 Microchip Technology Inc. DS60001290E-page 239

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NB — CH0SB<5:0>

23:16

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NA — CH0SA<5:0>

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 CH0NB: Negative Input Select bit for Sample B

1 = Channel 0 negative input is AN1

0 = Channel 0 negative input is V

REFL

bit 30 Unimplemented: Read as ‘0’

bit 29-24 CH0SB<5:0>: Positive Input Select bits for Sample B

For 64-pin devices:

011110 = Channel 0 positive input is Open

(1)

011101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)

(2)

011100 = Channel 0 positive input is IV

REF(3)

011011 = Channel 0 positive input is AN27

•

000001 = Channel 0 positive input is AN1

000000 = Channel 0 positive input is AN0

For 100-pin devices:

110010 = Channel 0 positive input is Open

(1)

110001 = Channel 0 positive input is CTMU temperature sensor (CTMUT)

(2)

110000 = Channel 0 positive input is IV

REF(3)

101111 = Channel 0 positive input is AN47

•

0000001 = Channel 0 positive input is AN1

0000000 = Channel 0 positive input is AN0

bit 23 CH0NA: Negative Input Select bit for Sample A Multiplexer Setting

(3)

1 = Channel 0 negative input is AN1

0 = Channel 0 negative input is V

REFL

bit 22 Unimplemented: Read as ‘0’

Note 1: This selection is only used with CTMU capacitive and time measurement.

2: See Section 26.0 “Charge Time Measurement Unit (CTMU)” for more information.

3: Internal precision 1.2V reference. See Section 24.0 “Comparator” for more information.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 240  2014-2017 Microchip Technology Inc.

bit 21-16 CH0SA<5:0>: Positive Input Select bits for Sample A Multiplexer Setting

For 64-pin devices:

011110 = Channel 0 positive input is Open

(1)

011101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)

(2)

011100 = Channel 0 positive input is IV

REF(3)

011011 = Channel 0 positive input is AN27

•

000001 = Channel 0 positive input is AN1

000000 = Channel 0 positive input is AN0

For 100-pin devices:

110010 = Channel 0 positive input is Open

(1)

110001 = Channel 0 positive input is CTMU temperature sensor (CTMUT)

(2)

110000 = Channel 0 positive input is IV

REF(3)

101111 = Channel 0 positive input is AN47

•

0000001 = Channel 0 positive input is AN1

0000000 = Channel 0 positive input is AN0

bit 15-0 Unimplemented: Read as ‘0’

Note 1: This selection is only used with CTMU capacitive and time measurement.

2: See Section 26.0 “Charge Time Measurement Unit (CTMU)” for more information.

3: Internal precision 1.2V reference. See Section 24.0 “Comparator” for more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 241

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSSL31

(2)

CSSL30

(1)

CSSL29

(1)

CSSL28

(1)

CSSL27 CSSL26 CSSL25 CSSL24

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSSL23 CSSL21 CSSL21 CSSL20 CSSL19 CSSL18 CSSL17 CSSL16

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CSSL<31:0>: ADC Input Pin Scan Selection bits

1 = Select ANx for input scan; CSSLx = ANx, where ‘x’ = 0-31

0 = Skip ANx for input scan; CSSLx = ANx, where ‘x’ = 0-31

Note 1: For devices with 64 pins, CSSL28 selects IV

REF

(Band Gap) for scan; CSSL29 selects CTMU temperature

diode for scan; and CSSL30 selects CTMU input for scan

2: On devices with less than 32 analog inputs, all CSSLx bits can be selected; however, inputs selected for

scan without a corresponding input on the device will convert to V

REFL

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CSSL50

(1)

CSSL49

(1)

CSSL48

(1)

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSSL47 CSSL46 CSSL45 CSSL44 CSSL43 CSSL42 CSSL41 CSSL40

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSSL39 CSSL38 CSSL37 CSSL36 CSSL35 CSSL34 CSSL33 CSSL32

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-19 Unimplemented: Read as ‘0’

bit 18-0 CSSL<50:32>: ADC Input Pin Scan Selection bits

1 = Select ANx for input scan; CSSLx = ANx, where ‘x’ = 32-50

0 = Skip ANx for input scan; CSSLx = ANx, where ‘x’ = 32-50

Note 1: For devices with 100 or more pins, CSSL48 selects IV

REF

(Band Gap) for scan; CSSL49 selects CTMU

temperature diode for scan; and CSSL50 selects CTMU input for scan

Note: The ANx inputs in this register only support devices with 100 or more pins.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 242  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 243

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

23.0 CONTROLLER AREA

NETWORK (CAN)

The Controller Area Network (CAN) module supports

the following key features:

• Standards Compliance:

- Full CAN 2.0B compliance

- Programmable bit rate up to 1 Mbps

• Message Reception and Transmission:

- 16 message FIFOs

- Each FIFO can have up to 16 messages for a

total of 256 messages

- FIFO can be a transmit message FIFO or a

receive message FIFO

- User-defined priority levels for message

FIFOs used for transmission

- 16 acceptance filters for message filtering

- Four acceptance filter mask registers for

message filtering

- Automatic response to remote transmit request

- DeviceNet™ addressing support

• Additional Features:

- Loopback, Listen All Messages, and Listen

Only modes for self-test, system diagnostics

and bus monitoring

- Low-power operating modes

- CAN module is a bus master on the PIC32

system bus

- Use of DMA is not required

- Dedicated time-stamp timer

- Dedicated DMA channels

- Data-only Message Reception mode

Figure 23-1 illustrates the general structure of the CAN

module.

FIGU RE 23 - 1: PIC32 CA N MO D UL E BL OCK D IA GRA M

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 34. “Controller

Area Network (CAN)” (DS60001154) in

the “PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32).

Message Buffer 15

Message Buffer 1

Message Buffer 0

Message Buffer 15

Message Buffer 1

Message Buffer 0

Message Buffer 15

Message Buffer 1

Message Buffer 0

FIFO0 FIFO1 FIFO15

System RAM

Up to 16 Message Buffers

CAN Message FIFO (up to 16 FIFOs)

Message

Buffer Size

2 or 4 Words

System Bus

CPU

CAN Module

16 Filters

4 Masks

CxTX

CxRX

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 244  2014-2017 Microchip Technology Inc.

23.1 Control Registers

TABLE 23-1: CAN1 REGISTER SUMMARY

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

B000 C1CON 31:16 — — — — ABAT REQOP<2:0> OPMOD<2:0> CANCAP — — — — 0480

15:0 ON —SIDLE —CANBUSY — — — — — — DNCNT<4:0> 0000

B010 C1CFG 31:16 — — — — — — — — — WAKFIL — — — SEG2PH<2:0> 0000

15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000

B020 C1INT 31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — — — — — MODIE CTMRIE RBIE TBIE 0000

15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF — — — — — — — MODIF CTMRIF RBIF TBIF 0000

B030 C1VEC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — FILHIT<4:0> —ICODE<6:0> 0040

B040 C1TREC 31:16 — — — — — — — — — — TXBO TXBP RXBP TXWARN RXWARN EWARN 0000

15:0 TERRCNT<7:0> RERRCNT<7:0> 0000

B050 C1FSTAT 31:16 — — — — — — — — — — — — — — — — 0000

15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000

B060 C1RXOVF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000

B070 C1TMR 31:16 CANTS<15:0> 0000

15:0 CANTSPRE<15:0> 0000

B080 C1RXM0 31:16 SID<10:0> -— MIDE —EID<17:16> xxxx

15:0 EID<15:0> xxxx

B090 C1RXM1 31:16 SID<10:0> -— MIDE —EID<17:16> xxxx

15:0 EID<15:0> xxxx

B0A0 C1RXM2 31:16 SID<10:0> -— MIDE —EID<17:16> xxxx

15:0 EID<15:0> xxxx

B0B0 C1RXM3 31:16 SID<10:0> -— MIDE —EID<17:16> xxxx

15:0 EID<15:0> xxxx

B0C0 C1FLTCON0 31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000

15:0 FLTEN1 MSEL1<1:0> FSEL1<4:0> FLTEN0 MSEL0<1:0> FSEL0<4:0> 0000

B0D0 C1FLTCON1 31:16 FLTEN7 MSEL7<1:0> FSEL7<4:0> FLTEN6 MSEL6<1:0> FSEL6<4:0> 0000

15:0 FLTEN5 MSEL5<1:0> FSEL5<4:0> FLTEN4 MSEL4<1:0> FSEL4<4:0> 0000

B0E0 C1FLTCON2 31:16 FLTEN11 MSEL11<1:0> FSEL11<4:0> FLTEN10 MSEL10<1:0> FSEL10<4:0> 0000

15:0 FLTEN9 MSEL9<1:0> FSEL9<4:0> FLTEN8 MSEL8<1:0> FSEL8<4:0> 0000

B0F0 C1FLTCON3 31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000

15:0 FLTEN13 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 0000

B140 C1RXFn

(n = 0-15)

31:16 SID<10:0> -— EXID —EID<17:16> xxxx

15:0 EID<15:0> xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 245

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

B340 C1FIFOBA 31:16 C1FIFOBA<31:0> 0000

15:0 0000

B350 C1FIFOCONn

(n = 0-15)

31:16 — — — — — — — — — — — FSIZE<4:0> 0000

15:0 —FRESET UINC DONLY — — — — TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000

B360 C1FIFOINTn

(n = 0-15)

31:16 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE — — — — RXOVFLIE RXFULLIE RXHALFIE RXN

EMPTYIE 0000

15:0 — — — — — TXNFULLIF TXHALFIF TXEMPTYIF — — — — RXOVFLIF RXFULLIF RXHALFIF RXN

EMPTYIF 0000

B370 C1FIFOUAn

(n = 0-15)

31:16 C1FIFOUA<31:0> 0000

15:0 0000

B380 C1FIFOCIn

(n = 0-15)

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — C1FIFOCIn<4:0> 0000

TABLE 23-1: CAN1 REGISTER SUMMARY (CONTINUED)

Virt ual Addres s

(BF88_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

information.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 246  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 S/HC-0 R/W-1 R/W-0 R/W-0

— — — — ABAT REQOP<2:0>

23:16

R-1 R-0 R-0 R/W-0 U-0 U-0 U-0 U-0

OPMOD<2:0> CANCAP — — — —

15:8

R/W-0 U-0 R/W-0 U-0 R-0 U-0 U-0 U-0

(1)

—SIDLE — CANBUSY — — —

7:0

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DNCNT<4:0>

Legend: HC = Hardware Clear S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 Unimplemented: Read as ‘0’

bit 27 ABAT: Abort All Pending Transmissions bit

1 = Signal all transmit buffers to abort transmission

0 = Module will clear this bit when all transmissions aborted

bit 26-24 REQOP<2:0>: Request Operation Mode bits

111 = Set Listen All Messages mode

110 = Reserved

101 = Reserved

100 = Set Configuration mode

011 = Set Listen Only mode

010 = Set Loopback mode

001 = Set Disable mode

000 = Set Normal Operation mode

bit 23-21 OPMOD<2:0>: Operation Mode Status bits

111 = Module is in Listen All Messages mode

110 = Reserved

101 = Reserved

100 = Module is in Configuration mode

011 = Module is in Listen Only mode

010 = Module is in Loopback mode

001 = Module is in Disable mode

000 = Module is in Normal Operation mode

bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit

1 = CANTMR value is stored on valid message reception and is stored with the message

0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power

bit 19-16 Unimplemented: Read as ‘0’

bit 15 ON: CAN On bit

(1)

1 = CAN module is enabled

0 = CAN module is disabled

bit 14 Unimplemented: Read as ‘0’

Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the

current transaction and responds to this request. The user application should poll the CANBUSY bit to

verify that the request has been honored.

 2014-2017 Microchip Technology Inc. DS60001290E-page 247

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 13 SIDLE: CAN Stop in Idle bit

1 = CAN Stops operation when system enters Idle mode

0 = CAN continues operation when system enters Idle mode

bit 12 Unimplemented: Read as ‘0’

bit 11 CANBUSY: CAN Module is Busy bit

1 = The CAN module is active

0 = The CAN module is completely disabled

bit 10-5 Unimplemented: Read as ‘0’

bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits

10011-11111 = Invalid Selection (compare up to 18-bits of data with EID)

10010 = Compare up to data byte 2 bit 6 with EID17 (C1RXFn<17>)

•

00001 = Compare up to data byte 0 bit 7 with EID0 (C1RXFn<0>)

00000 = Do not compare data bytes

Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the

current transaction and responds to this request. The user application should poll the CANBUSY bit to

verify that the request has been honored.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 248  2014-2017 Microchip Technology Inc.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— WAKFIL — — — SEG2PH<2:0>

(1,4)

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SEG2PHTS

(1)

SAM

(2)

SEG1PH<2:0> PRSEG<2:0>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SJW<1:0>

(3)

BRP<5:0>

Legend: HC = Hardware Clear S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 Unimplemented: Read as ‘0’

bit 22 WAKFIL: CAN Bus Line Filter Enable bit

1 = Use CAN bus line filter for wake-up

0 = CAN bus line filter is not used for wake-up

bit 21-19 Unimplemented: Read as ‘0’

bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits

(1,4)

111 = Length is 8 x T

•

000 = Length is 1 x T

bit 15 SEG2PHTS: Phase Segment 2 Time Select bit

(1)

1 = Freely programmable

0 = Maximum of SEG1PH or Information Processing Time, whichever is greater

bit 14 SAM: Sample of the CAN Bus Line bit

(2)

1 = Bus line is sampled three times at the sample point

0 = Bus line is sampled once at the sample point

bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits

(4)

111 = Length is 8 x T

•

000 = Length is 1 x T

Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.

2: 3 Time bit sampling is not allowed for BRP < 2.

3: SJW  SEG2PH.

4: The Time Quanta per bit must be greater than 7 (that is, T

QBIT

> 7).

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>

(C1CON<23:21>) = 100).

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 10-8 PRSEG<2:0>: Propagation Time Segment bits

(4)

111 = Length is 8 x T

•

000 = Length is 1 x T

bit 7-6 SJW<1:0>: Synchronization Jump Width bits

(3)

11 = Length is 4 x T

10 = Length is 3 x T

01 = Length is 2 x T

00 = Length is 1 x T

bit 5-0 BRP<5:0>: Baud Rate Prescaler bits

111111 = T

= (2 x 64)/SYSCLK

111110 = T

= (2 x 63)/SYSCLK

•

000001 = T

= (2 x 2)/SYSCLK

000000 = T

= (2 x 1)/SYSCLK

Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.

2: 3 Time bit sampling is not allowed for BRP < 2.

3: SJW  SEG2PH.

4: The Time Quanta per bit must be greater than 7 (that is, T

QBIT

> 7).

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>

(C1CON<23:21>) = 100).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

IVRIE WAKIE CERRIE SERRIE RBOVIE — — —

23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

———— MODIE CTMRIE RBIE TBIE

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

IVRIF WAKIF CERRIF SERRIF

(1)

RBOVIF — — —

7:0

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

———— MODIF CTMRIF RBIF TBIF

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 IVRIE: Invalid Message Received Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 30 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 29 CERRIE: CAN Bus Error Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 28 SERRIE: System Error Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 27 RBOVIE: Receive Buffer Overflow Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 26-20 Unimplemented: Read as ‘0’

bit 19 MODIE: Mode Change Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 18 CTMRIE: CAN Timestamp Timer Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 17 RBIE: Receive Buffer Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 16 TBIE: Transmit Buffer Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 15 IVRIF: Invalid Message Received Interrupt Flag bit

1 = An invalid messages interrupt has occurred

0 = An invalid message interrupt has not occurred

Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit

(C1CON<15>).

 2014-2017 Microchip Technology Inc. DS60001290E-page 251

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit

1 = A bus wake-up activity interrupt has occurred

0 = A bus wake-up activity interrupt has not occurred

bit 13 CERRIF: CAN Bus Error Interrupt Flag bit

1 = A CAN bus error has occurred

0 = A CAN bus error has not occurred

bit 12 SERRIF: System Error Interrupt Flag bit

(1)

1 = A system error occurred (typically an illegal address was presented to the system bus)

0 = A system error has not occurred

bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit

1 = A receive buffer overflow has occurred

0 = A receive buffer overflow has not occurred

bit 10-4 Unimplemented: Read as ‘0’

bit 3 MODIF: CAN Mode Change Interrupt Flag bit

1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP)

0 = A CAN module mode change has not occurred

bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit

1 = A CAN timer (CANTMR) overflow has occurred

0 = A CAN timer (CANTMR) overflow has not occurred

bit 1 RBIF: Receive Buffer Interrupt Flag bit

1 = A receive buffer interrupt is pending

0 = A receive buffer interrupt is not pending

bit 0 TBIF: Transmit Buffer Interrupt Flag bit

1 = A transmit buffer interrupt is pending

0 = A transmit buffer interrupt is not pending

Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit

(C1CON<15>).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — —FILHIT<4:0>

7:0

U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0

— ICODE<6:0>

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as ‘0’

bit 12-8 FILHIT<4:0>: Filter Hit Number bit

11111 = Reserved

•

10000 = Reserved

01111 = Filter 15

•

00000 = Filter 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 ICODE<6:0>: Interrupt Flag Code bits

(1)

1111111 = Reserved

•

1001001 = Reserved

1001000 = Invalid message received (IVRIF)

1000111 = CAN module mode change (MODIF)

1000110 = CAN timestamp timer (CTMRIF)

1000101 = Bus bandwidth error (SERRIF)

1000100 = Address error interrupt (SERRIF)

1000011 = Receive FIFO overflow interrupt (RBOVIF)

1000010 = Wake-up interrupt (WAKIF)

1000001 = Error Interrupt (CERRIF)

1000000 = No interrupt

0111111 = Reserved

•

0010000 = Reserved

0001111 = FIFO15 Interrupt (C1FSTAT<15> set)

•

0000000 = FIFO0 Interrupt (C1FSTAT<0> set)

Note 1: These bits are only updated for enabled interrupts.

 2014-2017 Microchip Technology Inc. DS60001290E-page 253

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

—— TXBO TXBP RXBP TXWARN RXWARN EWARN

15:8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TERRCNT<7:0>

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RERRCNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-22 Unimplemented: Read as ‘0’

bit 21 TXBO: Transmitter in Error State Bus OFF (TERRCNT  256)

bit 20 TXBP: Transmitter in Error State Bus Passive (TERRCNT  128)

bit 19 RXBP: Receiver in Error State Bus Passive (RERRCNT  128)

bit 18 TXWARN: Transmitter in Error State Warning (128 > TERRCNT  96)

bit 17 RXWARN: Receiver in Error State Warning (128 > RERRCNT  96)

bit 16 EWARN: Transmitter or Receiver is in Error State Warning

bit 15-8 TERRCNT<7:0>: Transmit Error Counter

bit 7-0 RERRCNT<7:0>: Receive Error Counter

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 FIFOIP<15:0>: FIFOx Interrupt Pending bits

1 = One or more enabled FIFO interrupts are pending

0 = No FIFO interrupts are pending

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8

7:0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 RXOVF<15:0>: FIFOx Receive Overflow Interrupt Pending bit

1 = FIFO has overflowed

0 = FIFO has not overflowed

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CANTS<15:8>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CANTS<7:0>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CANTSPRE<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CANTSPRE<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CANTS<15:0>: CAN Time Stamp Timer bits

This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit

(C1CON<20>) is set.

bit 15-0 CANTSPRE<15:0>: CAN Time Stamp Timer Prescaler bits

1111 1111 1111 1111 = CAN time stamp timer (CANTS) increments every 65,535 system clocks

•

0000 0000 0000 0000 = CAN time stamp timer (CANTS) increments every system clock

Note 1: C1TMR will be paused when CANCAP = 0.

2: The C1TMR prescaler count will be reset on any write to C1TMR (CANTSPRE will be unaffected).

 2014-2017 Microchip Technology Inc. DS60001290E-page 255

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SID<10:3>

23:16

R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0

SID<2:0> —MIDE— EID<17:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EID<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EID<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 SID<10:0>: Standard Identifier bits

1 = Include the SIDx bit in filter comparison

0 = The SIDx bit is a ‘don’t care’ in filter operation

bit 20 Unimplemented: Read as ‘0’

bit 19 MIDE: Identifier Receive Mode bit

1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter

0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message

SID) or if (FILTER SID/EID) = (Message SID/EID))

bit 18 Unimplemented: Read as ‘0’

bit 17-0 EID<17:0>: Extended Identifier bits

1 = Include the EIDx bit in filter comparison

0 = The EIDx bit is a ‘don’t care’ in filter operation

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>

(C1CON<23:21>) = 100).

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Bit Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN3 MSEL3<1:0> FSEL3<4:0>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN2 MSEL2<1:0> FSEL2<4:0>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN1 MSEL1<1:0> FSEL1<4:0>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN0 MSEL0<1:0> FSEL0<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN3: Filter 3 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL3<1:0>: Filter 3 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL3<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN2: Filter 2 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL2<1:0>: Filter 2 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

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bit 20-16 FSEL2<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 15 FLTEN1: Filter 1 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL1<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN0: Filter 0 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL0<1:0>: Filter 0 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL0<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN7 MSEL7<1:0> FSEL7<4:0>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN6 MSEL6<1:0> FSEL6<4:0>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN5 MSEL5<1:0> FSEL5<4:0>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN4 MSEL4<1:0> FSEL4<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN7: Filter 7 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL7<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN6: Filter 6 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

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bit 20-16 FSEL6<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 15 FLTEN5: Filter 17 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL5<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN4: Filter 4 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL4<1:0>: Filter 4 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL4<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN11 MSEL11<1:0> FSEL11<4:0>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN10 MSEL10<1:0> FSEL10<4:0>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN9 MSEL9<1:0> FSEL9<4:0>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN8 MSEL8<1:0> FSEL8<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN11: Filter 11 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL11<1:0>: Filter 11 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL11<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN10: Filter 10 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL10<1:0>: Filter 10 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2014-2017 Microchip Technology Inc. DS60001290E-page 261

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bit 20-16 FSEL10<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 15 FLTEN9: Filter 9 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL9<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN8: Filter 8 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL8<1:0>: Filter 8 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL8<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN15 MSEL15<1:0> FSEL15<4:0>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN14 MSEL14<1:0> FSEL14<4:0>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN13 MSEL13<1:0> FSEL13<4:0>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN12 MSEL12<1:0> FSEL12<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN15: Filter 15 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL15<1:0>: Filter 15 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL15<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN14: Filter 14 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL14<1:0>: Filter 14 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2014-2017 Microchip Technology Inc. DS60001290E-page 263

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bit 20-16 FSEL14<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 15 FLTEN13: Filter 13 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL13<1:0>: Filter 13 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL13<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN12: Filter 12 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL12<1:0>: Filter 12 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL12<4:0>: FIFO Selection bits

11111 = Reserved

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID<10:3>

23:16

R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x

SID<2:0> — EXID —EID<17:16>

15:8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID<15:8>

7:0

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 SID<10:0>: Standard Identifier bits

1 = Message address bit SIDx must be ‘1’ to match filter

0 = Message address bit SIDx must be ‘0’ to match filter

bit 20 Unimplemented: Read as ‘0’

bit 19 EXID: Extended Identifier Enable bits

1 = Match only messages with extended identifier addresses

0 = Match only messages with standard identifier addresses

bit 18 Unimplemented: Read as ‘0’

bit 17-0 EID<17:0>: Extended Identifier bits

1 = Message address bit EIDx must be ‘1’ to match filter

0 = Message address bit EIDx must be ‘0’ to match filter

Note: This register can only be modified when the filter is disabled (FLTENn = 0).

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C1FIFOBA<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C1FIFOBA<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C1FIFOBA<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0

(1)

R-0

(1)

C1FIFOBA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 C1FIFOBA<31:0>: CAN FIFO Base Address bits

These bits define the base address of all message buffers. Individual message buffers are located based

on the size of the previous message buffers. This address is a physical address. Bits <1:0> are read-only

and read as ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.

Note 1: This bit is unimplemented and will always read ‘0’, which forces word-alignment of messages.

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>

(C1CON<23:21>) = 100).

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

———FSIZE<4:0>

(1)

15:8

U-0 S/HC-0 S/HC-0 R/W-0 U-0 U-0 U-0 U-0

— FRESET UINC DONLY

(1)

— — — —

7:0

R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TXEN TXABAT

(2)

TXLARB

(3)

TXERR

(3)

TXREQ RTREN TXPR<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 Unimplemented: Read as ‘0’

bit 20-16 FSIZE<4:0>: FIFO Size bits

(1)

11111 = Reserved

•

10000 = Reserved

01111 = FIFO is 16 messages deep

•

00000 = FIFO is 1 message deep

bit 15 Unimplemented: Read as ‘0’

bit 14 FRESET: FIFO Reset bits

1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should

poll whether this bit is clear before taking any action.

0 = No effect

bit 13 UINC: Increment Head/Tail bit

TXEN = 1: (FIFO configured as a Transmit FIFO)

When this bit is set the FIFO head will increment by a single message

TXEN = 0: (FIFO configured as a Receive FIFO)

When this bit is set the FIFO tail will increment by a single message

bit 12 DONLY: Store Message Data Only bit

(1)

TXEN = 1: (FIFO configured as a Transmit FIFO)

This bit is not used and has no effect.

TXEN = 0: (FIFO configured as a Receive FIFO)

1 = Only data bytes will be stored in the FIFO

0 = Full message is stored, including identifier

bit 11-8 Unimplemented: Read as ‘0’

Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits

(C1CON<23:21>) = 100).

2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.

3: This bit is reset on any read of this register or when the FIFO is reset.

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bit 7 TXEN: TX/RX Buffer Selection bit

1 = FIFO is a Transmit FIFO

0 = FIFO is a Receive FIFO

bit 6 TXABAT: Message Aborted bit

(2)

1 = Message was aborted

0 = Message completed successfully

bit 5 TXLARB: Message Lost Arbitration bit

(3)

1 = Message lost arbitration while being sent

0 = Message did not lose arbitration while being sent

bit 4 TXERR: Error Detected During Transmission bit

(3)

1 = A bus error occured while the message was being sent

0 = A bus error did not occur while the message was being sent

bit 3 TXREQ: Message Send Request

TXEN = 1: (FIFO configured as a Transmit FIFO)

Setting this bit to ‘1’ requests sending a message.

The bit will automatically clear when all the messages queued in the FIFO are successfully sent.

Clearing the bit to ‘0’ while set (‘1’) will request a message abort.

TXEN = 0: (FIFO configured as a receive FIFO)

This bit has no effect.

bit 2 RTREN: Auto RTR Enable bit

1 = When a remote transmit is received, TXREQ will be set

0 = When a remote transmit is received, TXREQ will be unaffected

bit 1-0 TXPR<1:0>: Message Transmit Priority bits

11 = Highest message priority

10 = High intermediate message priority

01 = Low intermediate message priority

00 = Lowest message priority

Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits

(C1CON<23:21>) = 100).

2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.

3: This bit is reset on any read of this register or when the FIFO is reset.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — TXNFULLIE TXHALFIE TXEMPTYIE

23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

———— RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE

15:8

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — —TXNFULLIF

(1)

TXHALFIF TXEMPTYIF

(1)

7:0

U-0 U-0 U-0 U-0 R/W-0 R-0 R-0 R-0

———— RXOVFLIF RXFULLIF

(1)

RXHALFIF

(1)

RXNEMPTYIF

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-27 Unimplemented: Read as ‘0’

bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit

1 = Interrupt enabled for FIFO not full

0 = Interrupt disabled for FIFO not full

bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit

1 = Interrupt enabled for FIFO half full

0 = Interrupt disabled for FIFO half full

bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit

1 = Interrupt enabled for FIFO empty

0 = Interrupt disabled for FIFO empty

bit 23-20 Unimplemented: Read as ‘0’

bit 19 RXOVFLIE: Overflow Interrupt Enable bit

1 = Interrupt enabled for overflow event

0 = Interrupt disabled for overflow event

bit 18 RXFULLIE: Full Interrupt Enable bit

1 = Interrupt enabled for FIFO full

0 = Interrupt disabled for FIFO full

bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit

1 = Interrupt enabled for FIFO half full

0 = Interrupt disabled for FIFO half full

bit 16 RXNEMPTYIE: Empty Interrupt Enable bit

1 = Interrupt enabled for FIFO not empty

0 = Interrupt disabled for FIFO not empty

bit 15-11 Unimplemented: Read as ‘0’

bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a transmit buffer)

1 = FIFO is not full

0 = FIFO is full

TXEN = 0: (FIFO configured as a receive buffer)

Unused, reads ‘0’

Note 1: This bit is read-only and reflects the status of the FIFO.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a transmit buffer)

1 = FIFO is  half full

0 = FIFO is > half full

TXEN = 0: (FIFO configured as a receive buffer)

Unused, reads ‘0’

bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a transmit buffer)

1 = FIFO is empty

0 = FIFO is not empty, at least 1 message queued to be transmitted

TXEN = 0: (FIFO configured as a receive buffer)

Unused, reads ‘0’

bit 7-4 Unimplemented: Read as ‘0’

bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit

TXEN = 1: (FIFO configured as a transmit buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a receive buffer)

1 = Overflow event has occurred

0 = No overflow event occured

bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a transmit buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a receive buffer)

1 = FIFO is full

0 = FIFO is not full

bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a transmit buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a receive buffer)

1 = FIFO is half full

0 = FIFO is < half full

bit 0 RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a transmit buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a receive buffer)

1 = FIFO is not empty, has at least 1 message

0 = FIFO is empty

Note 1: This bit is read-only and reflects the status of the FIFO.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R-x R-x R-x R-x R-x R-x R-x R-x

C1FIFOUAn<31:24>

23:16

R-x R-x R-x R-x R-x R-x R-x R-x

C1FIFOUAn<23:16>

15:8

R-x R-x R-x R-x R-x R-x R-x R-x

C1FIFOUAn<15:8>

7:0

R-x R-x R-x R-x R-x R-x R-0

(1)

R-0

(1)

C1FIFOUAn<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 C1FIFOUAn<31:0>: CAN FIFO User Address bits

TXEN = 1: (FIFO configured as a transmit buffer)

A read of this register will return the address where the next message is to be written (FIFO head).

TXEN = 0: (FIFO configured as a receive buffer)

A read of this register will return the address where the next message is to be read (FIFO tail).

Note 1: This bit will always read ‘0’, which forces byte-alignment of messages.

Note: This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when

the module is not in Configuration mode.

(‘n’ = 0 THROUGH 15)

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

——— C1FIFOCIn<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-5 Unimplemented: Read as ‘0’

bit 4-0 C1FIFOCIn<4:0>: CAN Side FIFO Message Index bits

TXEN = 1: (FIFO configured as a transmit buffer)

A read of this register will return an index to the message that the FIFO will next attempt to transmit.

TXEN = 0: (FIFO configured as a receive buffer)

A read of this register will return an index to the message that the FIFO will use to save the next message.

 2014-2017 Microchip Technology Inc. DS60001290E-page 271

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

24.0 COMPARATOR

The Analog Comparator module contains three

comparators that can be configured in a variety of

ways.

The following are the key features of this module:

• Selectable inputs available include:

- Analog inputs multiplexed with I/O pins

- On-chip internal absolute voltage reference

(IV

REF

)

- Comparator voltage reference (CV

REF

)

• Outputs can be inverted

• Selectable interrupt generation

A block diagram of the comparator module is provided

in Figure 24-1.

FIGU RE 24 -1 : COMPARATOR BLO C K DI AGR AM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this

data sheet, refer to Section 19.

“Comparator” (DS60001110) in the

“PI C32 Fami ly Re ferenc e Manua l” , which

is available from the Microchip web site

(www.microchip.com/PIC32).

REF(1)

REF

(1.2V)

C2IND

C2INA

C2OUT

CMP2

COE

CREF

CCH<1:0>

CPOL

C2INC

C2INB

C1IND

C1INA

C1OUT

CMP1

COE

CREF

CCH<1:0>

CPOL

C1INC

C1INB

CMSTAT<C1OUT>

CM1CON<COUT>

CMSTAT<C2OUT>

CM2CON<COUT>

To CTMU module

(Pulse Generator)

Note 1: Internally connected. See Section 25.0 “Comparator Voltage Reference (CV

REF

)” for more information.

C3IND

C3INA

C3OUT

CMP3

COE

CREF

CCH<1:0>

CPOL

C3INC

C3INB

CMSTAT<C3OUT>

CM3CON<COUT>

To ADC (Internal AN28 on 64-pin devices; Internal AN48 on 100-pin devices)

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24.1 Control Registers

TABLE 24-1: COMPARATOR REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

A000 CM1CON 31:16 ————————————————0000

15:0 ON COE CPOL ————COUT EVPOL<1:0> —CREF — — CCH<1:0> E1C3

A010 CM2CON 31:16 ————————————————0000

15:0 ON COE CPOL ————COUT EVPOL<1:0> —CREF — — CCH<1:0> E1C3

A020 CM3CON 31:16 ————————————————0000

15:0 ON COE CPOL ————COUT EVPOL<1:0> —CREF — — CCH<1:0> E1C3

A060 CMSTAT 31:16 ————————————————0000

15:0 — — SIDL ——————————C3OUT C2OUT C1OUT 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 273

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R-0

(1)

COE CPOL

(2)

— — — —COUT

7:0

R/W-1 R/W-1 U-0 R/W-0 U-0 U-0 R/W-1 R/W-1

EVPOL<1:0> —CREF—— CCH<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Comparator ON bit

(1)

1 = Module is enabled. Setting this bit does not affect the other bits in this register

0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this

bit 14 COE: Comparator Output Enable bit

1 = Comparator output is driven on the output CxOUT pin

0 = Comparator output is not driven on the output CxOUT pin

bit 13 CPOL: Comparator Output Inversion bit

(2)

1 = Output is inverted

0 = Output is not inverted

bit 12-9 Unimplemented: Read as ‘0’

bit 8 COUT: Comparator Output bit

1 = Output of the Comparator is a ‘1’

0 = Output of the Comparator is a ‘0’

bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits

11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output

10 = Comparator interrupt is generated on a high-to-low transition of the comparator output

01 = Comparator interrupt is generated on a low-to-high transition of the comparator output

00 = Comparator interrupt generation is disabled

bit 5 Unimplemented: Read as ‘0’

bit 4 CREF: Comparator Positive Input Configure bit

1 = Comparator non-inverting input is connected to the internal CV

REF

0 = Comparator non-inverting input is connected to the C

INA pin

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator

11 = Comparator inverting input is connected to the IV

REF

10 = Comparator inverting input is connected to the CxIND pin

01 = Comparator inverting input is connected to the CxINC pin

00 = Comparator inverting input is connected to the CxINB pin

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an

interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——SIDL— — — — —

7:0

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — — C3OUT C2OUT C1OUT

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in IDLE Control bit

1 = All Comparator modules are disabled in IDLE mode

0 = All Comparator modules continue to operate in the IDLE mode

bit 12-3 Unimplemented: Read as ‘0’

bit 2 C3OUT: Comparator Output bit

1 = Output of Comparator 3 is a ‘1’

0 = Output of Comparator 3 is a ‘0’

bit 1 C2OUT: Comparator Output bit

1 = Output of Comparator 2 is a ‘1’

0 = Output of Comparator 2 is a ‘0’

bit 0 C1OUT: Comparator Output bit

1 = Output of Comparator 1 is a ‘1’

0 = Output of Comparator 1 is a ‘0’

 2014-2017 Microchip Technology Inc. DS60001290E-page 275

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

25.0 COMPARATO R VOLTAGE

REFERENCE (CV

REF

)

The CV

REF

module is a 16-tap, resistor ladder network

that provides a selectable reference voltage. Although

its primary purpose is to provide a reference for the

analog comparators, it also may be used independently

of them.

A block diagram of the module is illustrated in

Figure 25-1. The resistor ladder is segmented to

provide two ranges of voltage reference values and has

a power-down function to conserve power when the

reference is not being used. The module’s supply refer-

ence can be provided from either device V

or an

external voltage reference. The CV

REF

output is avail-

able for the comparators and typically available for pin

output.

The CV

REF

module has the following features:

• High and low range selection

• Sixteen output levels available for each range

• Internally connected to comparators to conserve

device pins

• Output can be connected to a pin

FIGU RE 25-1: COMPARATOR VOLTAGE RE FERE NCE BL OCK DI AGR AM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 20. “Comparator

Voltage Reference (CV

REF

)”

(DS60001109) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

16-to-1 MUX

CVR<3:0>

CVREN

CVRSS = 0

REF

+CVRSS = 1

CVRSS = 0

REF

-CVRSS = 1

16 Steps

CVRR

REFOUT

CVRCON<CVROE>

REF

RSRC

(DAC

REFH

)

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25.1 Control Registers

TABLE 25-1: COMPARATOR VOLTAGE REFERENCE REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

9800 CVRCON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON — — — — — — — — CVROE CVRR CVRSS CVR<3:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: The register in this table has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 277

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

(1)

— — — — — — —

7:0

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— CVROE CVRR CVRSS CVR<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Comparator Voltage Reference On bit

(1)

1 = Module is enabled

Setting this bit does not affect other bits in the register.

0 = Module is disabled and does not consume current

Clearing this bit does not affect the other bits in the register.

bit 14-7 Unimplemented: Read as ‘0’

bit 6 CVROE: CV

REFOUT

Enable bit

1 = Voltage level is output on CV

REFOUT

0 = Voltage level is disconnected from CV

REFOUT

bit 5 CVRR: CV

REF

Range Selection bit

1 = 0 to 0.625 CV

RSRC

, with CV

RSRC

/24 step size

0 = 0.25 CV

RSRC

to 0.719 CV

RSRC

, with CV

RSRC

/32 step size

bit 4 CVRSS: CV

REF

Source Selection bit

1 = Comparator voltage reference source, CV

RSRC

= (V

REF

+) – (V

REF

0 = Comparator voltage reference source, CV

RSRC

= AV

– AV

bit 3-0 CVR<3:0>: CV

REF

Value Selection 0  CVR<3:0>  15 bits

When CVRR = 1:

REF

= (CVR<3:0>/24)  (CV

RSRC

)

When CVRR = 0:

REF

= 1/4  (CV

RSRC

) + (CVR<3:0>/32)  (CV

RSRC

)

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 279

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

26.0 CHARGE TIME

MEASUREMENT UNIT (CTMU)

The Charge Time Measurement Unit (CTMU) is a

flexible analog module that has a configurable current

source with a digital configuration circuit built around it.

The CTMU can be used for differential time

measurement between pulse sources and can be used

for generating an asynchronous pulse. By working with

other on-chip analog modules, the CTMU can be used

for high resolution time measurement, measure

capacitance, measure relative changes in capacitance

or generate output pulses with a specific time delay.

The CTMU is ideal for interfacing with capacitive-based

sensors.

The CTMU module includes the following key features:

• Up to 13 channels available for capacitive or time

measurement input

• On-chip precision current source

• 16-edge input trigger sources

• Selection of edge or level-sensitive inputs

• Polarity control for each edge source

• Control of edge sequence

• Control of response to edges

• High precision time measurement

• Time delay of external or internal signal asynchro-

nous to system clock

• Integrated temperature sensing diode

• Control of current source during auto-sampling

• Four current source ranges

• Time measurement resolution of one nanosecond

A block diagram of the CTMU is shown in Figure 26-1.

FIGU RE 26-1: CTMU BLOC K DIAG RAM

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 37. “Charge

Time Measurement Unit (CTMU)”

(DS60001167) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

CTED1

CTED13

Current Source

Edge

Control

Logic

CTMUCON1 or CTMUCON2

Pulse

Generator

CTMUI

Comparator 2

Timer1

OC1

Current

Control

ITRIM<5:0>

IRNG<1:0>

CTMUICON

CTMU

Control

Logic

EDG1STAT

EDG2STAT

ADC

CTPLS

IC1-IC3

CMP1-CMP2

C2INB

CDelay

CTMUT

Temperature

Sensor

Current Control Selection TGEN EDG1STAT, EDG2STAT

CTMUT

EDG1STAT = EDG2STAT

CTMUI

EDG1STAT



EDG2STAT

CTMUP

EDG1STAT



EDG2STAT

No Connect

EDG1STAT = EDG2STAT

Trigger

TGEN

CTMUP

External capacitor

for pulse generation

(To ADC S&H capacitor)

(To ADC)

PBCLK

•

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26.1 Control Registers

TABLE 26-1: CTMU REGISTER MAP

Virtual Address

(BF80_#)

Name

(1)

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

A200 CTMUCON 31:16 EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0> — — 0000

15:0 ON —CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG ITRIM<5:0> IRNG<1:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

 2014-2017 Microchip Technology Inc. DS60001290E-page 281

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

EDG2MOD EDG2POL EDG2SEL<3:0> — —

15:8

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ON —CTMUSIDLTGEN

(1)

EDGEN EDGSEQEN IDISSEN

(2)

CTTRIG

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ITRIM<5:0> IRNG<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 EDG1MOD: Edge 1 Edge Sampling Select bit

1 = Input is edge-sensitive

0 = Input is level-sensitive

bit 30 EDG1POL: Edge 1 Polarity Select bit

1 = Edge 1 programmed for a positive edge response

0 = Edge 1 programmed for a negative edge response

bit 29-26 EDG1SEL<3:0>: Edge 1 Source Select bits

1111 = IC4 Capture Event is selected

1110 = C2OUT pin is selected

1101 = C1OUT pin is selected

1100 = IC3 Capture Event is selected

1011 = IC2 Capture Event is selected

1010 = IC1 Capture Event is selected

1001 = CTED8 pin is selected

1000 = CTED7 pin is selected

0111 = CTED6 pin is selected

0110 = CTED5 pin is selected

0101 = CTED4 pin is selected

0100 = CTED3 pin is selected

0011 = CTED1 pin is selected

0010 = CTED2 pin is selected

0001 = OC1 Compare Event is selected

0000 = Timer1 Event is selected

bit 25 EDG2STAT: Edge 2 Status bit

Indicates the status of Edge 2 and can be written to control edge source

1 = Edge 2 has occurred

0 = Edge 2 has not occurred

Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to ‘1110’ to select

C2OUT.

2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion

cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor

before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC

module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor

array.

3: Refer to the CTMU Current Source Specifications (Table 31-41) in Section 31.0 “40 MHz Electrical

Characteristics” for current values.

4: This bit setting is not available for the CTMU temperature diode.

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bit 24 EDG1STAT: Edge 1 Status bit

Indicates the status of Edge 1 and can be written to control edge source

1 = Edge 1 has occurred

0 = Edge 1 has not occurred

bit 23 EDG2MOD: Edge 2 Edge Sampling Select bit

1 = Input is edge-sensitive

0 = Input is level-sensitive

bit 22 EDG2POL: Edge 2 Polarity Select bit

1 = Edge 2 programmed for a positive edge response

0 = Edge 2 programmed for a negative edge response

bit 21-18 EDG2SEL<3:0>: Edge 2 Source Select bits

1111 = IC4 Capture Event is selected

1110 = C2OUT pin is selected

1101 = C1OUT pin is selected

1100 = PBCLK clock is selected

1011 = IC3 Capture Event is selected

1010 = IC2 Capture Event is selected

1001 = IC1 Capture Event is selected

1000 = CTED13 pin is selected

0111 = CTED12 pin is selected

0110 = CTED11 pin is selected

0101 = CTED10 pin is selected

0100 = CTED9 pin is selected

0011 = CTED1 pin is selected

0010 = CTED2 pin is selected

0001 = OC1 Compare Event is selected

0000 = Timer1 Event is selected

bit 17-16 Unimplemented: Read as ‘0’

bit 15 ON: ON Enable bit

1 = Module is enabled

0 = Module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 CTMUSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 TGEN: Time Generation Enable bit

(1)

1 = Enables edge delay generation

0 = Disables edge delay generation

bit 11 EDGEN: Edge Enable bit

1 = Edges are not blocked

0 = Edges are blocked

Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to ‘1110’ to select

C2OUT.

2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion

cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor

before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC

module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor

array.

3: Refer to the CTMU Current Source Specifications (Table 31-41) in Section 31.0 “40 MHz Electrical

Characteristics” for current values.

4: This bit setting is not available for the CTMU temperature diode.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

bit 10 EDGSEQEN: Edge Sequence Enable bit

1 = Edge 1 must occur before Edge 2 can occur

0 = No edge sequence is needed

bit 9 IDISSEN: Analog Current Source Control bit

(2)

1 = Analog current source output is grounded

0 = Analog current source output is not grounded

bit 8 CTTRIG: Trigger Control bit

1 = Trigger output is enabled

0 = Trigger output is disabled

bit 7-2 ITRIM<5:0>: Current Source Trim bits

011111 = Maximum positive change from nominal current

011110

•

000001 = Minimum positive change from nominal current

000000 = Nominal current output specified by IRNG<1:0>

111111 = Minimum negative change from nominal current

•

100010

100001 = Maximum negative change from nominal current

bit 1-0 IRNG<1:0>: Current Range Select bits

(3)

11 = 100 times base current

10 = 10 times base current

01 = Base current level

00 = 1000 times base current

(4)

Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to ‘1110’ to select

C2OUT.

2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion

cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor

before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC

module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor

array.

3: Refer to the CTMU Current Source Specifications (Table 31-41) in Section 31.0 “40 MHz Electrical

Characteristics” for current values.

4: This bit setting is not available for the CTMU temperature diode.

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NOTES:

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

27.0 POWER-SAVING FEATURES

This section describes power-saving features for the

PIC32MX1XX/2XX/5XX 64/100-pin family of devices.

These PIC32 devices offer a total of nine methods

and modes, organized into two categories, that allow

the user to balance power consumption with device

performance. In all of the methods and modes

described in this section, power-saving is controlled by

software.

27.1 Power Saving with CPU Running

When the CPU is running, power consumption can be

controlled by reducing the CPU clock frequency,

lowering the PBCLK and by individually disabling

modules. These methods are grouped into the

following categories:

• FRC Run mode: the CPU is clocked from the FRC

clock source with or without postscalers.

• LPRC Run mode: the CPU is clocked from the

LPRC clock source.

•S

OSC

Run mode: the CPU is clocked from the

OSC

clock source.

In addition, the Peripheral Bus Scaling mode is available

where peripherals are clocked at the programmable

fraction of the CPU clock (SYSCLK).

27.2 CPU Halted Methods

The device supports two power-saving modes, Sleep

and Idle, both of which Halt the clock to the CPU. These

modes operate with all clock sources, as listed below:

•P

OSC

Idle mode: the system clock is derived from

the P

OSC

. The system clock source continues to

operate. Peripherals continue to operate, but can

optionally be individually disabled.

• FRC Idle mode: the system clock is derived from

the FRC with or without postscalers. Peripherals

continue to operate, but can optionally be

individually disabled.

•S

OSC

Idle mode: the system clock is derived from

the S

OSC

. Peripherals continue to operate, but

can optionally be individually disabled.

• LPRC Idle mode: the system clock is derived from

the LPRC. Peripherals continue to operate, but

can optionally be individually disabled. This is the

lowest power mode for the device with a clock

running.

• Sleep mode: the CPU, the system clock source

and any peripherals that operate from the system

clock source are Halted. Some peripherals can

operate in Sleep using specific clock sources.

This is the lowest power mode for the device.

27.3 Power-Saving Operation

Peripherals and the CPU can be Halted or disabled to

further reduce power consumption.

27.3.1 SLEEP MODE

Sleep mode has the lowest power consumption of the

device power-saving operating modes. The CPU and

most peripherals are Halted. Select peripherals can

continue to operate in Sleep mode and can be used to

wake the device from Sleep. See the individual

peripheral module sections for descriptions of

behavior in Sleep.

Sleep mode includes the following characteristics:

• The CPU is Halted.

• The system clock source is typically shutdown.

See Section 27.3.3 “Peripheral Bus Scaling

Method” for specific information.

• There can be a wake-up delay based on the

oscillator selection.

• The Fail-Safe Clock Monitor (FSCM) does not

operate during Sleep mode.

• The BOR circuit remains operative during Sleep

mode.

• The WDT, if enabled, is not automatically cleared

prior to entering Sleep mode.

• Some peripherals can continue to operate at

limited functionality in Sleep mode. These periph-

erals include I/O pins that detect a change in the

input signal, WDT, ADC, UART and peripherals

that use an external clock input or the internal

LPRC oscillator (e.g., RTCC, Timer1 and Input

Capture).

• I/O pins continue to sink or source current in the

same manner as they do when the device is not in

Sleep.

• The USB module can override the disabling of the

Posc or FRC. Refer to the USB section for

specific details.

• Modules can be individually disabled by software

prior to entering Sleep in order to further reduce

consumption.

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 10. “Power-

Saving Features” (DS60001130) in the

“PIC32 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com/PIC32).

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The processor will exit, or ‘wake-up’, from Sleep on one

of the following events:

• On any interrupt from an enabled source that is

operating in Sleep. The interrupt priority must be

greater than the current CPU priority.

• On any form of device Reset

• On a WDT time-out

If the interrupt priority is lower than or equal to the

current priority, the CPU will remain Halted, but the

PBCLK will start running and the device will enter into

Idle mode.

27.3.2 IDLE MODE

In Idle mode, the CPU is Halted but the System Clock

(SYSCLK) source is still enabled. This allows peripher-

als to continue operation when the CPU is Halted.

Peripherals can be individually configured to Halt when

entering Idle by setting their respective SIDL bit.

Latency, when exiting Idle mode, is very low due to the

CPU oscillator source remaining active.

The device enters Idle mode when the SLPEN bit

(OSCCON<4>) is clear and a WAIT instruction is

executed.

The processor will wake or exit from Idle mode on the

following events:

• On any interrupt event for which the interrupt

source is enabled. The priority of the interrupt

event must be greater than the current priority of

the CPU. If the priority of the interrupt event is

lower than or equal to current priority of the CPU,

the CPU will remain Halted and the device will

remain in Idle mode.

• On any form of device Reset

• On a WDT time-out interrupt

27.3.3 PERIPHERAL BUS SCALING

METHOD

Most of the peripherals on the device are clocked using

the PBCLK. The peripheral bus can be scaled relative to

the SYSCLK to minimize the dynamic power consumed

by the peripherals. The PBCLK divisor is controlled by

PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to

PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals

using PBCLK are affected when the divisor is changed.

Peripherals such as the USB, Interrupt Controller, DMA,

and the bus matrix are clocked directly from SYSCLK.

As a result, they are not affected by PBCLK divisor

changes.

Changing the PBCLK divisor affects:

• The CPU to peripheral access latency. The CPU

has to wait for next PBCLK edge for a read to

complete. In 1:8 mode, this results in a latency of

one to seven SYSCLKs.

• The power consumption of the peripherals. Power

consumption is directly proportional to the

frequency at which the peripherals are clocked.

The greater the divisor, the lower the power

consumed by the peripherals.

To minimize dynamic power, the PB divisor should be

chosen to run the peripherals at the lowest frequency

that provides acceptable system performance. When

selecting a PBCLK divider, peripheral clock require-

ments, such as baud rate accuracy, should be taken

into account. For example, the UART peripheral may

not be able to achieve all baud rate values at some

PBCLK divider depending on the SYSCLK value.

Note 1: Changing the PBCLK divider ratio

requires recalculation of peripheral tim-

ing. For example, assume the UART is

configured for 9600 baud with a PB clock

ratio of 1:1 and a P

OSC

of 8 MHz. When

the PB clock divisor of 1:2 is used, the

input frequency to the baud clock is cut in

half; therefore, the baud rate is reduced

to 1/2 its former value. Due to numeric

truncation in calculations (such as the

baud rate divisor), the actual baud rate

may be a tiny percentage different than

expected. For this reason, any timing cal-

culation required for a peripheral should

be performed with the new PB clock fre-

quency instead of scaling the previous

value based on a change in the PB divisor

ratio.

2: Oscillator start-up and PLL lock delays

are applied when switching to a clock

source that was disabled and that uses a

crystal and/or the PLL. For example,

assume the clock source is switched from

OSC

to LPRC just prior to entering Sleep

in order to save power. No oscillator start-

up delay would be applied when exiting

Idle. However, when switching back to

OSC

, the appropriate PLL and/or

oscillator start-up/lock delays would be

applied.

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27.4 Peripher a l Module Disable

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled using the appropriate

PMD control bit, the peripheral is in a minimum power

consumption state. The control and status registers

associated with the peripheral are also disabled, so

writes to those registers do not have effect and read

values are invalid.

To disable a peripheral, the associated PMDx bit must

be set to ‘1’. To enable a peripheral, the associated

PMDx bit must be cleared (default). See Table 27-1 for

more information.

TABLE 27-1: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS

Note: Disabling a peripheral module while it’s

ON bit is set, may result in undefined

behavior. The ON bit for the associated

peripheral module must be cleared prior to

disable a module via the PMDx bits.

Peripheral

(1)

PMDx bit Name

(1)

ADC1 AD1MD PMD1<0>

CTMU CTMUMD PMD1<8>

Comparator Voltage Reference CVRMD PMD1<12>

Comparator 1 CMP1MD PMD2<0>

Comparator 2 CMP2MD PMD2<1>

Comparator 3 CMP3MD PMD2<2>

Input Capture 1 IC1MD PMD3<0>

Input Capture 2 IC2MD PMD3<1>

Input Capture 3 IC3MD PMD3<2>

Input Capture 4 IC4MD PMD3<3>

Input Capture 5 IC5MD PMD3<4>

Output Compare 1 OC1MD PMD3<16>

Output Compare 2 OC2MD PMD3<17>

Output Compare 3 OC3MD PMD3<18>

Output Compare 4 OC4MD PMD3<19>

Output Compare 5 OC5MD PMD3<20>

Timer1 T1MD PMD4<0>

Timer2 T2MD PMD4<1>

Timer3 T3MD PMD4<2>

Timer4 T4MD PMD4<3>

Timer5 T5MD PMD4<4>

UART1 U1MD PMD5<0>

UART2 U2MD PMD5<1>

UART3 U3MD PMD5<2>

UART4 U4MD PMD5<3>

UART5 U5MD PMD5<4>

SPI1 SPI1MD PMD5<8>

SPI2 SPI2MD PMD5<9>

SPI3 SPI3MD PMD5<10>

SPI4 SPI4MD PMD5<11>

I2C1 I2C1MD PMD5<16>

I2C2 I2C2MD PMD5<17>

USB

(2)

USBMD PMD5<24>

CAN CAN1MD PMD5<28>

RTCC RTCCMD PMD6<0>

Reference Clock Output REFOMD PMD6<1>

PMP PMPMD PMD6<16>

Note 1: Not all modules and associated PMDx bits are available on all devices. See T ABLE 1: “PIC32MX1XX/2XX/5XX

64/100-pin Con troller Fa m ily Feat ur es ” for the list of available peripherals.

2: Module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit.

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27.4.1 CONTROLLING CONFIGURATION

CHANGES

Because peripherals can be disabled during run time,

some restrictions on disabling peripherals are needed

to prevent accidental configuration changes. PIC32

devices include two features to prevent alterations to

enabled or disabled peripherals:

• Control register lock sequence

• Configuration bit select lock

27.4.1.1 Control Register Lock

Under normal operation, writes to the PMDx registers

are not allowed. Attempted writes appear to execute

normally, but the contents of the registers remain

unchanged. To change these registers, they must be

unlocked in hardware. The register lock is controlled by

the PMDLOCK Configuration bit (CFGCON<12>). Set-

ting PMDLOCK prevents writes to the control registers; 

clearing PMDLOCK allows writes.

To set or clear PMDLOCK, an unlock sequence must

be executed. Refer to Section 6. “Oscillator”

(DS60001112) in the “PIC32 Family Reference

Manual” for details.

27.4.1.2 Configuration Bit Select Lock

As an additional level of safety, the device can be

configured to prevent more than one write session to

the PMDx registers. The PMDL1WAY Configuration bit

(DEVCFG3<28>) blocks the PMDLOCK bit from being

cleared after it has been set once. If PMDLOCK

remains set, the register unlock procedure does not

execute, and the peripheral pin select control registers

cannot be written to. The only way to clear the bit and

re-enable PMD functionality is to perform a device

Reset.

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TABLE 27-2: PERIPHERAL MODULE DISABLE REGISTER SUMMARY

Virt ual Addres s

(BF80_#)

Name

Bit Range

Bits

All Resets

(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

F240 PMD1 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — —CVRMD———CTMUMD— — — — — — —AD1MD0000

F250 PMD2 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————— — ————— CMP3MD CMP2MD CMP1MD 0000

F260 PMD3 31:16 — — — — — — — — — — — OC5MD OC4MD OC3MD OC2MD OC1MD 0000

15:0 — — — — — — — — — — — IC5MD IC4MD IC3MD IC2MD IC1MD 0000

F270 PMD4 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — T5MDT4MDT3MDT2MDT1MD0000

F280 PMD5 31:16 — — —CAN1MD——— USBMD

(1)

—————— I2C1MD I2C1MD 0000

15:0 ———— SPI4MD SPI3MD SPI2MD SPI1MD — — — U5MDU4MDU3MDU2MDU1MD0000

F290 PMD6 31:16 — — — — — — — — — — — — — — —PMPMD0000

15:0 ——————— — —————— REFOMD RTCCMD 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This bit is only available on devices with a USB module.

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NOTES:

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
28.0 SPECIAL FEATURES
PIC32MX1XX/2XX/5XX 64/100-pin devices include 
several features intended to maximize application 
flexibility and reliability and minimize cost through 
elimination of external components. These are:
• Flexible device configuration
• Watchdog Timer (WDT)
• Joint Test Action Group (JTAG) interface
• In-Circuit Serial Programming™ (ICSP™)
28.1 Configur ation Bits
The Configuration bits can be programmed using the 
following registers to select various device 
configurations.
•DEVCFG0: Device Configuration Word 0
•DEVCFG1: Device Configuration Word 1
•DEVCFG2: Device Configuration Word 2
•DEVCFG3: Device Configuration Word 3
•CFGCON: Configuration Control Register
In addition, the DEVID register (Register 28-6) 
provides device and revision information.
Note: This data sheet summarizes the features 
of the PIC32MX1XX/2XX/5XX 64/100-pin 
family of devices. However, it is not 
intended to be a comprehensive 
reference source. To complement the 
information in this data sheet, refer to 
Section 9. “Watchdog Timer and 
Power-up Timer” (DS60001114), Section 
32. “Configuration” (DS60001124) and 
Section 33. “Programming and 
Diagnostics” (DS60001129) in the 
“PIC32 Family Reference Manual”, which 
are available from the Microchip web site 
(www.microchip.com/PIC32).

PIC32MX1XX/2XX/5XX 64/1 00 - P IN FAM I LY

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28.2 Registers

TABLE 28-1: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY

Virtual Address

(BFC0_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

0BF0 DEVCFG3 31:16 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY ————— — — — ————xxxx

15:0 USERID<15:0> xxxx

0BF4 DEVCFG2 31:16 — — — — — — — — — — — — — FPLLODIV<2:0> xxxx

15:0

UPLLEN

(1)

— — — — UPLLIDIV<2:0>

(1)

—FPLLMUL<2:0> —FPLLIDIV<2:0> xxxx

0BF8 DEVCFG1 31:16 — — — — — — FWDTWINSZ<1:0> FWDTEN WINDIS —WDTPS<4:0> xxxx

15:0 FCKSM<1:0> FPBDIV<1:0> —OSCIOFNC POSCMOD<1:0> IESO —FSOSCEN — — FNOSC<2:0> xxxx

0BFC DEVCFG0 31:16 — — — CP — — — BWP — — — — PWP<9:6> xxxx

15:0 PWP<5:0> — — — — — — — ICESEL<1:0> JTAGEN DEBUG<1:0> xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This bit is only available on devices with a USB module.

TABLE 28-2: DEVICE AND REVISION ID SUMMARY

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

F200 CFGCON 31:16 — — — — — — — — — — — — — — ——0000

15:0 — — IOLOCK PMDLOCK — — — — — — — — JTAGEN TROEN

(2)

—TDOEN 000B

F220 DEVID 31:16 VER<3:0> DEVID<27:16> xxxx

15:0 DEVID<15:0> xxxx

F230 SYSKEY

(3)

31:16 SYSKEY<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: Reset values are dependent on the device.

2: This bit is not available on 64-pin devices.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P

— — —CP— — —BWP

23:16

r-1 r-1 r-1 r-1 R/P R/P R/P R/P

— — — —PWP<9:6>

15:8

R/P R/P R/P R/P R/P R/P r-1 r-1

PWP<5:0> — —

7:0

r-1 r-1 r-1 R/P R/P R/P R/P R/P

— — — ICESEL<1:0> JTAGEN

(1)

DEBUG<1:0>

Legend: r = Reserved bit P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: Write ‘0’

bit 30-29 Reserved: Write ‘1’

bit 28 CP: Code-Protect bit

Prevents boot and program Flash memory from being read or modified by an external pro-

gramming device.

1 = Protection is disabled

0 = Protection is enabled

bit 27-25 Reserved: Write ‘1’

bit 24 BWP: Boot Flash Write-Protect bit

Prevents boot Flash memory from being modified during code execution.

1 = Boot Flash is writable

0 = Boot Flash is not writable

bit 23-20 Reserved: Write ‘1’

Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register.

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bit 19-10 PWP<9:0>: Program Flash Write-Protect bits

Prevents selected program Flash memory pages from being modified during code execution. The PWP bits

represent the one’s compliment of the number of write protected program Flash memory pages.

1111111111 = Disabled

1111111110 = Memory below 0x0400 address is write-protected

1111111101 = Memory below 0x0800 address is write-protected

1111111100 = Memory below 0x0C00 address is write-protected

1111111011 = Memory below 0x1000 (4K) address is write-protected

1111111010 = Memory below 0x1400 address is write-protected

1111111001 = Memory below 0x1800 address is write-protected

1111111000 = Memory below 0x1C00 address is write-protected

1111110111 = Memory below 0x2000 (8K) address is write-protected

1111110110 = Memory below 0x2400 address is write-protected

1111110101 = Memory below 0x2800 address is write-protected

1111110100 = Memory below 0x2C00 address is write-protected

1111110011 = Memory below 0x3000 address is write-protected

1111110010 = Memory below 0x3400 address is write-protected

1111110001 = Memory below 0x3800 address is write-protected

1111110000 = Memory below 0x3C00 address is write-protected

1111101111 = Memory below 0x4000 (16K) address is write-protected

•

1110111111 = Memory below 0x10000 (64K) address is write-protected

•

1101111111 = Memory below 0x20000 (128K) address is write-protected

•

1011111111 = Memory below 0x40000 (256K) address is write-protected

•

0111111111 = Memory below 0x80000 (512K) address is write-protected

•

0000000000 = All possible memory is write-protected

Note: These bits are effective only if Boot Flash is also protected by clearing the BWP bit

(DEVCFG0<24>).

bit 9-5 Reserved: Write ‘1’

bit 4-3 ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits

11 = PGEC1/PGED1 pair is used

10 = PGEC2/PGED2 pair is used

01 = PGEC3/PGED3 pair is used

00 = Reserved

bit 2 JTAGEN: JTAG Enable bit

(1)

1 = JTAG is enabled

0 = JTAG is disabled

bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)

1x = Debugger is disabled

0x = Debugger is enabled

Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

r-1 r-1 r-1 r-1 r-1 r-1 R/P R/P

— — — — — — FWDTWINSZ<1:0>

23:16

R/P R/P r-1 R/P R/P R/P R/P R/P

FWDTEN WINDIS — WDTPS<4:0>

15:8

R/P R/P R/P R/P r-1 R/P R/P R/P

FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0>

7:0

R/P r-1 R/P r-1 r-1 R/P R/P R/P

IESO — FSOSCEN ——FNOSC<2:0>

Legend: r = Reserved bit P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-26 Reserved: Write ‘1’

bit 25-24 FWDTWINSZ: Watchdog Timer Window Size bits

11 = Window size is 25%

10 = Window size is 37.5%

01 = Window size is 50%

00 = Window size is 75%

bit 23 FWDTEN: Watchdog Timer Enable bit

1 = Watchdog Timer is enabled and cannot be disabled by software

0 = Watchdog Timer is not enabled; it can be enabled in software

bit 22 WINDIS: Watchdog Timer Window Enable bit

1 = Watchdog Timer is in non-Window mode

0 = Watchdog Timer is in Window mode

bit 21 Reserved: Write ‘1’

bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits

10100 = 1:1048576

10011 = 1:524288

10010 = 1:262144

10001 = 1:131072

10000 = 1:65536

01111 = 1:32768

01110 = 1:16384

01101 = 1:8192

01100 = 1:4096

01011 = 1:2048

01010 = 1:1024

01001 = 1:512

01000 = 1:256

00111 = 1:128

00110 = 1:64

00101 = 1:32

00100 = 1:16

00011 = 1:8

00010 = 1:4

00001 = 1:2

00000 = 1:1

All other combinations not shown result in operation = 10100

Note 1: Do not disable the P

OSC

(POSCMOD = 11) when using this oscillator source.

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bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits

1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled

01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits

11 = PBCLK is SYSCLK divided by 8

10 = PBCLK is SYSCLK divided by 4

01 = PBCLK is SYSCLK divided by 2

00 = PBCLK is SYSCLK divided by 1

bit 11 Reserved: Write ‘1’

bit 10 OSCIOFNC: CLKO Enable Configuration bit

1 = CLKO output disabled

0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the

External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00)

bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits

11 = Primary Oscillator disabled

10 = HS Oscillator mode selected

01 = XT Oscillator mode selected

00 = External Clock mode selected

bit 7 IESO: Internal External Switchover bit

1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)

0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)

bit 6 Reserved: Write ‘1’

bit 5 FSOSCEN: Secondary Oscillator Enable bit

1 = Enable Secondary Oscillator

0 = Disable Secondary Oscillator

bit 4-3 Reserved: Write ‘1’

bit 2-0 FNOSC<2:0>: Oscillator Selection bits

111 = Fast RC Oscillator with divide-by-N (FRCDIV)

110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (S

OSC

)

011 = Primary Oscillator (P

OSC

) with PLL module (XT+PLL, HS+PLL, EC+PLL)

010 = Primary Oscillator (XT, HS, EC)

(1)

001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)

000 = Fast RC Oscillator (FRC)

Note 1: Do not disable the P

OSC

(POSCMOD = 11) when using this oscillator source.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1

— — — — — — — —

23:16

r-1 r-1 r-1 r-1 r-1 R/P R/P R/P

— — — — — FPLLODIV<2:0>

15:8

R/P r-1 r-1 r-1 r-1 R/P R/P R/P

UPLLEN

(1)

— — — — UPLLIDIV<2:0>

(1)

7:0

r-1 R/P-1 R/P R/P-1 r-1 R/P R/P R/P

—FPLLMUL<2:0>— FPLLIDIV<2:0>

Legend: r = Reserved bit P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-19 Reserved: Write ‘1’

bit 18-16 FPLLODIV<2:0>: Default PLL Output Divisor bits

111 = PLL output divided by 256

110 = PLL output divided by 64

101 = PLL output divided by 32

100 = PLL output divided by 16

011 = PLL output divided by 8

010 = PLL output divided by 4

001 = PLL output divided by 2

000 = PLL output divided by 1

bit 15 UPLLEN: USB PLL Enable bit

(1)

1 = Disable and bypass USB PLL

0 = Enable USB PLL

bit 14-11 Reserved: Write ‘1’

bit 10-8 UPLLIDIV<2:0>: USB PLL Input Divider bits

(1)

111 = 12x divider

110 = 10x divider

101 = 6x divider

100 = 5x divider

011 = 4x divider

010 = 3x divider

001 = 2x divider

000 = 1x divider

bit 7 Reserved: Write ‘1’

bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits

111 = 24x multiplier

110 = 21x multiplier

101 = 20x multiplier

100 = 19x multiplier

011 = 18x multiplier

010 = 17x multiplier

001 = 16x multiplier

000 = 15x multiplier

bit 3 Reserved: Write ‘1’

Note 1: This bit is available on PIC32MX2XX/5XX devices only.

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bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits

111 = 12x divider

110 = 10x divider

101 = 6x divider

100 = 5x divider

011 = 4x divider

010 = 3x divider

001 = 2x divider

000 = 1x divider

Note 1: This bit is available on PIC32MX2XX/5XX devices only.

 2014-2017 Microchip Technology Inc. DS60001290E-page 299

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

R/P R/P R/P R/P U-0 U-0 U-0 U-0

FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/P R/P R/P R/P R/P R/P R/P R/P

USERID<15:8>

7:0

R/P R/P R/P R/P R/P R/P R/P R/P

USERID<7:0>

Legend: r = Reserved bit P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FVBUSONIO: USB VBUS_ON Selection bit

1 = V

BUSON

pin is controlled by the USB module

0 = V

BUSON

pin is controlled by the port function

bit 30 FUSBIDIO: USB USBID Selection bit

1 = USBID pin is controlled by the USB module

0 = USBID pin is controlled by the port function

bit 29 IOL1WAY: Peripheral Pin Select Configuration bit

1 = Allow only one reconfiguration

0 = Allow multiple reconfigurations

bit 28 PMDL1WAY: Peripheral Module Disable Configuration bit

1 = Allow only one reconfiguration

0 = Allow multiple reconfigurations

bit 27-16 Unimplemented: Read as ‘0’

bit 15-0 USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—— IOLOCK

(1)

PMDLOCK

(1)

— — — —

7:0

U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-1

— — — —JTAGEN——TDOEN

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-14 Unimplemented: Read as ‘0’

bit 13 IOLOCK: Peripheral Pin Select Lock bit

(1)

1 = Peripheral Pin Select is locked. Writes to PPS registers is not allowed

0 = Peripheral Pin Select is not locked. Writes to PPS registers is allowed

bit 12 PMDLOCK: Peripheral Module Disable bit

(1)

1 = Peripheral module is locked. Writes to PMD registers is not allowed

0 = Peripheral module is not locked. Writes to PMD registers is allowed

bit 11-4 Unimplemented: Read as ‘0’

bit 3 JTAGEN: JTAG Port Enable bit

1 = Enable the JTAG port

0 = Disable the JTAG port

bit 2-1 Unimplemented: Read as ‘0’

bit 0 TDOEN: TDO Enable for 2-Wire JTAG

1 = 2-wire JTAG protocol uses TDO

0 = 2-wire JTAG protocol does not use TDO

Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 6. “Oscillator”

(DS60001112) in the “PIC32 Family Reference Manual” for details.

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Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

RR R R R R RR

VER<3:0>

(1)

DEVID<27:24>

(1)

23:16

RR R R R R RR

DEVID<23:16>

(1)

15:8

RR R R R R RR

DEVID<15:8>

(1)

7:0

RR R R R R RR

DEVID<7:0>

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 VER<3:0>: Revision Identifier bits

(1)

bit 27-0 DEVID<27:0>: Device ID

(1)

Note 1: See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID values.

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28.3 On-Chip Voltage Regulat or

All PIC32MX1XX/2XX/5XX 64/100-pin devices’ core

and digital logic are designed to operate at a nominal

1.8V. To simplify system designs, most devices in the

PIC32MX1XX/2XX/5XX 64/100-pin family incorporate

an on-chip regulator providing the required core logic

voltage from V

A low-ESR capacitor (such as tantalum) must be

connected to the V

CAP

pin (see Figure 28-1). This

helps to maintain the stability of the regulator. The

recommended value for the filter capacitor is provided

in Section 31.1 “DC Ch arac te r is tics” .

28.3.1 HIGH VOLTAGE DETECT (HVD)

The HVD module monitors the core voltage at the V

CAP

pin. If a voltage above the required level is detected on

CAP

, the I/O pins are disabled and the device is held

in Reset as long as the HVD condition persists. See

parameter HV10 (V

HVD

) in Tabl e 31-11 in Section 31.1

“DC Characteristics” for more information.

28.3.2 ON-CHIP REGULATOR AND POR

It takes a fixed delay for the on-chip regulator to generate

an output. During this time, designated as T

, code

execution is disabled. T

is applied every time the

device resumes operation after any power-down,

including Sleep mode.

28.3.3 ON-CHIP REGULATOR AND BOR

PIC32MX1XX/2XX/5XX 64/100-pin devices also have

a simple brown-out capability. If the voltage supplied to

the regulator is inadequate to maintain a regulated

level, the regulator Reset circuitry will generate a

Brown-out Reset. This event is captured by the BOR

flag bit (RCON<1>). The brown-out voltage levels are

specific in Section 31.1 “DC Characteristics”.

FIGURE 28-1: CONNE CTIONS FOR THE

ON-CHIP REGULATOR

28.4 Programming and Diagnostics

PIC32MX1XX/2XX/5XX 64/100-pin devices provide a

complete range of programming and diagnostic fea-

tures that can increase the flexibility of any application

using them. These features allow system designers to

include:

• Simplified field programmability using two-wire 

In-Circuit Serial Programming™ (ICSP™)

interfaces

• Debugging using ICSP

• Programming and debugging capabilities using

the EJTAG extension of JTAG

• JTAG boundary scan testing for device and board

diagnostics

PIC32 devices incorporate two programming and diag-

nostic modules that provide a range of functions to the

application developer.

FIGURE 28-2: BLOCK DIAGRAM OF

PROGRAMMING,

DEBUGGING AND TRACE

PORTS

Note: It is important that the low-ESR capacitor

is placed as close as possible to the V

CAP

pin.

CAP

PIC32

EFC(2,3)

3.3V

(1)

Note 1: These are typical operating voltages. Refer to

Section 31.1 “DC Characteristics”

for the full

operating ranges of V

It is important that the low-ESR capacitor is

placed as close as possible to the V

CAP

pin.

The typical voltage on the V

CAP

pin is 1.8V.

(10 F typ)

TDI

TDO

TCK

TMS

JTAG

Controller

ICSP™

Controller

Core

JTAGEN DEBUG<1:0>

ICESEL

PGEC1

PGED1

PGEC3

PGED3

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29.0 INSTRUCTION SET

The PIC32MX1XX/2XX/5XX 64/100-pin family

instruction set complies with the MIPS32

Release 2

instruction set architecture. The PIC32 device family

does not support the following features:

• Core extend instructions

• Coprocessor 1 instructions

• Coprocessor 2 instructions

Note: Refer to “MIPS32

Architecture for

Programmers Volume II: The MIPS32

Instruction Set” at www.imgtec.com for

more information.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 305

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

30.0 DEVELOPMENT SUPPORT

The PIC

microcontrollers (MCU) and dsPIC

digital

signal controllers (DSC) are supported with a full range

of software and hardware development tools:

• Integrated Development Environment

- MPLAB

X IDE Software

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

- MPASM

Assembler

-MPLINK

Object Linker/

MPLIB

Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB X SIM Software Simulator

•Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

- PICkit™ 3

• Device Programmers

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Third-party development tools

30.1 MPLAB X Integrated Devel opment

Environment Software

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

hardware development tool that runs on Windows

Linux and Mac OS

X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

With complete project management, visual call graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multiple projects with simultaneous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

Feature-Rich Editor:

• Color syntax highlighting

• Smart code completion makes suggestions and

provides hints as you type

• Automatic code formatting based on user-defined

rules

• Live parsing

User-Friendly, Customizable Interface:

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project-Based Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Simultaneous debugging sessions

File History and Bug Tracking:

• Local file history feature

• Built-in support for Bugzilla issue tracker

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30.2 MPLAB XC Compilers

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16, and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

MPLAB XC Compilers include an assembler, linker and

utilities. The assembler generates relocatable object

files that can then be archived or linked with other relo-

catable object files and archives to create an execut-

able file. MPLAB XC Compiler uses the assembler to

produce its object file. Notable features of the assem-

bler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

30.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel

standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline 

assembly code

• Conditional assembly for multipurpose 

source files

• Directives that allow complete control over the

assembly process

30.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

30.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archived or linked with other relocatable object

files and archives to create an executable file. Notable

features of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

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30.6 MPLAB X SIM Software Simulator

The MPLAB X SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

30.7 MPLAB R E AL ICE In -Circ u it

Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

The emulator is field upgradable through future firmware

downloads in MPLAB X IDE. MPLAB REAL ICE offers

significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cables.

30.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the MPLAB

IDE.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 interface and is connected to the target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

30.9 PICkit 3 In-Circuit De bugger/

Programmer

The MPLAB PICkit 3 allows debugging and program-

ming of PIC and dsPIC Flash microcontrollers at a most

affordable price point using the powerful graphical user

interface of the MPLAB IDE. The MPLAB PICkit 3 is

connected to the design engineer’s PC using a full-

speed USB interface and can be connected to the tar-

get via a Microchip debug (RJ-11) connector (compati-

ble with MPLAB ICD 3 and MPLAB REAL ICE). The

connector uses two device I/O pins and the Reset line

to implement in-circuit debugging and In-Circuit Serial

Programming™ (ICSP™).

30.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at V

DDMIN

and V

DDMAX

for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a mod-

ular, detachable socket assembly to support various

package types. The ICSP cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices, and incorporates an MMC card for file

storage and data applications.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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30.11 Demonstration/Development

Boards, Evaluation Ki ts, and

Starter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide applica-

tion firmware and source code for examination and

modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has a line of evaluation kits and demonstra-

tion software for analog filter design, K

security

ICs, CAN, IrDA

, PowerSmart battery management,

SEEVAL

evaluation system, Sigma-Delta ADC, flow

rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

30.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companies, such as Gimpel

and Trace Systems

• Protocol Analyzers from companies, such as

Saleae and Total Phase

• Demonstration Boards from companies, such as

MikroElektronika, Digilent

and Olimex

• Embedded Ethernet Solutions from companies,

such as EZ Web Lynx, WIZnet and IPLogika

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

31.0 40 MHz ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC32MX1XX/2XX/5XX 64/100-pin Family electrical characteristics for

devices that operate at 40 MHz. Refer to Section 32.0 “50 MHz Electrical Characteristics” for additional

specifications for operations at higher frequency. Additional information will be provided in future revisions of this

document as it becomes available.

Absolute maximum ratings for the PIC32MX1XX/2XX/5XX 64/100-pin Family devices are listed below. Exposure to

these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device

at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not

implied.

Absolute Maximum Ratings

(See Note 1)

Ambient temperature under bias.............................................................................................................-40°C to +105°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on V

with respect to V

......................................................................................................... -0.3V to +4.0V

Voltage on any pin that is not 5V tolerant, with respect to V

(Note 3)......................................... -0.3V to (V

+ 0.3V)

Voltage on any 5V tolerant pin with respect to V

when V

 2.3V (Note 3)........................................ -0.3V to +5.5V

Voltage on any 5V tolerant pin with respect to V

when V

< 2.3V (Note 3)........................................ -0.3V to +3.6V

Voltage on D+ or D- pin with respect to V

USB

.................................................................... -0.3V to (V

USB

+ 0.3V)

Voltage on V

BUS

with respect to V

....................................................................................................... -0.3V to +5.5V

Maximum current out of V

pin(s) .......................................................................................................................300 mA

Maximum current into V

pin(s) (Note 2)............................................................................................................300 mA

Maximum output current sunk by any I/O pin..........................................................................................................15 mA

Maximum output current sourced by any I/O pin ....................................................................................................15 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports (Note 2)....................................................................................................200 mA

Note 1: Stresses above those listed under “Absolute Ma ximum Rating s” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions,

above those indicated in the operation listings of this specification, is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

2: Maximum allowable current is a function of device maximum power dissipation (see Tab l e 31-2).

3: See the “Device Pin Tables” section for the 5V tolerant pins.

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31.1 DC Characteristics

TABLE 31-1: OPERATING MIPS VS. VOLTAGE

Characteristic V

Range

(in Volts)

(1)

Temp. Range

(in °C)

Max. Frequency

PIC32MX1XX/2XX/5XX 64/100-pin

Family

DC5 V

BOR

-3.6V -40°C to +105°C 40 MHz

Note 1: Overall functional device operation at V

BORMIN

< V

DDMIN

is tested, but not characterized. All device

Analog modules, such as ADC, etc., will function, but with degraded performance below V

DDMIN

. Refer to

parameter BO10 in Table 31-10 for BOR values.

TABLE 31-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typical Max. Unit

Industrial Temperature Devices

Operating Junction Temperature Range T

-40 —+125 °C

Operating Ambient Temperature Range T

-40 —+85 °C

V-temp Temperature Devices

Operating Junction Temperature Range T

-40 —+140 °C

Operating Ambient Temperature Range T

-40 —+105 °C

Power Dissipation:

Internal Chip Power Dissipation:

INT

= V

x (I

– S I

) P

INT

+ P

I/O Pin Power Dissipation:

I/O = S (({V

– V

} x I

) + S (V

x I

))

Maximum Allowed Power Dissipation P

DMAX

– T

)/

TABLE 31-3: THER MAL PACKAGING CHARACTERISTICS

Characteristics Symbol Typical Max. Unit Notes

Package Thermal Resistance, 64-pin QFN 

28 —°C/W 1

Package Thermal Resistance, 64-pin TQFP, 10 mm x 10 mm 

55 —°C/W 1

Package Thermal Resistance, 100-pin TQFP, 12 mm x 12 mm 

52 —°C/W 1

Package Thermal Resistance, 100-pin TQFP, 14 mm x 14 mm 

50 —°C/W 1

Note 1: Junction to ambient thermal resistance, Theta-

(

) numbers are achieved by package simulations.

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TABLE 31-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typ. Max. Units Conditions

Operating Voltage

DC10 V

Supply Voltage (Note 2) 2.3 — 3.6 V —

DC12 V

RAM Data Retention Voltage 

(Note 1) 1.75 — — V —

DC16 V

POR

Start Voltage

to Ensure Internal Power-on Reset

Signal

1.75 — 2.1 V —

DC17 SV

Rise Rate

to Ensure Internal Power-on Reset

Signal

0.00005 — 0.115 V/s—

Note 1: This is the limit to which V

can be lowered without losing RAM data.

2: Overall functional device operation at V

BORMIN

< V

DDMIN

is tested, but not characterized. All device

Analog modules, such as ADC, etc., will function, but with degraded performance below V

DDMIN

. Refer to

parameter BO10 in Table 31-10 for BOR values.

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TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (I

)

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Parameter

No. Typical

(3)

Max. Units Conditions

Operating Current (I

) (Notes 1, 2, 5)

DC20 2 8 mA 4 MHz (Note 4)

DC21 713 mA 10 MHz

DC22 10 18 mA 20 MHz (Note 4)

DC23 15 25 mA 30 MHz (Note 4)

DC24 20 32 mA 40 MHz

DC25 180 250 µA +25ºC, 3.3V LPRC (31 kHz) (Note 4)

Note 1: A device’s I

supply current is mainly a function of the operating voltage and frequency. Other factors,

such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code

execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,

oscillator type, as well as temperature, can have an impact on the current consumption.

2: The test conditions for I

measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by

external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin

• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8

• CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1

• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared

• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled

• All I/O pins are configured as inputs and pulled to V

•MCLR

= V

• CPU executing while(1) statement from Flash

• RTCC and JTAG are disabled

3: Data in the “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.

Parameters are for design guidance only and are not tested.

4: This parameter is characterized, but not tested in manufacturing.

5: I

electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.

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TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (I

IDLE

)

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Parameter

No. Typical

(2)

Max. Units Conditions

Idle Current (I

IDLE

): Core Off, Clock on Base Current (Notes 1, 4)

DC30a 1.5 5 mA 4 MHz (Note 3)

DC31a 3 8 mA 10 MHz

DC32a 5 12 mA 20 MHz (Note 3)

DC33a 6.5 15 mA 30 MHz (Note 3)

DC34a 8 20 mA 40 MHz

DC37a 75 100 µA -40°C

3.3V

LPRC (31 kHz)

(Note 3)

DC37b 180 250 µA +25°C

DC37c 280 380 µA +85°C

Note 1: The test conditions for I

IDLE

current measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by

external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin

• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8

• CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1

• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared

• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled

• All I/O pins are configured as inputs and pulled to V

•MCLR = V

• RTCC and JTAG are disabled

2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

3: This parameter is characterized, but not tested in manufacturing.

4: I

IDLE

electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.

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TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I

)

DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Typical

(2)

Max. Units Conditions

Power-Down Current (I

) (Notes 1, 5)

DC40k 33 78 A-40°C

Base Power-Down Current

DC40l 49 78 A +25°C

DC40n 281 450 A +85°C

DC40m 559 895 µA +105ºC

Module Differential Current

DC41e 10 25 A 3.6V Watchdog Timer Current: I

WDT

(Note 3)

DC42e 29 50 A 3.6V RTCC + Timer1 w/32 kHz Crystal: I

RTCC

(Note 3)

DC43d 1000 1300 A 3.6V ADC: I

ADC

(Notes 3,4)

Note 1: The test conditions for I

current measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by

external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin

• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8

• CPU is in Sleep mode, and SRAM data memory Wait states = 1

• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set

• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled

• All I/O pins are configured as inputs and pulled to V

•MCLR = V

• RTCC and JTAG are disabled

2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

3: The  current is the additional current consumed when the module is enabled. This current should be

added to the base I

current.

4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.

5: I

electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.

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TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise

stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typical

(1)

Max. Units Conditions

Input Low Voltage

DI10 I/O Pins with PMP V

— 0.15 V

I/O Pins V

— 0.2 V

DI18 SDAx, SCLx V

— 0.3 V

V SMBus disabled 

(Note 4)

DI19 SDAx, SCLx V

— 0.8 V SMBus enabled 

(Note 4)

Input High Voltage

DI20 I/O Pins not 5V-tolerant

(5)

0.65 V

—V

V(No te 4,6)

I/O Pins 5V-tolerant with

PMP

(5)

0.25 V

+ 0.8V — 5.5 V (Note 4,6)

I/O Pins 5V-tolerant

(5)

0.65 V

—5.5V

DI28 SDAx, SCLx 0.65 V

— 5.5 V SMBus disabled 

(No te 4,6)

DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled, 

2.3V  V

 5.5 

(No te 4,6)

DI30 I

CNPU

Change Notification 

Pull-up Current — -200 -50 AV

= 3.3V, V

= V

(No te 3,6)

DI31 I

CNPD

Change Notification 

Pull-down Current

(4)

50 200 — µA V

= 3.3V, V

= V

Input Leak age Current

(Note 3)

DI50 I/O Ports — — +1AV

 V

,

Pin at high-impedance

DI51 Analog Input Pins — — +1AV

 V

,

Pin at high-impedance

DI55 MCLR

(2)

——+1AV

 V

DI56 OSC1 — — +1AV

 V

V

, 

XT and HS modes

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: This parameter is characterized, but not tested in manufacturing.

5: See the “Device Pin Tables” section for the 5V-tolerant pins.

6: The V

specifications are only in relation to externally applied inputs, and not with respect to the user-

selectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32

device are guaranteed to be recognized only as a logic “high” internally to the PIC32 device, provided that

the external load does not exceed the minimum value of I

CNPU

. For External “input” logic inputs that require

a pull-up source, to guarantee the minimum V

of those components, it is recommended to use an

external pull-up resistor rather than the internal pull-ups of the PIC32 device.

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TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param. Symbol Characteristic Min. Typ. Max. Units Conditions

DO10 V

Output Low Voltage

I/O Pins:

4x Sink Driver Pins - All I/O

output pins not defined as 8x

Sink Driver pins

——0.4V I

 9 mA, V

= 3.3V

Output Low Voltage

I/O Pins:

8x Sink Driver Pins - RB14,

RC15, RD2, RD10, RD15, RF6,

RF13, RG6

——0.4VI

 15 mA, V

= 3.3V

DO20 V

Output High Voltage

I/O Pins:

4x Source Driver Pins - All I/O

output pins not defined as 8x

Source Driver pins

2.4 — — V I

 -10 mA, V

= 3.3V

Output High Voltage

I/O Pins:

8x Source Driver Pins - RB14,

RC15, RD2, RD10, RD15, RF6,

RF13, RG6

2.4 — — V I

 -15 mA, V

= 3.3V

DO20A V

Output High Voltage

I/O Pins:

4x Source Driver Pins - All I/O

output pins not defined as 8x

Sink Driver pins

1.5

(1)

——

 -14 mA, V

= 3.3V

2.0

(1)

—— I

 -12 mA, V

= 3.3V

3.0

(1)

—— I

 -7 mA, V

= 3.3V

Output High Voltage

I/O Pins:

8x Source Driver Pins - RB14,

RC15, RD2, RD10, RD15, RF6,

RF13, RG6

1.5

(1)

——

 -22 mA, V

= 3.3V

2.0

(1)

—— I

 -18 mA, V

= 3.3V

3.0

(1)

—— I

 -10 mA, V

= 3.3V

Note 1:

Parameters are characterized, but not tested.

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TABLE 31-10: ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwis e stated )

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min.

(1)

Typical Max. Units Conditions

BO10 V

BOR

BOR Event on V

transition

high-to-low

(2)

2.0 — 2.3 V —

Note 1:

Parameters are for design guidance only and are not tested in manufacturing.

Overall functional device operation at V

BORMIN

< V

DDMIN

is tested, but not characterized. All device

Analog modules, such as ADC, etc., will function, but with degraded performance below V

DDMIN

TABLE 31-11: ELECTRICAL CHARACTERISTICS: HVD

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwis e stated )

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No.

(1)

Symbol Characteristics Min. Typical Max. Units Conditions

HV10 V

HVD

High Voltage Detect on V

CAP

—2.5 — V —

Note 1:

Parameters are for design guidance only and are not tested in manufacturing.

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TABLE 31-12: DC CHARACTERISTICS: PROGRAM MEMORY

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typical

(1)

Max. Units Conditions

Program Flash Memory

(3)

D130 E

Cell Endurance 20,000 — — E/W —

D131 V

for Read 2.3 — 3.6 V —

D132 V

PEW

for Erase or Write 2.3 — 3.6 V —

D134 T

RETD

Characteristic Retention 20 — — Year Provided no other

specifications are

violated

D135 I

DDP

Supply Current during

Programming

—10 — mA —

Word Write Cycle Time — 411 — FRC Cycles See

Note 4

D136 T

Row Write Cycle Time — 6675 — FRC Cycles See

Note 2,4

D137 T

Page Erase Cycle Time — 20011 — FRC Cycles See

Note 4

Chip Erase Cycle Time — 80180 — FRC Cycles See

Note 4

Note 1:

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities

during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus

loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The

default Arbitration mode is mode 1 (CPU has lowest priority).

Refer to the “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during

programming and erase cycles.

This parameter depends on FRC accuracy (See Table 31-19) and FRC tuning values (See Register 8-2).

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TABLE 31-13: COMPARATOR SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions (see Note 4): 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typ. Max. Units Comments

D300 V

IOFF

Input Offset Voltage — ±7.5 ±25 mV AV

= V

,

= V

D301 V

ICM(2)

Input Common Mode Voltage 0 — V

VAV

= V

,

= V

D302 CMRR

(2)

Common Mode Rejection Ratio 55 — — dB Max V

ICM

= (V

- 1)V

D303 T

RESP(1,2)

Response Time — 150 400 ns AV

= V

,

= V

D304 ON2

OV(2)

Comparator Enabled to Output

Valid

——10s Comparator module is

configured before setting

the comparator ON bit

D305 IV

REF

Internal Voltage Reference 1.14 1.2 1.26 V —

Note 1:

Response time measured with one comparator input at (V

– 1.5)/2, while the other input transitions 

from V

to V

These parameters are characterized but not tested.

Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter

is characterized, but not tested in manufacturing.

The Comparator module is functional at V

BORMIN

< V

DDMIN

, but with degraded performance. Unless

otherwise stated, module functionality is tested, but not characterized.

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TABLE 31-14: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typ. Max. Units Comments

D312 T

SET

Internal 4-bit DAC

Comparator Reference

Settling time.

— — 10 µs See

Note 1

D313 DAC

REFH

REF

Input Voltage

Reference Range

—AV

VCV

RSRC

with CVRSS = 0

REF

-— V

REF

+VCV

RSRC

with CVRSS = 1

D314 DV

REF

Programmable

Output Range

0 — 0.625 x

DAC

REFH

V 0 to 0.625 DAC

REFH

with

DAC

REFH

/24 step size

0.25 x

DAC

REFH

— 0.719 x

DAC

REFH

V0.25 x DAC

REFH

to 0.719

DAC

REFH

with DAC

REFH

32 step size

D315 DAC

RES

Resolution — — DAC

REFH

/24 CVRCON<CVRR> = 1

——DAC

REFH

/32 CVRCON<CVRR> = 0

D316 DAC

ACC

Absolute Accuracy

(2)

—— 1/4LSBDAC

REFH

/24,

CVRCON<CVRR> = 1

—— 1/2LSBDAC

REFH

/32,

CVRCON<CVRR> = 0

Note 1:

Settling time was measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This param-

eter is characterized, but is not tested in manufacturing.

These parameters are characterized but not tested.

TABLE 31-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwis e stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typical Max. Units Comments

D321 C

EFC

External Filter Capacitor Value 810 —FCapacitor must be low series

resistance ( 3 ohm). Typical

voltage on the V

CAP

pin is

1.8V.

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31.2 AC Characteristics and Timing

Parameters

The information contained in this section defines

PIC32MX1XX/2XX/5XX 64/100-pin AC characteristics

and timing parameters.

FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

FIGURE 31-2: EX TER NAL CLOCK TIMING

=464

= 50 pF for all pins

50 pF for OSC2 pin (EC mode)

Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2

TABLE 31-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typical

(1)

Max. Units Conditions

DO50 C

OSCO

OSC2 pin — — 15 pF

In XT and HS modes when an

external crystal is used to drive

OSC1

DO50a C

SOSC

SOSCI/SOSCO pins —33 —pF Epson P/N: MC-306 32.7680K-

A0:ROHS

DO56 C

All I/O pins and OSC2 — — 50 pF EC mode

DO58 C

SCLx, SDAx — — 400 pF In I

C mode

Note 1:

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

OSC1

OS20 OS30

OS30

OS31

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TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typical

(1)

Max. Units Conditions

OS10 F

OSC

External CLKI Frequency

(External clocks allowed only

in EC and ECPLL modes)

—

MHz

(Note 4)



ECPLL

(Note 3)

OS11 Oscillator Crystal Frequency 3 — 10 MHz XT

(Note 4)

OS12 4 — 10 MHz XTPLL

(Notes 3,4)

OS13 10 — 25 MHz HS

(Note 5)

OS14 10 — 25 MHz HSPLL

(Notes 3,4)

OS15 32 32.768 100 kHz S

OSC

(Note 4)

OS20 T

OSC

= 1/F

OSC

= T

(Note 2)

— — — — See parameter

OS10 for F

OSC

value

OS30 T

External Clock

In (OSC1)

High or Low Time

0.45 x T

OSC

——nsEC

(Note 4)

OS31 T

External Clock

In (OSC1)

Rise or Fall Time

— — 0.05 x T

OSC

ns EC

(Note 4)

OS40 T

OST

Oscillator Start-up Timer Period

(Only applies to HS, HSPLL,

XT, XTPLL and S

OSC

Clock

Oscillator modes)

— 1024 — T

OSC

(Note 4)

OS41 T

FSCM

Primary Clock Fail Safe 

Time-out Period

—2—ms

(Note 4)

OS42 G

External Oscillator

Transconductance (Primary

Oscillator only)

—12—mA/VV

= 3.3V,

= +25°C

(Note 4)

Note 1:

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not

tested.

Instruction cycle period (T

) equals the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device

executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min.” values with an

external clock applied to the OSC1/CLKI pin.

PLL input requirements: 4 MH

 F

PLLIN

 5 MH

(use PLL prescaler to reduce F

OSC

). This parameter is

characterized, but tested at 10 MHz only at manufacturing.

This parameter is characterized, but not tested in manufacturing.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V



(unless otherwis e st ated )

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typical Max. Units Conditions

OS50 F

PLLI

PLL Voltage Controlled 

Oscillator (VCO) Input 

Frequency Range

3.92 — 5 MHz ECPLL, HSPLL, XTPLL,

FRCPLL modes

OS51 F

SYS

On-Chip VCO System 

Frequency

60 — 120 MHz —

OS52 T

LOCK

PLL Start-up Time (Lock Time) — — 2 ms —

OS53 D

CLK

CLKO Stability

(2)

(Period Jitter or Cumulative)

-0.25 — +0.25 % Measured over 100 ms

period

Note 1:

These parameters are characterized, but not tested in manufacturing.

This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for

individual time-bases on communication clocks, use the following formula:

For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:

EffectiveJitter D

CLK

SYSCLK

CommunicationClock

----------------------------------------------------------

--------------------------------------------------------------

EffectiveJitter D

CLK

------

--------------D

CLK

1.41

--------------

TABLE 31-19: INTERNAL FRC ACCURACY

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V



(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Characteristics Min. Typical Max. Units Conditions

Internal FRC Accur acy @ 8.00 MHz

(1)

F20a FRC -0.9 —+0.9 %-40°C  T

 +85°C

F20b FRC -2 —+2 %-40°C  T

 +105°C

Note 1:

Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.

TABLE 31-20: INTERNAL LPRC ACCURACY

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V



(unless otherwis e stated )

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Characteristics Min. Typical Max. Units Conditions

LPRC @ 31.25 kHz

(1)

F21 LPRC -15 —+15 % —

Note 1:

Change of LPRC frequency as V

changes.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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FIGURE 31-3: I/O TIMING CHARACTERISTICS

Note:

Refer to Figure 31-1 for load conditions.

I/O Pin

(Input)

I/O Pin

(Output)

DI35

DI40

DO31

DO32

TABLE 31-21: I/O TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwis e stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(2)

Min. Typical

(1)

Max. Units Conditions

DO31 T

RPort Output Rise Time — 5 15 ns V

< 2.5V

— 5 10 ns V

> 2.5V

DO32 T

FPort Output Fall Time — 5 15 ns V

< 2.5V

— 5 10 ns V

> 2.5V

DI35 T

INP

INTx Pin High or Low Time 10 — — ns —

DI40 T

RBP

CNx High or Low Time (input) 2 — — T

SYSCLK

—

Note 1:

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

This parameter is characterized, but not tested in manufacturing.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS

POR

Note 1:

The power-up period will be extended if the power-up sequence completes before the device exits from BOR

< V

DDMIN

Includes interval voltage regulator stabilization delay.

SY00

Power-up Sequence

(Note 2)

Internal Voltage Regulator Enabled

)

SY10 CPU Starts Fetching Code

Clock Sources = (HS, HSPLL, XT, XTPLL and S

OSC

)

POR

SY00

Power-up Sequence

(Note 2)

Internal Voltage Regulator Enabled

)

SYSDLY

)

CPU Starts Fetching Code

(Note 1)

Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)

OST

)

SY02

SYSDLY

)

SY02

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FIGURE 31-5: EXTERNAL RESET TIMING CHARACTERISTICS

TABLE 31-22: RESETS TIMING

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typical

(2)

Max. Units Conditions

SY00 T

Power-up Period

Internal Voltage Regulator Enabled

—400 600 s—

SY02 T

SYSDLY

System Delay Period:

Time Required to Reload Device

Configuration Fuses plus SYSCLK

Delay before First instruction is

Fetched.

—s +

8 SYSCLK

cycles

— — —

SY20 T

MCLR

MCLR Pulse Width (low) 2 — — s—

SY30 T

BOR

BOR Pulse Width (low) — 1 — s —

Note 1:

These parameters are characterized, but not tested in manufacturing.

Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.

MCLR

(SY20)

Reset Sequence

(SY10)

CPU Starts Fetching Code

BOR

(SY30)

OST

MCLR

BOR

Reset Sequence

CPU Starts Fetching Code

Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)

Clock Sources = (HS, HSPLL, XT, XTPLL and S

OSC

)

SYSDLY

)

SY02

SYSDLY

)

SY02

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 31-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS

Note:

Refer to Figure 31-1 for load conditions.

Tx11

Tx15

Tx10

Tx20

TMRx

OS60

TxCK

TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

(1)

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwis e st ated )

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(2)

Min. Typical Max. Units Conditions

TA10 T

HTxCK

High Time

Synchronous,

with prescaler

[(12.5 ns or 1 T

)/N]

+ 25 ns

— — ns Must also meet

parameter TA15

Asynchronous,

with prescaler

10 — — ns —

TA11 T

LTxCK

Low Time

Synchronous,

with prescaler

[(12.5 ns or 1 T

)/N]

+ 25 ns

— — ns Must also meet

parameter TA15

Asynchronous,

with prescaler

10 — — ns —

TA15 T

PTxCK

Input Period

Synchronous,

with prescaler

[(Greater of 25 ns or

2 T

)/N] + 30 ns

— — ns V

> 2.7V

[(Greater of 25 ns or

2 T

)/N] + 50 ns

— — ns V

< 2.7V

Asynchronous,

with prescaler

20 — — ns V

> 2.7V

(Note 3)

50 — — ns V

< 2.7V

(Note 3)

OS60 F

1SOSC1/T1CK Oscillator

Input Frequency Range

(oscillator enabled by setting

the TCS (T1CON<1>) bit)

32 —100 kHz —

TA20 T

CKEXTMRL

Delay from External TxCK

Clock Edge to Timer 

Increment

— 1 T

—

Note 1:

Timer1 is a Type A timer.

This parameter is characterized, but not tested in manufacturing.

N = Prescale Value (1, 8, 64, 256).

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FIGURE 31-7: INP UT CAPTURE (CAPx) TIMING CHARACTERISTICS

TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHAR ACTE RISTI CS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Max. Units Conditions

TB10 T

HTxCK

High Time

Synchronous, with

prescaler

[(12.5 ns or 1 T

)/N]

+ 25 ns

— ns Must also meet

parameter

TB15

N = prescale

value 

(1, 2, 4, 8,

16, 32, 64,

256)

TB11 T

LTxCK

Low Time

Synchronous, with

prescaler

[(12.5 ns or 1 T

)/N]

+ 25 ns

— ns Must also meet

parameter

TB15

TB15 T

PTxCK

Input

Period

Synchronous, with

prescaler

[(Greater of [(25 ns or

2 T

)/N] + 30 ns

—nsV

> 2.7V

[(Greater of [(25 ns or

2 T

)/N] + 50 ns

—nsV

< 2.7V

TB20 T

CKEXTMRL

Delay from External TxCK

Clock Edge to Timer Increment

—1T

—

Note 1:

These parameters are characterized, but not tested in manufacturing.

ICx

IC10 IC11

IC15

Note:

Refer to Figure 31-1 for load conditions.

TABLE 31-25: INPUT CAPTURE MODULE TIMING REQUIRE MENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Max. Units Conditions

IC10 T

LICx Input Low Time [(12.5 ns or 1 T

)/N]

+ 25 ns

—ns Must also

meet

parameter

IC15.

N = prescale

value (1, 4, 16)

IC11 T

HICx Input High Time [(12.5 ns or 1 T

)/N]

+ 25 ns

—ns Must also

meet

parameter

IC15.

IC15 T

PICx Input Period [(25 ns or 2 T

)/N]

+ 50 ns

—ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 31-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

FIGURE 31-9: OCx/PWM MODULE TIMING CHARACTERISTICS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typical

(2)

Max. Units Conditions

OC10 T

FOCx Output Fall Time — — — ns See parameter DO32

OC11 T

ROCx Output Rise Time — — — ns See parameter DO31

Note 1:

These parameters are characterized, but not tested in manufacturing.

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

OCx

OC11 OC10

(Output Compare

Note:

Refer to Figure 31-1 for load conditions.

or PWM mode)

OCFA/OCFB

OCx

OC20

OC15

Note:

Refer to Figure 31-1 for load conditions.

OCx is tri-stated

TABLE 31-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param

No. Symbol Characteristics

(1)

Min Typical

(2)

Max Units Conditions

OC15 T

Fault Input to PWM I/O Change — — 50 ns —

OC20 T

FLT

Fault Input Pulse Width 50 — — ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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FIGURE 31-10 : SPIx MO DULE MAS TER MO DE (CKE = 0) TIMING CHARACTERISTICS

TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREM ENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typical

(2)

Max. Units Conditions

SP10 T

LSCKx Output Low Time



(Note 3)

SCK

/2 — — ns —

SP11 T

HSCKx Output High Time



(Note 3)

SCK

/2 — — ns —

SP20 T

FSCKx Output Fall Time



(Note 4)

— — — ns See parameter DO32

SP21 T

RSCKx Output Rise Time



(Note 4)

—— — ns See parameter DO31

SP30 T

FSDOx Data Output Fall Time



(Note 4)

—— — ns See parameter DO32

SP31 T

RSDOx Data Output Rise Time



(Note 4)

—— — ns See parameter DO31

SP35 T

V,

SDOx Data Output Valid after

SCKx Edge

— — 15 ns V

> 2.7V

— — 20 ns V

< 2.7V

SP40 T

H,

Setup Time of SDIx Data Input

to SCKx Edge

10 — — ns —

SP41 T

L,

Hold Time of SDIx Data Input

to SCKx Edge

10 — — ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not

violate this specification.

Assumes 50 pF load on all SPIx pins.

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP11 SP10

SP40 SP41

SP21

SP20

SP35

SP20

SP21

MSb LSb

Bit 14 - - - - - -1

MSb In LSb In

Bit 14 - - - -1

SP30

SP31

Note:

Refer to Figure 31-1 for load conditions.

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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS

TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIM ING REQUI REMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwis e stated )

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typ.

(2)

Max. Units Conditions

SP10 T

LSCKx Output Low Time

(Note 3)

SCK

/2 — — ns —

SP11 T

HSCKx Output High Time

(Note 3)

SCK

/2 — — ns —

SP20 T

FSCKx Output Fall Time

(Note 4)

— — — ns See parameter DO32

SP21 T

RSCKx Output Rise Time

(Note 4)

— — — ns See parameter DO31

SP30 T

FSDOx Data Output Fall Time



(Note 4)

— — — ns See parameter DO32

SP31 T

RSDOx Data Output Rise Time



(Note 4)

— — — ns See parameter DO31

SP35 T

SDOx Data Output Valid after

SCKx Edge

— — 15 ns V

> 2.7V

— — 20 ns V

< 2.7V

SP36 T

SDOx Data Output Setup to

First SCKx Edge

15 — — ns —

SP40 T

Setup Time of SDIx Data Input to

SCKx Edge

15 — — ns V

> 2.7V

20 — — ns V

< 2.7V

SP41 T

Hold Time of SDIx Data Input

to SCKx Edge

15 — — ns V

> 2.7V

20 — — ns V

< 2.7V

Note 1:

These parameters are characterized, but not tested in manufacturing.

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not

violate this specification.

Assumes 50 pF load on all SPIx pins.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SP36

SP30,SP31

SP35

MSb Bit 14 - - - - - -1

LSb In

Bit 14 - - - -1

LSb

Note:

Refer to Figure 31-1 for load conditions.

SP11 SP10

SP21

SP20

SP40 SP41

SP20

SP21

MSb In

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FIGURE 31-12 : SPI x MODUL E SLAV E MOD E (CKE = 0) TIMING CHARACTERISTICS

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SP50

SP40 SP41

SP30,SP31 SP51

SP35

MSb LSb

Bit 14 - - - - - -1

Bit 14 - - - -1 LSb In

SP52

SP73

SP72

SP73

SP71 SP70

Note:

Refer to Figure 31-1 for load conditions.

SDI

MSb In

TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typ.

(2)

Max. Units Conditions

SP70 T

LSCKx Input Low Time

(Note 3)

SCK

/2 — — ns —

SP71 T

HSCKx Input High Time

(Note 3)

SCK

/2 — — ns —

SP72 T

FSCKx Input Fall Time — — — ns See parameter DO32

SP73 T

RSCKx Input Rise Time — — — ns See parameter DO31

SP30 T

FSDOx Data Output Fall Time

(Note 4)

— — — ns See parameter DO32

SP31 T

RSDOx Data Output Rise Time

(Note 4)

— — — ns See parameter DO31

SP35 T

SDOx Data Output Valid after

SCKx Edge

— — 15 ns V

> 2.7V

— — 20 ns V

< 2.7V

SP40 T

Setup Time of SDIx Data Input

to SCKx Edge

10 — — ns —

SP41 T

Hold Time of SDIx Data Input

to SCKx Edge

10 — — ns —

SP50 T

SSx  to SCKx  or SCKx Input 175 — — ns —

SP51 T

ZSSx  to SDOx Output 

High-Impedance

(Note 3)

5 — 25 ns —

SP52 T

SSx after SCKx Edge T

SCK

+ 20 — — ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

The minimum clock period for SCKx is 50 ns.

Assumes 50 pF load on all SPIx pins.

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FIGURE 31-13 : SPIx MO DULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDI

SP60

SDIx

SP30,SP31

MSb Bit 14 - - - - - -1 LSb

SP51

MSb In Bit 14 - - - -1 LSb In

SP52

SP73

SP72

SP73

SP71

SP40 SP41

Note:

Refer to Figure 31-1 for load conditions.

SP50

SP70

SP35

TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typical

(2)

Max. Units Conditions

SP70 T

LSCKx Input Low Time

(Note 3)

SCK

/2 — — ns —

SP71 T

HSCKx Input High Time

(No te 3)

SCK

/2 — — ns —

SP72 T

FSCKx Input Fall Time — 5 10 ns —

SP73 T

RSCKx Input Rise Time — 5 10 ns —

SP30 T

FSDOx Data Output Fall Time



(Note 4)

— — — ns See parameter DO32

SP31 T

RSDOx Data Output Rise Time



(Note 4)

— — — ns See parameter DO31

SP35 T

SDOx Data Output Valid after

SCKx Edge

— — 20 ns V

> 2.7V

— — 30 ns V

< 2.7V

SP40 T

Setup Time of SDIx Data Input

to SCKx Edge

10 — — ns —

SP41 T

Hold Time of SDIx Data Input

to SCKx Edge

10 — — ns —

SP50 T

SSx  to SCKx  or SCKx  Input 175 — — ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

The minimum clock period for SCKx is 50 ns.

Assumes 50 pF load on all SPIx pins.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 334  2014-2017 Microchip Technology Inc.

SP51 T

ZSSx  to SDO

Output

High-Impedance



(Note 4)

5 — 25 ns —

SP52 T

SSx  after SCKx Edge T

SCK

— — ns —

SP60 T

VSDOx Data Output Valid after

SSx Edge

— — 25 ns —

TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typical

(2)

Max. Units Conditions

Note 1:

These parameters are characterized, but not tested in manufacturing.

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

The minimum clock period for SCKx is 50 ns.

Assumes 50 pF load on all SPIx pins.

 2014-2017 Microchip Technology Inc. DS60001290E-page 335

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 31-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

FIGURE 31-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

SCLx

SDAx

Start

Condition

Stop

Condition

Note:

Refer to Figure 31-1 for load conditions.

IM30

IM31 IM34

IM33

IM11 IM10 IM33

IM11

IM10

IM20

IM26 IM25

IM40 IM40 IM45

IM21

SCLx

SDAx

Out

Note:

Refer to Figure 31-1 for load conditions.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 336  2014-2017 Microchip Technology Inc.

TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min.

(1)

Max. Units Conditions

IM10 T

SCL

Clock Low Time 100 kHz mode T

* (BRG + 2) — s—

400 kHz mode T

* (BRG + 2) — s—

1 MHz mode



(Note 2)

* (BRG + 2) — s—

IM11 T

SCL

Clock High Time 100 kHz mode T

* (BRG + 2) — s—

400 kHz mode T

* (BRG + 2) — s—

1 MHz mode



(Note 2)

* (BRG + 2) — s—

IM20 T

SCL

SDAx and SCLx

Fall Time

100 kHz mode — 300 ns C

is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 C

300 ns

1 MHz mode



(Note 2)

— 100 ns

IM21 T

SCL

SDAx and SCLx

Rise Time

100 kHz mode — 1000 ns C

is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 C

300 ns

1 MHz mode



(Note 2)

— 300 ns

IM25 T

DAT

Data Input

Setup Time

100 kHz mode 250 — ns —

400 kHz mode 100 — ns

1 MHz mode



(Note 2)

100 — ns

IM26 T

DAT

Data Input

Hold Time

100 kHz mode 0 — s—

400 kHz mode 0 0.9 s

1 MHz mode



(Note 2)

0 0.3 s

IM30 T

STA

Start Condition

Setup Time

100 kHz mode T

* (BRG + 2) — s Only relevant for

Repeated Start

condition

400 kHz mode T

* (BRG + 2) — s

1 MHz mode



(Note 2)

* (BRG + 2) — s

IM31 T

STA

Start Condition

Hold Time

100 kHz mode T

* (BRG + 2) — s After this period, the

first clock pulse is

generated

400 kHz mode T

* (BRG + 2) — s

1 MHz mode



(Note 2)

* (BRG + 2) — s

IM33 T

STO

Stop Condition

Setup Time

100 kHz mode T

* (BRG + 2) — s—

400 kHz mode T

* (BRG + 2) — s

1 MHz mode



(Note 2)

* (BRG + 2) — s

IM34 T

STO

Stop Condition 100 kHz mode T

* (BRG + 2) — ns —

Hold Time 400 kHz mode T

* (BRG + 2) — ns

1 MHz mode



(Note 2)

* (BRG + 2) — ns

Note 1:

BRG is the value of the I

C Baud Rate Generator.

Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

The typical value for this parameter is 104 ns.

 2014-2017 Microchip Technology Inc. DS60001290E-page 337

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

IM40 T

SCL

Output Valid

from Clock

100 kHz mode — 3500 ns —

400 kHz mode — 1000 ns —

1 MHz mode



(Note 2)

— 350 ns —

IM45 T

SDA

Bus Free Time 100 kHz mode 4.7 — s The amount of time the

bus must be free

before a new

transmission can start

400 kHz mode 1.3 — s

1 MHz mode



(Note 2)

0.5 — s

IM50 C

Bus Capacitive Loading — 400 pF —

IM51 T

PGD

Pulse Gobbler Delay 52 312 ns See

Note 3

TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min.

(1)

Max. Units Conditions

Note 1:

BRG is the value of the I

C Baud Rate Generator.

Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

The typical value for this parameter is 104 ns.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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FIGURE 31-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

FIGURE 31-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS34

SCLx

SDAx

Start

Condition

Stop

Condition

IS33

Note:

Refer to Figure 31-1 for load conditions.

IS31

IS30

IS30 IS31 IS33

IS11

IS10

IS20

IS26 IS25

IS40 IS40 IS45

IS21

SCLx

SDAx

Out

Note:

Refer to Figure 31-1 for load conditions.

 2014-2017 Microchip Technology Inc. DS60001290E-page 339

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Max. Units Conditions

IS10 T

SCL

Clock Low Time 100 kHz mode 4.7 — s PBCLK must operate at a

minimum of 800 kHz

400 kHz mode 1.3 — s PBCLK must operate at a

minimum of 3.2 MHz

1 MHz mode



(Note 1)

0.5 — s—

IS11 T

SCL

Clock High Time 100 kHz mode 4.0 — s PBCLK must operate at a

minimum of 800 kHz

400 kHz mode 0.6 — s PBCLK must operate at a

minimum of 3.2 MHz

1 MHz mode



(Note 1)

0.5 — s—

IS20 T

SCL

SDAx and SCLx

Fall Time

100 kHz mode — 300 ns C

is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 C

300 ns

1 MHz mode



(Note 1)

— 100 ns

IS21 T

SCL

SDAx and SCLx

Rise Time

100 kHz mode — 1000 ns C

is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 C

300 ns

1 MHz mode



(Note 1)

— 300 ns

IS25 T

DAT

Data Input

Setup Time

100 kHz mode 250 — ns —

400 kHz mode 100 — ns

1 MHz mode



(Note 1)

100 — ns

IS26 T

DAT

Data Input

Hold Time

100 kHz mode 0 — ns —

400 kHz mode 0 0.9 s

1 MHz mode



(Note 1)

00.3s

IS30 T

STA

Start Condition

Setup Time

100 kHz mode 4700 — ns Only relevant for Repeated

Start condition

400 kHz mode 600 — ns

1 MHz mode



(Note 1)

250 — ns

IS31 T

STA

Start Condition

Hold Time

100 kHz mode 4000 — ns After this period, the first

clock pulse is generated

400 kHz mode 600 — ns

1 MHz mode



(Note 1)

250 — ns

IS33 T

STO

Stop Condition

Setup Time

100 kHz mode 4000 — ns —

400 kHz mode 600 — ns

1 MHz mode



(Note 1)

600 — ns

Note 1:

Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 340  2014-2017 Microchip Technology Inc.

IS34 T

STO

Stop Condition

Hold Time

100 kHz mode 4000 — ns —

400 kHz mode 600 — ns

1 MHz mode



(Note 1)

250 ns

IS40 T

SCL

Output Valid from

Clock

100 kHz mode 0 3500 ns —

400 kHz mode 0 1000 ns

1 MHz mode



(Note 1)

0 350 ns

IS45 T

SDA

Bus Free Time 100 kHz mode 4.7 — s The amount of time the bus

must be free before a new

transmission can start

400 kHz mode 1.3 — s

1 MHz mode



(Note 1)

0.5 — s

IS50 C

Bus Capacitive Loading — 400 pF —

TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Max. Units Conditions

Note 1:

Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

 2014-2017 Microchip Technology Inc. DS60001290E-page 341

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 31-34: ADC MODULE SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions (see Note 5): 2.5V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typical Max. Units Conditions

Device Supply

AD01 AV

Module V

Supply Greater of

– 0.3

or 2.5

— Lesser of

+ 0.3 or

3.6

V—

AD02 AV

Module V

Supply V

—AV

(Note 1)

Reference Input s

AD05

AD05a

REFH

Reference Voltage High AV

+ 2.0

2.5

—

3.6

(Note 1)

REFH

= AV

(Note 3)

AD06 V

REFL

Reference Voltage Low AV

—V

REFH

– 2.0 V

(Note 1)

AD07 V

REF

Absolute Reference

Voltage (V

REFH

– V

REFL

)

2.0 — AV

(Note 3)

AD08

AD08a

REF

Current Drain —

—

250

—

400

µA

ADC operating

ADC off

Analog Input

AD12 V

INH

-V

INL

Full-Scale Input Span V

REFL

—V

REFH

V—

AD13 V

INL

Absolute V

INL

Input

Voltage

– 0.3 — AV

/2 V —

AD14 V

Absolute Input Voltage AV

– 0.3 — AV

+ 0.3 V —

AD15 — Leakage Current — ±0.001 ±0.610 µA V

INL

= AV

= V

REFL

= 0V,

= V

REFH

= 3.3V

Source Impedance = 10 k

AD17 R

Recommended

Impedance of Analog

Voltage Source

—— 5k

(Note 1)

ADC Accuracy – Measurements with External V

REF

+/V

REF

AD20c Nr Resolution 10 data bits bits —

AD21c INL Integral Non-linearity > -1 — < 1 LSb V

INL

= AV

= V

REFL

= 0V,

= V

REFH

= 3.3V

AD22c DNL Differential Non-linearity > -1 — < 1 LSb V

INL

= AV

= V

REFL

= 0V,

= V

REFH

= 3.3V

(Note 2)

AD23c G

ERR

Gain Error > -1 — < 1 LSb V

INL

= AV

= V

REFL

= 0V,

= V

REFH

= 3.3V

AD24c E

OFF

Offset Error > -1 — < 1 Lsb V

INL

= AV

= 0V, 

= 3.3V

AD25c — Monotonicity — — — — Guaranteed

Note 1:

These parameters are not characterized or tested in manufacturing.

With no missing codes.

These parameters are characterized, but not tested in manufacturing.

Characterized with a 1 kHz sine wave.

The ADC module is functional at V

BORMIN

< V

< 2.5V, but with degraded performance. Unless otherwise

stated, module functionality is tested, but not characterized.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 342  2014-2017 Microchip Technology Inc.

ADC Ac cur ac y – Measu r eme nts wit h Intern al V

REF

+/V

REF

AD20d Nr Resolution 10 data bits bits

(Note 3)

AD21d INL Integral Non-linearity > -1 — < 1 LSb V

INL

= AV

= 0V, 

= 2.5V to 3.6V 

(Note 3)

AD22d DNL Differential Non-linearity > -1 — < 1 LSb V

INL

= AV

= 0V, 

= 2.5V to 3.6V

(Notes 2,3)

AD23d G

ERR

Gain Error > -4 — < 4 LSb V

INL

= AV

= 0V, 

= 2.5V to 3.6V

(Note 3)

AD24d E

OFF

Offset Error > -2 — < 2 Lsb V

INL

= AV

= 0V, 

= 2.5V to 3.6V

(Note 3)

AD25d — Monotonicity — — — — Guaranteed

Dynamic Performance

AD32b SINAD Signal to Noise and

Distortion

55 58.5 — dB

(Notes 3,4)

AD34b ENOB Effective Number of bits 9.0 9.5 — bits

(Notes 3,4)

TABLE 31-34: ADC MODULE SPECIFICATIONS (CONTINUED)

AC CHARACTERISTICS

Standard Operating Conditions (see Note 5): 2.5V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typical Max. Units Conditions

Note 1:

These parameters are not characterized or tested in manufacturing.

With no missing codes.

These parameters are characterized, but not tested in manufacturing.

Characterized with a 1 kHz sine wave.

The ADC module is functional at V

BORMIN

< V

< 2.5V, but with degraded performance. Unless otherwise

stated, module functionality is tested, but not characterized.

 2014-2017 Microchip Technology Inc. DS60001290E-page 343

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 31-35: 10-BIT CONVERSION RATE PARAMETERS

AC CHARACTERISTICS

(2)

Standard Operating Conditions (see Note 3): 2.5V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

ADC Speed T

Min. Sampling

Time Min. R

Max. V

ADC Channels Configuration

1 Msps to 400 ksps

(1)

65 ns 132 ns 5003.0V to

3.6V

Up to 400 ksps 200 ns 200 ns 5.0 k2.5V to

3.6V

Note 1:

External V

REF

- and V

REF

+ pins must be used for correct operation.

These parameters are characterized, but not tested in manufacturing.

The ADC module is functional at V

BORMIN

< V

< 2.5V, but with degraded performance. Unless otherwise

stated, module functionality is tested, but not characterized.

REF

-V

REF

ADC

ANx

SHA

REF

-V

REF

ADC

ANx

SHA

ANx or V

REF

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 344  2014-2017 Microchip Technology Inc.

TABLE 31-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions (see Note 4): 2.5V to 3.6V

(unless otherwis e st ated )

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typical

(1)

Max. Units Conditions

Clock Parameters

AD50 T

ADC Clock Period

(2)

65 — — ns See Table 31-35

Conversion Rate

AD55

TCONV

Conversion Time — 12 T

—— —

AD56 F

CNV

Throughput Rate 

(Sampling Speed)

— — 1000 ksps AV

= 3.0V to 3.6V

——400kspsAV

= 2.5V to 3.6V

AD57 T

SAMP

Sample Time 1 T

———T

SAMP

must be  132 ns

Timing Parameters

AD60

TPCS

Conversion Start from Sample

Trigger

(3)

—1.0 T

— — Auto-Convert Trigger

(SSRC<2:0> = 111)

not selected

AD61

TPSS

Sample Start from Setting

Sample (SAMP) bit

0.5 T

—1.5 T

——

AD62

TCSS

Conversion Completion to

Sample Start (ASAM = 1)

(3)

—0.5 T

—— —

AD63

TDPU

Time to Stabilize Analog Stage 

from ADC Off to ADC On

(3)

—— 2s—

Note 1:

These parameters are characterized, but not tested in manufacturing.

Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

Characterized by design but not tested.

The ADC module is functional at V

BORMIN

< V

< 2.5V, but with degraded performance. Unless otherwise

stated, module functionality is tested, but not characterized.

 2014-2017 Microchip Technology Inc. DS60001290E-page 345

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 31-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING

CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000)

AD55

SAMP

Clear SAMPSet SAMP

AD61

ADCLK

Instruction

SAMP

ch0_dischrg

AD60

CONV

ADxIF

Buffer(

)

Buffer(

)

1 2 3 4 5 6 8 5 6 7

1– Software sets ADxCON. SAMP to start sampling.

2– Sampling starts after discharge period. T

SAMP

is described in

Section 17. “10-bi t Analog-to-Digital Converter (ADC)”

3– Software clears ADxCON. SAMP to start conversion.

4– Sampling ends, conversion sequence starts.

5– Convert bit 9.

8– One T

for end of conversion.

AD50

ch0_samp

eoc

AD55

6– Convert bit 8.

7– Convert bit 0.

Execution

(DS60001104) in the “PIC32 Family Reference Manual”.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

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FIGURE 31-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS

(ASAM = 1, SSRC<2:0> = 111, SAM C<4: 0 > = 00001)

AD55

SAMP

Set ADON

ADCLK

Instruction

SAMP

ch0_dischrg

CONV

ADxIF

Buffer(0)

Buffer(1)

1 2 3 4 5 6 4 5 6 8

1– Software sets ADxCON. ADON to start AD operation.

2– Sampling starts after discharge period.

3– Convert bit 9.

4– Convert bit 8.

5– Convert bit 0.

AD50

ch0_samp

eoc

7 3

AD55

6– One T

for end of conversion.

7– Begin conversion of next channel.

8– Sample for time specified by SAMC<4:0>.

SAMP

CONV

3 4

Execution

SAMP

is described in

Section 17. “10-bit Analog-to-Digital

Converter (ADC)”

(DS60001104).

 2014-2017 Microchip Technology Inc. DS60001290E-page 347

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 31-20: PARALLEL SLAVE PORT TIMING

PMD<7:0>

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 348  2014-2017 Microchip Technology Inc.

FIGURE 31-21: PARALLEL MASTER PORT READ TIMING DIAGRAM

TABLE 31-37: PARALLEL SLAVE PORT REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Para

m.No. Symbol Characteristics

(1)

Min. Typ. Max. Units Conditions

PS1 TdtV2wr

Data In Valid before WR or CS

Inactive (setup time)

20 — — ns —

PS2 TwrH2dt

WR or CS Inactive to Data-In

Invalid (hold time)

40 — — ns —

PS3 TrdL2dt

RD and CS Active to Data-Out

Valid

— — 60 ns —

PS4 TrdH2dtI RD Activeor CS Inactive to

Data-Out Invalid

0 — 10 ns —

PS5 Tcs CS Active Time T

+ 40 — — ns —

PS6 T

WR Active Time T

+ 25 — — ns —

PS7 T

RD Active Time T

+ 25 — — ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

PB Clock

PMALL/PMALH

PMD<7:0>

PMA<13:18>

PMRD

PMCS<2:1>

PMWR

PM5

Data

Address<7:0>

PM1

PM3

PM6

Data

PM7

Address<7:0>

Address

PM4

PM2

 2014-2017 Microchip Technology Inc. DS60001290E-page 349

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

FIGURE 31-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM

TABLE 31-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typ. Max. Units Conditions

PM1 T

LAT

PMALL/PMALH Pulse Width — 1 T

—— —

PM2 T

ADSU

Address Out Valid to PMALL/

PMALH Invalid (address setup

time)

—2 T

—— —

PM3 T

ADHOLD

PMALL/PMALH Invalid to

Address Out Invalid (address

hold time)

—1 T

—— —

PM4 T

AHOLD

PMRD Inactive to Address Out

Invalid

(address hold time)

5——ns —

PM5 T

PMRD Pulse Width — 1 T

—— —

PM6 T

DSU

PMRD or PMENB Active to Data

In Valid (data setup time)

15 — — ns —

PM7 T

DHOLD

PMRD or PMENB Inactive to

Data In Invalid (data hold time)

—80—ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

PB Clock

PMALL/PMALH

PMD<7:0>

PMA<13:18>

PMWR

PMCS<2:1>

PMRD

PM12 PM13

PM11

Address

Address<7:0> Data

PM2 + PM3

PM1

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 350  2014-2017 Microchip Technology Inc.

TABLE 31-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typ. Max. Units Conditions

PM11 T

PMWR Pulse Width — 1 T

—— —

PM12 T

DVSU

Data Out Valid before PMWR or

PMENB goes Inactive (data setup

time)

—2 T

—— —

PM13 T

DVHOLD

PMWR or PMEMB Invalid to Data

Out Invalid (data hold time)

—1 T

—— —

Note 1:

These parameters are characterized, but not tested in manufacturing.

TABLE 31-40: OTG ELECTRICAL SPECI FICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwis e stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics

(1)

Min. Typ. Max. Units Conditions

USB313 V

USB

USB Voltage 3.0 —3.6 VVoltage on V

USB

must be in this range

for proper USB

operation

USB315 V

ILUSB

Input Low Voltage for USB Buffer — — 0.8 V —

USB316 V

IHUSB

Input High Voltage for USB Buffer 2.0 — — V —

USB318 V

DIFS

Differential Input Sensitivity — — 0.2 VThe difference

between D+ and D-

must exceed this value

while VCM is met

USB319 VCM Differential Common Mode Range 0.8 —2.5 V —

USB320 Z

OUT

Driver Output Impedance 28.0 —44.0 —

USB321 V

Voltage Output Low 0.0 —0.3 V1.425 k load

connected to V

USB

USB322 V

Voltage Output High 2.8 —3.6 V1.425 k load

connected to ground

Note 1:

These parameters are characterized, but not tested in manufacturing.

 2014-2017 Microchip Technology Inc. DS60001290E-page 351

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 31-41: CTMU CURRENT SOURCE SPECIFICATIONS

DC CHARACTERISTICS Standard Operating Conditions (see Note 3):2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

-40°C  T

 +105°C for V-temp

Param

No. Symbol Characteristic Min. Typ. Max. Units Conditions

CTMU C

URRENT

OURCE

CTMUI1 I

OUT

1 Base Range

(1)

— 0.55 — µA CTMUCON<9:8> = 01

CTMUI2 I

OUT

2 10x Range

(1)

— 5.5 — µA CTMUCON<9:8> = 10

CTMUI3 I

OUT

3 100x Range

(1)

— 55 — µA CTMUCON<9:8> = 11

CTMUI4 I

OUT

4 1000x Range

(1)

— 550 — µA CTMUCON<9:8> = 00

CTMUFV1 V

Temperature Diode Forward

Voltage

(1,2)

—0.598— VT

= +25ºC, 

CTMUCON<9:8> = 01

—0.658— VT

= +25ºC, 

CTMUCON<9:8> = 10

—0.721— VT

= +25ºC, 

CTMUCON<9:8> = 11

CTMUFV2 V

FVR

Temperature Diode Rate of

Change

(1,2)

— -1.92 — mV/ºC CTMUCON<9:8> = 01

— -1.74 — mV/ºC CTMUCON<9:8> = 10

— -1.56 — mV/ºC CTMUCON<9:8> = 11

Note 1:

Nominal value at center point of current trim range (CTMUCON<15:10> = 000000).

Parameters are characterized but not tested in manufacturing. Measurements taken with the following

conditions:

•V

REF

+ = AV

= 3.3V

• ADC module configured for conversion speed of 500 ksps

• All PMD bits are cleared (PMDx = 0)

• Executing a while(1) statement

• Device operating from the FRC with no PLL

The CTMU module is functional at V

BORMIN

< V

DDMIN

, but with degraded performance. Unless

otherwise stated, module functionality is tested, but not characterized.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 352  2014-2017 Microchip Technology Inc.

FIGURE 31-23: EJTAG TIMING CHARACTERISTICS

TCKcyc

TCKhigh

TCKlow

Tsetup

Thold

TDOout

TDOzstate

Defined Undefined

TRST*low

TCK

TDO

TRST*

TDI

TMS

TABLE 31-42: EJTAG TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial 

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Description

(1)

Min. Max. Units Conditions

EJ1 T

TCKCYC

TCK Cycle Time 25 —ns —

EJ2 T

TCKHIGH

TCK High Time 10 —ns —

EJ3 T

TCKLOW

TCK Low Time 10 —ns —

EJ4 T

TSETUP

TAP Signals Setup Time Before

Rising TCK

5 — ns —

EJ5 T

THOLD

TAP Signals Hold Time After

Rising TCK

3 — ns —

EJ6 T

TDOOUT

TDO Output Delay Time from

Falling TCK

— 5 ns —

EJ7 T

TDOZSTATE

TDO 3-State Delay Time from

Falling TCK

— 5 ns —

EJ8 T

TRSTLOW

TRST Low Time 25 —ns —

EJ9 T

TAP Signals Rise/Fall Time, All

Input and Output

— — ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

 2014-2017 Microchip Technology Inc. DS60001290E-page 353

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

32.0 50 MHz ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC32MX1XX/2XX/5XX 64/100-pin Family electrical characteristics for devices

operating at 50 MHz.

The specifications for 50 MHz are identical to those shown in

Section 31.0 “ 40 M Hz Ele ctric al C h arac ter isti cs”

, with

the exception of the parameters listed in this chapter.

Parameters in this chapter begin with the letter “M”, which denotes 50 MHz operation. For example, parameter DC29a

Section 31.0 “40 MHz Electrical Characteristics”

, is the up to 40 MHz operation equivalent for MDC29a.

Absolute maximum ratings for the PIC32MX1XX/2XX/5XX 64/100-pin Family 50 MHz devices are listed below.

Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of

the device at these or any other conditions, above the parameters indicated in the operation listings of this specification,

is not implied.

Absolute Maximum Ratings

(See Note 1)

Ambient temperature under bias...............................................................................................................-40°C to +85°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on V

with respect to V

......................................................................................................... -0.3V to +4.0V

Voltage on any pin that is not 5V tolerant, with respect to V

(Note 3)

......................................... -0.3V to (V

+ 0.3V)

Voltage on any 5V tolerant pin with respect to V

when V

 2.3V

(Note 3)

........................................ -0.3V to +5.5V

Voltage on any 5V tolerant pin with respect to V

when V

< 2.3V

(Note 3)

........................................ -0.3V to +3.6V

Voltage on D+ or D- pin with respect to V

USB

.................................................................... -0.3V to (V

USB

+ 0.3V)

Voltage on V

BUS

with respect to V

....................................................................................................... -0.3V to +5.5V

Maximum current out of V

pin(s) .......................................................................................................................300 mA

Maximum current into V

pin(s)

(Note 2)

............................................................................................................300 mA

Maximum output current sunk by any I/O pin..........................................................................................................15 mA

Maximum output current sourced by any I/O pin ....................................................................................................15 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports

(Note 2)

....................................................................................................200 mA

Note 1:

Stresses above those listed under

“Abso lute Maxim um Ratings”

may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions,

above those indicated in the operation listings of this specification, is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

Maximum allowable current is a function of device maximum power dissipation (see Tab l e 32-2).

See the

“Device Pin Tables”

section for the 5V tolerant pins.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 354  2014-2017 Microchip Technology Inc.

32.1 DC Characteristics

TABLE 32-2: DC CHARACTERISTICS: OPERATING CURRENT (I

)

TABLE 32-1: OPERATING MIPS VS. VOLTAGE

Characteristic V

Range

(in Volts)

(1)

Temp. Range

(in °C)

Max. Frequency

PIC32MX1XX/2XX/5XX 64/100-pin

Family

MDC5 V

BOR

-3.6V -40°C to +85°C 50 MHz

Note 1:

Overall functional device operation at V

BORMIN

< V

DDMIN

is tested, but not characterized. All device

Analog modules, such as ADC, etc., will function, but with degraded performance below V

DDMIN

. Refer to

parameter BO10 in Table 31-10 for BOR values.

DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

Parameter

No. Typical

(3)

Max. Units Conditions

Operating Current (I

) (Note 1, 2)

MDC24 25 40 mA 50 MHz

Note 1:

A device’s I

supply current is mainly a function of the operating voltage and frequency. Other factors,

such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code

execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,

oscillator type, as well as temperature, can have an impact on the current consumption.

The test conditions for I

measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by

external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin

• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8

• CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1

• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared

• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled

• All I/O pins are configured as inputs and pulled to V

•MCLR

= V

• CPU executing while(1) statement from Flash

RTCC and JTAG are disabled

Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.

Parameters are for design guidance only and are not tested.

 2014-2017 Microchip Technology Inc. DS60001290E-page 355

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 32-3: DC CHARACTERISTICS: IDLE CURRENT (I

IDLE

)

DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

Parameter

No. Typical

(2)

Max. Units Conditions

Idle Current (I

IDLE

): Core Off, Clock on Base Current (Note 1)

MDC34a 9.5 24 mA 50 MHz

Note 1:

The test conditions for I

IDLE

current measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by

external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin

• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8

• CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1

• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared

• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled

• All I/O pins are configured as inputs and pulled to V

•MCLR = V

• RTCC and JTAG are disabled

Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

TABLE 32-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (I

)

DC CHARACTERISTICS Standar d Oper a tin g Conditio ns: 2.3V to 3.6 V (unless o the r wise s tate d)

Operating temperature -40°C  T

 +85°C for Industrial

Param.

No. Typical

(2)

Max. Units Conditions

Power-Down Current (I

) (Note 1)

MDC40k 50 150 A-40°C Base Power-Down Current

MDC40n 250 650 A+85°C

Module Differential Current

MDC41e 15 55 A3.6V Watchdog Timer Current: I

WDT

(Note 3)

MDC42e 34 55 A3.6V RTCC + Timer1 w/32 kHz Crystal: I

RTCC

(Note 3)

MDC43d 1100 1800 A3.6V ADC: I

ADC

(Notes 3,4)

Note 1:

The test conditions for I

current measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by

external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin

• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8

• CPU is in Sleep mode, and SRAM data memory Wait states = 1

• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set

• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled

• All I/O pins are configured as inputs and pulled to V

•MCLR = V

• RTCC and JTAG are disabled

Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

The  current is the additional current consumed when the module is enabled. This current should be

added to the base I

current.

Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 356  2014-2017 Microchip Technology Inc.

32.2 AC Characteristics and Timing

Parameters

The information contained in this section defines

PIC32MX1XX/2XX/5XX 64/100-pin AC characteristics

and timing parameters.

TABLE 32-5: EXTERN AL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

Param.

No. Symbol Characteristics Min. Typical Max. Units Conditions

MOS10 F

OSC

External CLKI Frequency

(External clocks allowed only

in EC and ECPLL modes)

—

MHz

(Note 2)



ECPLL

(Note 1)

Note 1:

PLL input requirements: 4 MHz  F

PLLIN

 5 MHz (use PLL prescaler to reduce Fosc). This parameter is

characterized, but tested at 10 MHz only at manufacturing.

This parameter is characterized, but not tested in manufacturing.

TABLE 32-6: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

Param.

No. Symbol Characteristics Min. Typical Max. Units Conditions

MSP10 T

LSCKx Output Low Time



(Note 1,2)

SCK

/2 — — ns —

MSP11 T

HSCKx Output High Time



(Note 1,2)

SCK

/2 — — ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not

violate this specification.

TABLE 32-7: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V

(unless otherwis e stated )

Operating temperature -40°C  T

 +85°C for Industrial

Param.

No. Symbol Characteristics

(1)

Min. Typ. Max. Units Conditions

MSP10 T

LSCKx Output Low Time



(Note 1,2)

SCK

/2 — — ns —

MSP11 T

HSCKx Output High Time



(Note 1,2)

SCK

/2 — — ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not

violate this specification.

 2014-2017 Microchip Technology Inc. DS60001290E-page 357

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 32-8: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

-40°C  T

 +105°C for V-temp

Param.

No. Symbol Characteristics Min. Typ. Max. Units Conditions

MSP70 T

L SCKx Input Low Time

(Note 1,2)

SCK

/2 — — ns —

MSP71 T

H SCKx Input High Time

(Note 1,2)

SCK

/2 — — ns —

MSP51 T

Z SSx  to SDOx Output 

High-Impedance

(Note 2)

5—25ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

The minimum clock period for SCKx is 40 ns.

TABLE 32-9: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

 +85°C for Industrial

Param.

No. Symbol Characteristics Min. Typical Max. Units Conditions

SP70 T

LSCKx Input Low Time

(Note 1,2)

SCK

/2 — — ns —

SP71 T

HSCKx Input High Time

(No te 1,2)

SCK

/2 — — ns —

Note 1:

These parameters are characterized, but not tested in manufacturing.

The minimum clock period for SCKx is 40 ns.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 358  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page 359

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

33.0 DC AN D AC DEVICE CHARACTERISTICS GRAPHS

FIGURE 33-1: V

– 4x DRIVER PINS

FIGURE 33-2: V

– 8x DRIVER PINS

FIGURE 33-3: V

– 4x DRIVER PINS

FIGURE 33-4: V

– 8x DRIVER PINS

Note:

The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes

only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating

range (e.g., outside specified power supply range) and therefore, outside the warranted range.

Ͳ40.00

Ͳ35.00

Ͳ30.00

Ͳ25.00

Ͳ20.00

Ͳ15.00

Current(mA)

Ͳ10.00

Ͳ5.00

0.00

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Voltage(V)

3.3V

Absolute Maximum

Ͳ70.00

Ͳ60.00

Ͳ50.00

Ͳ40.00

Ͳ30.00

Current(mA)

Ͳ20.00

Ͳ10.00

0.00

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Voltage(V)

3.3V

Absolute Maximum

15.000

20.000

25.000

30.000

35.000

40.000

45.000

Current(mA)

0.000

5.000

10.000

0.000 0.500 1.000 1.500 2.000 2.500 3.000

Voltage(V)

3.3V

Absolute Maximum

30.000

40.000

50.000

60.000

70.000

80.000

Current(mA)

0.000

10.000

20.000

0.000 0.500 1.000 1.500 2.000 2.500 3.000

Voltage(V)

3.3V

Absolute Maximum

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 360  2014-2017 Microchip Technology Inc.

FIGURE 33-5: TYPICAL CTMU TEMPERATURE DIODE

FORWARD VOLTAGE

0500

0.550

0.600

0.650

0.700

0.750

0.800

0.850

Forward Voltage (V)

0.350

0.400

0.450

0.500

0.550

0.600

0.650

0.700

0.750

0.800

0.850

-40-30-20-100 102030405060708090100110

Forward Voltage (V)

Temperature (Celsius)

= 0.598

= 0.658

= 0.721

55 µA, V

FVR

= -1.56 mV/ºC

5.5 µA, V

FVR

= -1.74 mV/ºC

0.55 µA, V

FVR

= -1.92 mV/ºC

 2014-2017 Microchip Technology Inc. DS60001290E-page 361

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

34.0 PACKAGING INFORMATION

34.1 Package Marking Information

PIC32MX150F

256H-I/PT

0510017

Legend:

XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note:

In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

64-Lead TQFP (10x10x1 mm)

XXXXXXXXXX

YYWWNNN

Example

100-Lead TQFP (12x12x1 mm)

XXXXXXXXXXXX

YYWWNNN

Example

PIC32MX150F

256L-I/PT

0510017

100-Lead TQFP (14x14x1 mm)

XXXXXXXXXXXX

YYWWNNN

Example

PIC32MX150F

256L-I/PF

0510017

XXXXXXXXXX

64-Lead QFN (9x9x0.9 mm)

XXXXXXXXXX

YYWWNNN

PIC32MX150F

Example

256H-I/MR

0510017

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 362  2014-2017 Microchip Technology Inc.

34.2 Package Details

The following sections give the technical details of the packages.

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1RWHV

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6WDQGRII $  ± 

)RRW/HQJWK /   

)RRWSULQW / 5()

)RRW$QJOH   

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0ROGHG3DFNDJH/HQJWK ' %6&

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E   

0ROG'UDIW$QJOH7RS   

0ROG'UDIW$QJOH%RWWRP   

NOTE 1 123 NOTE 2

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 2014-2017 Microchip Technology Inc. DS60001290E-page 363

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 364  2014-2017 Microchip Technology Inc.

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)RRW/HQJWK /   

)RRWSULQW / 5()

)RRW$QJOH   

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NOTE 1 NOTE 2

123

LA1 L1

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 2014-2017 Microchip Technology Inc. DS60001290E-page 365

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 366  2014-2017 Microchip Technology Inc.

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123

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 2014-2017 Microchip Technology Inc. DS60001290E-page 367

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 368  2014-2017 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2014-2017 Microchip Technology Inc. DS60001290E-page 369

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 370  2014-2017 Microchip Technology Inc.

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

 2014-2017 Microchip Technology Inc. DS60001290E-page  371
PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
INDEX
A
AC Characteristics .................................................... 321, 356
10-Bit Conversion Rate Parameters ......................... 343
ADC Specifications ................................................... 341
Analog-to-Digital Conversion Requirements............. 344
EJTAG Timing Requirements ................................... 352
Internal FRC Accuracy.............................................. 323
Internal RC Accuracy ................................................ 323
OTG Electrical Specifications ................................... 350
Parallel Master Port Read Requirements ................. 349
Parallel Master Port Write......................................... 350
Parallel Master Port Write Requirements.................. 350
Parallel Slave Port Requirements ............................. 348
PLL Clock Timing...................................................... 323
Analog-to-Digital Converter (ADC).................................... 231
B
Block Diagrams
ADC Module.............................................................. 231
Comparator I/O Operating Modes............................. 271
Comparator Voltage Reference ................................ 275
Connections for On-Chip Voltage Regulator............. 302
CPU ............................................................................ 35
CTMU Configurations
Time Measurement........................................... 279
DMA ............................................................................ 85
Input Capture ............................................................ 173
Inter-Integrated Circuit (I
2
C)...................................... 192
Interrupt Controller ...................................................... 53
JTAG Programming, Debugging and Trace Ports .... 302
Output Compare Module........................................... 177
PIC32 CAN Module................................................... 243
PMP Pinout and Connections to External Devices ... 207
Reset System.............................................................. 69
RTCC ........................................................................ 221
SPI Module ............................................................... 181
Timer1....................................................................... 159
Timer2/3/4/5 (16-Bit)................................................. 163
Typical Multiplexed Port Structure ............................ 129
UART ........................................................................ 199
WDT and Power-up Timer ........................................ 169
Brown-out Reset (BOR)
and On-Chip Voltage Regulator................................ 302
C
C Compilers
MPLAB C18 .............................................................. 306
Charge Time Measurement Unit. See CTMU.
Clock Diagram .................................................................... 74
Comparator
Specifications.................................................... 319, 320
Comparator Module .......................................................... 271
Comparator Voltage Reference (CVref ............................. 275
Configuration Bit ............................................................... 291
Configuring Analog Port Pins............................................ 130
Controller Area Network (CAN)......................................... 243
CPU
Architecture Overview................................................. 36
Coprocessor 0 Registers ............................................ 37
Core Exception Types................................................. 38
EJTAG Debug Support ............................................... 38
Power Management .................................................... 38
CPU Module.................................................................. 25, 35
CTMU
Registers .................................................................. 281
Customer Change Notification Service............................. 379
Customer Notification Service .......................................... 379
Customer Support............................................................. 379
D
DC and AC Characteristics
Graphs and Tables ................................................... 359
DC Characteristics............................................................ 310
I/O Pin Input Specifications ...................................... 315
I/O Pin Output Specifications.................................... 316
Idle Current (I
IDLE
) .................................................... 313
Power-Down Current (I
PD
)........................................ 314
Program Memory...................................................... 318
Temperature and Voltage Specifications.................. 311
DC Characteristics (50 MHz)............................................ 354
Idle Current (I
IDLE
) .................................................... 355
Power-Down Current (I
PD
)........................................ 355
Development Support....................................................... 305
Direct Memory Access (DMA) Controller............................ 85
E
Electrical Characteristics .................................................. 309
50 MHz ..................................................................... 353
Errata.................................................................................. 10
External Clock
Timer1 Timing Requirements ................................... 327
Timer2, 3, 4, 5 Timing Requirements ....................... 328
Timing Requirements ............................................... 322
External Clock (50 MHz)
Timing Requirements ............................................... 356
F
Flash Program Memory ...................................................... 63
RTSP Operation ......................................................... 63
H
High Voltage Detect (HVD)......................................... 71, 302
I
I/O Ports ........................................................................... 129
Parallel I/O (PIO) ...................................................... 130
Write/Read Timing.................................................... 130
Input Change Notification ................................................. 130
Instruction Set................................................................... 303
Inter-Integrated Circuit (I
2
C) ............................................. 191
Internal Voltage Reference Specifications........................ 320
Internet Address ............................................................... 379
Interrupt Controller.............................................................. 53
IRG, Vector and Bit Location...................................... 54
M
Memory Maps
Devices with 128 KB of Program Memory .................. 41
Devices with 256 KB of Program Memory .................. 42
Devices with 512 KB of Program Memory .................. 43
Devices with 64 KB of Program Memory.................... 40
Memory Organization ......................................................... 39
Layout......................................................................... 39
Microchip Internet Web Site.............................................. 379
MPASM Assembler........................................................... 306
MPLAB ASM30 Assembler, Linker, Librarian................... 306
MPLAB Integrated Development Environment Software.. 305

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
DS60001290E-page  372  2014-2017 Microchip Technology Inc.
MPLAB PM3 Device Programmer.....................................307
MPLAB REAL ICE In-Circuit Emulator System.................307
MPLINK Object Linker/MPLIB Object Librarian ................306
O
Oscillator Configuration....................................................... 73
Output Compare................................................................ 177
P
Packaging ......................................................................... 361
Details ....................................................................... 362
Marking ..................................................................... 361
Parallel Master Port (PMP) ...............................................207
PIC32 Family USB Interface Diagram............................... 106
Pinout I/O Descriptions (table) ............................................ 14
Power-on Reset (POR)
and On-Chip Voltage Regulator................................ 302
Power-Saving Features.....................................................285
CPU Halted Methods ................................................285
Operation .................................................................. 285
with CPU Running.....................................................285
R
Real-Time Clock and Calendar (RTCC)............................ 221
Register Map
ADC .......................................................................... 233
Bus Matrix ...................................................................45
Comparator ............................................................... 272
Comparator Voltage Reference ................................ 276
CTMU........................................................................ 280
Device and Revision ID Summary ............................ 292
Device Configuration Word Summary....................... 292
DMA Channel 0-3 ....................................................... 87
DMA CRC ...................................................................86
DMA Global................................................................. 86
Flash Controller...........................................................64
I2C1 and I2C2 ........................................................... 193
Input Capture 1-5 ...................................................... 174
Interrupt....................................................................... 56
Oscillator Configuration....................................... 76, 170
Output Compare1-5 ..................................................178
Parallel Master Port ..................................................208
Peripheral Pin Select Input ....................................... 151
Peripheral Pin Select Output..................................... 153
PORTA (100-pin Devices Only) ................................ 137
PORTB...................................................................... 138
PORTB (100-pin Devices Only) ................................ 139
PORTC (64-pin Devices Only)..................................140
PORTD (100-pin Devices Only) ................................ 141
PORTD (64-pin Devices Only)..................................142
PORTE (100-pin Devices Only) ................................ 143
PORTE (64-pin Devices Only) ..................................144
PORTF (100-pin General Purpose Devices Only) .... 145
PORTF (100-pin USB Devices Only) ........................ 146
PORTF (64-pin General Purpose Devices Only) ...... 147
PORTF (64-pin USB Devices Only)..........................148
PORTG (100-pin Devices Only)................................149
PORTG (64-pin Devices Only)..................................150
RTCC ........................................................................ 222
SPI1 through SPI4 .................................................... 182
Timer1....................................................................... 160
Timer2-5.................................................................... 165
UART1-5 ................................................................... 200
USB........................................................................... 107
Registers
[pin name]R (Peripheral Pin Select Input)................. 157
AD1CHS (ADC Input Select) .................................... 239
AD1CON1 (A/D Control 1)........................................ 230
AD1CON1 (ADC Control 1) .............................. 230, 235
AD1CON2 (ADC Control 2) ...................................... 237
AD1CON3 (ADC Control 3) ...................................... 238
AD1CSSL (ADC Input Scan Select) ......................... 241
AD1CSSL2 (ADC Input Scan Select 2) .................... 241
ALRMDATE (Alarm Date Value)............................... 230
ALRMDATECLR (ALRMDATE Clear) ...................... 230
ALRMTIME (Alarm Time Value) ............................... 229
ALRMTIMECLR (ALRMTIME Clear) ........................ 230
ALRMTIMEINV (ALRMTIME Invert) ......................... 230
ALRMTIMESET (ALRMTIME Set)............................ 230
BMXBOOTSZ (Boot Flash (IFM) Size ........................ 51
BMXCON (Bus Matrix Configuration) ......................... 46
BMXDKPBA (Data RAM Kernel Program 
Base Address).................................................... 47
BMXDRMSZ (Data RAM Size Register)..................... 50
BMXDUDBA (Data RAM User Data Base Address)... 48
BMXDUPBA (Data RAM User Program 
Base Address).................................................... 49
BMXPFMSZ (Program Flash (PFM) Size).................. 51
BMXPUPBA (Program Flash (PFM) User Program 
Base Address).................................................... 50
CiCFG (CAN Baud Rate Configuration) ................... 248
CiCON (CAN Module Control).................................. 246
CiFIFOBA (CAN Message Buffer Base Address)..... 265
CiFIFOCINn (CAN Module Message Index Register ‘n’)
270
CiFIFOCONn (CAN FIFO Control Register ‘n’) ........ 266
CiFIFOINTn (CAN FIFO Interrupt Register ‘n’)......... 268
CiFIFOUAn (CAN FIFO User Address Register ‘n’) . 270
CiFLTCON0 (CAN Filter Control 0) .......................... 256
CiFLTCON1 (CAN Filter Control 1) .......................... 258
CiFLTCON2 (CAN Filter Control 2) .......................... 260
CiFLTCON3 (CAN Filter Control 3) .......................... 262
CiFSTAT (CAN FIFO Status).................................... 253
CiINT (CAN Interrupt) ............................................... 250
CiRXFn (CAN Acceptance Filter ‘n’)......................... 264
CiRXMn (CAN Acceptance Filter Mask ‘n’) .............. 255
CiRXOVF (CAN Receive FIFO Overflow Status) ..... 254
CiTMR (CAN Timer) ................................................. 254
CiTREC (CAN Transmit/Receive Error Count)......... 253
CiVEC (CAN Interrupt Code).................................... 252
CM1CON (Comparator 1 Control) ............................ 273
CMSTAT (Comparator Control Register).................. 274
CNCONx (Change Notice Control for PORTx) ......... 158
CTMUCON (CTMU Control)..................................... 281
CVRCON (Comparator Voltage Reference Control) 277
DCHxCON (DMA Channel x Control) ......................... 95
DCHxCPTR (DMA Channel x Cell Pointer) .............. 102
DCHxCSIZ (DMA Channel x Cell-Size).................... 102
DCHxDAT (DMA Channel x Pattern Data) ............... 103
DCHxDPTR (Channel x Destination Pointer) ........... 101
DCHxDSA (DMA Channel x Destination 
Start Address)..................................................... 99
DCHxDSIZ (DMA Channel x Destination Size) ........ 100
DCHxECON (DMA Channel x Event Control) ............ 96
DCHxINT (DMA Channel x Interrupt Control)............. 97
DCHxSPTR (DMA Channel x Source Pointer) ......... 101
DCHxSSA (DMA Channel x Source Start Address) ... 99
DCHxSSIZ (DMA Channel x Source Size) ............... 100
DCRCCON (DMA CRC Control)................................. 92
DCRCDATA (DMA CRC Data) ................................... 94
DCRCXOR (DMA CRCXOR Enable) ......................... 94

 2014-2017 Microchip Technology Inc. DS60001290E-page  373
PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
DEVCFG0 (Device Configuration Word 0................. 293
DEVCFG1 (Device Configuration Word 1................. 295
DEVCFG2 (Device Configuration Word 2................. 297
DEVCFG3 (Device Configuration Word 3................. 299
DEVID (Device and Revision ID) .............................. 301
DMAADDR (DMA Address) ........................................ 91
DMAADDR (DMR Address) ........................................ 91
DMACON (DMA Controller Control) ........................... 90
DMASTAT (DMA Status) ............................................ 91
I2CxCON (I2C ‘x’ Control Register (‘x’ = 1 and 2)) ... 194
I2CxSTAT (I2C Status Register)............................... 196
ICxCON (Input Capture x Control) ............................ 175
IFSx (Interrupt Flag Status)......................................... 60
INTCON (Interrupt Control)......................................... 58
INTSTAT (Interrupt Status)......................................... 59
IPCx (Interrupt Priority Control)................................... 61
IPTMR Interrupt Proximity Timer) ............................... 59
NVMADDR (Flash Address) ....................................... 66
NVMCON (Programming Control) .............................. 65
NVMDATA (Flash Program Data)............................... 67
NVMKEY (Programming Unlock)................................ 66
NVMSRCADDR (Source Data Address)..................... 67
OCxCON (Output Compare x Control) ..................... 179
OSCCON (Oscillator Control) ..................................... 77
PMADDR (Parallel Port Address) ............................. 213
PMAEN (Parallel Port Pin Enable) ............................ 215
PMCON (Parallel Port Control) ................................. 209
PMDIN (Parallel Port Input Data)...................... 214, 219
PMDOUT (Parallel Port Output Data) ....................... 214
PMMODE (Parallel Port Mode)................................. 211
PMRADDR (Parallel Port Read Address) ................. 218
PMSTAT (Parallel Port Status (Slave Modes Only).. 216
PMWADDR (Parallel Port Write Address) ................ 217
REFOCON (Reference Oscillator Control) ................. 81
REFOTRIM (Reference Oscillator Trim) ..................... 83
RPnR (Peripheral Pin Select Output)........................ 157
RSWRST (Software Reset) ........................................ 72
RTCCON (RTC Control) ........................................... 223
RTCDATE (RTC Date Value) ................................... 228
RTCTIME (RTC Time Value) .................................... 227
SPIxCON (SPI Control)............................................. 184
SPIxCON2 (SPI Control 2)........................................ 187
SPIxSTAT (SPI Status)............................................. 188
T1CON (Type A Timer Control) ................................ 161
TxCON (Type B Timer Control) ................................ 166
U1ADDR (USB Address) .......................................... 123
U1BDTP1 (USB BDT Page 1) .................................. 125
U1BDTP2 (USB BDT Page 2) .................................. 126
U1BDTP3 (USB BDT Page 3) .................................. 126
U1CNFG1 (USB Configuration 1)............................. 127
U1CON (USB Control) .............................................. 121
U1EIE (USB Error Interrupt Enable) ......................... 119
U1EIR (USB Error Interrupt Status) .......................... 117
U1EP0-U1EP15 (USB Endpoint Control) ................. 128
U1FRMH (USB Frame Number High)....................... 124
U1FRML (USB Frame Number Low) ........................ 123
U1IE (USB Interrupt Enable)..................................... 116
U1IR (USB Interrupt)................................................. 115
U1OTGCON (USB OTG Control) ............................. 113
U1OTGIE (USB OTG Interrupt Enable) .................... 111
U1OTGIR (USB OTG Interrupt Status)..................... 110
U1OTGSTAT (USB OTG Status).............................. 112
U1PWRC (USB Power Control)................................ 114
U1SOF (USB SOF Threshold).................................. 125
U1STAT (USB Status) .............................................. 120
U1TOK (USB Token)................................................ 124
WDTCON (Watchdog Timer Control) ....................... 171
Reset SFR Summary.......................................................... 70
Resets ................................................................................ 69
Revision History................................................................ 375
RTCALRM (RTC ALARM Control).................................... 225
S
Serial Peripheral Interface (SPI) ....................................... 181
Software Simulator (MPLAB SIM) .................................... 307
Special Features............................................................... 291
T
Timer1 Module.................................................................. 159
Timer2/3, Timer4/5 Modules............................................. 163
Timing Diagrams
10-Bit Analog-to-Digital Conversion 
(ASAM = 0, SSRC<2:0> = 000)........................ 345
10-Bit Analog-to-Digital Conversion (ASAM = 1, 
SSRC<2:0> = 111, SAMC<4:0> = 00001) ....... 346
EJTAG ...................................................................... 352
External Clock .......................................................... 321
I/O Characteristics.................................................... 324
I2Cx Bus Data (Master Mode) .................................. 335
I2Cx Bus Data (Slave Mode) .................................... 338
I2Cx Bus Start/Stop Bits (Master Mode)................... 335
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 338
Input Capture (CAPx) ............................................... 328
OCx/PWM................................................................. 329
Output Compare (OCx) ............................................ 329
Parallel Master Port Read ........................................ 348
Parallel Master Port Write......................................... 349
Parallel Slave Port .................................................... 347
SPIx Master Mode (CKE = 0) ................................... 330
SPIx Master Mode (CKE = 1) ................................... 331
SPIx Slave Mode (CKE = 0) ..................................... 332
SPIx Slave Mode (CKE = 1) ..................................... 333
Timer1, 2, 3, 4, 5 External Clock .............................. 327
UART Reception....................................................... 206
UART Transmission (8-bit or 9-bit Data) .................. 206
Timing Requirements
CLKO and I/O ........................................................... 324
Timing Specifications
I2Cx Bus Data Requirements (Master Mode)........... 336
I2Cx Bus Data Requirements (Slave Mode)............. 339
Input Capture Requirements .................................... 328
Output Compare Requirements................................ 329
Simple OCx/PWM Mode Requirements ................... 329
SPIx Master Mode (CKE = 0) Requirements............ 330
SPIx Master Mode (CKE = 1) Requirements............ 331
SPIx Slave Mode (CKE = 1) Requirements.............. 333
SPIx Slave Mode Requirements (CKE = 0).............. 332
Timing Specifications (50 MHz)
SPIx Master Mode (CKE = 0) Requirements............ 356
SPIx Master Mode (CKE = 1) Requirements............ 356
SPIx Slave Mode (CKE = 1) Requirements.............. 357
SPIx Slave Mode Requirements (CKE = 0).............. 357
U
UART................................................................................ 199
USB On-The-Go (OTG).................................................... 105
V
V
CAP
 pin............................................................................ 302
Voltage Regulator (On-Chip) ............................................ 302

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 374  2014-2017 Microchip Technology Inc.

WWW Address..................................................................379

WWW, On-Line Support...................................................... 10

 2014-2017 Microchip Technology Inc. DS60001290E-page 375

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

APPENDIX A: REVISION HISTOR Y

Revision A (July 2014)

This is the initial released version of the document.

Revision B (September 2014)

This revision includes the following major changes,

which are referenced by their respective chapter in

Table A-1.

In addition, minor updates to text and formatting were

incorporated throughout the document.

Revision C (November 2014)

This revision includes the following major changes,

which are referenced by their respective chapter in

Table A-2.

In addition, minor updates to text and formatting were

incorporated throughout the document.

TABLE A-1: MAJOR SECTION UPDATES

Section Name Update Description

1.0 “Device Over vie w”

Added the USBOEN pin to the Pinout I/O Descriptions (see Table 1-1).

2.0 “Guidelines for Getting Started

with 32-bit MCUs”

Updated the Primary Oscillator loading capacitor calculations (see

2.8.1 “Crystal Oscillator Design Consideration”

Added

2.11 “Considerations When Interfacing to Remotely Powered

Circuits”

10.0 “USB On-The-Go (OTG)”

Updated the UOEMON bit definitions (see Register 10-20).

31.0 “40 MHz Electrical

Characteristics”

Updated DC Characteristics I/O Pin Input Specification parameters DI30 and

DI31 (see Table 31-8).

TABLE A-2: MAJOR SECTION UPDATES

Section Name Update Description

20.0 “Parallel Master Port (PMP)”

Added the RDSTART bit to the Parallel Port Control Register (see Table 20-1

and Register 20-1).

31.0 “40 MHz Electrical

Characteristics”

Updated the I

Operating Current DC Characteristics (see Table 31-5).

Updated the I

IDLE

Idle Current DC Characteristics (see Table 31-6).

Updated the I

Power Down Current DC Characteristics (see Table 31-7).

Updated the Internal FRC Accuracy (see Table 31-19).

32.0 “50 MHz Electrical

Characteristics”

Updated the I

Operating Current DC Characteristics (see Table 32-2).

Updated the I

IDLE

Idle Current DC Characteristics (see Table 32-3).

Updated the I

Power Down Current DC Characteristics (see Table 32-4).

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
DS60001290E-page  376  2014-2017 Microchip Technology Inc.
Revision D (April 2016)
This revision includes the following major changes, 
which are referenced by their respective chapter in 
Table A-2.
TABLE A-3: MAJOR SECTION UPDATES 
Section Name Update Description
1.0 “Devi ce Ov er vie w ”
Removed the USBOEN pin and all trace-related pins from the Pinout I/O 
Descriptions (see Tab l e 1-1).
2.0 “Guidelines for Getting Started 
with 32-bit MCUs” Section 2.7 “Trace”
 was removed.
Section 2.10 “Sosc Design Recommendation” 
was removed.
3.0 “CPU”
References to the Shadow Register Set (SRS), which is not supported by 
PIC32MX1XX/2XX/5XX 64/100-pin Family devices, were removed from 
3.1 “Features”
, 
3.2.1 “Execution Unit”
, and Coprocessor 0 Registers 
(Table 3-2).
4.0 “Memory Organization”
The SFR Memory Map was added (see Table 4-1).
5.0 “Interrupt Controller”
The Single Vector Shadow Register Set (SSO) bit (INTCON<16>) was 
removed (see Register 5-1).
10.0 “USB On-The-Go (OTG)”
The UOEMON bit (U1CNFG1<6>) was removed (see Register 10-20).
23.0 “Controller Area  Network 
(CAN)”
The CAN features (number of messages and FIFOs) were updated.
The PIC32 CAN Block Diagram was updated (see Figure 23-1).
The following registers were updated:
•C1FSTAT (see Register 23-6)
• C1RXOVF (see Register 23-7)
• C1RXFn (see Register 23-14)
• C1FIFOCONn (see Register 23-16)
• C1FIFOINTn (see Register 23-17)
• C1FIFOUAn (see Register 23-18)
• C1FIFOCIn (see Register 23-19)
The C1FLTCON4 through C1FLTCON7 registers were removed.
28.0 “Special Features”
The virtual addresses for the Device Configuration Word registers were 
updated (see Table 28-1).
31.0 “40 MHz Electrical 
Characteristics”
The EJTAG Timing Characteristics diagram was updated (see Figure 31-23).

 2014-2017 Microchip Technology Inc. DS60001290E-page 377

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

Revision E (October 2017)

In this revision, the Preliminary status was removed.

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

DS60001290E-page 378  2014-2017 Microchip Technology Inc.

NOTES:

 2014-2017 Microchip Technology Inc. DS60001290E-page  379
PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at 
www.microchip.com. This web site is used as a means 
to make files and information easily available to 
customers. Accessible by using your favorite Internet 
browser, the web site contains the following 
information:
•
Product Support
 – Data sheets and errata, 
application notes and sample programs, design 
resources, user’s guides and hardware support 
documents, latest software releases and archived 
software
•
General Technical Support
 – Frequently Asked 
Questions (FAQ), technical support requests, 
online discussion groups, Microchip consultant 
program member listing
•
Business of Microchip
 – Product selector and 
ordering guides, latest Microchip press releases, 
listing of seminars and events, listings of 
Microchip sales offices, distributors and factory 
representatives
CUSTOMER CHANGE NOTIFICATION 
SERVICE
Microchip’s customer notification service helps keep 
customers current on Microchip products. Subscribers 
will receive e-mail notification whenever there are 
changes, updates, revisions or errata related to a 
specified product family or development tool of interest.
To register, access the Microchip web site at 
www.microchip.com. Under “Support”, click on 
“Customer Change Notification” and follow the 
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance 
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, 
representative or Field Application Engineer (FAE) for 
support. Local sales offices are also available to help 
customers. A listing of sales offices and locations is 
included in the back of this document.
Technical s upport  is avail able through the  web si te 
at: http://microchip.com/support

 2014-2017 Microchip Technology Inc. DS60001290E-page 380

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

PRODUCT IDENTIFICATION SYS TEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office

Architecture MX = 32-bit RISC MCU core

Product Groups 1XX = General Purpose microcontroller family

2XX = USB microcontroller family

5XX = USB and CAN microcontroller family

Flash Memory Family F = Flash program memory

Program Memory Size 064 = 64 KB

128 = 128 KB

256 = 256 KB

512 = 512 KB

Pin Count H = 64-pin

L = 100-pin

Speed = 40 MHz (blank, no marking on package)

50 = 50 MHz

Temperature Range I = -40°C to +85°C (Industrial)

V = -40°C to +105°C (V-Temp)

Package PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)

PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)

PF = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)

MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)

Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)

ES = Engineering Sample

Example:

PIC32MX170F512H-50I/PT:



General Purpose PIC32, 32-bit RISC MCU,



512 KB program memory,



64-pin, Industrial temperature,



TQFP package.

Microchi p Brand

Architecture

Flash Memory Family

Pin Count

Prod uct Groups

Program Memor y Size (KB)

PIC32 MX 1XX F064 H T - 50 I / PT - XXX

Flash Memory Family

Speed

Pattern

Package

Temperature Range

Tape and Reel Flag (if applicable)

 2014-2017 Microchip Technology Inc. DS60001290E-page 381

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE

Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate,

dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,

KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,

MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,

RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O

are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company,

ETHERSYNCH, Hyper Speed Control, HyperLight Load,

IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,

BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,

EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip

Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,

MPLINK, MultiTRAK, NetDetach, Omniscient Code

Generation, PICDEM, PICDEM.net, PICkit, PICtail,

PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,

Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-2242-6

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microch ip rece iv ed ISO/T S -16 94 9:20 09 certific at ion for i ts worldw id e

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC

MCUs and dsPIC

DSCs, K

code hopping

devices, Serial EEPROMs, microperiph erals, nonvolat ile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949

DS60001290E-page 382  2014-2017 Microchip Technology Inc.

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10/10/17