1
Data sheet acquired from Harris Semiconductor
SCHS245B
Features
Buffered Inputs
Typical Propagation Delay
- 4ns at VCC = 5V, TA = 25oC, CL = 50pF
Exceeds 2kV ESD Protection per MIL-STD-883,
Method 3015
SCR-Latchup-Resistant CMOS Process and Circuit
Design
Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
Balanced Propagation Delays
AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50 Transmission Lines
Description
The ’AC245 and ’ACT245 are octal-bus transceivers that
utilize Advanced CMOS Logic technology. They are non-
inverting three-state bidirectional transceiver-buffers
intended for two-way transmission from “A” bus to “B” bus or
“B” bus to “A”. The logic level present on the direction input
(DIR) determines the data direction. When the output enable
input (OE) is HIGH, the outputs are in the high-impedance
state.
Pinout
CD54AC245, CD54ACT245
(CERDIP)
CD74AC245, CD74ACT245
(PDIP, SOIC, SSOP)
TOP VIEW
Ordering Information
PART
NUMBER TEMP.
RANGE (oC) PACKAGE
CD54AC245F3A -55 to 125 20 Ld CERDIP
CD74AC245E -55 to 125 20 Ld PDIP
CD74AC245M -55 to 125 20 Ld SOIC
CD74AC245SM -55 to 125 20 Ld SSOP
CD54ACT245F3A -55 to 125 20 Ld CERDIP
CD74ACT245E -55 to 125 20 Ld PDIP
CD74ACT245M -55 to 125 20 Ld SOIC
CD74ACT245SM -55 to 125 20 Ld SSOP
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DIR
A0
A1
A2
A3
A4
A6
A5
A7
GND
VCC
B0
B1
B2
OE
B3
B4
B5
B6
B7
September 1998 - Revised October 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
CD54/74AC245,
CD54/74ACT245
Octal-Bus Transceiver,
Three-State, Non-Inverting
[ /Title
(CD74
AC245
,
CD74
ACT24
5)
/Sub-
ject
(Octal-
Bus
Trans-
ceiver,
Three-
State,
Non-
Invert-
ing)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Advan
ced
CMOS
,Harris
Semi-
con-
2
Functional Diagram
TRUTH TABLE
CONTROL INPUTS
OPERATIONOE DIR
L L B Data to A Bus
L H A Data to B Bus
H X Isolation
H = High Level, L = Low Level, X = Irrelevant
To prevent excess currents in the High-Z (isolation) modes, all I/O
terminals should be terminated with 10k to 1M resistors.
18
17
16
15
13
11
12
14
2B0
B1
B2
B3
B4
B5
B6
B7
OE
DIR 1
19
4
9
3
5
6
7
8
A0
A1
A2
A3
A4
A5
A6
A7
CD54/74AC245, CD54/74ACT245
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
Thermal Resistance (Typical, Note 5) θJA (oC/W)
E Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SM Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX
AC TYPES
High Level Input Voltage VIH - - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V
5.5 3.85 - 3.85 - 3.85 - V
Low Level Input Voltage VIL - - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V
5.5 - 1.65 - 1.65 - 1.65 V
High Level Output Voltage VOH VIH or VIL -0.05 1.5 1.4 - 1.4 - 1.4 - V
-0.05 3 2.9 - 2.9 - 2.9 - V
-0.05 4.5 4.4 - 4.4 - 4.4 - V
-4 3 2.58 - 2.48 - 2.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
(Note 6, 7) 5.5 - - 3.85 - - - V
-50
(Note 6, 7) 5.5----3.85 - V
CD54/74AC245, CD54/74ACT245
4
Low Level Output Voltage VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V
0.05 3 - 0.1 - 0.1 - 0.1 V
0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75
(Note 6, 7) 5.5 - - - 1.65 - - V
50
(Note 6, 7) 5.5-----1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1 - ±1-±1µA
Three-State Leakage
Current IOZ VIH or VIL
VO=V
CC
or GND
- 5.5 - ±0.5 - ±5-±10 µA
Quiescent Supply Current
MSI ICC VCC or
GND 0 5.5 - 8 - 80 - 160 µA
ACT TYPES
High Level Input Voltage VIH - - 4.5 to
5.5 2-2-2-V
Low Level Input Voltage VIL - - 4.5 to
5.5 - 0.8 - 0.8 - 0.8 V
High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
(Note 6, 7) 5.5 - - 3.85 - - - V
-50
(Note 6, 7) 5.5----3.85 - V
Low Level Output Voltage VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75
(Note 6, 7) 5.5 - - - 1.65 - - V
50
(Note 6, 7) 5.5-----1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1 - ±1-±1µA
Three-State or Leakage
Current IOZ VIH or VIL
VO=V
CC
or GND
- 5.5 - ±0.5 - ±5-±10 µA
Quiescent Supply Current
MSI ICC VCC or
GND 0 5.5 - 8 - 80 - 160 µA
AdditionalSupplyCurrentper
Input Pin TTL Inputs High
1 Unit Load
ICC VCC
-2.1 - 4.5 to
5.5 - 2.4 - 2.8 - 3 mA
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50 transmission-line-drive capability at 85oC, 75 at 125oC.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX
CD54/74AC245, CD54/74ACT245
5
ACT Input Load Table
INPUT UNIT LOAD
An, Bn 0.83
OE 0.64
DIR 0.25
NOTE: Unit load is ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
Switching Specifications Input tr, tf = 3ns, CL= 50pF (Worst Case)
PARAMETER SYMBOL VCC (V)
-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX
AC TYPES
Propagation Delay,
Data to Output tPLH, tPHL 1.5 - - 96 - - 106 ns
3.3
(Note 9) 3.2 - 10.8 3 - 11.9 ns
5
(Note 10) 2.2 - 7.7 2.1 - 8.5 ns
Propagation Delay,
Output Disable to Output tPLZ, tPHZ 1.5 - - 159 - - 175 ns
3.3 4.7 - 15.9 4.4 - 17.5 ns
5 3.7 - 12.7 3.5 - 14 ns
Propagation Delay,
Output Enable to Output tPZL, tPZH 1.5 - - 159 - - 175 ns
3.3 5.6 - 19 5.3 - 21 ns
5 3.7 - 12.7 3.5 - 14 ns
Minimum (Valley) VOH During
Switching of Other Outputs
(Output Under Test Not Switching)
VOHV
See Figure 1 5 - 4 at
25oC- - 4 at
25oC-V
Maximum (Peak) VOL During
Switching of Other Outputs
(Output Under Test Not Switching)
VOLP
See Figure 1 5 - 1 at
25oC- - 1 at
25oC-V
Three-State Output Capacitance CO- - 15 - - 15 - pF
Input Capacitance CI- - -10- -10pF
Power Dissipation Capacitance CPD
(Note 11) - - 57 - - 57 - pF
ACT TYPES
Propagation Delay,
Data to Output tPLH, tPHL 5
(Note 10) 2.7 - 9.1 2.5 - 10 ns
Propagation Delay,
Output Disable to Output tPLZ, tPHZ 5 3.7 12.7 3.5 14 ns
Propagation Delay,
Output Enable to Output tPZL, tPZH 5 3.8 13.1 3.6 14.4 ns
Minimum (Valley) VOH During
Switching of Other Outputs
(Output Under Test Not Switching)
VOHV
See Figure 1 5 - 4 at
25oC- - 4 at
25oC-V
Maximum (Peak) VOL During
Switching of Other Outputs
(Output Under Test Not Switching)
VOLP
See Figure 1 5 - 1 at
25oC- - 1 at
25oC-V
CD54/74AC245, CD54/74ACT245
6
Three-State Output Capacitance CO- - 15 - - 15 - pF
Input Capacitance CI- - -10- -10pF
Power Dissipation Capacitance CPD
(Note 11) - - 57 - - 57 - pF
NOTES:
8. Limits tested 100%
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CPD is used to determine the dynamic power consumption per channel.
AC: PD = VCC2 fi(CPD + CL)
ACT: PD = VCC2 fi(CPD + CL) + VCC ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
NOTES:
12. Input pulses have the follo wing char acteristics: PRR 1MHz, tr = 3ns, SKEW 1ns .
13. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.
FIGURE 1. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
Switching Specifications Input tr, tf = 3ns, CL= 50pF (Worst Case) (Continued)
PARAMETER SYMBOL VCC (V)
-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX
OTHER
OUTPUTS
OUTPUT
UNDER
TEST
VOH
VOL
VOHV
VOLP
VOL
VOH
CD54/74AC245, CD54/74ACT245
7
NOTE:
14. For AC Series only: When VCC = 1.5V, RL = 1k.
FIGURE 2. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT
FIGURE 3. PROPAGATION DELAY TIMES
DUT WITH
THREE-
STATE
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
GND (tPHZ, tPZH)
OPEN (tPHL, tPLH)
OUTPUT RL
CL
50pF
2 VCC (tPLZ, tPZL)
(OPEN DRAIN)
500
RL
500OUT
INPUT LEVEL
90%
VS
10%
GND
tr = 3ns
tPZL
0.2 VCC VOL (VCC)
0.8 VCC
OUTPUTS
ENABLED
OUTPUTS
DISABLED
VS
VS
OUTPUTS
ENABLED
tPLZ
tPHZ tPZH
OUTPUTS
DISABLED
tf = 3ns
OUTPUT:
LOW TO OFF
TO LOW
OUTPUT:
HIGH TO OFF
TO HIGH
(NOTE 14)
tr = 3ns
INPUT
LEVEL
An
GND
Bn
tPLH
tf = 3ns
90%
VS
10%
VS
tPHL
DUT
OUTPUT
RL (NOTE)
OUTPUT
LOAD
500
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
FIGURE 4. PROPAGATION DELAY TIMES
AC ACT
Input Level VCC 3V
Input Switching Voltage, VS0.5 VCC 1.5V
Output Switching Voltage, VS0.5 VCC 0.5 VCC
CD54/74AC245, CD54/74ACT245
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD54AC245F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
CD54ACT245F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
CD74AC245E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74AC245EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74AC245M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC245M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC245M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC245M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC245ME4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC245MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC245SM96 ACTIVE SSOP DB 20 TBD Call TI Call TI
CD74AC245SM96E4 ACTIVE SSOP DB 20 TBD Call TI Call TI
CD74AC245SM96G4 ACTIVE SSOP DB 20 TBD Call TI Call TI
CD74ACT245E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74ACT245EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74ACT245M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT245M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT245M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT245M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT245ME4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT245MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD74ACT245SM96 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT245SM96E4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT245SM96G4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54AC245, CD54ACT245, CD74AC245, CD74ACT245 :
Catalog: CD74AC245, CD74ACT245
Military: CD54AC245, CD54ACT245
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74AC245M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
CD74ACT245M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
CD74ACT245SM96 SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74AC245M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74ACT245M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74ACT245SM96 SSOP DB 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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