Precision MEMS IMU Module
Data Sheet ADIS16467
Rev. C Document Feedback
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FEATURES
Triaxial, digital gyroscope
±125°/sec, ±500°/sec, ±2000°/sec dynamic range models
2°/hr in-run bias stability (ADIS16467-1)
0.15°/√hr angular random walk (ADIS16467-1 and
ADIS16467-2)
±0.05° axis to axis misalignment error
Triaxial, digital accelerometer, ±40 g
13 μg in-run bias stability
Triaxial, delta angle, and delta velocity outputs
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +85°C
SPI-compatible data communications
Programmable operation and control
Automatic and manual bias correction controls
Data ready indicator for synchronous data acquisition
External sync modes: direct, pulse, scaled, and output
On demand self test of inertial sensors
On demand self test of flash memory
Single-supply operation (VDD): 3.0 V to 3.6 V
2000 g mechanical shock survivability
Operating temperature range: −40°C to +105°C
APPLICATIONS
Navigation, stabilization, and instrumentation
Unmanned and autonomous vehicles
Smart agriculture and construction machinery
Factory/industrial automation, robotics
Virtual/augmented reality
Internet of Moving Things
GENERAL DESCRIPTION
The ADIS16467 is a precision, microelectric mechanical system
(MEMS), inertial measurement unit (IMU) that includes a triaxial
gyroscope and a triaxial accelerometer. Each inertial sensor in
the ADIS16467 combines with signal conditioning to optimize
dynamic performance. The factory calibration characterizes
each sensor for sensitivity, bias, alignment, linear acceleration
(gyroscope bias), and point of percussion (accelerometer location).
Therefore, each sensor has dynamic compensation formulas
that provide accurate sensor measurements over a broad set of
conditions.
The ADIS16467 provides a simple, cost effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared to the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation
systems. The serial peripheral interface (SPI) and register structure
provide a simple interface for data collection and configuration
control.
The ADIS16467 is in an aluminum module package that is
approximately 22.4 mm × 24.3 mm × 9 mm with a 14-lead
connector interface.
FUNCTIONAL BLOCK DIAGRAM
CONTROLLER
POWER
MANAGEMENT
CS
SCLK
DIN
DOUT
GND
VDD
DR
SYNC
RST
SPI
SELF TEST INPUT/OUTPUT
OUTPUT
DATA
REGISTERS
USER
CONTROL
REGISTERS
CALIBRATION
AND
FILTERS
ADIS16467
CLOCK
TRIAXIAL
GYROSCOPE
TEMPERATURE
SENSOR
TRIAXIAL
ACCELEROMETER
15439-001
Figure 1.
ADIS16467 Data Sheet
Rev. C | Page 2 of 34
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ....................................................... 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions ............................ 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Introduction ................................................................................ 11
Inertial Sensor Signal Chain ..................................................... 11
Register Structure ....................................................................... 12
Serial Peripheral Interface (SPI) ............................................... 13
Data Ready (DR) ........................................................................ 13
Reading Sensor Data .................................................................. 14
Device Configuration ................................................................ 15
User Register Memory Map .......................................................... 16
User Register Defintions ............................................................... 18
Gyroscope Data .......................................................................... 18
Delta Angles ................................................................................ 21
Delta Velocity ............................................................................. 22
Calibration .................................................................................. 24
Applications Information ............................................................. 31
Assembly and Handling Tips ................................................... 31
Power Supply Considerations .................................................. 31
Breakout Board ........................................................................... 31
Serial Port Operation ................................................................. 32
Digital Resolution of Gyroscopes and Accelerometers ........ 32
PC-Based Evaluation Tools ...................................................... 33
Packaging and Ordering Information ......................................... 34
Outline Dimensions ................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
2/2020—Rev. B to Rev. C
Changes to Table 1 ........................................................................... 3
Added Figure 18 ............................................................................. 10
Changes to Reading Sensor Data Section and Burst Read
Function Section ............................................................................. 14
4/2019—Rev. A to Rev. B
Changes to Serial Peripheral Interface (SPI) Section ................ 13
Changes to Figure 32 ..................................................................... 14
Changes to Table 10 ....................................................................... 18
Changes to Gyroscope Data Section ............................................ 18
Changes to Acceleration Data Section ........................................ 19
Added Accelerometer Data Formatting Section ........................ 20
Deleted Accelerometer Resolution Section ................................ 20
Added Serial Port Operation Section, Maximum Throughput
Section, and Serial Port SCLK Underrun/Overrun Conditions
Section .............................................................................................. 32
Added Digital Resolution of Gyroscopes and Accelerometers
Section .............................................................................................. 32
Moved Gyroscope Data Width (Digital Resolution) Section ........ 32
Moved Accelerometer Data Width (Digital Resolution) Section . 32
2/2019—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Figure 5 .......................................................................... 6
Added Figure 11, Figure 12, and Figure 13; Renumbered
Sequentially ........................................................................................ 9
Added Figure 14, Figure 15, Figure 16, and Figure 17 .............. 10
Changes to Figure 18, Figure 19, and Figure 20 ........................ 11
Changes to Figure 22 and Figure 23 ............................................ 12
Added Gyroscope Data Width (Digital Resolution) Section ... 18
Changes to Gyroscope Measurement Range/Scale Factor Section,
Table 11, Table 12, Table 13, Table 17, Table 21, and Table 25 19
Added Accelerometer Data Width (Digital Resolution) Section
........................................................................................................... 20
Change to Calibration, Accelerometer Bias (XA_BIAS_LOW
and XA_BIAS_HIGH) Section ..................................................... 25
Change to Filter Control Register (FILT_CTRL) Section ........ 26
Changes to Direct Sync Mode Section ........................................ 27
Changes to Pulse Sync Mode Section .......................................... 28
Changes to Sensor Self Test Section ............................................ 29
Changes to Figure 52 ..................................................................... 31
Changes to Outline Dimensions .................................................. 33
12/2017—Revision 0: Initial Version
Data Sheet ADIS16467
Rev. C | Page 3 of 34
SPECIFICATIONS
Case temperature (TC) = 25°C, VDD = 3.3 V, angular rate = 0°/sec, and dynamic range = ±2000°/sec ± 1 g, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
GYROSCOPES
Dynamic Range ADIS16467-1 ±125 °/sec
ADIS16467-2 ±500 °/sec
ADIS16467-3 ±2000 °/sec
Sensitivity ADIS16467-1, 16-bit 160 LSB/°/sec
ADIS16467-2, 16-bit 40 LSB/°/sec
ADIS16467-3, 16-bit 10 LSB/°/sec
ADIS16467-1, 32-bit 10,485,760 LSB/°/sec
ADIS16467-2, 32-bit 2,621,440 LSB/°/sec
ADIS16467-3, 32-bit 655,360 LSB/°/sec
Repeatability1 −40°C ≤ TC ≤ +85°C, 1 σ ±0.3 %
Error over Temperature −40°C ≤ TC ≤ +85°C, 1 σ ±0.1 %
Misalignment Error Axis to axis, 1 σ ±0.05 Degrees
Nonlinearity2 ADIS16467-1, full scale (FS) = 125°/sec 0.2 % FS
ADIS16467-2, FS = 500°/sec 0.2 % FS
ADIS16467-3, FS = 2000°/sec 0.25 % FS
Bias
In-Run Bias Stability ADIS16467-1, 1 σ 2 °/hr
ADIS16467-2, 1 σ 2.5 °/hr
ADIS16467-3, 1 σ 6 °/hr
Angular Random Walk ADIS16467-1, 1 σ 0.15 °/√hr
ADIS16467-2, 1 σ 0.15 °/√hr
ADIS16467-3, 1 σ 0.26 °/√hr
Repeatability1 −40°C ≤ TC ≤ +85°C, 1 σ ±0.4 °/sec
Error over Temperature −40°C ≤ TC ≤ +85°C, 1 σ ±0.2 °/sec
Linear Acceleration Effect Any direction, 1 σ 0.009 °/sec/g
Vibration Rectification Effect Random vibration, 2 g rms, bandwidth = 50 Hz to 2 kHz 0.0005 °/sec/g2
Output Noise ADIS16467-1, 1 σ, no filtering, x-axis 0.05 °/sec rms
ADIS16467-1, 1 σ, no filtering, y-axis and z-axis 0.07 °/sec rms
ADIS16467-2, 1 σ, no filtering, x-axis 0.05 °/sec rms
ADIS16467-2, 1 σ, no filtering, y-axis and z-axis 0.08 °/sec rms
ADIS16467-3, 1 σ, no filtering, x-axis 0.11 °/sec rms
ADIS16467-3, 1 σ, no filtering, y-axis and z-axis 0.16 °/sec rms
Rate Noise Density ADIS16467-1, 10 Hz to 40 Hz, x-axis 0.002 °/sec/√Hz rms
ADIS16467-1, 10 Hz to 40 Hz, y-axis and z-axis 0.003 °/sec/√Hz rms
ADIS16467-2, 10 Hz to 40 Hz, x-axis 0.002 °/sec/√Hz rms
ADIS16467-2, 10 Hz to 40 Hz, y-axis and z-axis 0.003 °/sec/√Hz rms
ADIS16467-3, 10 Hz to 40 Hz, x-axis 0.004 °/sec/√Hz rms
ADIS16467-3, 10 Hz to 40 Hz, y-axis and z-axis 0.0065 °/sec/√Hz rms
3 dB Bandwidth 550 Hz
Sensor Resonant Frequency 66 kHz
ACCELEROMETERS3 Each axis
Dynamic Range ±40 g
Sensitivity 32-bit data format 52,428,800 LSB/g
Repeatability1 −40°C ≤ TC ≤ +85°C, 1 σ ±0.2 %
Error over temperature −40°C ≤ TC ≤ +85°C, 1 σ ±0.1 %
Misalignment Error Axis to axis ±0.05 Degrees
Nonlinearity Best fit straight line, ±10 g ±0.02 % FS
Best fit straight line, ±20 g ±0.4 % FS
Best fit straight line, ±40 g ±1.5 % FS
ADIS16467 Data Sheet
Rev. C | Page 4 of 34
Parameter Test Conditions/Comments Min Typ Max Unit
Bias
In-Run Bias Stability 1 σ, y-axis and z-axis 13 μg
Velocity Random Walk 1 σ 0.037 m/sec/√hr
Repeatability1 −40°C ≤ TC ≤ +85°C, 1 σ ±6 mg
Error over Temperature −40°C ≤ TC ≤ +85°C, 1 σ ±3 mg
Output Noise No filtering 2.3 mg rms
Noise Density Bandwidth = 10 Hz to 40 Hz, no filtering 100 μg/√Hz rms
3 dB Bandwidth 600 Hz
Sensor Resonant Frequency Y-axis and z-axis 5.65 kHz
X-axis 5.25 kHz
TEMPERATURE SENSOR
Scale Factor Output = 0x0000 at 0°C (±5°C) 0.1 °C/LSB
LOGIC INPUTS4
Input Voltage
High, VIH 2.0 V
Low, VIL 0.8 V
RST Pulse Width 1 μs
CS Wake-Up Pulse Width 20 μs
Input Current
Logic 1, IIH V
IH = 3.3 V 10 μA
Logic 0, IIL V
IL = 0 V
All Pins Except RST 10 μA
RST Pin 0.33 mA
Input Capacitance, CIN 10 pF
DIGITAL OUTPUTS
Output Voltage
High, VOH I
SOURCE = 0.5 mA 2.4 V
Low, VOL I
SINK = 2.0 mA 0.4 V
FLASH MEMORY Endurance5 10000 Cycles
Data Retention6 T
J = 85°C 20 Years
FUNCTIONAL TIMES7 Time until data is available
Power-On Start-Up Time 259 ms
Reset Recovery Time Register GLOB_CMD, Bit 7 = 1 (see Table 113) 198 ms
RST pulled low, then restored to high8 198 ms
Factory Calibration Restore Register GLOB_CMD, Bit 1 = 1 (see Table 113) 142 ms
Flash Memory Backup Register GLOB_CMD, Bit 3 = 1 (see Table 113) 72 ms
Flash Memory Test Time Register GLOB_CMD, Bit 4 = 1 (see Table 113) 32 ms
Self Test Time9 Register GLOB_CMD, Bit 2 = 1 (see Table 113) 14 ms
CONVERSION RATE 2000 SPS
Initial Clock Accuracy 3 %
Sync Input Clock 1.9 2.1 kHz
POWER SUPPLY, VDD Operating voltage range 3.0 3.6 V
Power Supply Current10 Normal mode, VDD = 3.3 V 44 55 mA
1 Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of High-Temperature Operating Life (HTOL) at +105°C.
2 This measurement is based on the deviation from a best fit linear model.
3 All specifications associated with the accelerometers relate to the full-scale range of ±40 g, unless otherwise noted.
4 The digital input/output signals use a 3.3 V system.
5 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.
6 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.
7 These times do not include thermal settling and internal filter response times, which may affect overall accuracy.
8 The RST line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery.
9 The self test time can extend when using external clock rates lower than 2000 Hz.
10 Power supply current transients can reach 100 mA during initial startup or reset recovery.
Data Sheet ADIS16467
Rev. C | Page 5 of 34
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Parameter Description
Normal Mode Burst Read Mode
Unit Min Typ Max Min1 Typ Max
fSCLK Serial clock 0.1 2 0.1 1 MHz
tSTALL Stall period between data 16 N/A μs
tREADRATE Read rate 24 μs
tCS Chip select to SCLK edge 200 200 ns
tDAV DOUT valid after SCLK edge 25 25 ns
tDSU DIN setup time before SCLK rising edge 25 25 ns
tDHD DIN hold time after SCLK rising edge 50 50 ns
tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 ns
tDR, tDF DOUT rise/fall times 5 12.5 5 12.5 ns
tSFS CS high after SCLK edge 0 0 ns
t1 Input sync positive pulse width; pulse sync mode,
Register MSC_CTRL, Bits[4:1] (binary, see Table 105)
5 5 μs
tSTDR Input sync to data ready valid transition
Direct sync mode, Register MSC_CTRL, Bits[4:2] (binary, see Table 105) 256 256 μs
Pulse sync mode, Register MSC_CTRL, Bits[4:2] (binary, see Table 105) 256 256 μs
tNV Data invalid time 20 20 μs
t2 Input sync period2 477 477 μs
1 N/A means not applicable.
2 This specification is rounded up from the cycle time that comes from the maximum input clock frequency (2100 Hz).
Timing Diagrams
CS
SCLK
DOUT
DIN
1 2 3 4 5 6 15 16
R/W A5A6 A4 A3 A2 D2
MSB DB14
D1 LSB
DB13 DB12 DB10DB11 DB2 LSBDB1
t
CS
t
DR
t
SFS
t
DF
t
DAV
t
SCLKR
t
SCLKF
t
DHD
t
DSU
15439-002
Figure 2. SPI Timing and Sequence Diagram
CS
SCLK
t
STALL
t
READR ATE
15439-003
Figure 3. Stall Time and Data Rate Timing Diagram
ADIS16467 Data Sheet
Rev. C | Page 6 of 34
SYNC
DR
t
1
t
2
t
NV
t
STDR
15439-004
Figure 4. Input Clock Timing Diagram, Pulse Sync Mode, Register MSC_CTRL, Bits[4:2] = 101 (Binary)
SYNC
DR
t
2
t
NV
t
STDR
t
1
15439-005
Figure 5. Input Clock Timing Diagram, Direct Sync Mode, Register MSC_CTRL, Bits[4:2] = 001 (Binary)
Data Sheet ADIS16467
Rev. C | Page 7 of 34
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Mechanical Shock Survivability
Any Axis, Unpowered 2000 g
Any Axis, Powered 2000 g
VDD to GND −0.3 V to +3.6 V
Digital Input Voltage to GND −0.3 V to VDD + 0.2 V
Digital Output Voltage to GND −0.3 V to VDD + 0.2 V
Calibration Temperature Range −40°C to +85°C
Operating Temperature Range −40°C to +105°C
Storage Temperature Range1 −65°C to +150°C
Barometric Pressure 2-bar
1 Extended exposure to temperatures that are lower than −40°C or higher
than +105°C can adversely affect the accuracy of the factory calibration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
The ADIS16467 is a multichip module that includes many active
components. The values in Table 4 identify the thermal
response of the hottest component inside of the ADIS16467,
with respect to the overall power dissipation of the module.
This approach enables a simple method for predicting the
temperature of the hottest junction, based on either ambient or
case temperature.
For example, when the ambient temperature is 70°C, the hottest
junction temperature (TJ) inside of the ADIS16467 is 75.3°C.
TJ = θJA × VDD × IDD + 70°C
TJ = 36.5°C/W × 3.3 V × 0.044 A + 70°C
TJ = 75.3°C
Table 4. Thermal Resistance
Package Type θJA1 θ
JC2 Mass (g)
ML-14-63 36.5°C/W 16.9C/W 15
1 θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure.
2 θJC is the junction to case thermal resistance.
3 Thermal impedance values come from direct observation of the hottest
temperature inside of the ADIS16467, when it is attached to an FR4-08 PCB
that has two metal layers and has a thickness of 0.063 inches.
ESD CAUTION
ADIS16467 Data Sheet
Rev. C | Page 8 of 34
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC
DOUT
CS
RST
DNC DNC
DNC
DR
SCLK
DIN
DNC
DNC VDD
GND
13
14
11
12
9
10
7
8
5
6
3
4
1
2
ADIS16467
TOP VIEW
(Not to Scale)
NOTES
1. THIS REPRESENTS THE PIN ASSIGNMENTS WHEN
LOOKING DOWNAT THE CONNECTOR. SEE FIGURE 7.
2. MATING CONNECTOR:
SAMTEC CLM-107-02 SERIES OR EQUIVALENT.
3. DNC = DO NOT CONNECT.
15439-006
Figure 6. Pin Assignments, Bottom View
PIN 1
PIN 14
15439-007
Figure 7. Pin Assignments, Package Level View
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type Description
1 DR Output Data Ready Indicator.
2 SYNC Input/output External Sync Input/Output, per MSC_CTRL. See Table 105.
3 SCLK Input SPI Serial Clock.
4 DOUT Output SPI Data Output. This pin clocks the output on the SCLK falling edge.
5 DIN Input SPI Data Input. This pin clocks the input on the SCLK rising edge.
6 CS Input SPI Chip Select.
7 DNC Not applicable Do Not Connect. Do not connect to this pin.
8 RST Input Reset.
9 DNC Not applicable Do Not Connect. Do not connect to this pin.
10 DNC Not applicable Do Not Connect. Do not connect to this pin.
11 VDD Supply Power Supply.
12 DNC Not applicable Do Not Connect. Do not connect to this pin.
13 GND Supply Power Ground.
14 DNC Not applicable Do Not Connect. Do not connect to this pin.
Data Sheet ADIS16467
Rev. C | Page 9 of 34
TYPICAL PERFORMANCE CHARACTERISTICS
0.001 0.01 0.1 1 10 100 1000 10000 100000
INTEGRATION PERIOD (Seconds)
0.1
1
10
100
1000
ALLAN DEVI
A
TION (Degrees/Hour)
X-AXIS
Y-AXIS
Z-AXIS
15439-008
Figure 8. Gyroscope Allan Deviation, TC = 25°C, ADIS16467-1
0.001 0.01 0.1 1 10 100 1000 10000 100000
INTEGRATION PERIOD (Seconds)
0.1
1
10
100
1000
ALLAN DEVIATION (Degrees/Hour)
X-AXIS
Y-AXIS
Z-AXIS
15439-009
Figure 9. Gyroscope Allan Deviation, TC = 25°C, ADIS16467-2
0.001 0.01 0.1 1 10 100 1000 10000 100000
INTEGRATION PERIOD (Seconds)
0.1
1
10
100
1000
ALLAN DEVIATION (Degrees/Hour)
X-AXIS
Y-AXIS
Z-AXIS
15439-010
Figure 10. Gyroscope Allan Deviation, TC = 25°C, ADIS16467-3
0.001 0.01 0.1 1 10 100 1000 10000 100000
INTEGRATION PERIOD (Seconds)
ALLAN DEVIATION (µg)
X-AXIS
Y-AXIS
Z-AXIS
15437-011
Figure 11. Accelerometer Allan Deviation, TC = 25°C
0.4
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–60 –40 –20 0 20 40 60 80 100
SENSITIVITY ERROR (%)
AMBIENT TEMPERATURE (°C)
15439-112
µ
µ – 1σ
µ + 1σ
Figure 12. ADIS16467-1 Gyroscope Sensitivity Error vs. Ambient Temperature
0.4
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–60 –40 –20 0 20 40 60 80 100
SENSITIVITY ERROR (%)
AMBIENT TEMPERATURE (°C)
15439 -113
µ – 1σ
µ + 1σ
µ
Figure 13. ADIS16467-2 Gyroscope Sensitivity Error vs. Ambient Temperature
ADIS16467 Data Sheet
Rev. C | Page 10 of 34
0.4
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–60 –40 –20 0 20 40 60 80 100
SENSITIVITY ERROR (%)
AMBIENT TEMPERATURE (°C)
15439-114
µ – 1σ
µ + 1σ
µ
Figure 14. ADIS16467-3 Gyroscope Sensitivity Error vs. Ambient Temperature
0.5
0.4
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–60 –40 –20 0 20 40 60 80 100
BIAS ERROR (°/sec)
AMBIENT TEMPERATURE (°C)
15439-115
µ – 1σ
µ + 1σ
µ
Figure 15. ADIS16467-1 Gyroscope Bias Error vs. Ambient Temperature
0.5
0.4
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–60 –40 –20 0 20 40 60 80 100
BIAS ERROR (°/sec)
AMBIENT TEMPERATURE (°C)
15439-116
µ – 1σ
µ + 1σ
µ
Figure 16. ADIS16467-2 Gyroscope Bias Error vs. Ambient Temperature
0.5
0.4
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–60 –40 –20 0 20 40 60 80 100
BIAS ERROR (°/sec)
AMBIENT TEMPERATURE (°C)
15439-117
µ – 1σ
µ + 1σ
µ
Figure 17. ADIS16467-3 Gyroscope Bias Error vs. Ambient Temperature
0 5 10 15 20 25 30 35
POWER-ON TIME (Minutes)
BIAS ERROR (Degrees/Second)
15439-118
Figure 18. ADIS16467-3 Gyroscope Bias Error vs. Power-On Time at 25°C.
(Applicable to All ADIS16467 Models)
Data Sheet ADIS16467
Rev. C | Page 11 of 34
THEORY OF OPERATION
INTRODUCTION
When using the factory default configuration for all user
configurable control registers, the ADIS16467 initializes and
automatically starts a continuous process of sampling, processing,
and loading calibrated sensor data into the output registers at a
rate of 2000 SPS.
INERTIAL SENSOR SIGNAL CHAIN
Figure 19 shows the basic signal chain for the inertial sensors in the
ADIS16467. This signal chain produces an update rate of 2000
SPS in the output data registers when it operates in internal clock
mode (default, see Register MSC_CTRL, Bits[4:2] in Table 105).
OUTPUT
DATA
REGISTERS
AVERAGING
DECIMATING
FILTER
CALIBRATION
BARTLETT
WINDOW
FIR
FILTER
MEMS
SENSORS
15439-011
Figure 19. Signal Processing Diagram, Inertial Sensors
Gyroscope Data Sampling
The three gyroscopes produce angular rate measurements around
three orthogonal axes (x, y, and z). Figure 20 shows the data
sampling plan for each gyroscope when the ADIS16467 operates in
internal clock mode (default, see Register MSC_CTRL, Bits[4:2] in
Table 105). Each gyroscope has an analog-to-digital converter
(ADC) and sample clock (fSG) that drives data sampling at a rate
of 4100 Hz (±5%). The internal processor reads and processes
this data from each gyroscope at a rate of 2000 Hz (fSM).
MEMS
GYROSCOPE
f
SM
= 2000Hz
INTERNAL
DATA
REGISTER
TO
BARTLETT
WINDOW
FIR FILTER
f
SG
= 4100Hz
ADC
15439-012
Figure 20. Gyroscope Data Sampling
Accelerometer Data Sampling
The three accelerometers produce linear acceleration measurements
along the same orthogonal axes (x, y, and z) as the gyroscopes.
Figure 21 shows the data sampling plan for each accelerometer
when the ADIS16467 operates in internal clock mode (default,
see Register MSC_CTRL, Bits[4:2] in Table 105).
MEMS
ACCELEROMETER
2 ×
f
SM
= 4000Hz
ADC 1
2
2
n = 1
a(n)
÷2
15439-013
TO
BARTLETT
WINDOW
FIR FILTER
Figure 21. Accelerometer Data Sampling
External Clock Options
The ADIS16467 provides three different modes of operation
that support the device using an external clock to control the
internal processing rate (fSM in Figure 20 and Figure 21)
through the SYNC pin. Register MSC_CTRL (see Table 105)
provides the configuration options for these external clock
modes in Bits[4:2].
Inertial Sensor Calibration
The inertial sensor calibration function for the gyroscopes and the
accelerometers has two components: factory calibration and
user calibration (see Figure 22).
TO
AVERAGING
DECIMATING
FILTER
FACTORY
CALIBRATION
USER
CALIBRATION
FROM
BARTLETT
WINDOW
FIR FILTER
15439-014
Figure 22. Inertial Sensor Calibration Processing
The factory calibration of the gyroscope applies the following
correction formulas to the data of each gyroscope:
ZC
YC
XC
333231
232221
131211
Z
Y
X
Z
Y
X
333231
232221
131211
ZC
YC
XC
a
a
a
lll
lll
lll
b
b
b
ω
ω
ω
mmm
mmm
mmm
ω
ω
ω
where:
ωXC, ωYC, and ωZC are the gyroscope outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
ωX, ωY, and ωZ are the gyroscope outputs (precalibration).
bX, bY, and bZ provide bias correction.
l11, l12, l13, l21, l22, l23, l31, l32, and l33 provide linear g correction
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
All correction factors in this relationship come from direct
observation of the response of each gyroscope at multiple
temperatures over the calibration temperature range (−40°C ≤
TC ≤ +85°C). These correction factors are stored in the flash
memory bank, but they are not available for observation or
configuration. Register MSC_CTRL, Bit 7 (see Table 105) provides
the only user configuration option for the factory calibration of
the gyroscopes: an on/off control for the linear g compensation.
See Figure 45 for more details on the user calibration options
available for the gyroscopes.
ADIS16467 Data Sheet
Rev. C | Page 12 of 34
The factory calibration of the accelerometer applies the following
correction formulas to the data of each accelerometer:
2
ZC
2
YC
2
XC
3231
2321
1312
Z
Y
X
Z
Y
X
333231
232221
131211
ZC
YC
XC
ω
ω
ω
pp
pp
pp
b
b
b
a
a
a
mmm
mmm
mmm
a
a
a
0
0
0
where:
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
aX, aY, and aZ are the accelerometer outputs (precalibration).
bX, bY, and bZ provide bias correction.
p12, p13, p21, p23, p31 and p32 provide a point of percussion
alignment correction (see Figure 48).
ω2XC, ω2YC, and ω2ZC are the square of the gyroscope outputs
(post calibration).
All of the correction factors in this relationship come from direct
observation of the response of each accelerometer at multiple
temperatures, over the calibration temperature range (−40°C ≤
TC ≤ +85°C). These correction factors are stored in the flash
memory bank, but they are not available for observation or
configuration. Register MSC_CTRL, Bit 6 (see Table 105) provides
the only user configuration option for the factory calibration of
the accelerometers: an on/off control for the point of percussion,
alignment function. See Figure 46 for more details on the user
calibration options available for the accelerometers.
Bartlett Window FIR Filter
The Bartlett window finite impulse response (FIR) filter (see
Figure 23) contains two averaging filter stages, in a cascade
configuration. The FILT_CTRL register (see Table 101) provides
the configuration controls for this filter.
FROM
MEMS
SENSOR
TO
FACTORY
CALIBRATION
1
N
N
n = 1
ω(n)
1
N
N
n = 1
ω(n)
15439-015
Figure 23. Bartlett Window FIR Filter Signal Path
Averaging/Decimating Filter
The second digital filter averages multiple samples together to
produce each register update. In this type of filter structure, the
number of samples in the average is equal to the reduction in the
update rate for the output data registers. The DEC_RATE register
(see Table 109) provides the configuration controls for this filter.
FROM
USER
CALIBRATION ÷N
TO OUTPUT
REGISTERS
Σ
1
N
N
n = 1
ω(n)
15439-016
Figure 24. Averaging/Decimating Filter Diagram
REGISTER STRUCTURE
All communication between the ADIS16467 and an external
processor involves either reading the contents of an output register
or writing configuration or command information to a control
register. The output data registers include the latest sensor data,
error flags, and identification information. The control registers
include sample rate, filtering, calibration, and diagnostic options.
Each user accessible register has two bytes (upper and lower),
each of which has a unique address. See Table 8 for a detailed
list of all user registers and the corresponding addresses.
TRIAXIAL
GYROSCOPE
TEMPERATURE
SENSOR
TRIAXIAL
ACCELEROMETER
OUTPUT
REGISTERS
CONTROL
REGISTERS
CONTROLLER
SENSOR
SIGNAL
PROCESSING
SPI
15439-017
Figure 25. Basic Operation of the ADIS16467
Data Sheet ADIS16467
Rev. C | Page 13 of 34
SERIAL PERIPHERAL INTERFACE (SPI)
The SPI provides access to the user registers (see Table 8).
Figure 26 shows the most common connections between the
ADIS16467 and a SPI master device, which is often an embedded
processor that has an SPI-compatible interface. In this example,
the SPI master uses an interrupt service routine to collect data
every time the data ready (DR) signal pulses.
Additional information on ADIS16467 SPI can be found in the
Applications Information section of this datasheet.
CS
SYSTEM
PROCESSOR
SPI MASTER
VDD
INPUT/OUTPUT LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
SCLK
DIN
DR
DOUT
SS
SCLK
MOSI
IRQ
MISO
ADIS16467
+3.3V
15439-018
Figure 26. Electrical Connection Diagram
Table 6. Generic SPI Master Pin Mnemonics and Functions
Mnemonic Function
SS Slave select
SCLK Serial clock
MOSI Master output, slave input
MISO Master input, slave output
IRQ Interrupt request
Embedded processors typically use control registers to configure
serial ports for communicating with SPI slave devices, such as
the ADIS16467. Table 7 provides a list of settings that describe
the SPI protocol of the ADIS16467. The initialization routine
of the master processor typically establishes these settings using
firmware commands to write them into the control registers.
Table 7. Generic Master Processor SPI Settings
Processor Setting Description
Master ADIS16467 operates as slave
SCLK ≤ 2 MHz1 Maximum serial clock rate
SPI Mode 3 CPOL = 1 (polarity), CPHA = 1 (phase)
MSB First Mode Bit sequence, see Figure 31 for coding
16-Bit Mode Shift register and data length
1 A burst mode read requires this value to be ≤1 MHz (see Table 2 for more
information).
DATA READY (DR)
The factory default configuration provides users with a DR signal
on the DR pin (see Table 5) that pulses when the output data
registers update. Connect the DR pin to a pin on the embedded
processor to trigger data collection, on the second edge of this
pulse. Register MSC_CTRL, Bit 0 (see Table 105), controls the
polarity of this signal. In Figure 27, Register MSC_CTRL, Bit 0 = 1,
which means that data collection must start on the rising edges
of the DR pulses.
DR
ACTIVE INACTIVE
15439-019
Figure 27. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default)
During the start-up and reset recovery processes, the DR signal
may exhibit some transient behavior before data production
begins. Figure 28 shows an example of the DR behavior during
startup, and Figure 29 and Figure 30 provide examples of the
DR behavior during recovery from reset commands.
VDD
DR
START-UP TIME
TIME THAT VDD > 3V
PULSING INDICATES
DATA PRODUCTION
15439-020
Figure 28. Data Ready Response During Startup
DR
RESET RECOVERY TIME
SOFTWARE RESET COMMAND
GLOB_CMD[7] = 1
DR PULSING
RESUMES
15439-021
Figure 29. Data Ready Response During Reset
(Register GLOB_CMD, Bit 7 = 1) Recovery
DR
RST
RESET RECOVERY TIME
RST PIN
RELEASED
DR PULSING
RESUMES
15439-022
Figure 30. Data Ready Response During Reset (RST = 0) Recovery
ADIS16467 Data Sheet
Rev. C | Page 14 of 34
R/W R/W
A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
CS
SCLK
DIN
DOUT
A6 A5
D13D14D15
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
15439-023
Figure 31. SPI Communication Bit Sequence
CS 12311
SCLK
DIN
DOUT
0x6800
DIAG_STAT XGYRO_OUT CHECKSUM
15439-024
Figure 32. Burst Read Sequence
15439-025
CS
SCLK
DIN
DOUT
DIN = 0x7200 = 0111 0010 0000 0000
DOUT = 0100 0000 0101 0011 = 0x4053 = 16467 (PROD_ID)
HIGH-ZHIGH-Z
Figure 33. SPI Signal Pattern, Repeating Read of the PROD_ID Register
READING SENSOR DATA
Reading a single register requires two 16-bit cycles on the SPI:
one to request the contents of a register and another to receive
those contents. The 16-bit command code (see Figure 31) for a
read request on the SPI has three parts: the read bit (R/W = 0),
either address of the register, [A6:A0], and eight don’t care bits,
[DC7:DC0]. Figure 34 shows an example that includes two register
reads in succession. This example starts with DIN = 0x0C00, to
request the contents of the Z_GYRO_LOW register, and follows
with 0x0E00, to request the contents of the Z_GYRO_OUT
register. The sequence in Figure 34 also shows full duplex mode
of operation, which means that the ADIS16467 can receive
requests on DIN while also transmitting data out on DOUT
within the same 16-bit SPI cycle.
DIN
DOUT
0x0C00 0x0E00 NEXT
ADDRESS
Z_GYRO_LOW Z_GYRO_OUT
15439-026
Figure 34. SPI Read Example
Figure 33 shows an example of the four SPI signals when reading
the PROD_ID register (see Table 121) in a repeating pattern.
This pattern can be helpful when troubleshooting the SPI
interface setup and communications because the signals are
the same for each 16-bit sequence, except during the first cycle.
Note that the read and write functions using the SPI interface
are always 16-bits long. The only exception is the burst read
function described in the Burst Read Function section.
Burst Read Function
The burst read function provides a way to read the same group
of output data registers using a continuous stream of bits at an
SCLK rate of up to 1 MHz. This method does not require a stall
time between each 16-bit segment (see Figure 3). To start this
mode, set DIN = 0x6800 to read register 0x6800, and then read
each register in the sequence out of DOUT while keeping CS
low for the entire 176-bit sequence (see Figure 32). It is critical
to read all 176 bits before the CS pin goes high.
The sequence of registers (and checksum value) in the burst
read response depends on which sample clock mode that the
ADIS16467 is operating in (Register MSC_CTRL, Bits[4:2], see
Table 105). In all clock modes, except when operating in scaled
sync mode (Register MSC_CTRL, Bits[4:2] = 010), the burst
read response includes the following registers and value:
DIAG_STAT, X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT,
X_ACCL_OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT,
DATA_CNTR, and the checksum value. In these cases, use the
following formula to verify the checksum value, treating each
byte in the formula as an independent, unsigned, 8-bit number:
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]
Data Sheet ADIS16467
Rev. C | Page 15 of 34
When operating in scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010), the burst read response includes the following
registers and value: DIAG_STAT, X_GYRO_OUT, Y_GYRO_
OUT, Z_GYRO_OUT, X_ACCL_OUT, Y_ACCL_OUT,
Z_ACCL_OUT, TEMP_OUT, TIME_STAMP, and the checksum
value. In this case, use the following formula to verify the
checksum value, treating each byte in the formula as an
independent, unsigned, 8-bit number:
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
TIME_STAMP, Bits[15:8] + TIME_STAMP, Bits[7:0]
DEVICE CONFIGURATION
Each configuration register contains 16 bits (two bytes). Bits[7:0]
contain the low byte, and Bits[15:8] contain the high byte of each
register. Each byte has a unique address in the user register map
(see Table 8). Updating the contents of a register requires writing
to both bytes in the following sequence: low byte first, high byte
second. There are three parts to coding an SPI command (see
Figure 31) that write a new byte of data to a register: the write bit
(R/W = 1), the address of the byte, [A6:A0], and the new data for
that location, [DC7:DC0]. Figure 35 shows a coding example
for writing 0x0004 to the FILT_CTRL register (see Table 101).
In Figure 35, the 0xDC04 command writes 0x04 to Address
0x5C (lower byte) and the 0xDD00 command writes 0x00 to
Address 0x5D (upper byte).
CS
SCLK
DIN 0xDC04 0xDD00
15439-027
Figure 35. SPI Sequence for Writing 0x0004 to FILT_CTRL
Memory Structure
Figure 36 shows a functional diagram for the memory structure of
the ADIS16467. The flash memory bank contains the operational
code, unit specific calibration coefficients and user configuration
settings. During initialization (power application or reset recover),
this information loads from the flash memory into the static
random access memory (SRAM), which supports all normal
operation, including register access through the SPI port. Writing
to a configuration register using the SPI updates the SRAM
location of the register but does not automatically update the
settings in the flash memory bank. The manual flash memory
update command (Register GLOB_CMD, Bit 3, see Table 113)
provides a convenient method for saving all of these settings to
the flash memory bank at one time. A yes in the Flash Backup
column of Table 8 identifies the registers that have storage
support in the flash memory bank.
NONVOLATILE
FLASH MEMORY
(NO SPI ACCESS)
MANUAL
FLASH
BACKUP
START-UP
RESET
VOLATILE
SRAM
SPI ACCESS
15439-028
Figure 36. SRAM and Flash Memory Diagram
ADIS16467 Data Sheet
Rev. C | Page 16 of 34
USER REGISTER MEMORY MAP
Table 8. User Register Memory Map (N/A Means Not Applicable)
Name R/W Flash Backup Address Default Register Description
Reserved N/A N/A 0x00, 0x01 N/A Reserved
DIAG_STAT R No 0x02, 0x03 0x0000 Output, system error flags
X_GYRO_LOW R No 0x04, 0x05 N/A Output, x-axis gyroscope, low word
X_GYRO_OUT R No 0x06, 0x07 N/A Output, x-axis gyroscope, high word
Y_GYRO_LOW R No 0x08, 0x09 N/A Output, y-axis gyroscope, low word
Y_GYRO_OUT R No 0x0A, 0x0B N/A Output, y-axis gyroscope, high word
Z_GYRO_LOW R No 0x0C, 0x0D N/A Output, z-axis gyroscope, low word
Z_GYRO_OUT R No 0x0E, 0x0F N/A Output, z-axis gyroscope, high word
X_ACCL_LOW R No 0x10, 0x11 N/A Output, x-axis accelerometer, low word
X_ACCL_OUT R No 0x12, 0x13 N/A Output, x-axis accelerometer, high word
Y_ACCL_LOW R No 0x14, 0x15 N/A Output, y-axis accelerometer, low word
Y_ACCL_OUT R No 0x16, 0x17 N/A Output, y-axis accelerometer, high word
Z_ACCL_LOW R No 0x18, 0x19 N/A Output, z-axis accelerometer, low word
Z_ACCL_OUT R No 0x1A, 0x1B N/A Output, z-axis accelerometer, high word
TEMP_OUT R No 0x1C, 0x1D N/A Output, temperature
TIME_STAMP R No 0x1E, 0x1F N/A Output, time stamp
Reserved N/A N/A 0x20, 0x21 N/A Reserved
DATA_CNTR R No 0x22, 0x23 N/A New data counter
X_DELTANG_LOW R No 0x24, 0x25 N/A Output, x-axis delta angle, low word
X_DELTANG_OUT R No 0x26, 0x27 N/A Output, x-axis delta angle, high word
Y_DELTANG_LOW R No 0x28, 0x29 N/A Output, y-axis delta angle, low word
Y_DELTANG_OUT R No 0x2A, 0x2B N/A Output, y-axis delta angle, high word
Z_DELTANG_LOW R No 0x2C, 0x2D N/A Output, z-axis delta angle, low word
Z_DELTANG_OUT R No 0x2E, 0x2F N/A Output, z-axis delta angle, high word
X_DELTVEL_LOW R No 0x30, 0x31 N/A Output, x-axis delta velocity, low word
X_DELTVEL_OUT R No 0x32, 0x33 N/A Output, x-axis delta velocity, high word
Y_DELTVEL_LOW R No 0x34, 0x35 N/A Output, y-axis delta velocity, low word
Y_DELTVEL_OUT R No 0x36, 0x37 N/A Output, y-axis delta velocity, high word
Z_DELTVEL_LOW R No 0x38, 0x39 N/A Output, z-axis delta velocity, low word
Z_DELTVEL_OUT R No 0x3A, 0x3B N/A Output, z-axis delta velocity, high word
Reserved N/A N/A 0x3C to 0x3F N/A Reserved
XG_BIAS_LOW R/W Yes 0x40, 0x41 0x0000 Calibration, offset, gyroscope, x-axis, low word
XG_BIAS_HIGH R/W Yes 0x42, 0x43 0x0000 Calibration, offset, gyroscope, x-axis, high word
YG_BIAS_LOW R/W Yes 0x44, 0x45 0x0000 Calibration, offset, gyroscope, y-axis, low word
YG_BIAS_HIGH R/W Yes 0x46, 0x47 0x0000 Calibration, offset, gyroscope, y-axis, high word
ZG_BIAS_LOW R/W Yes 0x48, 0x49 0x0000 Calibration, offset, gyroscope, z-axis, low word
ZG_BIAS_HIGH R/W Yes 0x4A, 0x4B 0x0000 Calibration, offset, gyroscope, z-axis, high word
XA_BIAS_LOW R/W Yes 0x4C, 0x4D 0x0000 Calibration, offset, accelerometer, x-axis, low word
XA_BIAS_HIGH R/W Yes 0x4E, 0x4F 0x0000 Calibration, offset, accelerometer, x-axis, high word
YA_BIAS_LOW R/W Yes 0x50, 0x51 0x0000 Calibration, offset, accelerometer, y-axis, low word
YA_BIAS_HIGH R/W Yes 0x52, 0x53 0x0000 Calibration, offset, accelerometer, y-axis, high word
ZA_BIAS_LOW R/W Yes 0x54, 0x55 0x0000 Calibration, offset, accelerometer, z-axis, low word
ZA_BIAS_HIGH R/W Yes 0x56, 0x57 0x0000 Calibration, offset, accelerometer, z-axis, high word
Reserved N/A N/A 0x58 to 0x5B N/A Reserved
FILT_CTRL R/W Yes 0x5C, 0x5D 0x0000 Control, Bartlett window FIR filter
RANG_MDL R No 0x5E, 0x5F N/A1 Measurement range (model specific) identifier
MSC_CTRL R/W Yes 0x60, 0x61 0x00C1 Control, input/output and other miscellaneous options
UP_SCALE R/W Yes 0x62, 0x63 0x07D0
Control, scale factor for input clock, pulse per second (PPS)
mode
DEC_RATE R/W Yes 0x64, 0x65 0x0000 Control, decimation filter (output data rate)
Data Sheet ADIS16467
Rev. C | Page 17 of 34
Name R/W Flash Backup Address Default Register Description
NULL_CNFG R/W Yes 0x66, 0x67 0x070A Control, bias estimation period
GLOB_CMD W No 0x68, 0x69 N/A Control, global commands
Reserved N/A N/A 0x6A to 0x6B N/A Reserved
FIRM_REV R No 0x6C, 0x6D N/A Identification, firmware revision
FIRM_DM R No 0x6E, 0x6F N/A Identification, date code, day and month
FIRM_Y R No 0x70, 0x71 N/A Identification, date code, year
PROD_ID R No 0x72, 0x73 0x4053 Identification, device number
SERIAL_NUM R No 0x74, 0x75 N/A Identification, serial number
USER_SCR_1 R/W Yes 0x76, 0x77 N/A User Scratch Register 1
USER_SCR_2 R/W Yes 0x78, 0x79 N/A User Scratch Register 2
USER_SCR_3 R/W Yes 0x7A, 0x7B N/A User Scratch Register 3
FLSHCNT_LOW R No 0x7C, 0x7D N/A Output, flash memory write cycle counter, lower word
FLSHCNT_HIGH R No 0x7E, 0x7E N/A Output, flash memory write cycle counter, upper word
1 See Table 102 for the default value in this register, which is model specific.
ADIS16467 Data Sheet
Rev. C | Page 18 of 34
USER REGISTER DEFINTIONS
Status/Error Flag Indicators (DIAG_STAT)
Table 9. DIAG_STAT Register Definition
Addresses Default Access Flash Backup
0x02, 0x03 0x0000 R No
Table 10. DIAG_STAT Bit Assignments
Bits Description
[15:8] Reserved.
7 Clock error. A 1 indicates that the internal data sampling
clock (fSM, see Figure 20 and Figure 21) does not
synchronize with the external clock, which only applies
when using scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010, see Table 105. When this error occurs,
adjust the frequency of the clock signal on the SYNC pin
to operate within the appropriate range.
6 Memory failure. A 1 indicates a failure in the flash memory
test (Register GLOB_CMD, Bit 4, see Table 113), which
involves a comparison between a cyclic redundancy
check (CRC) calculation of the present flash memory and
a CRC calculation from the same memory locations at
the time of initial programming (during the production
process). If this error occurs, repeat the same test. If this
error persists, replace the ADIS16467.
5 Sensor failure. A 1 indicates failure of at least one sensor,
at the conclusion of the self test (Register GLOB_CMD,
Bit 2, see Table 113). If this error occurs, repeat the same
test. If this error persists, replace the ADIS16467. Motion,
during the execution of this test, can cause a false failure.
4 Standby mode. A 1 indicates that the voltage across
VDD and GND is <2.8 V, which causes data processing to
stop. When VDD ≥ 2.8 V for 250 ms, the ADIS16467
reinitializes and starts producing data again.
3 SPI communication error. A 1 indicates that the total
number of SCLK cycles is not equal to an integer multiple
of 16. When this error occurs, repeat the previous
communication sequence. Persistence in this error may
indicate a weakness in the SPI service that the ADIS16467
is receiving from the system it is supporting.
2 Flash memory update failure. A 1 indicates that the most
recent flash memory update (Register GLOB_CMD, Bit 3,
see Table 113) failed. If this error occurs, ensure that
VDD ≥ 3 V and repeat the update attempt. If this error
persists, replace the ADIS16467.
1 Datapath overrun. A 1 indicates that one of the datapaths
experienced an overrun condition. If this error occurs,
initiate a reset using the RST pin (see Table 5, Pin 8) or
Register GLOB_CMD, Bit 7 (see Table 113). See the Serial
Port Operation section for more details on conditions
that may cause this bit to be set to 1.
0 Reserved.
The DIAG_STAT register (see Table 9 and Table 10) provides
error flags for monitoring the integrity and operation of the
ADIS16467. Reading this register causes all bits to return to 0.
The error flags in DIAG_STAT are sticky, meaning that, when
the flags raise to 1, the flags remain there until a read request
clears the flags. If an error condition persists, the flag (bit)
automatically returns to an alarm value of 1.
GYROSCOPE DATA
The gyroscopes in the ADIS16467 measure the angular rate of
rotation around three orthogonal axes (x, y, and z). Figure 37
shows the orientation of each gyroscope axis, along with the
direction of rotation that produces a positive response in each
measurement.
Y-AXIS
ω
z
X-AXIS
Z-AXIS
ω
x
ω
y
15439-029
Figure 37. Gyroscope Axis and Polarity Assignments
Each gyroscope has two output data registers. Figure 38 shows how
these two registers combine to support a 32-bit, twos complement
data format for the x-axis gyroscope measurements. This format
also applies to the y- and z-axes. Additional information on the
resolution of the accelerometers can be found in the Gyroscope
Data Width (Digital Resolution) section.
X-AXIS GYROSCOPE DATA
X_GYRO_OUT X_GYRO_LOW
BIT 0 BIT 15BIT 15 BIT 0
15439-030
Figure 38. Gyroscope Output Data Structure
Gyroscope Measurement Range/Scale Factor
Table 11 provides the measurement range (±ωMAX) and scale
factor (KG) for the gyroscopes in each ADIS16467 model.
Table 11. Gyroscope Measurement Range and Scale Factors
Model
Range, ±ωMAX
(°/sec)
Scale Factor, KG
(LSB/°/sec)
ADIS16467-1BMLZ ±125 160
ADIS16467-2BMLZ ±500 40
ADIS16467-3BMLZ ±2000 10
Gyroscope Data Formatting
Table 12 and Table 13 offer various numerical examples that
demonstrate the format of the rotation rate data in both 16-bit
and 32-bit formats.
Table 12. 16-Bit Gyroscope Data Format Examples
Rotation Rate Decimal Hex. Binary
+ωMAX +20,000 0x4E20 0100 1110 0010 0000
+2/KG +2 0x0002 0000 0000 0000 0010
+1/KG +1 0x0001 0000 0000 0000 0001
0°/sec 0 0x0000 0000 0000 0000 0000
−1/KG −1 0xFFFF 1111 1111 1111 1111
−2/KG −2 0xFFFE 1111 1111 1111 1110
−ωMAX −20,000 0xB1E0 1011 0001 1110 0000
Data Sheet ADIS16467
Rev. C | Page 19 of 34
Table 13. 32-Bit Gyroscope Data Format Examples
Rotation Rate (°/sec) Decimal Hex.
+ωMAX +1,310,720,000 0x4E200000
+2/(KG × 216) +2 0x00000002
+1/(KG × 216) +1 0x00000001
0 0 0x0000000
−1/(KG × 216) −1 0xFFFFFFFF
−2/(KG × 216) −2 0xFFFFFFFE
−ωMAX −1,310,720,000 0xB1E00000
X-Axis Gyroscope (X_GYRO_LOW and X_GYRO_OUT)
Table 14. X_GYRO_LOW Register Definition
Addresses Default Access Flash Backup
0x04, 0x05 Not applicable R No
Table 15. X_GYRO_LOW Bit Definitions
Bits Description
[15:0] X-axis gyroscope data; additional resolution bits
Table 16. X_GYRO_OUT Register Definition
Addresses Default Access Flash Backup
0x06, 0x07 Not applicable R No
Table 17. X_GYRO_OUT Bit Definitions
Bits Description
[15:0] X-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG)
The X_GYRO_LOW (see Table 14 and Table 15) and X_GYRO_
OUT (see Table 16 and Table 17) registers contain the gyroscope
data for the x-axis.
Y-Axis Gyroscope (Y_GYRO_LOW and Y_GYRO_OUT)
Table 18. Y_GYRO_LOW Register Definition
Addresses Default Access Flash Backup
0x08, 0x09 Not applicable R No
Table 19. Y_GYRO_LOW Bit Definitions
Bits Description
[15:0] Y-axis gyroscope data; additional resolution bits
Table 20. Y_GYRO_OUT Register Definition
Addresses Default Access Flash Backup
0x0A, 0x0B Not applicable R No
Table 21. Y_GYRO_OUT Bit Definitions
Bits Description
[15:0] Y-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG)
The Y_GYRO_LOW (see Table 18 and Table 19) and Y_GYRO_
OUT (see Table 20 and Table 21) registers contain the gyroscope
data for the y-axis.
Z-Axis Gyroscope (Z_GYRO_LOW and Z_GYRO_OUT)
Table 22. Z_GYRO_LOW Register Definition
Addresses Default Access Flash Backup
0x0C, 0x0D Not applicable R No
Table 23. Z_GYRO_LOW Bit Definitions
Bits Description
[15:0] Z-axis gyroscope data; additional resolution bits
Table 24. Z_GYRO_OUT Register Definition
Addresses Default Access Flash Backup
0x0E, 0x0F Not applicable R No
Table 25. Z_GYRO_OUT Bit Definitions
Bits Description
[15:0] Z-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG)
The Z_GYRO_LOW (see Table 22 and Table 23) and Z_GYRO_
OUT (see Table 24 and Table 25) registers contain the gyroscope
data for the z-axis.
Acceleration Data
The accelerometers in the ADIS16467 measure both dynamic
and static (response to gravity) acceleration along the same three
orthogonal axes that define the axes of rotation for the gyroscopes
(x, y, and z). Figure 39 shows the orientation of each accelerometer
axis, along with the direction of acceleration that produces a
positive response in each measurement.
a
z
a
x
a
y
Y-AXIS X-AXIS
Z-AXIS
15439-031
Figure 39. Accelerometer Axis and Polarity Assignments
Each accelerometer has two output data registers. Figure 40
shows how these two registers combine to support a 32-bit,
twos complement data format for the x-axis accelerometer
measurements. This format also applies to the y- and z-axes.
Additional information on the resolution of the accelerometers
can be found in the Accelerometer Data Width (Digital
Resolution) section.
X-AXIS ACCELEROMETER DATA
X_ACCL_OUT X_ACCL_LOW
BIT 0 BIT 15BIT 15 BIT 0
15439-032
Figure 40. Accelerometer Output Data Structure
ADIS16467 Data Sheet
Rev. C | Page 20 of 34
Accelerometer Data Formatting
Table 26 and Table 27 show various numerical examples that
demonstrate the format of the linear acceleration data in both
16-bit and 32-bit formats.
Table 26. 16-Bit Accelerometer Data Format Examples
Acceleration Decimal Hex. Binary
+40 g +32,000 0x7D00 0111 1101 0000 0000
+2.5 mg +2 0x0002 0000 0000 0000 0010
+1.25 mg +1 0x0001 0000 0000 0000 0001
0 mg 0 0x0000 0000 0000 0000 0000
−1.25 mg −1 0xFFFF 1111 1111 1111 1111
−2.5 mg −2 0xFFFE 1111 1111 1111 1110
−40 g −32,000 0x8300 1000 0011 0000 0000
Table 27. 32-Bit Accelerometer Data Format Examples
Acceleration Decimal Hex.
+40 g +2,097,152,000 0x7D000000
+1.25/215 mg +2 0x00000002
+1.25/216 mg +1 0x00000001
0 0 0x00000000
−1.25/216 mg −1 0xFFFFFFFF
−1.25/215 mg −2 0xFFFFFFFE
−40 g −2,097,152,000 0x83000000
X-Axis Accelerometer (X_ACCL_LOW and X_ACCL_OUT)
Table 28. X_ACCL_LOW Register Definition
Addresses Default Access Flash Backup
0x10, 0x11 Not applicable R No
Table 29. X_ACCL_LOW Bit Definitions
Bits Description
[15:0] X-axis accelerometer data; additional resolution bits
Table 30. X_ACCL_OUT Register Definition
Addresses Default Access Flash Backup
0x12, 0x13 Not applicable R No
Table 31. X_ACCL_OUT Bit Definitions
Bits Description
[15:0] X-axis accelerometer data, high word; twos complement,
±40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg
The X_ACCL_LOW (see Table 28 and Table 29) and X_ACCL_
OUT (see Table 30 and Table 31) registers contain the
accelerometer data for the x-axis.
Y-Axis Accelerometer (Y_ACCL_LOW and Y_ACCL_OUT)
Table 32. Y_ACCL_LOW Register Definition
Addresses Default Access Flash Backup
0x14, 0x15 Not applicable R No
Table 33. Y_ACCL_LOW Bit Definitions
Bits Description
[15:0] Y-axis accelerometer data; additional resolution bits
Table 34. Y_ACCL_OUT Register Definition
Addresses Default Access Flash Backup
0x16, 0x17 Not applicable R No
Table 35. Y_ACCL_OUT Bit Definitions
Bits Description
[15:0] Y-axis accelerometer data, high word; twos complement,
±40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg
The Y_ACCL_LOW (see Table 32 and Table 33) and Y_ACCL_
OUT (see Table 34 and Table 35) registers contain the
accelerometer data for the y-axis.
Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT)
Table 36. Z_ACCL_LOW Register Definition
Addresses Default Access Flash Backup
0x18, 0x19 Not applicable R No
Table 37. Z_ACCL_LOW Bit Definitions
Bits Description
[15:0] Z-axis accelerometer data; additional resolution bits
Table 38. Z_ACCL_OUT Register Definition
Addresses Default Access Flash Backup
0x1A, 0x1B Not applicable R No
Table 39. Z_ACCL_OUT Bit Definitions
Bits Description
[15:0] Z-axis accelerometer data, high word; twos complement,
±40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg
The Z_ACCL_LOW (see Table 36 and Table 37) and Z_ACCL_
OUT (see Table 38 and Table 39) registers contain the
accelerometer data for the z-axis.
Internal Temperature (TEMP_OUT)
Table 40. TEMP_OUT Register Definition
Addresses Default Access Flash Backup
0x1C, 0x1D Not applicable R No
Table 41. TEMP_OUT Bit Definitions
Bits Description
[15:0] Temperature data; twos complement,
1 LSB = 0.1°C, 0°C = 0x0000
The TEMP_OUT register (see Table 40 and Table 41) provides
a coarse measurement of the temperature inside of the ADIS16467.
This data is most useful for monitoring relative changes in the
thermal environment.
Data Sheet ADIS16467
Rev. C | Page 21 of 34
Table 42. TEMP_OUT Data Format Examples
Temperature (°C) Decimal Hex. Binary
+105 +1050 0x041A 0000 0100 0001 1010
+25 +250 0x00FA 0000 0000 1111 1010
+0.2 +2 0x0002 0000 0000 0000 0010
+0.1 +1 0x0001 0000 0000 0000 0001
+0 0 0x0000 0000 0000 0000 0000
+0.1 −1 0xFFFF 1111 1111 1111 1111
+0.2 −2 0xFFFE 1111 1111 1111 1110
−40 −400 0xFE70 1111 1110 0111 0000
Time Stamp (TIME_STAMP)
Table 43. TIME_STAMP Register Definition
Addresses Default Access Flash Backup
0x1E, 0x1F Not applicable R No
Table 44. TIME_STAMP Bit Definitions
Bits Description
[15:0] Time from the last pulse on the SYNC pin; offset binary
format, 1 LSB = 49.02 μs
The TIME_STAMP register (see Table 43 and Table 44) works
in conjunction with scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010, see Table 105). The 16-bit number in TIME_
STAMP contains the time associated with the last sample in
each data update relative to the most recent edge of the clock
signal in the SYNC pin. For example, when the value in the
UP_SCALE register (see Table 107) represents a scale factor of
20, DEC_RATE = 0, and the external SYNC rate = 100 Hz, the
following time stamp sequence results: 0 LSB, 10 LSB, 21 LSB,
31 LSB, 41 LSB, 51 LSB, 61 LSB, 72 LSB, …, 194 LSB for the 20th
sample, which translates to 0 μs, 490 μs, …, 9510 μs, the time
from the first SYNC edge.
Data Update Counter (DATA_CNTR)
Table 45. DATA_CNTR Register Definition
Addresses Default Access Flash Backup
0x22, 0x23 Not applicable R No
Table 46. DATA_CNTR Bit Definitions
Bits Description
[15:0] Data update counter, offset binary format
When the ADIS16467 goes through the power-on sequence or
when it recovers from a reset command, DATA_CNTR (see
Table 45 and Table 46) starts with a value of 0x0000 and
increments every time new data loads into the output registers.
When the DATA_CNTR value reaches 0xFFFF, the next data
update causes it to wrap back around to 0x0000, where it
continues to increment every time new data loads into the
output registers.
DELTA ANGLES
In addition to the angular rate of rotation (gyroscope)
measurements around each axis (x, y, and z), the ADIS16467 also
provides delta angle measurements that represent a calculation
of angular displacement between each sample update.
Δθ
z
Δθ
x
Δθ
y
Y-AXIS X-AXIS
Z-AXIS
15439-033
Figure 41. Delta Angle Axis and Polarity Assignments
The delta angle outputs represent an integration of the gyroscope
measurements and use the following formula for all three axes
(x-axis displayed):

1
0
1,,
,2
1D
d
dDnxdDnx
S
Dnx f
where:
x is the x-axis.
n is the sample time, prior to the decimation filter.
D is the decimation rate (DEC_RATE + 1, see Table 109).
fS is the sample rate.
d is the incremental variable in the summation formula.
ωX is the x-axis rate of rotation (gyroscope).
When using the internal sample clock, fS is equal to a nominal
rate of 2000 SPS. For better precision in this measurement,
measure the internal sample rate (fS) using the data ready signal
on the DR pin (DEC_RATE = 0x0000, see Table 108), divide
each delta angle result (from the delta angle output registers) by
the data ready frequency and multiply it by 2000. Each axis of
the delta angle measurements has two output data registers.
Figure 42 shows how these two registers combine to support a
32-bit, twos complement data format for the x-axis delta angle
measurements. This format also applies to the y- and z-axes.
X-AXIS DELTA ANGLE DATA
X_DELTANG_OUT X_DELTANG_LOW
BIT 0 BIT 15BIT 15 BIT 0
15439-034
Figure 42. Delta Angle Output Data Structure
Delta Angle Measurement Range
Table 47 shows the measurement range and scale factor for
each ADIS16467 model.
Table 47. Delta Angle Measurement Range and Scale Factor
Model Measurement Range, ±ΔθMAX (°)
ADIS16467-1BMLZ ±360
ADIS16467-2BMLZ ±720
ADIS16467-3BMLZ ±2160
ADIS16467 Data Sheet
Rev. C | Page 22 of 34
X-Axis Delta Angle (X_DELTANG_LOW and
X_DELTANG_OUT)
Table 48. X_DELTANG_LOW Register Definitions
Addresses Default Access Flash Backup
0x24, 0x25 Not applicable R No
Table 49. X_DELTANG_LOW Bit Definitions
Bits Description
[15:0] X-axis delta angle data; low word
Table 50. X_DELTANG_OUT Register Definitions
Addresses Default Access Flash Backup
0x26, 0x27 Not applicable R No
Table 51. X_DELTANG_OUT Bit Definitions
Bits Description
[15:0] X-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 47 for ΔθMAX)
The X_DELTANG_LOW (see Table 48 and Table 49) and
X_DELTANG_OUT (see Table 50 and Table 51) registers
contain the delta angle data for the x-axis.
Y-Axis Delta Angle (Y_DELTANG_LOW and
Y_DELTANG_OUT)
Table 52. Y_DELTANG_LOW Register Definitions
Addresses Default Access Flash Backup
0x28, 0x29 Not applicable R No
Table 53. Y_DELTANG_LOW Bit Definitions
Bits Description
[15:0] Y-axis delta angle data; low word
Table 54. Y_DELTANG_OUT Register Definitions
Addresses Default Access Flash Backup
0x2A, 0x2B Not applicable R No
Table 55. Y_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Y-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 47 for ΔθMAX)
The Y_DELTANG_LOW (see Table 52 and Table 53) and
Y_DELTANG_OUT (see Table 54 and Table 55) registers
contain the delta angle data for the y-axis.
Z-Axis Delta Angle (Z_DELTANG_LOW and
Z_DELTANG_OUT)
Table 56. Z_DELTANG_LOW Register Definitions
Addresses Default Access Flash Backup
0x2C, 0x2D Not applicable R No
Table 57. Z_DELTANG_LOW Bit Definitions
Bits Description
[15:0] Z-axis delta angle data; low word
Table 58. Z_DELTANG_OUT Register Definitions
Addresses Default Access Flash Backup
0x2E, 0x2F Not applicable R No
Table 59. Z_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Z-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 47 for ΔθMAX)
The Z_DELTANG_LOW (see Table 56 and Table 57) and
Z_DELTANG_OUT (see Table 58 and Table 59) registers
contain the delta angle data for the z-axis.
Delta Angle Resolution
Table 60 and Table 61 show various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
Table 60. 16-Bit Delta Angle Data Format Examples
Delta Angle (°) Decimal Hex. Binary
ΔθMAX × (215−1)/215 +32,767 0x7FFF 0111 1111 1110 1111
+ΔθMAX/214 +2 0x0002 0000 0000 0000 0010
+ΔθMAX/215 +1 0x0001 0000 0000 0000 0001
0 0 0x0000 0000 0000 0000 0000
−ΔθMAX/215 −1 0xFFFF 1111 1111 1111 1111
−ΔθMAX/214 −2 0xFFFE 1111 1111 1111 1110
−ΔθMAX −32,768 0x8000 1000 0000 0000 0000
Table 61. 32-Bit Delta Angle Data Format Examples
Delta Angle (°) Decimal Hex.
+ΔθMAX × (231 − 1)/231 +2,147,483,647 0x7FFFFFFF
+ΔθMAX/230 +2 0x00000002
+ΔθMAX/231 +1 0x00000001
0 0 0x00000000
−ΔθMAX/231 −1 0xFFFFFFFF
−ΔθMAX/230 −2 0xFFFFFFFE
−ΔθMAX −2,147,483,648 0x80000000
DELTA VELOCITY
In addition to the linear acceleration measurements along each
axis (x, y, and z), the ADIS16467 also provides delta velocity
measurements that represent a calculation of linear velocity
change between each sample update.
ΔV
z
ΔV
x
ΔV
y
Y-AXIS X-AXIS
Z-AXIS
15439-035
Figure 43. Delta Velocity Axis and Polarity Assignments
Data Sheet ADIS16467
Rev. C | Page 23 of 34
The delta velocity outputs represent an integration of the
acceleration measurements and use the following formula for
all three axes (x-axis displayed):

1
0
1,,
,2
1D
d
dDnxdDnx
S
Dnx aa
f
V
where:
x is the x-axis.
n is the sample time, prior to the decimation filter.
D is the decimation rate (DEC_RATE + 1, see Table 109).
fS is the sample rate.
d is the incremental variable in the summation formula.
aX is the x-axis acceleration.
When using the internal sample clock, fS is equal to a nominal rate
of 2000 SPS. For better precision in this measurement, measure the
internal sample rate (fS) using the data ready signal on the DR pin
(DEC_RATE = 0x0000, see Table 108), divide each delta angle
result (from the delta angle output registers) by the data ready
frequency and multiply it by 2000. Each axis of the delta velocity
measurements has two output data registers. Figure 44 shows how
these two registers combine to support a 32-bit, twos complement
data format for the delta velocity measurements along the x-axis.
This format also applies to the y- and z-axes.
X-AXIS DELTA VELOCITY DATA
X_DELTVEL_OUT X_DELTVEL_LOW
BIT 0 BIT 15BIT 15 BIT 0
15439-036
Figure 44. Delta Velocity Output Data Structure
X-Axis Delta Velocity (X_DELTVEL_LOW and
X_DELTVEL_OUT)
Table 62. X_DELTVEL_LOW Register Definition
Addresses Default Access Flash Backup
0x30, 0x31 Not applicable R No
Table 63. X_DELTVEL_LOW Bit Definitions
Bits Description
[15:0] X-axis delta velocity data; additional resolution bits
Table 64. X_DELTVEL_OUT Register Definition
Addresses Default Access Flash Backup
0x32, 0x33 Not applicable R No
Table 65. X_DELTVEL_OUT Bit Definitions
Bits Description
[15:0] X-axis delta velocity data; twos complement,
±400 m/sec range, 0 m/sec = 0x0000;
1 LSB = 400 m/sec ÷ 215 = ~0.01221 m/sec
The X_DELTVEL_LOW (see Table 62 and Table 63) and
X_DELTVEL_OUT (see Table 64 and Table 65) registers
contain the delta velocity data for the x-axis.
Y-Axis Delta Velocity (Y_DELTVEL_LOW and
Y_DELTVEL_OUT)
Table 66. Y_DELTVEL_LOW Register Definition
Addresses Default Access Flash Backup
0x34, 0x35 Not applicable R No
Table 67. Y_DELTVEL_LOW Bit Definitions
Bits Description
[15:0] Y-axis delta velocity data; additional resolution bits
Table 68. Y_DELTVEL_OUT Register Definition
Addresses Default Access Flash Backup
0x36, 0x37 Not applicable R No
Table 69. Y_DELTVEL_OUT Bit Definitions
Bits Description
[15:0] Y-axis delta velocity data; twos complement,
±400 m/sec range, 0 m/sec = 0x0000;
1 LSB = 400 m/sec ÷ 215 = ~0.01221 m/sec
The Y_DELTVEL_LOW (see Table 66 and Table 67) and
Y_DELTVEL_OUT (see Table 68 and Table 69) registers
contain the delta velocity data for the y-axis.
Z-Axis Delta Velocity (Z_DELTVEL_LOW and
Z_DELTVEL_OUT)
Table 70. Z_DELTVEL_LOW Register Definition
Addresses Default Access Flash Backup
0x38, 0x39 Not applicable R No
Table 71. Z_DELTVEL_LOW Bit Definitions
Bits Description
[15:0] Z-axis delta velocity data; additional resolution bits
Table 72. Z_DELTVEL_OUT Register Definition
Addresses Default Access Flash Backup
0x3A, 0x3B Not applicable R No
Table 73. Z_DELTVEL_OUT Bit Definitions
Bits Description
[15:0] Z-axis delta velocity data; twos complement,
±400 m/sec range, 0 m/sec = 0x0000;
1 LSB = 400 m/sec ÷ 215 = ~0.01221 m/sec
The Z_DELTVEL_LOW (see Table 70 and Table 71) and
Z_DELTVEL_OUT (see Table 72 and Table 73) registers
contain the delta velocity data for the z-axis.
Delta Velocity Resolution
Table 74 and Table 75 offer various numerical examples that
demonstrate the format of the delta velocity data in both 16-bit
and 32-bit formats.
ADIS16467 Data Sheet
Rev. C | Page 24 of 34
Table 74. 16-Bit Delta Velocity Data Format Examples
Velocity (m/sec) Decimal Hex. Binary
+400 × (215 − 1)/215 +32,767 0x7FFF 0111 1111 1111 1111
+400/214 +2 0x0002 0000 0000 0000 0010
+400/215 +1 0x0001 0000 0000 0000 0001
0 0 0x0000 0000 0000 0000 0000
−400/215 −1 0xFFFF 1111 1111 1111 1111
−400/214 −2 0xFFFE 1111 1111 1111 1110
−400 −32,768 0x8000 1000 0000 0000 0000
Table 75. 32-Bit Delta Velocity Data Format Examples
Velocity (m/sec) Decimal Hex.
+400 × (231 − 1)/231 +2,147,483,647 0x7FFFFFFF
+400/230 +2 0x00000002
+400/231 +1 0x00000001
0 0 0x00000000
−400/231 −1 0xFFFFFFFF
−400/230 −2 0xFFFFFFFE
−400 +2,147,483,648 0x80000000
CALIBRATION
The signal chain of each inertial sensor (accelerometers and
gyroscopes) includes the application of unique correction
formulas, which are derived from extensive characterization of
bias, sensitivity, alignment, response to linear acceleration
(gyroscopes), and point of percussion (accelerometer location)
over a temperature range of −40°C to +85°C, for each ADIS16467.
These correction formulas are not accessible, but users do have
the opportunity to adjust the bias for each sensor individually
through user accessible registers. These correction factors
follow immediately after the factory derived correction formulas
in the signal chain, which processes at a rate of 2000 Hz when
using the internal sample clock.
Calibration, Gyroscope Bias (XG_BIAS_LOW and
XG_BIAS_HIGH)
Table 76. XG_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x40, 0x41 0x0000 R/W Yes
Table 77. XG_BIAS_LOW Bit Definitions
Bits Description
[15:0] X-axis gyroscope offset correction; lower word
Table 78. XG_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x42, 0x43 0x0000 R/W Yes
Table 79. XG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] X-axis gyroscope offset correction factor, upper word
The XG_BIAS_LOW (see Table 76 and Table 77) and XG_BIAS_
HIGH (see Table 78 and Table 79) registers combine to allow
users to adjust the bias of the x-axis gyroscopes. The data format
examples in Table 12 also apply to the XG_BIAS_HIGH register,
and the data format examples in Table 13 apply to the 32-bit
combination of the XG_BIAS_LOW and XG_BIAS_HIGH
registers. See Figure 45 for an illustration of how these two registers
combine and influence the x-axis gyroscope measurements.
X-AXIS
GYRO
FACTORY
CALIBRATION
AND
FILTERING
X_GYRO_OUT X_GYRO_LOW
XG_BIAS_HIGH XG_BIAS_LOW
15439-037
Figure 45. User Calibration Signal Path, Gyroscopes
Calibration, Gyroscope Bias (YG_BIAS_LOW and
YG_BIAS_HIGH)
Table 80. YG_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x44, 0x45 0x0000 R/W Yes
Table 81. YG_BIAS_LOW Bit Definitions
Bits Description
[15:0] Y-axis gyroscope offset correction; lower word
Table 82. YG_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x46, 0x47 0x0000 R/W Yes
Table 83. YG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis gyroscope offset correction factor, upper word
The YG_BIAS_LOW (see Table 80 and Table 81) and YG_BIAS_
HIGH (see Table 82 and Table 83) registers combine to allow
users to adjust the bias of the y-axis gyroscopes. The data format
examples in Table 12 also apply to the YG_BIAS_HIGH register,
and the data format examples in Table 13 apply to the 32-bit
combination of the YG_BIAS_LOW and YG_BIAS_HIGH
registers. These registers influence the y-axis gyroscope
measurements in the same manner that the XG_BIAS_LOW
and XG_BIAS_HIGH registers influence the x-axis gyroscope
measurements (see Figure 45).
Calibration, Gyroscope Bias (ZG_BIAS_LOW and
ZG_BIAS_HIGH)
Table 84. ZG_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x48, 0x49 0x0000 R/W Yes
Table 85. ZG_BIAS_LOW Bit Definitions
Bits Description
[15:0] Z-axis gyroscope offset correction; lower word
Table 86. ZG_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x4A, 0x4B 0x0000 R/W Yes
Data Sheet ADIS16467
Rev. C | Page 25 of 34
Table 87. ZG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis gyroscope offset correction factor, upper word
The ZG_BIAS_LOW (see Table 84 and Table 85) and ZG_BIAS_
HIGH (see Table 86 and Table 87) registers combine to allow
users to adjust the bias of the z-axis gyroscopes. The data format
examples in Table 12 also apply to the ZG_BIAS_HIGH register,
and the data format examples in Table 13 apply to the 32-bit
combination of the ZG_BIAS_LOW and ZG_BIAS_HIGH
registers. These registers influence the z-axis gyroscope
measurements in the same manner that the XG_BIAS_LOW
and XG_BIAS_HIGH registers influence the x-axis gyroscope
measurements (see Figure 45).
Calibration, Accelerometer Bias (XA_BIAS_LOW and
XA_BIAS_HIGH)
Table 88. XA_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x4C, 0x4D 0x0000 R/W Yes
Table 89. XA_BIAS_LOW Bit Definitions
Bits Description
[15:0] X-axis accelerometer offset correction; lower word
Table 90. XA_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x4E, 0x4F 0x0000 R/W Yes
Table 91. XA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] X-axis accelerometer offset correction, upper word
The XA_BIAS_LOW (see Table 88 and Table 89) and XA_BIAS_
HIGH (see Table 90 and Table 91) registers combine to allow users
to adjust the bias of the x-axis accelerometers. The data format
examples in Table 26 also apply to the XA_BIAS_HIGH register,
and the data format examples in Table 27 apply to the 32-bit
combination of the XA_BIAS_LOW and XA_BIAS_HIGH
registers. See Figure 46 for an illustration of how these two registers
combine and influence the x-axis accelerometer measurements.
X-AXIS
ACCL
FACTORY
CALIBRATION
AND
FILTERING
X_ACCL_OUT X_ACCL_LOW
XA_BIAS_HIGH XA_BIAS_LOW
15439-038
Figure 46. User Calibration Signal Path, Accelerometers
Calibration, Accelerometer Bias (YA_BIAS_LOW and
YA_BIAS_HIGH)
Table 92. YA_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x50, 0x51 0x0000 R/W Yes
Table 93. YA_BIAS_LOW Bit Definitions
Bits Description
[15:0] Y-axis accelerometer offset correction; lower word
Table 94. YA_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x52, 0x53 0x0000 R/W Yes
Table 95. YA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis accelerometer offset correction, upper word
The YA_BIAS_LOW (see Table 92 and Table 93) and YA_BIAS_
HIGH (see Table 94 and Table 95) registers combine to allow users
to adjust the bias of the y-axis accelerometers. The data format
examples in Table 26 also apply to the YA_BIAS_HIGH register,
and the data format examples in Table 27 apply to the 32-bit
combination of the YA_BIAS_LOW and YA_BIAS_HIGH
registers. These registers influence the y-axis accelerometer
measurements in the same manner that the XA_BIAS_LOW and
XA_BIAS_HIGH registers influence the x-axis accelerometer
measurements (see Figure 46).
Calibration, Accelerometer Bias (ZA_BIAS_LOW and
ZA_BIAS_HIGH)
Table 96. ZA_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x54, 0x55 0x0000 R/W Yes
Table 97. ZA_BIAS_LOW Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction; lower word
Table 98. ZA_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x56, 0x57 0x0000 R/W Yes
Table 99. ZA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction, upper word
The ZA_BIAS_LOW (see Table 96 and Table 97) and ZA_BIAS_
HIGH (see Table 98 and Table 99) registers combine to allow
users to adjust the bias of the z-axis accelerometers. The data
format examples in Table 26 also apply to the ZA_BIAS_HIGH
register, and the data format examples in Table 27 apply to the
32-bit combination of the ZA_BIAS_LOW and ZA_BIAS_HIGH
registers. These registers influence the z-axis accelerometer
measurements in the same manner that the XA_BIAS_LOW and
XA_BIAS_HIGH registers influence the x-axis accelerometer
measurements (see Figure 46).
Filter Control Register (FILT_CTRL)
Table 100. FILT_CTRL Register Definition
Addresses Default Access Flash Backup
0x5C, 0x5D 0x0000 R/W Yes
Table 101. FILT_CTRL Bit Definitions
Bits Description
[15:3] Not used
[2:0] Filter Size Variable B, number of taps in each stage; N = 2B
ADIS16467 Data Sheet
Rev. C | Page 26 of 34
The FILT_CTRL register (see Table 100 and Table 101)
provides user controls for the Bartlett window FIR filter (see
Figure 23), which contains two cascaded averaging filters. For
example, use the following sequence to set Register FILT_CTRL,
Bits[2:0] = 100, which sets each stage to have 16 taps: 0xCC04 and
0xCD00. Figure 47 provides the frequency response for several
settings in the FILT_CTRL register.
0
–20
–40
–60
–80
–100
–120
–140
0.001 0.01 0.1 1
MAGNITUDE (dB)
FREQUENCY (
f
/
f
S
N = 2
N = 4
N = 16
N = 64
15439-039
Figure 47. Bartlett Window, FIR Filter Frequency Response
(Phase Delay = N Samples)
Range Identifier (RANG_MDL)
Table 102. RANG_MDL Register Definition
Addresses Default Access Flash Backup
0x5E, 0x5F Not applicable R No
Table 103. RANG_MDL Bit Definitions
Bits Description
[15:3] Not used
[3:2] Gyroscope measurement range
00 = ±125°/sec (ADIS16467-1BMLZ)
01 = ±500°/sec (ADIS16467-2BMLZ)
10 = reserved
11 = ±2000°/sec (ADIS16467-3BMLZ)
[1:0] Reserved, binary value = 11
Miscellaneous Control Register (MSC_CTRL)
Table 104. MSC_CTRL Register Definition
Addresses Default Access Flash Backup
0x60, 0x61 0x00C1 R/W Yes
Table 105. MSC_CTRL Bit Definitions
Bits Description
[15:8] Not used
7 Linear g compensation for gyroscopes (1 = enabled)
6 Point of percussion alignment (1 = enabled)
5 Not used, always set to zero
[4:2] SYNC function setting
111 = reserved (do not use)
110 = reserved (do not use)
101 = pulse sync mode
100 = reserved (do not use)
011 = output sync mode
010 = scaled sync mode
001 = direct sync mode
000 = internal clock mode (default)
1 SYNC polarity (input or output)
1 = rising edge triggers sampling
0 = falling edge triggers sampling
0 DR polarity
1 = active high when data is valid
0 = active low when data is valid
Point of Percussion
Register MSC_CTRL, Bit 6 (see Table 105) offers an on/off control
for the point of percussion alignment function, which maps the
accelerometer sensors to the corner of the package shown in
Figure 48. The factory default setting in the MSC_CTRL register
activates this function. To turn this function off while retaining
the rest of the factory default settings in the MSC_CTRL register,
set Register MSC_CTRL, Bit 6 = 0, using the following command
sequence on the DIN pin: 0xE081, then 0xE100.
POINT OF PERCUSSION
ALIGNMENT REFERENCE POINT
SEE MSC_CTRL[6]
15439-040
Figure 48. Point of Percussion Reference Point
Linear Acceleration Effect on Gyroscope Bias
Register MSC_CTRL, Bit 7 (see Table 105) provides an on/off
control for the linear g compensation in the signal calibration
routines of the gyroscope. The factory default contents in the
MSC_CTRL register enable this compensation. To turn the
compensation off, set Register MSC_CTRL, Bit 7 = 0, using
the following sequence on the DIN pin: 0xE041, 0xE100.
Data Sheet ADIS16467
Rev. C | Page 27 of 34
Internal Clock Mode
Register MSC_CTRL, Bits[4:2] (see Table 105), provide five
different configuration options for controlling the clock (fSM; see
Figure 20 and Figure 21), which controls data acquisition and
processing for the inertial sensors. The default setting for Register
MSC_CTRL, Bits[4:2] is 000 (binary), which places the ADIS16467
in internal clock mode. In this mode, an internal clock controls
inertial sensor data acquisition and processing at a nominal rate
of 2000 Hz. In this mode, each accelerometer data update comes
from an average of two data samples (sample rate = 4000 Hz).
Direct Sync Mode
When Register MSC_CTRL, Bits[4:2] = 001, the ADIS16467
operates in direct sync mode. The signal on the SYNC pin directly
controls the sample clock. In this mode, the internal processor
collects gyroscope data samples on the rising edge of the clock
signal (SYNC pin) and collects accelerometer data samples on both
rising and falling edges of the clock signal. The internal processor
averages both accelerometer samples (from rising and falling edge
of the clock signal) together to produce a single data sample.
Therefore, when operating the ADIS16467 in this mode, the clock
signal (SYNC pin) must have a duty cycle of 50% and a frequency
that is within the range of 1900 Hz to 2100 Hz. The ADIS16467 is
capable of operating when the clock frequency (SYNC pin) is less
than 1900 Hz, but with risk of performance degradation, especially
when tracking dynamic inertial conditions (including vibration).
Scaled Sync Mode
When Register MSC_CTRL, Bits[4:2] = 010, the ADIS16467
operates in scaled sync mode that supports a frequency range of
1 Hz to 128 Hz for the clock signal on the SYNC pin. This
mode of operation is particularly useful when synchronizing
the data processing with a PPS signal from a global positioning
system (GPS) receiver or with a synchronization signal from a
video processing system. When operating in scaled sync mode,
the frequency of the sample clock is equal to the product of the
external clock scale factor, KECSF (from the UP_SCALE register,
see Table 106 and Table 107), and the frequency of the clock
signal on the SYNC pin.
For example, when using a 1 Hz input signal, set UP_SCALE =
0x07D0 (KECSF = 2000 (decimal)) to establish a sample rate of
2000 SPS for the inertial sensors and the signal processing. Use
the following sequence on the DIN pin to configure UP_SCALE
for this scenario: 0xE2D0, then 0xE307.
Table 106. UP_SCALE Register Definition
Addresses Default Access Flash Backup
0x62, 0x63 0x07D0 R/W Yes
Table 107. UP_SCALE Bit Definitions
Bits Description
[15:0] KECSF; binary format
Output Sync Mode
When Register MSC_CTRL, Bits[4:2] = 011, the ADIS16467
operates in output sync mode, which is the same as internal
clock mode with one exception: the SYNC pin pulses when
the internal processor collects data from the inertial sensors.
Figure 49 provides an example of this signal.
SYNC
250µs
500µs
GYROSCOPE AND
ACCELEROMETER
DATA ACQUISITION
ACCELEROMETER
DATA ACQUISITION
15439-041
Figure 49. Sync Output Signal, Register MSC_CTRL, Bits[4:2] = 011
Pulse Sync Mode
When operating in pulse sync mode (Register MSC_CTRL,
Bits[4:2] = 101), the internal processor only collects accelerometer
samples on the leading edge of the clock signal, which enables the
use of a narrow pulse width (see Table 2) in the clock signal on
the SYNC pin. Using pulse sync mode also lowers the bandwidth
on the inertial sensors to 370 Hz. When operating in the pulse
sync mode, the ADIS16467 provides the best performance when
the frequency of the clock signal (SYNC pin) is within the range
of 1000 Hz to 2100 Hz. The ADIS16467 is capable of operating
when the clock frequency (SYNC pin) is less than 1000 Hz, but
with risk of performance degradation, especially when tracking
dynamic inertial conditions (including vibration).
Decimation Filter (DEC_RATE)
Table 108. DEC_RATE Register Definition
Addresses Default Access Flash Backup
0x64, 0x65 0x0000 R/W Yes
Table 109. DEC_RATE Bit Definitions
Bits Description
[15:11] Don’t care
[10:0] Decimation rate, binary format, maximum = 1999
The DEC_RATE register (see Table 108 and Table 109) provides
user control for the averaging decimating filter, which averages
and decimates the gyroscope and accelerometer data; it also
extends the time that the delta angle and the delta velocity track
between each update. When the ADIS16467 operates in internal
clock mode (see Register MSC_CTRL, Bits[4:2], in Table 105),
the nominal output data rate is equal to 2000/(DEC_RATE + 1).
For example, set DEC_RATE = 0x0013 to reduce the output
sample rate to 100 SPS (2000 ÷ 20), using the following DIN pin
sequence: 0xE413, then 0xE500.
Data Update Rate in External Sync Modes
When using the input sync option, in scaled sync mode
(Register MSC_CTRL, Bits[4:2] = 010, see Table 105), the
output data rate is equal to
(fSYNC × KECSF)/(DEC_RATE + 1)
ADIS16467 Data Sheet
Rev. C | Page 28 of 34
where:
fSYNC is the frequency of the clock signal on the SYNC pin.
KESCF is the value from the UP_SCALE register (see Table 107).
When using direct sync mode and pulse sync mode, KESCF = 1.
Continuous Bias Estimation (NULL_CNFG)
Table 110. NULL_CNFG Register Definition
Addresses Default Access Flash Backup
0x66, 0x67 0x070A R/W Yes
Table 111. NULL_CNFG Bit Definitions
Bits Description
[15:14] Not used
13 Z-axis accelerometer bias correction enable (1 = enabled)
12 Y-axis accelerometer bias correction enable (1 = enabled)
11 X-axis accelerometer bias correction enable (1 = enabled)
10 Z-axis gyroscope bias correction enable (1 = enabled)
9 Y-axis gyroscope bias correction enable (1 = enabled)
8 X-axis gyroscope bias correction enable (1 = enabled)
[7:4] Not used
[3:0] Time base control (TBC), range: 0 to 12 (default = 10);
tB = 2TBC/2000, time base; tA = 64 × tB, average time
The NULL_CNFG register (see Table 110 and Table 111) provides
the configuration controls for the continuous bias estimator (CBE),
which associates with the bias correction update command in
Register GLOB_CMD, Bit 0 (see Table 113). Register NULL_
CNFG, Bits[3:0], establishes the total average time (tA) for the
bias estimates and Register NULL_CNFG, Bits[13:8], provide the
on/off controls for each sensor. The factory default configuration
for the NULL_CNFG register enables the bias null command
for the gyroscopes, disables the bias null command for the
accelerometers, and sets the average null time to ~32 sec.
Global Commands (GLOB_CMD)
Table 112. GLOB_CMD Register Definition
Addresses Default Access Flash Backup
0x68, 0x69 Not applicable W No
Table 113. GLOB_CMD Bit Definitions
Bits Description
[15:8] Not used
7 Software reset
[6:5] Not used
4 Flash memory test
3 Flash memory update
2 Sensor self test
1 Factory calibration restore
0 Bias correction update
The GLOB_CMD register (see Table 112 and Table 113) provides
trigger bits for several operations. Write a 1 to the appropriate bit
in GLOB_CMD to start a particular function. During the
execution of these commands, data production stops, pulsing stops
on the DR pin, and the SPI interface does not respond to requests.
Table 1 provides the execution time for each GLOB_CMD
command.
Software Reset
Use the following DIN sequence to set Register GLOB_CMD,
Bit 7 = 1, which triggers a reset: 0xE880, then 0xE900. This reset
clears all data, and then restarts data sampling and processing.
This function provides a firmware alternative to toggling the
RST pin (see Table 5, Pin 8).
Flash Memory Test
Use the following DIN sequence to set Register GLOB_CMD,
Bit 4 = 1, which tests the flash memory: 0xE810, then 0xE900.
The command performs a CRC computation on the flash memory
(excluding user register locations) and compares it to the original
CRC value, which comes from the factory configuration process.
If the current CRC value does not match the original CRC
value, Register DIAG_STAT, Bit 6 (see Table 10), rises to 1,
indicating a failing result.
Flash Memory Update
Use the following DIN sequence to set Register GLOB_CMD,
Bit 3 = 1, which triggers a backup of all user configurable registers
in the flash memory: 0xE808, then 0xE900. Register DIAG_STAT,
Bit 2 (see Table 10), identifies success (0) or failure (1) in
completing this process.
Sensor Self Test
Use the following DIN sequence to set Register GLOB_CMD,
Bit 2 = 1, which triggers the self test routine for the inertial sensors:
0xE804, then 0xE900. The self test routine uses the following
steps to validate the integrity of each inertial sensor:
1. Measure the output on each sensor.
2. Activate an internal stimulus on the mechanical elements of
each sensor to move them in a predictable manner and
create an observable response in the sensors.
3. Measure the output response on each sensor.
4. Deactivate the internal stimulus on each sensor.
5. Calculate the difference between the sensor measurements
from Step 1 (stimulus is off) and from Step 3 (stimulus is on).
6. Compare the difference with internal pass and fail criteria.
7. Report the pass and fail result to Register DIAG_STAT, Bit 5
(see Table 10).
Motion during the execution of this test can indicate a false failure.
Factory Calibration Restore
Use the following DIN sequence to set Register GLOB_CMD,
Bit 1 = 1 to restore the factory default settings for the MSC_
CTRL, DEC_RATE, and FILT_CTRL registers and to clear all
user configurable bias correction settings: 0xE802, then 0xE900.
Executing this command results in writing 0x0000 to the following
registers: XG_BIAS_LOW, XG_BIAS_HIGH, YG_BIAS_LOW,
YG_BIAS_HIGH, ZG_BIAS_LOW, ZG_BIAS_HIGH,
XA_BIAS_LOW, XA_BIAS_HIGH, YA_BIAS_LOW,
YA_BIAS_HIGH, ZA_BIAS_LOW, and ZA_BIAS_HIGH.
Data Sheet ADIS16467
Rev. C | Page 29 of 34
Bias Correction Update
Use the following DIN pin sequence to set Register GLOB_CMD,
Bit 0 = 1 to trigger a bias correction, using the correction factors
from the CBE (see Table 111): 0xE801, then 0xE900.
Firmware Revision (FIRM_REV)
Table 114. FIRM_REV Register Definition
Addresses Default Access Flash Backup
0x6C, 0x6D Not applicable R No
Table 115. FIRM_REV Bit Definitions
Bits Description
[15:0] Firmware revision, binary coded decimal (BCD) format
The FIRM_REV register (see Table 114 and Table 115) provides
the firmware revision for the internal firmware. This register uses a
BCD format, where each nibble represents a digit. For example,
if FIRM_REV = 0x0104, the firmware revision is 1.04.
Firmware Revision Day and Month (FIRM_DM)
Table 116. FIRM_DM Register Definition
Addresses Default Access Flash Backup
0x6E, 0x6F Not applicable R No
Table 117. FIRM_DM Bit Definitions
Bits Description
[15:8] Factory configuration month, BCD format
[7:0] Factory configuration day, BCD format
The FIRM_DM register (see Table 116 and Table 117) contains
the month and day of the factory configuration date. Register
FIRM_DM, Bits[15:8], contain digits that represent the month
of the factory configuration. For example, November is the 11th
month in a year and is represented by Register FIRM_DM,
Bits[15:8] = 0x11. Register FIRM_DM, Bits[7:0], contain the
day of factory configuration. For example, the 27th day of the
month is represented by Register FIRM_DM, Bits[7:0] = 0x27.
Firmware Revision Year (FIRM_Y)
Table 118. FIRM_Y Register Definition
Addresses Default Access Flash Backup
0x70, 0x71 Not applicable R No
Table 119. FIRM_Y Bit Definitions
Bits Description
[15:0] Factory configuration year, BCD format
The FIRM_Y register (see Table 118 and Table 119) contains
the year of the factory configuration date. For example, the
year, 2017, is represented by FIRM_Y = 0x2017.
Product Identification (PROD_ID)
Table 120. PROD_ID Register Definition
Addresses Default Access Flash Backup
0x72, 0x73 0x4053 R No
Table 121. PROD_ID Bit Definitions
Bits Description
[15:0] Product identification = 0x4053
The PROD_ID register (see Table 120 and Table 121) contains
the numerical portion of the device number (16,467). See Figure 33
for an example of how to use a looping read of this register to
validate the integrity of the communication.
Serial Number (SERIAL_NUM)
Table 122. SERIAL_NUM Register Definition
Addresses Default Access Flash Backup
0x74, 0x75 Not applicable R No
Table 123. SERIAL_NUM Bit Definitions
Bits Description
[15:0] Lot specific serial number
Scratch Registers (USER_SCR_1 to USER_SCR_3)
Table 124. USER_SCR_1 Register Definition
Addresses Default Access Flash Backup
0x76, 0x77 Not applicable R/W Yes
Table 125. USER_SCR_1 Bit Definitions
Bits Description
[15:0] User defined
Table 126. USER_SCR_2 Register Definition
Addresses Default Access Flash Backup
0x78, 0x79 Not applicable R/W Yes
Table 127. USER_SCR_2 Bit Definitions
Bits Description
[15:0] User defined
Table 128. USER_SCR_3 Register Definition
Addresses Default Access Flash Backup
0x7A, 0x7B Not applicable R/W Yes
Table 129. USER_SCR_3 Bit Definitions
Bits Description
[15:0] User defined
The USER_SCR_1 (see Table 124 and Table 125), USER_SCR_2
(see Table 126 and Table 127), and USER_SCR_3 (see Table 128
and Table 129) registers provide three locations for the user to
store information. For nonvolatile storage, use the manual flash
memory update command (Register GLOB_CMD, Bit 3, see
Table 113), after writing information to these registers.
Flash Memory Endurance Counter (FLSHCNT_LOW and
FLSHCNT_HIGH)
Table 130. FLSHCNT_LOW Register Definition
Addresses Default Access Flash Backup
0x7C, 0x7D Not applicable R No
ADIS16467 Data Sheet
Rev. C | Page 30 of 34
Table 131. FLSHCNT_LOW Bit Definitions
Bits Description
[15:0] Flash memory write counter, low word
Table 132. FLSHCNT_HIGH Register Definition
Addresses Default Access Flash Backup
0x7E, 0x7F Not applicable R No
Table 133. FLSHCNT_HIGH Bit Definitions
Bits Description
[15:0] Flash memory write counter, high word
The FLSHCNT_LOW (see Table 130 and Table 131) and
FLSHCNT_HIGH (see Table 132 and Table 133) registers
combine to provide a 32-bit, binary counter that tracks the
number of flash memory write cycles. In addition to the
number of write cycles, the flash memory has a finite service
lifetime, which depends on the junction temperature. Figure 50
provides guidance for estimating the retention life for the flash
memory at specific junction temperatures. The junction
temperature is approximately 7°C above the case temperature.
600
450
300
150
030 40
RETENTION (Years)
JUNCTION TEMPERATURE (°C)
55 70 85 100 125 135 150
15439-042
Figure 50. Flash Memory Retention
Data Sheet ADIS16467
Rev. C | Page 31 of 34
APPLICATIONS INFORMATION
ASSEMBLY AND HANDLING TIPS
Mounting Tips
The ADIS16467 package supports installation onto a PCB or
rigid enclosure, using three M2 or 2-56 machine screws, using
a torque that is between 20 inch ounces and 40 inch ounces.
When designing a mechanical interface for the ADIS16467,
avoid placing unnecessary translational stress on the electrical
connector because this can influence the bias repeatability
behaviors of the inertial sensors. When the same PCB also has
the mating connector, the use of passthrough holes for the
mounting screws may be required. Figure 51 shows a detailed
view of the PCB pad design when using one of the connector
variants in the CLM-107-02 family.
0.2364 [6.0]
0.0240 [0.610]
0.019685
[0.5000]
(TYP)
0.054 [1.37]
0.0394 [1.00]
0.0394 [1.00] 0.1800
[4.57]
NONPLATED
THROUGH HOLE 2×
0.022± DIA (TYP)
0.022 DIA THROUGH HOLE (TYP)
NONPLATED THROUGH HOLE
15439-043
Figure 51. Mating Connector Design Detail
POWER SUPPLY CONSIDERATIONS
The ADIS16467 contains 6 μF of decoupling capacitance across
the VDD and GND pins. When the VDD voltage raises from 0 V
to 3.3 V, the charging current for this capacitor bank imposes the
following current profile (in amperes):
 
dt
tdVDD
dt
dVDD
CtIDD 6
106
where:
IDD(t)is the current demand on the VDD pin during the initial
power supply ramp, with respect to time.
C is the internal capacitance across the VDD and GND pins (6 μF).
VDD(t) is the voltage on the VDD pin, with respect to time.
For example, if VDD follows a linear ramp from 0 V to 3.3 V, in
66 μs, the charging current is 300 mA for that timeframe. The
ADIS16467 also contains embedded processing functions that
present transient current demands during initialization or reset
recovery operations. During these processes, the peak current
demand reaches 250 mA and occurs at a time that is approximately
40 ms after VDD reaches 3.0 V (or ~40 ms after initiating a
reset sequence).
BREAKOUT BOARD
The ADIS16IMU4/PCBZ breakout board provides a ribbon
cable interface for simple connection to an embedded processor
development system. Figure 52 shows the electrical schematic,
and Figure 53 shows a top view for this breakout board. J2 mates
directly to the electrical connector on the ADIS16467, and J1 easily
mates to a 1 mm ribbon cable system.
C1
0805
10µF
C2
0603
1µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J2 J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DR
SYNC
SCLK
DOUT
DIN
CS
DNC
RST
DNC
DNC
VDD
DNC
GND
DNC
15439-044
Figure 52. ADIS16IMU4/PCBZ Electrical Schematic
15439-045
Figure 53. ADIS16IMU4/PCBZ Top View
1RST 2
J1
3CS 4DOUT
SCLK
5DNC 6DIN
7GND 8GND
9GND 10 VDD
11VDD 12 VDD
13DR 14 SYNC
15NC 16 NC
15439-046
Figure 54. ADIS16IMU4/PCBZ J1 Pin Assignments
ADIS16467 Data Sheet
Rev. C | Page 32 of 34
SERIAL PORT OPERATION
Maximum Throughput
When operating with the maximum output data (DEC_RATE =
0x0000, as described in Table 109), the maximum SCLK rate
(defined in Table 2) and minimum stall time, the SPI port can
support up to 12, 16-bit register reads in between each pulse of
the data ready signal. Attempting to read more than 12 registers
can result in a datapath overrun error in the DIAG_STAT register
(see Table 10). The serial port stall time (tSTALL) to meet these
requirements must be no more than 10% greater than the
minimum specification for tSTALL in Table 2.
The number of allowable registers reads between each pulse on
the data ready line increases proportionally with the decimation
rate (set by the DEC_RATE register, see Table 109). For example,
when the decimation rate equals 3 (DEC_RATE = 0x0002), the
SPI is able to support up to 36 register reads, assuming maximum
SCLK rate and minimum stall times in the protocol. Decreasing
the SCLK rate and increasing the stall time lowers the total
number of register reads supported by the ADIS16467 before a
datapath overrun error occurs.
This limitation of reading 12, 16-bit registers does not impact the
ability of the user to access the full precision of the gyroscopes and
accelerometers if the factory default settings of DEC_RATE =
0x0000 and FILT_CTRL = 0x0000 are used. In this case, the
data width for the gyroscope and accelerometer data is 16 bits,
and application processors can acquire all relevant information
through the X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT,
X_ACCEL_OUT, Y_ACCEL_OUT, and Z_ACCEL_OUT
registers. Thirty-two bit reads of the sensor data do not provide
additional precision in this case. See the Gyroscope Data Width
(Digital Resolution) section and the Accelerometer Data Width
(Digital Resolution) section for more information.
Serial Port SCLK Underrun/Overrun Conditions
The serial port operates in 16-bit segments and it is critical that
the number of SCLK cycles be equal to an integer multiple of 16
when the CS pin is low. Failure to meet this condition causes
the serial port controller inside of the ADIS16467 to be unable
to correctly receive and respond to new requests.
If too many SCLK cycles are received before the CS pin is
deasserted, the user can recover serial port operation by asserting
CS, providing 17 rising edges on the SCLK line, deasserting CS,
and then attempting to correctly read the PROD_ID (or other
read-only) register on the ADIS16467. The user should repeat
these steps up to a maximum of 15 times until the correct data
is read.
If CS is deasserted before enough SCLK cycles are received, the
user must either power cycle or issue a hard reset (using the
RST pin) to regain SPI port access.
DIGITAL RESOLUTION OF GYROSCOPES AND
ACCELEROMETERS
Gyroscope Data Width (Digital Resolution)
The decimation filter (DEC_RATE register, see Table 109) and
Bartlett window filter (FILT_CTRL register, see Table 101) have
direct influence over the total number of bits in the output data
registers, which contain relevant information. When using the
factory default settings (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) for these filters, the data width for the gyroscope data
width is 16 bits, which means that application processors can
acquire all relevant information through the X_GYRO_OUT,
Y_GYRO_OUT, and Z_GYRO_OUT registers.
The X_GYRO_LOW, Y_GYRO_LOW, and Z_GYRO_
LOW registers capture the bit growth that comes from each
accumulation operation in the decimation and Bartlett window
filters. When using these filters (DEC_RATE ≠ 0x0000 and/or
FILT_CTRL ≠ 0x0000), the bit growth is equal to the square root
of the number of summations in each filter stage. For example,
when DEC_RATE = 0x0007, the decimation filter adds eight (7 +
1 = 8, see Table 109) successful samples together, which causes
the data width to increase by 3 bits (80.5 = 3). When FILT_CTRL =
0x0002, both stages in the Bartlett window filter use four (22 = 4,
see Table 101) summation operations, which increases the data
width by two bits (40.5 = 2). When using both DEC_RATE =
0x0007 and FILT_CTRL = 0x0002, the total bit growth is 7 bits,
which increases the overall data width to 23 bits.
Accelerometer Data Width (Digital Resolution)
The decimation filter (DEC_RATE register, see Table 109) and
Bartlett window filter (FILT_CTRL register, see Table 101) have
direct influence over the total number of bits in the output data
registers, which contain relevant information. When using the
factory default settings (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) for these filters, the data width for the accelerometer
data will be 20 bits. The X_ACCL_OUT, Y_ACCL_OUT, and
Z_ACCL_OUT registers contain the most significant 16 bits of this
data, while the remaining (least significant) bits are in the upper 4
bits of the X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW
registers. Because the total noise (0.6 mg rms, see Table 1) in
the accelerometer data (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) is greater than the 16-bit quantization noise (0.25 mg ÷
120.5 = 0.072 mg), application processors can acquire all relevant
information through the X_ACCL_OUT, Y_ACCL_OUT, and
Z_ACCL_OUT registers. This setup enables applications to
preserve optimal performance, while using the burst read (see
Figure 32), which only provides 16-bit data for the accelerometers.
The X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW
registers also capture the bit growth that comes from each
accumulation operation in the decimation and Bartlett window
filters. When using these filters (DEC_RATE ≠ 0x0000 and/or
FILT_CTRL ≠ 0x0000), the bit growth is proportional to the
square root of the number of summations in each filter stage.
For example, when DEC_RATE = 0x0001, the decimation filter
Data Sheet ADIS16467
Rev. C | Page 33 of 34
adds two (1 + 1 = 2, see Table 109) successful samples together,
which causes the data width to increase by 1 bit (20.5 = 1). When
FILT_CTRL = 0x0001, both stages in the Bartlett window filter
use two (21 = 2, see Table 101) summation operations, which
increases the data width by 1 bit (20.5 = 1). When using both
DEC_RATE = 0x0001 and FILT_CTRL = 0x0001, the total bit
growth is 3 bits, which increases the overall data width to 23 bits.
PC-BASED EVALUATION TOOLS
The ADIS16IMU4/PCBZ provides a simple way to connect the
ADIS16467 to the EVAL-ADIS2 evaluation system, which
provides a PC-based method for evaluation of basic function
and performance. For more information, visit the EVAL-
ADIS2 Wiki Guide.
ADIS16467 Data Sheet
Rev. C | Page 34 of 34
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
11-09-2018-B
TOP VIEW
END VIEW
22.47
22.40
22.33
22.47
22.40
22.33
24.37
24.30
24.23
9.07
9.00
8.93
18.25 BSC
14.20 BSC
1.00 BSC
PITCH
7.10
REF
0.19
0.57
R 2.75
Ø2.40
1.50°
Figure 55. 14-Lead Module with Connector Interface [MODULE]
(ML-14-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADIS16467-1BMLZ −40°C to +105°C 14-Lead Module with Connector Interface [MODULE] ML-14-6
ADIS16467-2BMLZ −40°C to +105°C 14-Lead Module with Connector Interface [MODULE] ML-14-6
ADIS16467-3BMLZ −40°C to +105°C 14-Lead Module with Connector Interface [MODULE] ML-14-6
ADIS16IMU4/PCBZ Breakout Board
EVAL-ADIS2Z Evaluation System
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D15439-2/20(C)