RK80546PG0801MSL88J - Intel Corporation

Intel® Pentium® 4 Processors

570/571, 560/561, 550/551,

540/541, 530/531 and 520/521∆

Supporting Hyper-Threading

Technology1

Datasheet

On 90 nm Process in 775-land LGA Package and

supporting Intel® Extended Memory 64 TechnologyΦ

May 2005

Document Number: 302351-004

2 Datasheet

Contents

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OT HERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WA RRA NTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT O F A NY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® Pentium® 4 processor in the 775-land package on 90 nm process may contain design defects or errors known as errata which may ca use

the product to deviate from published specifications. Current characterized errata are avai lable on request.

∆Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

different processor families.

1Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting Hyper-Th reading Technology and an HT

Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http:/

/www.intel.com/info/hyperthreading/ for more inf ormation including details on which processors support HT Technology.

ΦIntel® Extended Memory 64 Technology (Intel® EM64T) requires a computer system with a processor, chipset, BIOS, ope rating system, device

drivers and applications enabled for Intel EM64T. Processor will not operate (including 32- bit operation) without an Intel EM64T-enabled BIOS.

Performance will vary depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including

details on which processors support EM64T or consult with your system vendor for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system.

Check with your PC manufacturer on whether your system delivers Execut e Di sable Bit functionality.

Contact your local Intel sales office or your distributor to obtain the latest specifications and befor e placing your product order.

Intel, Penti um, Itanium, Intel Xeon, Intel NetBurst and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in

the United States and other countries.

*Other names and brands may be claimed as the property of others.

 Datasheet 3
Contents
Contents
Introduction....................................................................................................................................11
1 Terminology........................................................................................................................12
1.1 Processor Packaging Terminology........................................................................12
2 References .........................................................................................................................13
Electrical Specifications.......... ... ... .... ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ... ... ... ..........................15
1 FSB and GTLREF...............................................................................................................15
2 Power and Ground Lands...................................................................................................15
3 Decoupling Guidelines........................................................................................................15
3.1 VCC Decoupling ....................................................................................................16
3.2 FSB GTL+ Decoupling...........................................................................................16
3.3 FSB Clock (BCLK[1:0]) and Processor Clocking...................................................16
4 Voltage Identification ..........................................................................................................17
4.1 Phase Lock Loop (PLL) Power and Filter..............................................................19
5 Reserved, Unused, FC and TESTHI Signals......................................................................20
6 FSB Signal Groups.............................................................................................................21
7 GTL+ Asynchronous Signals..............................................................................................22
8 Test Access Port (TAP) Connection...................................................................................23
9 FSB Frequency Select Signals (BSEL[2:0]) .......................................................................23
10 Absolute Maximum and Minimum Ratings .........................................................................24
11 Processor DC Specifications ..............................................................................................24
12 VCC Overshoot Specification ................... ... ................ .... ... ... ... ... .... ... ... ................ ... .... ... ...33
12.1 Die Voltage Validation ...........................................................................................33
13 GTL+ FSB Specifications....................................................................................................34
Package Mechanical Specifications ..............................................................................................35
1 Package Mechanical Drawing ............................................................................................35
2 Processor Component Keep-Out Zones.............................................................................39
3 Package Loading Specifications.........................................................................................39
4 Package Handling Guidelines.............................................................................................39
5 Package Insertion Specifications........................................................................................40
6 Processor Mass Specification.............................................................................................40
7 Processor Materials............................................................................................................40
8 Processor Markings............................................................................................................40
9 Processor Land Coordinates ..............................................................................................41
Land Listing and Signal Descriptions ..... ... ... .... .............................................................................43
1 Processor Land Assignments.............................................................................................43
2 Alphabetical Signals Reference..........................................................................................66
Thermal Specifications and Design Considerations......................................................................75
1 Processor Thermal Specifications ......................................................................................75
1.1 Thermal Specifications ..........................................................................................75
1.2 Thermal Metrology.................................................................................................79
2 Processor Thermal Features ..............................................................................................79
2.1 Thermal Monitor.....................................................................................................79
2.2 Thermal Monitor 2..................................................................................................80

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Contents
2.3 On-Demand Mode.................................................................................................81
2.4 PROCHOT# Signal................................................................................................82
2.5 THERMTRIP# Signal.............................................................................................82
2.6 TCONTROL and Fan Speed Reduction....................................................................82
2.7 Thermal Diode...................... ... .... ... ... ................ .... ... ... ... ... .... ... ................ ... ... .... ...83
Features ........................................................................................................................................85
1 Power-On Configuration Options.... ... ... .... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... .... ...85
2 Clock Control and Low Power States.................................................................................85
2.1 Normal State...... ... ... .... ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ... .......86
2.2 HALT and Enhanced HALT Powerdown States ....................................................86
2.3 Stop-Grant State...... .... ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ... .......87
2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State......................88
Boxed Processor Specifications....................................................................................................89
1 Mechanical Specifications ..................................................................................................90
1.1 Boxed Processor Cooling Solution Dimensions ....................................................90
1.2 Boxed Processor Fan Heatsink Weight.................................................................91
1.3 Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly.............................................................................................91
2 Electrical Requirements......................................................................................................91
2.1 Fan Heatsink Power Supply ..................................................................................91
3 Thermal Specifications ................... ... ................ .... ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ...93
3.1 Boxed Processor Cooling Requirements...............................................................93
3.2 Variable Speed Fan...............................................................................................95

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Contents
Figures
2-1 Phase Lock Loop (PLL) Filter Requirements.... ..........................................................................19
2-2 VCC Static and Transient Tolerance for 775_VR_CONFIG_04A...............................................28
2-3 VCC Static and Transient Tolerance for 775_VR_CONFIG_04B...............................................30
2-4 VCC Overshoot Example Waveform ..........................................................................................33
3-1 Processor Package Assembly Sketch........................................................................................35
3-2 Processor Package Drawing 1 ...................................................................................................36
3-3 Processor Package Drawing 2 ...................................................................................................37
3-4 Processor Package Drawing 3 ...................................................................................................38
3-5 Processor Top-Side Marking Example.......................................................................................40
3-6 Processor Top-Side Marking Example for Processors Supporting Intel® EM64T... ... ... ... .... ... ...41
3-7 Processor Land Coordinates (Top View)....................................................................................42
4-1 Landout Diagram (Top View – Left Side)....................................................................................44
4-2 Landout Diagram (Top View – Right Side).................................................................................45
5-1 Thermal Profile for Processors with PRB = 1 .............................................................................77
5-2 Thermal Profile for Processors with PRB = 0 .............................................................................78
5-3 Case Temperature (TC) Measurement Location........................................................................79
5-4 Thermal Monitor 2 Frequency and Voltage Ordering .................................................................81
6-1 Processor Low Power State Machine.........................................................................................87
7-1 Mechanical Representation of the Boxed Processor..................................................................89
7-2 Space Requirements for the Boxed Processor (Side View) .......................................................90
7-3 Space Requirements for the Boxed Processor (Top View) ........................................................90
7-4 Space Requirements for the Boxed Processor (Overall View)...................................................91
7-5 Boxed Processor Fan Heatsink Power Cable Connector Description........................................92
7-6 Baseboard Power Header Placement Relative to Processor Socket.........................................93
7-7 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)..... ... ... ... ... .... ... ...94
7-8 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side View)............. ... .... ... ...94
7-9 Boxed Processor Fan Heatsink Set Points.................................................................................95

6 Datasheet 
Contents
Tables
1-1 References .................................................................................................................................13
2-1 Core Frequency to FSB Multiplier Configuration........................................................................16
2-2 Voltage Identification Definition..................................................................................................18
2-3 FSB Signal Groups.....................................................................................................................21
2-4 Signal Characteristics.................................................................................................................22
2-5 Signal Reference Voltages.........................................................................................................22
2-6 BSEL[2:0] Frequency Table for BCLK[1:0].................................................................................23
2-7 Processor DC Absolute Maximum Ratings ................................................................................24
2-8 Voltage and Current Specifications ............................................................................................25
2-9 VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Processors . ... .... ...... ... ... .... ...27
2-10VCC Static and Transient Tolerance for 775_VR_CONFIG_04B Processors .... .... ... ... ... ... .... ...29
2-11 GTL+ Asynchronous Signal Group DC Specifications ..............................................................31
2-12GTL+ Signal Group DC Specifications.......................................................................................31
2-13PWRGOOD and TAP Signal Group DC Specifications..............................................................32
2-14VTTPWRGD DC Specifications..................................................................................................32
2-15BSEL [2:0] and VID[5:0] DC Specifications................................................................................32
2-16BOOTSELECT DC Specifications..............................................................................................32
2-17VCC Overshoot Specifications .. ... .... ... ... ... ... ..............................................................................33
2-18GTL+ Bus Voltage Definitions ....................................................................................................34
3-1 Processor Loading Specifications ..............................................................................................39
3-2 Package Handling Guidelines ....................................................................................................39
3-3 Processor Materials....................................................................................................................40
4-1 Alphabetical Land Assignments .................................................................................................46
4-2 Numerical Land Assignment... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... .............56
4-3 Signal Description.......................................................................................................................66
5-1 Processor Thermal Specifications..............................................................................................76
5-2 Thermal Profile for Processors with PRB = 1.............................................................................77
5-3 Thermal Profile for Processors with PRB = 0.............................................................................78
5-4 Thermal Diode Parameters ........................................................................................................83
5-5 Thermal Diode Interface.............................................................................................................83
6-1 Power-On Configuration Option Signals.....................................................................................85
7-1 Fan Heatsink Power and Signal Specifications..........................................................................92
7-2 Fan Heatsink Power and Signal Specifications..........................................................................96
§

Datasheet 7

Contents

Revision History

Revision No. Description Date of Release

-001 • Initial release June 2004

-002

• Added specifications for processor number 550 with PRB = 0

• Added support for Execute Disable Bit capability

• Added Icc Enhanced Auto Halt specifications

• Added support for Thermal Monitor 2

September 2004

-003 • Added specifications for processor number 570 with PRB = 1 November 2004

-004

• Added specifications for processor numbers 571, 561, 551, 541,

531, and 521.

• Modified Table 2-3, “FSB Signal Groups“.

• Added Note 5 to Table 2-18.

• Updated Figure 3-5 Top SIde Marking Example and a dded

Figure 3-6.

• Minor edits throughout for clarity.

May 2005

8 Datasheet

Contents

Datasheet 9

Contents

Intel® Pentium® 4 Processors 570/571,

560/561, 550/551, 540/541, 530/531, and

520/521

The Intel® Pentium® 4 processor family supporting Hyper-Threading Technology1 (HT Technology) delivers

Intel's advanced, powerful processors for desktop PCs and entry-level workstations that are based on the Intel

NetBurst® microarchitecture. The Pentium 4 processor is designed to de liver perform a nce acro ss applications and

usages where end-users can truly appreciate and experience the performance. These applications include Internet

audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and

multitasking user environments. Intel® Extended Memory 64 Technology enables the Intel® Pentium® processor to

execute operating systems and applications written to take advang e of the Intel EM64TΦ

•Available at 3.80 GHz, 3.60 GHz, 3.40 GHz,

3.20 GHz, 3 GHz, and 2.80 GHz

•Supports Hyper-Threading Technology1

(HT Technology) for all frequencies wi th

800 MHz front side bus (FSB)

•Intel® Pentium® 4 processo rs 571, 561, 551, 541,

531, and 521 support Intel® Extended Memory 64

Technology (EM64T)Φ

•Supports Execute Disable Bit capability

•Binary compatible with app licati ons running on

previous members of the Intel microprocessor line

•Intel NetBurst® microarchitecture

•FSB frequency at 800 MHz

•Hyper-Pipelined Technology

•Advance Dynamic Execution

•Very deep out-of-order execution

•Enhanced branch prediction

•Optimized for 32-bit applications running on

advanced 32-bit operating systems

•16-KB Level 1 data cache

•1-MB Advanced Transfer Cache (on-die, full-

speed Level 2 (L2) cache) with 8-way associativity

and Error Correcting Code (ECC )

•144 Streaming SIMD Extensions 2 (SSE2)

instructions

•13 Streaming SIMD Extensions 3 (SSE3)

instructions

•Enhanced floating point and mult imedia unit for

enhanced video, audio, encryption, and 3D

performance

•Power Management capabilities

•System Management mode

•Multiple low-power states

•8-way cache associativity provides improved

cache hit rate on load/store operations

•775-land Package

10 Datasheet

Contents

Datasheet 11

Introduction

1Introduction

The Intel® Pentium® 4 processor on 90 nm process in the 775-land package is a follow on to the

Pentium 4 processor in the 478-pin package with enhancements to the Intel NetBurst®

microarchitecture. The Pentium 4 processor on 90 nm process in the 775-land package uses Flip-

Chip Land Grid Array (FC-LGA4) package technology, and plugs into a 775LGA socket. The

Pentium 4 processor in the 775-land package, like its predecessor, the Pentium 4 processor in the

478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of

compatibility wit h IA-32 software.

Note: In this document the Pentium 4 processor on 90 nm process in the 775-land package is also referred

to as the processor.

The Pentium 4 processor on 90 nm process in the 775-land package supports Hyper-Threading

Technology1. Hyper-Threading Technology allows a single, physical processor to fu nction as two

logical processors. While some execution resources (such as caches, execution units, and buses)

are shared, each logical processor has its own architecture state with its own set of general-purpose

registers, control registers to provide increased system responsiveness in multitasking

environments, and headroom for next generati on multithreaded applications. Intel recommends

enabling Hyper-Threading Technology with Microsoft Windows* XP Professional or

Windows* XP Home, and disabling Hyper-Threading Technology via the BIOS for all previo us

versions of Wi ndows operating systems. For more informat ion on Hyper-Threading Technology,

see http://www.intel.com/info/hyperthreading. Refer to Section 6.1, for Hyper-Threading

Technology configuration details.

The Intel Pentium 4 processor 571, 561, 541, 531 , and 521 support Intel® Extended Memory 64

Technology (EM64T)Φ as an enhancement to Intel’s IA-32 architecture. This enhancement enables

the processor to execute operating systems and applications written to take advantage of Intel

EM64T. With appropriate 64 bit supporting hardware and software, platforms based on an Intel

processor supporting In tel® EM64T can enable use of extended virtual and physical memory.

Further details on the 64-bit extension architecture and programming m odel is provided in the

Intel® Extended Memory 64 Technology Software Developer Guide at: http://developer.intel.com/

technology/64bitextensions/.

In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new

instructions that further extend the capabilities of Intel processor technology. These new

instructions are called Streaming SIMD Extensions 3 (SSE3). These new instructions enhance the

performance of optimized applications for the di git a l hom e such as video, image processing, and

media compression technology. 3D graphics and other entertainment appl ications such as gaming

will have the opportunity to take advantage of these new instructions as platforms with the Pentium

4 processor in the 775-land package and SSE3 become available in the market place.

The processor’s Intel NetBurst microarchitecture FSB uses a split-transaction, deferred reply

protocol like the Pentium 4 processor. The Intel NetBurst microarchitecture FSB uses Source-

Synchronous Transfer (SST) of address and data to improve performance by transferring data four

times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address

bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X

address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth

of up to 6.4 GB/s.

12 Datasheet

Introduction

The Pentium 4 processor on 90 nm process in the LGA775-land package will also include the

Execute Disable Bit capability previously available in Intel® Itanium® processors. This feature

combined with a support operating system allows memory to be marked as executable or non-

executable. If code attempts to run in non-executable memory the processor raises an error to the

operating system. This feature can prevent some classes of viruses or worms th at exploit buffer

overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel®

Architecture Software Developer's Manual for more detailed infor mati on.

Intel will enable support components for the processor including heatsink, heatsi nk ret e nti on

mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be

completed from the top of the baseboard and should not require any special tooli ng.

The processor includes an address bus powerdown capability that removes power from the address

and data pins when the FSB is not in use. This feature is always enabled on the processor.

1.1 Terminology

A ‘#’ symbol after a signal name ref e rs to an active low signal, indicating a signal is in the active

state when driven to a low level. For example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where

the name does not imply an active state but describes part of a binary sequence (such as address or

data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a

hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“FSB” refers to the interface between the processor and system core logic (a.k.a. the chipset

components). The FSB is a multiprocessing interface to processors, memory, and I/O.

1.1.1 Processor Packaging Terminology

Commonly used terms are explained here for clarificatio n:

•Pentium 4 processor on 90 nm process in the 775-land package — Processor in the FC-

LGA4 package with a 1-MB L2 cache.

•Processor — For this document, the term processor is the generic form of the Pentium 4

processor in the 775-land package.

•Keep-out zone — The area on or near the processor that system design can not use.

•Intel 925X/915G/915P Express chipsets — Chipsets that supports DDR and DDR2 memory

technology for the Pentium 4 processor in the 775-land package.

•Processor core — Processor core die with integrated L2 cache.

•FC-LGA4 package — The Pentium 4 pro cessor in the 775-l and package is available in a Flip-

Chip Land Grid Array 4 package, consisting of a processor core mounted on a substrate with

an integrated heat spreader (IHS).

•LGA775 socket — The Pentium 4 pro cessor in the 775-land package mates with the system

board through a surface mount, 775-land, LGA socket.

•Integrated heat spreader (IHS) —A component of the processor package used to enhance

the thermal performance of the package. Component thermal solutions interface with the

processor at the IHS surface.

Datasheet 13

Introduction

•Retention mechanism (RM)—Since the LGA775 socket does not include any mechanical

features for heatsink attach, a retention mechan ism is required. Component thermal solutions

should attach to the processor via a retention mechanism that is independent of the socket.

•Storage conditions—Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be seal ed in packaging or exposed to free air.

Under these conditions, processor lands should not be connected to any supply voltages, have

any I/Os biased, or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or

a device removed from packaging material) the process or must be handled in accordance with

moisture sensitivity labeling (MSL) as indicated on the packaging material.

•Function a l operation —Refers to normal operating conditions in which all processor

specifications, including DC, AC, system bus, signal quality, mechanical and thermal, are

satisfied.

1.2 References

Material and concepts available in the following documents may be beneficial when reading this

document.

Table 1-1. References

Document Document Numbers/

Location

Intel® Pentium® 4 Processor on 90 nm Process Specification Update http://developer.intel.com/

design/Pentium4/

specupdt/302352.htm

Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land Package

Thermal Design Guidelines http://developer.intel.com/

design/Pentium4/guides/

302553.htm

Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket http://developer.intel.com/

design/Pentium4/guides/

302356.htm

Intel® Architecture Software Developer's Manual

http://developer.intel.com/

design/pentium4/

manuals/index_new.htm

IA-32 Intel® Architecture Software Developer's Manual Volume 1: Basic

Architecture

IA-32 Intel® Architecture Software Developer's Manual V olume 2A: Instruction

Set Reference Manual A–M

IA-32 Intel® Architecture Software Developer's Manual V olume 2B: Instruction

Set Reference Manual, N–Z

IA-32 Intel® Architecture Software Developer's Manual Volume 3: System

Programming Guide

IA-32 Intel® Architecture and Intel® Extended Memory 64 Software

Developer's Manual Documentation Changes http://developer.intel.com/

design/pentium4/

manuals/index_new.htm

14 Datasheet

Introduction

Datasheet 15

Electrical Specifications

2Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC

electrical characteristics are provided.

2.1 FSB and GTLREF

Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology.

Platforms implement a termination voltage level for GTL+ signals defined as VTT. VTT m ust be

provided via a separate voltage source and not be connected to VCC. This configuration allows for

improved noise tolerance as processor frequency increases. Because of the speed improvements to

the data and address bus, signal integrity and platform design method s hav e be co me more critical

than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine

if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board (see

Table 2-18 for GTLREF specifications). Termination resistors are provided on the processor silicon

and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the

need to terminate the bus on the system board for most GTL+ signals.

Some GTL+ signals do not include on-die termination and must be terminated on the system board.

See Table 2-4 for details regarding these signals.

The GTL+ bus depends on incident wave switching. Therefore, timing calculations for GTL+

signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the

FSB, including trace lengths, is highly recommended when designing a system.

2.2 Power and Ground Lands

For clean on-chip power distribution, the Pentium 4 processor in th e 775-land package has

226 VCC (power), 24 VTT and 273 VSS (ground) lands. All power lands must be connected to VCC,

all VTT lands must be connected to VTT, while all VSS lands must be connected to a system ground

plane. The processor VCC lands must be supplied th e voltage determined by the Voltage

IDentification (VID) signals.

2.3 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large current swings between low and full power states. This may cause voltages on

power planes to sag below their minimum values if bulk decoupling is not adequ a te. Care must be

taken in the board design to ensure that the voltage provided to the processor remains within the

specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime

of the component. For further information and desig n gui delines, refer to the Volta ge Reg ulator

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

16 Datasheet

Electrical Specifications

2.3.1 VCC Decoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the

large current swings when the part is powering on, or entering/exiting low power states, must be

provided by the voltage regulator solution (VR). For more details on this topic, refer to the Voltage

Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

2.3.2 FSB GTL+ Decoupling

The Pentium 4 processor in the 775-land package integrates signal termination on the die as well as

incorporating high frequency decoupling capacitance on the processor package. Decoupling must

also be provided by the system baseboard for proper GTL+ bus operation.

2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.

As in previous generation processors, the Pentium 4 processo r in the 775-land package core

frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set

at its default ratio during manufacturing. No user intervention is necessary, and the processor will

automatically run at the speed indicated on the package.

The Pentium 4 processor in the 775-land package uses a differential clocking implementation . For

more information on the Pentium 4 processor in the 775-land package clocking, refer to the

CK410/CK410M Clock Synthesizer/Driver Specification.

Table 2-1. Core Frequency to FSB Multiplier Configuration

Multiplication of System Core

Frequency to FSB Frequency Core Frequency (200 MHz

BCLK/800 MHz FSB) Notes1, 2

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Listed frequencies are not necessarily committed production frequencies.

1/14 2.80 GHz -

1/15 3 GHz -

1/16 3.20 GHz -

1/17 3.40 GHz -

1/18 3.60 GHz -

1/19 3.80 GHz -

Datasheet 17

Electrical Specifications

2.4 Voltage Identification

The VID specification for the Pentium 4 processor in the 775-land package is supported by the

Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set

by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins. A

minimum voltage is provided in Table 2-8 and changes with frequency. This allows processors

running at a higher frequency to have a relaxed minimum voltage specification. The specifications

have been set such that one voltage regulator can work with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two devices at

the same speed may have different VID settings.

The Pentium 4 processor in the 775-land package uses six voltage identification signals, VID[5:0],

to support automatic selection of po wer supply voltages. Table 2-2 specifies th e voltage level

corresponding to the st ate of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’

refers t o low voltage l evel. If the processor socket is empty (VID[5:0] = x11111), or the voltage

regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Voltage

Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for more details.

Power source characteristics must be guaranteed to be stable when the supply to the voltag e

regulator is stable.

The LL_ID[1:0] lands are used by the platform to configure the proper loadline sl ope for the

processor. LL_ID[1: 0] = 00 fo r the Pentium 4 processor in the 775-land package.

The VTT_SEL land is used by the platform to configure the proper VTT voltage level for the

processor. VTT_SEL = 1 for the Pentium 4 processor in the 775-land package.

The GTLREF_SEL signal is used by the platform to select the appropriate chipset GTLREF level.

GTLREF_SEL = 0 for the Pentium 4 processor in the 775-land package.

LL_ID[1:0] and VTT_SEL are signals that are implemented on the processor package. That is,

they are either connected directly to VSS or are open lands.

18 Datasheet

Electrical Specifications

Table 2-2. Voltage Identification Definition

VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID

001010 0.8375 0110101.2125

101001 0.8500 1110011.2250

001001 0.8625 0110011.2375

101000 0.8750 1110001.2500

001000 0.8875 0110001.2625

100111 0.9000 1101111.2750

000111 0.9125 0101111.2875

100110 0.9250 1101101.3000

000110 0.9375 0101101.3125

100101 0.9500 1101011.3250

000101 0.9625 0101011.3375

100100 0.9750 1101001.3500

000100 0.9875 0101001.3625

100011 1.0000 1100111.3750

000011 1.0125 0100111.3875

100010 1.0250 1100101.4000

000010 1.0375 0100101.4125

100001 1.0500 1100011.4250

000001 1.0625 0100011.4375

100000 1.0750 1100001.4500

000000 1.0875 0100001.4625

111111VR output off 1011111.4750

011111VR output off 0011111.4875

111110 1.1000 1011101.5000

011110 1.1125 0011101.5125

111101 1.1250 1011011.5250

011101 1.1375 0011011.5375

111100 1.1500 1011001.5500

011100 1.1625 0011001.5625

111011 1.1750 1010111.5750

011011 1.1875 0010111.5875

111010 1.2000 1010101.6000

Datasheet 19

Electrical Specifications

2.4.1 Phase Lock Loop (PLL) Power and Filter

VCCA and VCCIOPLL are power sources required by the PLL clock generators for the Pentium 4

processor in the 775-land package. Since these PLLs are analog, they require low noise power

supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as

well as internal core timings (i.e., maximum frequency). T o prevent this degradation, these supplies

must be low pass filtered from VTT.

The AC low-pass requirements, with input at VTT are as follows:

•< 0.2 dB gain in pass band

•< 0.5 dB attenuation in pass band < 1 Hz

•> 34 dB attenuation from 1 MHz to 66 MHz

•> 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 2-1.

NOTES:

1. Diagram not to scale.

2. No specification exists for frequencies beyond fcore (core frequency).

3. fpeak, if existent, should be less than 0.05 MHz.

Figure 2-1. Phase Lock Loop (PLL) Filter Requirements

0 dB

–28 dB

–34 dB

0.2 dB

–0.5 dB

1 MHz 66 MH z fcorefpeak1 HzDC

Passband High

Frequency

Band Filter_Spec

Forbidden

Zone

Forbidden

Zone

20 Datasheet

Electrical Specifications

2.5 Reserved, Unused, FC and TESTHI Signals

All RESERVED signals must remain unconnected. Connection of these signals to VCC, VSS, VTT,

or to any other signal (including each other) can result in component malfunction or

incompatibility with future processors. See Chapter 4 for a land listing of the processor and the

location of all RESERVED signals.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate

signal level. In a system level design, on-die termination has been incl uded on the Pentium 4

processor in the 775-land package to allow signals to be terminated within the processor silicon.

Most unused GTL+ inputs should be left as no connects, as GTL+ termination is provided on the

processor silicon. However, see Table 2-4 for details on GTL+ signals that do not include on-die

termination. Unused active high inputs should be connected th rough a resistor to ground (VSS).

Unused outputs can be left unconnected, however this may interfere with some test access port

(TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be

used when tying bidirectional signals to power or ground. When tying any signal to power or

ground, a resistor will also allow for system testability. For unused GTL+ input or I/O si gnal s, use

pull-up resistors of the same value as the on-die termination resistors (R TT). Refer to Table 2-18 for

more details.

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die

termination. Inputs and used outputs must be terminated on the system board. Unused outputs may

be terminated on the system board or left un conn ected. Note that leaving unused outputs

unterminated may interfere with some TAP function s, com plicate debug probing, and prevent

boundary scan testing.

FCx signals are signals that are available for compatibility with other processors.

The TESTHI signals must be tied to the processor VTT using a matched resistor, where a matched

resistor has a resistance value within ±20% of the impedance of the board transmission line traces.

For example, if the trace impedance is 60 Ω, then a value between 48 Ω and 72 Ω is required.

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.

A matched resistor must be used for each group:

•TESTHI[1:0]

•TESTHI[7:2]

•TESTHI8 – cannot be grouped with other TESTHI signals

•TESTHI9 – cannot be grouped with other TESTHI signals

•TESTHI10 – cannot be grouped with other TESTHI signals

•TESTHI11 – cannot be grouped with other TESTHI signals

•TESTHI12 – cannot be grouped with other TESTHI signals

•TESTHI13 – cannot be grouped with other TESTHI signals

Datasheet 21

Electrical Specifications

2.6 FSB Signal Groups

The FSB signals have been combined into groups by buffer type. GTL+ input signals have

differential input buffers, which use GTLREF as a reference level. In this document, the term

"GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving.

Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when

driving.

With the im plementation of a source synchronous data bus comes the need to sp ecify two sets of

timing parameters. One set is for common clock signals which are dependent upon the rising edge

of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals

which are relative to their respective strobe lines (data and address) as well as the rising edge of

BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at

any time during the clock cycle. Table 2-3 identifies which signals are common clock, source

synchronous, and asynchronous.

Table 2-3. FSB Signal Groups

Signal Group Type Signals1

GTL+ Common Clock Input Synchronous to

BCLK[1:0] BPRI#, DEFER#, RS[2:0]#, RSP#, TRDY#

GTL+ Common Clock I/O Synchronous to

BCLK[1:0] AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#,

DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#

GTL+ Source Synchronous I/O Synchronous to assoc.

strobe

GTL+ Strobes Synchronous to

BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

GTL+ Asynchronous Input A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,

STPCLK#, RESET#

GTL+ Asynchronous Output FERR#/PBE#, IERR#, THERMTRIP#

GTL+ Asynchronous Input/Output PROCHOT#

TAP Input Synchronous to TCK TCK, TDI, TMS, TRST#

TAP Output Synchronous to TCK TDO

FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]2

Power/Other

VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF,

COMP[1:0], RESERVED, TESTHI[13:0], THERMDA,

THERMDC, VCC_SENSE, VSS_SENSE, BSEL[2:0],

SKTOCC#, DBR#2, VTTPWRGD, BOOTSELECT, PWRGOOD,

VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0],

FCx, VSS_MB_REGULATION, VCC_MB_REGULATION,

MSID[1:0]

Signals Associated Strobe

REQ[4:0]#, A[16:3]#3ADSTB0#

A[35:17]#3ADSTB1#

D[15:0]#, DBI0# DSTBP0#, DSTBN0#

D[31:16]#, DBI1# DSTBP1#, DSTBN1#

D[47:32]#, DBI2# DSTBP2#, DSTBN2#

D[63:48]#, DBI3# DSTBP3#, DSTBN3#

22 Datasheet

Electrical Specifications

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. In processor systems where there is no debug port implemented on the system board, these signals are used

to support a debug port interposer. In systems with the debug port implemented on the system board, these

signals are no connects.

3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration

options. See Section 6.1 for details.

2.7 GTL+ Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input

buffers. All of these signals follow the same DC requirements as GTL+ signals, however the

outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. These

signals do not have setup or hold time specifications in rel ation to BCLK[1 :0].

All of the GTL+ Asynchronous signals are required to be asserted/de-asserted for at least six

BCLKs for the processor to recognize the proper signal state. See Section 6.2 for additional timing

requirements for entering and leaving the low power states.

Table 2-4. Signal Characteristics

Signals with RTT Signals with no RTT

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,

BNR#, BOOTSELECT1, BPRI#, D[63:0]#, DBI[3:0]#,

DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,

PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

NOTES:

1. The BOOTSELECT signal has a 500-5000 Ω pull-up to VTT rather than on-die te rmination.

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0],

COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,

LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,

SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0],

THERMDA, THERMDC, THERMTRIP#, VID[5:0],

VTTPWRGD, GTLREF, TCK, TDI, TRST#, TMS

Open Drain Signals2

2. Signals that do not have RTT, nor are actively driven to their high-voltage level.

BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/PBE#,

IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, LL_ID[1:0],

MSID[1:0]

Table 2-5. Signal Reference Voltages

GTLREF VTT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#,

BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#,

A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,

DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,

RSP#, TRDY#

BOOTSELECT, VTTPWRGD, A20M#,

IGNNE#, INIT#, PWRGOOD1, SMI#,

STPCLK#, TCK1, TDI1, TMS1, TRST#1

NOTES:

1. These signals also have hysteresis added to the reference voltage. See Table 2-13 for more information.

Datasheet 23

Electrical Specifications

2.8 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is

recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and

followed by any other componen ts within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of accepting an input

of the appropriate voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI,

and TDO. Two copies of each signal may be required, with each driving a different voltage level.

2.9 FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor in put clock (BCLK[1:0]).

Table 2-6 defines the possible combinations of the signals and the frequency associated with each

combination. The required freque ncy is determined by the processor, chipset, and clock

synthesizer. All agents must operate at the same frequency.

The Pentium 4 processor in the 775-land package currently operates at a 533 MHz or 800 MHz

FSB frequency (selected by a 133 MHz or 200 MHz BCLK[1:0] frequency). Individual processors

will only operate at their specified FSB frequency.

For more information about these signals, refer to Section 4.2.

Table 2-6. BSEL [2 :0 ] Freq u en cy Table fo r BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L RESERVED

L L H 133 MHz

L H H RESERVED

L H L 200 MHz

H L L RESERVED

H L H RESERVED

H H H RESERVED

H H L RESERVED

24  Datasheet
Electrical Specifications
2.10 Absolute Maximum and Minimum Ratings
Table 2-7 specifies absolute maxi mum and minimum ratings. Within functional operation limits, 
functionality and long-term reliability can be expected.
At conditions outside functional  operation condition limits, but within absolute maximum and  
minimum ratings, neither functionality nor long-term reliability can be expected. If a device is 
returned to conditions within functional operation limits after having been subjected to conditions 
outside these limits, bu t within the absolute maximum and minimum ratings, the device may be 
functional, but with its lifetime degraded depending on exposure to conditions exceeding the 
functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-
term reliability can be expected. Moreover, if a device is subjected to these conditions for any 
length of time then, when returned to conditions within the functional operating condition limits, it 
will either not function, or its reliability will be severely degraded.
Although the processor contains protective circuitry to resist damage from static electric discharge, 
precautions should always be taken to avoid high static voltages or electric fields.
2.11 Processor DC Specifications
The processor DC specifications in this section are defined at the processor core silicon and 
not at the package lands unless noted otherwise. See Chapter 4 for the signal definitions and 
signal assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The 
DC specifications for these signals are listed in Table 2-12.
Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-vo ltage 
CMOS buffe r types. However , thes e interfaces now follow DC specifications similar to GTL+. The 
DC specifications for these signal groups are listed in Table 2-11 and Table 2-13.
Table 2-8 through Table 2-15 list the DC specifications for the Pentium 4 processor in the 775-land 
package and are valid only while meeting specifications for case temperature, clock frequency, and 
input voltages. Care should be taken to read all notes associated with each parameter.
MSR_PLATFORM_BRV bit 18 is a Platform Requirement Bit (PRB) that indicates that the 
processor has specific platform requirements.
Table 2-7. Processor DC Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes1, 2
NOTES:
1. For functional operation,  all processor electrical, signal quality,  mechanical and thermal specificatio ns must be satisfied.
2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
VCC Core voltage with respect to 
VSS  –0.3 1.55 V —
VTT FSB termination voltage with 
respect to VSS –0.3 1.55 V —
TCProcessor case temperature See Section 5 See Section 5 °C —
TSTORAGE Processor storage temperature  –40  +85 °C 3, 4
3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and
no lands can be connected to a vo ltage bia s. Storage within these limits will not affe ct the lon g-term rel iabili ty of th e device.
For functional operation,  refer to the processor case temperature specifications.
4. This rating applies to the processor and does not include any tray or packaging.

 Datasheet 25
Electrical Specifications
Table 2-8. Voltage and Current Specifications (Sheet 1 of 2)
Symbol Parameter Min Typ Max Unit Notes1
VID range VID 1.200 — 1.425 V 2
Processor Number Core Frequency
VCC 570/571
560/561
550
VCC for 775_VR_CONFIG_04B 
processors
3.80 GHZ (PRB = 1)
3.60 GHz (PRB = 1)
3.40 GHz (PRB = 1)
Refer to Table 2-10 and 
Figure 2-3 V3, 4, 5, 6
VCC 550/551
540/541
530/531
520/521
VCC for 775_VR_CONFIG_04A 
processors
3.40 GHz (PRB = 0)
3.20 GHz (PRB = 0)
3 GHz (PRB = 0)
2.80 GHz (PRB = 0)
Refer to Table 2-9 and 
Figure 2-2 V3, 4, 6, 7, 8
ICC
570/571
560/561
550
550/551
540/541
530/531
520/521
ICC for processor with multiple 
VID 3.80 GHZ (PRB = 1)
3.60 GHz (PRB = 1)
3.40 GHz (PRB = 1)
3.40 GHz (PRB = 0)
3.20 GHz (PRB = 0)
3 GHz (PRB = 0)
2.80 GHz (PRB = 0)
——
119
119
119
78
78
78
78
A9
ISGNT
570/571
560/561
550
550/551
540/541
530/531
520/521
ICC Stop-Grant
3.80 GHZ (PRB = 1)
3.60 GHz (PRB = 1)
3.40 GHz (PRB = 1)
3.40 GHz (PRB = 0)
3.20 GHz (PRB = 0)
3 GHz (PRB = 0)
2.80 GHz (PRB = 0)
——
56
56
56
40
40
40
40
A10, 11, 15
IENHANCED_AUTO_
HALT
570/571
560/561
550/551
540/541
530/531
520/521
ICC Enhanced Auto Halt
3.80 GHZ (PRB = 1)
3.60 GHz (PRB = 1)
3.40 GHz (PRB = 0)
3.20 GHz (PRB = 0)
3 GHz (PRB = 0)
2.80 GHz (PRB = 0)
——
37
37
31
31
40
40
A11, 15
ITCC ICC TCC active — — ICC A12
VTT FSB termination voltage (DC+AC specifications) 1.14 1.20 1.26 V 13, 14
VTT_OUT ICC DC Current that may be drawn from VTT_OUT per pin — — 580 mA
ITT FSB termination current — — 3.5 A 15, 16

26  Datasheet
Electrical Specifications
ICC_VCCA ICC FOR PLL LANDS — — 120 mA 15
ICC_VCCIOPLL ICC FOR I/O PLL LAND — — 100 mA 15
ICC_GTLREF ICC for GTLREF — — 200 µA15
NOTES:
1. Unless otherwise note d, al l specificat ions in t his table ar e  based on esti mates an d si mulat ions  or emp irical dat a. Th ese spec ifications will be up-
dated with characterized data from silicon measur ements at a later date.
2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered.
Individual maximum VID values are calibrate d during manu facturing su ch tha t two pro cessors at th e same freque ncy may ha ve diffe r ent se ttings
within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2 or En-
hanced HALT State).
3. These voltages are targets onl y. A variable voltage source should exist on systems in the even t that a different voltage is required. Se e Section 2.4
and Table 2-2 for more information.
4. The voltage specificat ion  requiremen ts ar e mea sured a cross  VCC_SE NSE a nd VS S_S ENSE land s a t the  socke t with a  100  MHz  band width os-
cilloscope, 1.5 pF maximum pr obe capacitance, and 1 MΩ minimum imped ance. The maximum length of ground wir e on the probe should be less
than 5 mm. Ensure external noise from t he system i s not coupled into the oscilloscope probe.
5. Refer to Table 2-10 and Figure 2-3 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be sub-
jected to any Vcc and Icc combination wherein VCC exceeds Vcc_max for a given current.
6. 775_VR_CONFIG_04A and 775_VR_CONFIG_04B refer to voltage regulator configurations that are defined in the Voltage Regulator Down
(VRD) 10.1 Design Guide For Desktop LGA775 Socket.
7. Refer to Table 2-9 and Figure 2-2  for the minimum, typical, an d maximum VCC allowed for a g iven current. The processor sho uld not be subjected
to any VCC and ICC combination wherein VCC exceeds VCC_max for a given current.
8. These frequencies will operate in a system designed for 775_VR_CONFIG_04B processors. The power and ICC will be incrementally higher in
this configuration due to the improved loadline and resulting higher VCC.
9. Icc_max is specified at VCC_max.
10. The current specified is also for AutoHALT State.
11. Icc Stop-Grant and ICC Enhanced Auto Halt are specified at  VCC_max.
12. The maximum insta ntaneous current the processor  will draw while the thermal contr ol circuit is active as indicated by the assertion of PROCHOT#
is the same as the maximum Icc for the processor.
13. VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured  at the land.
14. Baseboard bandwi dth is limited to 20 MHz.
15. These parameters are based on design characterizatio n and are not tested.
16. This is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT
(through the signal line). Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket to determine the total ITT
drawn by the system.
Table 2-8. Voltage and Current Specifications (Sheet 2 of 2)
Symbol Parameter Min Typ Max Unit Notes1

Datasheet 27

Electrical Specifications

Table 2-9. VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Processors

ICC (A)

Voltage Deviation from VID Setting (V)1, 2, 3, 4

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.12.

2. This table is intended to aid in reading discrete points on Figure 2-2.

3. The loadlines specif y voltage limit s at the die measured at the VCC_SENS E and VSS_SENSE lands. V oltage

regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to

the V oltage Regulator Down (VRD) 10.1 Desi gn Guide For Desktop LGA775 Socket for socket loadline guide-

lines and VR implementation detail s.

4. Adherence to this loadline specificat ion for the processor is required to ensure reliable processor operation.

Maximum Voltage

1.70 mΩ

Typical Voltage

1.75 mΩ

Minimum Voltage

1.80 mΩ

0 0.000 -0.025 -0.050

5 -0.009 -0.034 -0.059

10 -0.017 -0.043 -0.068

15 -0.026 -0.051 -0.077

20 -0.034 -0.060 -0.086

25 -0.043 -0.069 -0.095

30 -0.051 -0.078 -0.104

35 -0.060 -0.086 -0.113

40 -0.068 -0.095 -0.122

45 -0.077 -0.104 -0.131

50 -0.085 -0.113 -0.140

55 -0.094 -0.121 -0.149

60 -0.102 -0.130 -0.158

65 -0.111 -0.139 -0.167

70 -0.119 -0.148 -0.176

75 -0.128 -0.156 -0.185

78 -0.133 -0.162 -0.190

28 Datasheet

Electrical Specifications

NOTES:

1. The loadline specification includes both static and transient limits except for oversho ot allowed as shown in Section 2.12.

2. This loadline specifica tion shows the deviation from the VID set po int.

3. The loadlines specify voltag e limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation

feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadl ine guidelines and VR implementation deta ils.

4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

Figure 2-2. VCC Static and Transient Tolerance for 775_VR_CONFIG_04A

VID - 0.000

VID - 0.025

VID - 0.050

VID - 0.075

VID - 0.100

VID - 0.125

VID - 0.150

VID - 0.175

VID - 0.200

0 10203040506070

Icc [A]

Vcc [V]

Vcc Maximum

Vcc Typical

Vcc Minimum

Datasheet 29

Electrical Specifications

Table 2-10. VCC Static and Transient Tolerance for 775_VR_CONFIG_04B Processors

ICC (A)

Voltage Deviation from VID Setting (V)1, 2, 3, 4

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.12.

2. This table is intended to aid in reading discrete points on Figure 2-2.

3. The loadlines specif y voltage limit s at the die measured at the VCC_SENS E and VSS_SENSE lands. V oltage

regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to

the V oltage Regulator Down (VRD) 10.1 Desi gn Guide For Desktop LGA775 Socket for socket loadline guide-

lines and VR implementation detail s.

4. Adherence to this loadline specificat ion for the processor is required to ensure reliable processor operation.

Maximum Voltage

1.30 mΩ

Typical Voltage

1.35 mΩ

Minimum Voltage

1.40 mΩ

0 0.000 -0.019 -0.038

5 -0.007 -0.026 -0.045

10 -0.013 -0.033 -0.052

15 -0.020 -0.039 -0.059

20 -0.026 -0.046 -0.066

25 -0.033 -0.053 -0.073

30 -0.039 -0.060 -0.080

35 -0.046 -0.066 -0.087

40 -0.052 -0.073 -0.094

45 -0.059 -0.080 -0.101

50 -0.065 -0.087 -0.108

55 -0.072 -0.093 -0.115

60 -0.078 -0.100 -0.122

65 -0.085 -0.107 -0.129

70 -0.091 -0.114 -0.136

75 -0.098 -0.120 -0.143

80 -0.104 -0.127 -0.150

85 -0.111 -0.134 -0.157

90 -0.117 -0.141 -0.164

95 -0.124 -0.147 -0.171

100 -0.130 -0.154 -0.178

105 -0.137 -0.161 -0.185

110 -0.143 -0.168 -0.192

115 -0.150 -0.174 -0.199

119 -0.155 -0.180 -0.205

30 Datasheet

Electrical Specifications

NOTES:

1. The loadline specification includes both static and transient limits except for oversho ot allowed as shown in Section 2.12.

2. This loadline specifica tion shows the deviation from the VID set po int.

3. The loadlines specify voltag e limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation

feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadl ine guidelines and VR implementation deta ils.

4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

Figure 2-3. VCC Static and Transient Tolerance for 775_VR_CONFIG_04B

VID - 0.000

VID - 0.019

VID - 0.038

VID - 0.057

VID - 0.076

VID - 0.095

VID - 0.114

VID - 0.133

VID - 0.152

VID - 0.171

VID - 0.190

VID - 0.209

VID - 0.228

0 102030405060708090100110120

Icc [A]

Vcc [V]

Vcc Maximum

Vcc Typical

Vcc Minimum

Datasheet 31

Electrical Specifications

Table 2-11. GTL+ Asynchronous Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

VIL Input Low Voltage 0.0 VTT/2 – (0.10 * VTT)V

2, 3

2. VIL is defined as the voltage range at a receiving agent that wi ll be interpreted as a logical low value.

3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals VIH = GTLREF + (0.10 * VTT) and

VIL= GTLREF – (0.10 * VTT).

VIH Input High Voltage VTT/2 + (0.10 * VTT)V

TT V3, 4, 5, 6

4. VIH is defined as the voltage range at a recei vin g agent that will be interpreted as a logical high value.

5. VIH and VOH may expe rience excursions abo ve VTT. However, input sig nal drivers must comply with the signal qu ality spec-

ifications.

6. The VTT referred to in these specifications refers to instantaneous VTT.

VOH Output High Voltage 0.90*VTT VTT V5, 6, 7

7. All outputs are open drain.

IOL Output Low Current — VTT/[(0.50*RTT_MIN) +

RON_MIN]A8

8. The maximum output current is based on maximum current handling capabilit y of the buffer and is not specified into the test

load.

ILI Input Leakage Current N/A ± 200 µA 9

9. Leakage to VSS with land held at VTT.

ILO Output Leakage Current N/A ± 200 µA 10

10. Leakage to VTT with land held at 300 mV.

RON Buffer On Resistance 8 12 Ω-

Table 2-12. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

VIL Input Low Voltage 0.0 GTLREF – (0.10 * VTT)V

2, 3

2. VIL is defined as the voltage range at a receiving agent that wi ll be interpreted as a logical low value.

3. The VTT referred to in these specifications is the instantan eous VTT.

VIH Input High Voltage GTLREF + (0.10 * VTT)V

TT V3, 4

4. VIH is defined as the voltage range at a recei vin g agent that will be interpreted as a logical high value.

VOH Output High Voltage 0.90*VTT VTT V3

IOL Output Low Current N/A VTT/[(0.50*RTT_MIN) +

RON_MIN]A-

ILI Input Leakage Current N/A ± 200 µA 5

5. Leakage to VSS with land held at VTT.

ILO Output Leakage Current N/A ± 200 µA -

RON Buffer On Resistance 8 12 Ω-

32 Datasheet

Electrical Specifications

Table 2-13. PWRGOOD and TAP Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1, 2

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. All outputs are open drain.

VHYS Input Hysteresis 200 350 mV 3

3. VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT, for all TAP inputs.

VT+ Input low to high

threshold voltage 0.5 * (VTT + VHYS_MIN) 0.5 * (VTT + VHYS_MAX)V 4

4. The VTT referred to in these specifications refers to instantaneous VTT.

VT- Input high to low

threshold voltage 0.5 * (VTT – VHYS_MAX) 0.5 * (VTT – VHYS_MIN)V 4

VOH Output High Voltage N/A VTT V4

IOL Output Low Current — 45 mA 5

5. The maximum output current is based o n maximum current handlin g capabil ity of the b uffer and is not specified i nto the test

load.

ILI Input Leakage Current — ± 200 µA 6

6. Leakage to VSS with land held at VTT.

ILO Output Leakage Current — ± 200 µA -

RON Buffer On Resistance 7 12 Ω-

Table 2-14. VTTPWRGD DC Specifications

Symbol Parameter Min Typ Max Unit Notes

VIL Input Low Voltage — — 0.3 V

VIH Input High Voltage 0.9 — — V

Table 2-15. BSEL [2:0] and VID[5:0] DC Specifications

Symbol Parameter Max Unit Notes1, 2

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. These parameters are not tested and are based on design simulations.

RON (BSEL) Buffer On Resistance 60 Ω—

RON (VID) Buffer On Resistance 60 Ω—

IOL Max Land Current 8 mA —

ILO Output Leakage Current 200 µA 3

3. Leakage to VSS with land held at 2.5 V.

VTOL Voltage Tolerance VTT (max) V —

Table 2-16. BOOTSELECT DC Specifications

Symbol Parameter Min Typ Max Unit Notes

VIL Input Low Voltage — — 0.24 V 1

NOTES:

1. These parameters are not tested and are based on design simulations.

VIH Input High Voltage 0.96 — — V —

Datasheet 33

Electrical Specifications

2.12 VCC Overshoot Specification

The Pentium 4 processor in the 775-land package can tolerate short transient overshoot event s

where VCC exceeds the VID voltage when transitioning from a high to low current load condition.

This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot

voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the

maximum allowable ti me duration above VID). These specifications apply to the processor die

voltage as measured across the VCC _SEN SE and VSS_ SENSE lands.

NOTES:

1. VOS is measured overshoot voltage.

2. TOS is measured time duration above VID.

2.12.1 Die Voltage Validation

Overshoot events from application testing on real processors must meet the specificatio ns in

Table 2-17 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that

are < 10 ns in duration may be ignored. These measurements of processor die level overshoot

should be taken with a 100 MHz bandwidth limited os cilloscope. Refer to the Voltage Regulator

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for additional voltage regulator

validation details.

Table 2-17. VCC Overshoot Specifications

Symbol Parameter Min Typ Max Unit Figure

VOS_MAX Magnitude of VCC

overshoot above VID — — 0.050 V 2-4

TOS_MAX Tim e duration of VCC

overshoot above VID —— 25 µs2-4

Figure 2- 4. VCC Overshoot Example Waveform

Time

Example Overshoot Waveform

Voltage (V)

VID

VID + 0.050

TOS

VOS

TOS: Overshoot time above VID

VOS: Overshoot above VID

34 Datasheet

Electrical Specifications

2.13 GTL+ FSB Specifications

Termination resistors are not required for most GTL+ signals, as these are integrated into the

processor silicon.Valid high and low levels are determined by the input buffers which compare a

signal’s voltage with a reference voltage called GTLREF. Table 2-18 lists the GTLREF

specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board

using high precision vo ltage di vider circuits.

Table 2-18. GTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes1

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

GTLREF Bus Reference

Voltage (0.98 * 0.67) * VTT 0.67 * VTT (1.02 * 0.67 ) * VTT V2, 3, 4, 5

2. The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum

and maximum values across the range of VTT.

3. GTLREF should be generated from VTT by a vo ltage divider of 1% resistors or 1% matched resistors.

4. The VTT referred to in these specifications is the instantaneous VTT.

5. The Intel® 915G/915GV/ 915P and 910GL Express chip set platforms use a pull-up resist or of 100 Ω and a pull- down resistor

of 210 Ω. Contact your Intel representati ve for further details and documentation.

RPULLUP

On die pullup for

BOOTSELECT

signal 500 — 5000 Ω6

6. These pull-ups are to VTT.

RTT Termination

Resistance 54 60 66 Ω7

7. RTT is the on-die termination resistance measured at VTT/2 of the GTL+ output driver.

COMP[1:0] COMP Resistance 59.8 60.4 61 Ω8

8. COMP resistance must be provided on the system board with 1% resistors. COMP[1:0] resistors are to VSS.

Datasheet 35

Package Mechanical Specifications

3Package Mechanical

Specifications

The Pentium 4 processor in the 775-land package is packaged in a Flip-Chip Land Grid Array

(FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package

consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)

is attached to the package substrate and core and serves as the mating surface for processor

component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor

package components and how they are assembled toge th er. Refer to the LGA775 Socket

Mechanical Design Guide for complete details on the LGA775 socket .

The package components shown in Figure 3-1 include the following:

•Integrated Heat Spreader (IHS)

•Thermal Interface Material (TIM)

•Processor core (die)

•Package substrate

•Capacitors

NOTE:

1. Socket and motherboard are included for reference and are not part of processor package.

3.1 Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-4. The drawings include

dimensions necessary to design a thermal solution for the processor. These dimensions include:

•Package reference with tolerances (total height, length, width, etc.)

•IHS parallelism and tilt

•Land dimensions

•Top-side and back-side compon ent keep-out dim ensions

•Reference datums

All drawing dimensions are in mm [in].

Note: Guidelines on potential IH S flatness variation with socket load plate actuatio n and installation of

the cooling solution is available in the processor Thermal/Mechanical Design Guidelines.

Figure 3-1. Processor Package Assembly Sketch

IHS

Substrate

LGA775 Socket

System Board

Capacitors

Core (die) TIM

IHS

Substrate

LGA775 Socket

System Board

Capacitors

Core (die) TIM

36 Datasheet

Package Mechanical Specificatio ns

Figure 3-2. Processor Package Drawing 1

Datasheet 37

Package Mechanical Specifications

Figure 3-3. Processor Package Drawing 2

38 Datasheet

Package Mechanical Specificatio ns

Figure 3-4. Processor Package Drawing 3

Datasheet 39

Package Mechanical Specifications

3.2 Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-out zone

requirements. A thermal and mechanical solution design must not intrude into the required keep-

out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the

package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.

The location and quantity of package capacitors may change due to manufacturing efficiencies but

will remain within the component keep-in.

3.3 Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package. These

mechanical maximum load limits should not be exceeded during heatsink assembly, shipping

conditions, or standard use condit ion. Also, any mechanical system or component testing shoul d

not exceed the maximum limits. The processor package substrate should not be used as a

mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum

loading specification must be maintained by any thermal and mechanical solutions.

3.4 Package Handling Guidelines

Table 3-2 includes a list of guideli nes on package hand ling in terms of recommended maximum

loading on the processor IHS relative to a fixed substrate. These package handling loads may be

experienced during heatsink removal.

Table 3-1. Processor Loading Specifications

Parameter Minimum Maximum Notes

Static 80 N [18 lbf] 311 N [70 lbf] 1, 2, 3

NOTES:

1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS.

2. This is the maximum force that ca n be applied by a heatsink retentio n clip. The clip must also provide t he minimum specified

load on the processor package.

3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and

does not include the limit s of the processor socket.

Dynamic — 756 N [170 lbf] 1, 3, 4

4. Dynamic loading is defined as the sum of the load on the package from a 1 lb heatsink mass accelerating through a 11 ms

trapezoidal pulse of 50 g and the maximum static load.

Table 3-2. Package Handling Guidelines

Parameter Maximum Recommended Notes

Shear 311 N [70 lbf] 1, 4

NOTES:

1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

Tensile 111 N [25 lbf] 2, 4

2. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.

Torque 3.95 N-m [35 lbf-in] 3, 4

3. A torque load is defined as a twisting loa d applied to the IHS in an axis of rotation normal to the IHS top surfa ce.

4. These guidelines are based on limite d test ing for design characterizatio n.

40 Datasheet

Package Mechanical Specificatio ns

3.5 Package Insertion Specifications

The Pentium 4 processor in the 775-land pack ag e can be inserted into and removed from a

LGA775 socket 15 times. The socket should meet the LGA775 requirem e nts detail ed in the

LGA775 Socket Mechanical Design Guide.

3.6 Processor Mass Specification

The typical mass of the Pentium 4 processor in the 775-land package is 21.5 g [0.76 oz]. This mass

[weight] includes all the components that are included in the package.

3.7 Processor Materials

Table 3-3 lists some of the package components and associated materials.

3.8 Processor Markings

Figure 3-5 and Figure 3-6 show the topside markings on the processor. These diagrams aid in the

identification of the Pentiu m 4 processo r in the 775-land package.

Table 3-3. Processor Materials

Component Material

Integrated Heat Spreader (IHS) Nickel Plated Copper

Substrate Fiber Reinforced Resin

Substrate Lands Gold Plated Copper

Figure 3-5. Processor Top-Side Marking Example

ATPO

S/N

S- Spec/Country of Assy INTEL

Pentium 4

SLxxx [COO]

[FPO]

m©‘04

Frequency/L2 Cache/Bus/

775_VR_CONFIG_04x

FPO

2-D Matrix Mark Unique Unit

Identifier

ATPO Serial #

3.60GHz/1M/800/04B

Datasheet 41

Package Mechanical Specifications

3.9 Processor Land Coordinates

Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to

throughout the document to identify processor lands.

Figure 3-6. Processor Top-Side Marking Example for Processors Supporting Intel® EM64T

ATPO

S/N

Processor Number/S-Spec/

Country of Assy INTEL

Pentium 4

3.80GHZ/1M/800/04B

[FPO]

m©‘04

Fr equency/L2 Cache/Bus/

775_VR_CONFIG_04x

FPO

2-D Matrix Mark Unique Unit

Identifier

ATPO Serial #

571 SLxxx [COO]

42 Datasheet

Package Mechanical Specificatio ns

Figure 3-7. Processor Land Coordinates (Top View)

123456789101112131415161718192021222324252627282930

123456789

101112131415161718192021222324252627282930

Socket 775

Quadrants

Top V iew

VCC / VSS

VTT / Clo ck s Data

Address / Common

Clock / Async

Datasheet 43

Land Listing and Signal Descriptions

4Land Listing and Signal

Descriptions

This chapter provides the processor land assignment and signal de script ions.

4.1 Processor Land Assignments

This section contains the land listings for the Pentium 4 pro cessor in the 775-land package. The

landout footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the landout

arranged by land number and they show the physical location of each signal on the package land

array (to p view). Table 4-1 is a listing of all processor lands ordered alphabetically by land (signal)

name. Table 4-2 is also a listing of all processo r lands; the ordering is by land numb er.

44 Datasheet

Land Listing and Signal Descriptions

Figure 4-1. Landout Diagram (Top View – Left Side)

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15

AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AM VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AL VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AK VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AJ VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AH VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AG VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AF VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC

AE VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC

AD VCC VCC VCC VCC VCC VCC VCC VCC

AC VCC VCC VCC VCC VCC VCC VCC VCC

AB VSS VSS VSS VSS VSS VSS VSS VSS

AA VSS VSS VSS VSS VSS VSS VSS VSS

YVCC VCC VCC VCC VCC VCC VCC VCC

WVCC VCC VCC VCC VCC VCC VCC VCC

VVSS VSS VSS VSS VSS VSS VSS VSS

UVCC VCC VCC VCC VCC VCC VCC VCC

TVCC VCC VCC VCC VCC VCC VCC VCC

RVSS VSS VSS VSS VSS VSS VSS VSS

PVSS VSS VSS VSS VSS VSS VSS VSS

NVCC VCC VCC VCC VCC VCC VCC VCC

MVCC VCC VCC VCC VCC VCC VCC VCC

LVSS VSS VSS VSS VSS VSS VSS VSS

KVCC VCC VCC VCC VCC VCC VCC VCC

JVCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DP3# DP0# VCC

HBSEL1 GTLREF

_SEL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DP2# DP1#

GBSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31#

FRSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD VSS D43# D41# VSS D38# D37# VSS D30#

EVSS VSS VSS VSS VSS RSVD RSVD D45# D42# VSS D40# D39# VSS D34# D33#

DVTT VTT VTT VTT VTT VTT VSS RSVD D46# VSS D48# DBI2# VSS D49# RSVD VSS

CVTT VTT VTT VTT VTT VTT VSS VCCIO

PLL VSS D58# DBI3# VSS D54# DSTBP3# VSS D51#

BVTT VTT VTT VTT VTT VTT VSS VSSA D63# D59# VSS D60# D57# VSS D55# D53#

AVTT VTT VTT VTT VTT VTT VSS VCCA D62# VSS RSVD D61# VSS D56# DSTBN3# VSS

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15

Datasheet 45

Land Listing and Signal Descriptions

Figure 4-2. Landout Diagram (Top View – Right Side)

14 13 12 11 10 9 8 7 6 5 4 3 2 1

VCC VSS VCC VCC VSS VCC VCC FC16 VSS_MB_

REGULATION VCC_MB_

REGULATION VSS_

SENSE VCC_

SENSE VSS VSS AN

VCC VSS VCC VCC VSS VCC VCC FC12 VTTPWRGD FC11 VSS VID2 VID0 VSS AM

VCC VSS VCC VCC VSS VCC VCC VSS VID3 VID1 VID5 VSS PROCHOT# THERMDA AL

VCC VSS VCC VCC VSS VCC VCC VSS RSVD VSS VID4 ITP_CLK0 VSS THERMDC AK

VCC VSS VCC VCC VSS VCC VCC VSS A35# A34# VSS ITP_CLK1 BPM0# BPM1# AJ

VCC VSS VCC VCC VSS VCC VCC VSS VSS A33# A32# VSS RSVD VSS AH

VCC VSS VCC VCC VSS VCC VCC VSS A29# A31# A30# BPM5# BPM3# TRST# AG

VCC VSS VCC VCC VSS VCC VCC VSS VSS A27# A28# VSS BPM4# TDO AF

VCC VSS VCC VCC VSS VCC SKTOCC# VSS RSVD VSS RSVD RSVD VSS TCK AE

VCC VSS A22# ADSTB1# VSS BINIT# BPM2# TDI AD

VCC VSS VSS A25# RSVD VSS DBR# TMS AC

VCC VSS A17# A24# A26# MCERR# IERR# VSS AB

VCC VSS VSS A23# A21# VSS LL_ID1 VTT_OUT_

RIGHT AA

VCC VSS A19# VSS A20# RSVD VSS BOOT

SELECT Y

VCC VSS A18# A16# VSS TESTHI1 TESTHI12 MSID0 W

VCC VSS VSS A14# A15# VSS LL_ID0 MSID1 V

VCC VSS A10# A12# A13# AP1# AP0# VSS U

VCC VSS VSS A9# A11# VSS FC4 COMP1 T

VCC VSS ADSTB0# VSS A8# FERR#/

PBE# VSS FC2 R

VCC VSS A4# RSVD VSS INIT# SMI# TESTHI11 P

VCC VSS VSS RSVD RSVD VSS IGNNE# PWRGOOD N

VCC VSS REQ2# A5# A7# STPCLK# THER-

MTRIP# VSS M

VCC VSS VSS A3# A6# VSS TESTHI13 LINT1 L

VCC VSS REQ3# VSS REQ0# A20M# VSS LINT0 K

VCC VCC VCC VCC VCC VCC VCC VSS REQ4# REQ1# VSS RSVD FC3 VTT_OUT_

LEFT J

VSS VSS VSS VSS VSS VSS VSS VSS VSS TESTHI10 RSP# VSS FC6 GTLREF H

D29# D27# DSTBN1# DBI1# RSVD D16# BPRI# DEFER# RSVD FC7 TESTHI9 TESTHI8 FC1 VSS G

D28# VSS D24# D23# VSS D18# D17# VSS RSVD RS1# VSS BR0# FC5 F

VSS D26# DSTBP1# VSS D21# D19# VSS RSVD RSVD RSVD HITM# TRDY# VSS E

RSVD D25# VSS D15# D22# VSS D12# D20# VSS VSS HIT# VSS ADS# RSVD D

D52# VSS D14# D11# VSS RSVD DSTBN0# VSS D3# D1# VSS LOCK# BNR# DRDY# C

VSS RSVD D13# VSS D10# DSTBP0# VSS D6# D5# VSS D0# RS0# DBSY# VSS B

D50# COMP0 VSS D9# D8# VSS DBI0# D7# VSS D4# D2# RS2# VSS A

14 13 12 11 10 9 8 7 6 5 4 3 2 1

Land Listing and Signal Descriptions

46 Datasheet

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

A3# L5 Source Synch Input/Output

A4# P6 Source Synch Input/Output

A5# M5 Source Synch Input/Output

A6# L4 Source Synch Input/Output

A7# M4 Source Synch Input/Output

A8# R4 Source Synch Input/Output

A9# T5 Source Synch Input/Output

A10# U6 Source Synch Input/Output

A11# T4 Source Synch Input/Output

A12# U5 Source Synch Input/Output

A13# U4 Source Synch Input/Output

A14# V5 Source Synch Input/Output

A15# V4 Source Synch Input/Output

A16# W5 Source Synch Input/Output

A17# AB6 Source Synch Input/Output

A18# W6 Source Synch Input/Output

A19# Y6 Source Synch Input/Output

A20# Y4 Source Synch Input/Output

A20M# K3 Asynch GTL+ Input

A21# AA4 Source Synch Input/Output

A22# AD6 Source Synch Input/Output

A23# AA5 Source Synch Input/Output

A24# AB5 Source Synch Input/Output

A25# AC5 Source Synch Input/Output

A26# AB4 Source Synch Input/Output

A27# AF5 Source Synch Input/Output

A28# AF4 Source Synch Input/Output

A29# AG6 Source Synch Input/Output

A30# AG4 Source Synch Input/Output

A31# AG5 Source Synch Input/Output

A32# AH4 Source Synch Input/Output

A33# AH5 Source Synch Input/Output

A34# AJ5 Source Synch Input/Output

A35# AJ6 Source Synch Input/Output

ADS# D2 Common Clock Input/Output

ADSTB0# R6 Source Synch Input/Output

ADSTB1# AD5 Source Synch Input/Output

AP0# U 2 Comm o n C l oc k In pu t/ Ou tput

AP1# U 3 Comm o n C l oc k In pu t/ Ou tput

BCLK0 F28 Clock Input

BCLK1 G28 Clock Input

BINIT# AD3 Common Clock Input/Output

BNR# C2 Common Clock Input/Output

BOOTSELECT Y1 Power/Other Input

BPM0# AJ2 Common Clock Input/Output

BPM1# AJ1 Common Clock Input/Output

BPM2# AD2 Common Clock Input/Output

BPM3# AG2 Common Clock Input/Output

BPM4# AF2 Common Clock Input/Output

BPM5# AG3 Common Clock Input/Output

BPRI# G8 Common Clock Input

BR0# F3 Common Clock Input/Output

BSEL0 G29 Power/Other Output

BSEL1 H30 Power/Other Output

BSEL2 G30 Power/Other Output

COMP0 A13 Power/Other Input

COMP1 T1 Power/Other Input

D0# B4 Source Synch I nput/Output

D1# C5 Source Synch Input/Output

D2# A4 Source Synch I nput/Output

D3# C6 Source Synch Input/Output

D4# A5 Source Synch I nput/Output

D5# B6 Source Synch I nput/Output

D6# B7 Source Synch I nput/Output

D7# A7 Source Synch I nput/Output

D8# A10 Source Synch Input/Output

D9# A11 Source Synch Input/Output

D10# B10 Source Synch Input/Output

D11# C11 Source Synch Input/Output

D12# D8 Source Synch Input/Output

D13# B12 Source Synch Input/Output

D14# C12 Source Synch Input/Output

D15# D11 Source Synch I nput/Output

D16# G9 Source Synch Input/Output

D17# F8 Source Synch Input/Output

D18# F9 Source Synch Input/Output

D19# E9 Source Synch Input/Output

D20# D7 Source Synch Input/Output

D21# E10 Source Synch Input/Output

D22# D10 Source Synch Input/Output

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 47

D23# F11 Source Synch Input/Output

D24# F12 Source Synch Input/Output

D25# D13 S ource Synch Input/Output

D26# E13 Source Synch Input/Output

D27# G13 Source Synch Input/Output

D28# F14 Source Synch Input/Output

D29# G14 Source Synch Input/Output

D30# F15 Source Synch Input/Output

D31# G15 Source Synch Input/Output

D32# G16 Source Synch Input/Output

D33# E15 Source Synch Input/Output

D34# E16 Source Synch Input/Output

D35# G18 Source Synch Input/Output

D36# G17 Source Synch Input/Output

D37# F17 Source Synch Input/Output

D38# F18 Source Synch Input/Output

D39# E18 Source Synch Input/Output

D40# E19 Source Synch Input/Output

D41# F20 Source Synch Input/Output

D42# E21 Source Synch Input/Output

D43# F21 Source Synch Input/Output

D44# G21 Source Synch Input/Output

D45# E22 Source Synch Input/Output

D46# D22 S ource Synch Input/Output

D47# G22 Source Synch Input/Output

D48# D20 S ource Synch Input/Output

D49# D17 S ource Synch Input/Output

D50# A14 Source Synch Input/Output

D51# C15 S ource Synch Input/Output

D52# C14 S ource Synch Input/Output

D53# B15 Source Synch Input/Output

D54# C18 S ource Synch Input/Output

D55# B16 Source Synch Input/Output

D56# A17 Source Synch Input/Output

D57# B18 Source Synch Input/Output

D58# C21 S ource Synch Input/Output

D59# B21 Source Synch Input/Output

D60# B19 Source Synch Input/Output

D61# A19 Source Synch Input/Output

D62# A22 Source Synch Input/Output

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

D63# B22 So urce Synch Input/Output

DBI0# A8 Source Synch Input/Output

DBI1# G11 Source Synch Input/Output

DBI2# D19 Source Synch Input/Output

DBI3# C20 Source Synch Input/Output

DBR# AC2 Power/Other Output

DBSY# B2 Common Clock Input/Output

DEFER# G7 Common Clock Input

DP0# J16 Common Clock Input/Output

DP1# H15 Common Clock Input/Output

DP2# H16 Common Clock Input/Output

DP3# J17 Common Clock Input/Output

DRDY# C1 Common Clock Input/Output

DSTBN0# C8 Source Synch Input/Output

DSTBN1# G12 Source Synch Input/Output

DSTBN2# G20 Source Synch Input/Output

DSTBN3# A16 Source Synch Input/Output

DSTBP0# B9 Source Synch Input/Output

DSTBP1# E12 Source Synch Input/Out put

DSTBP2# G19 Source Synch Input/Output

DSTBP3# C17 Source Synch Input/Output

FC1 G2 Power/Other Input

FC2 R1 Power/Other Input

FC3 J2 Power/Other Input

FC4 T2 Power/Other Input

FC5 F2 Common Clock Input

FC6 H2 Power/Other Input

FC7 G5 Source Synch Output

FC11 AM5 Power/Other Output

FC12 AM7 Power/Other Output

FC16 AN7 Power/Other Output

FERR#/PBE# R3 Asynch GTL+ Output

GTLREF H1 Power/Other Input

GTLREF_SEL H29 Power/Other Output

HIT# D4 Common Clock Input/Output

HITM# E4 Common Clock Input/Output

IERR# AB2 Asynch GTL+ Output

IGNNE# N2 Asynch GTL+ Input

INIT# P3 Asynch GTL+ Input

ITP_CLK0 AK3 TAP Input

Table 4-1. Alphabetical Land

Assignments

Land Na me Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

48 Datasheet

ITP_CLK1 AJ3 TAP Input

LINT0 K1 Asynch GTL+ Input

LINT1 L1 Asynch GTL+ Input

LL_ID0 V2 Power/Other Output

LL_ID1 AA2 Power/Other Output

LOCK# C3 Common Clock Input/Output

MCERR# AB3 Common Clock Input/Output

MSID0 W1 Power/Other Output

MSID1 V1 Power/Other Output

PROCHOT# AL2 Asynch GTL+ Input/Output

PWRGOOD N1 Power/Other Input

REQ0# K4 Source Synch Input/Output

REQ1# J5 Source Synch Input/Output

REQ2# M6 Source Synch Input/Output

REQ3# K6 Source Synch Input/Output

REQ4# J6 Source Synch Input/Output

RESERVED A20

RESERVED AC4

RESERVED AE3

RESERVED AE4

RESERVED AE6

RESERVED AH2

RESERVED C9

RESERVED D1

RESERVED D14

RESERVED D16

RESERVED E23

RESERVED E24

RESERVED E5

RESERVED E6

RESERVED E7

RESERVED F23

RESERVED F29

RESERVED F6

RESERVED G10

RESERVED B13

RESERVED J3

RESERVED N4

RESERVED N5

RESERVED P5

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

RESERVED Y3

RESERVED D23

RESERVED AK6

RESERVED G6

RESET# G23 Common Clock Input

RS0# B3 Common Clock Input

RS1# F 5 Common Clock Input

RS2# A3 Common Clock Input

RSP# H4 Common Clock Input

SKTOCC# AE8 Power/Other Output

SMI# P2 Asynch GTL+ Input

STPCLK# M3 Asynch GTL+ Input

TCK AE1 TAP Input

TDI AD1 TAP Input

TDO AF1 TAP Output

TESTHI0 F26 Power/Other Input

TESTHI1 W3 Power/Other Input

TESTHI2 F25 Power/Other Input

TESTHI3 G25 Power/Other Input

TESTHI4 G27 Power/Other Input

TESTHI5 G26 Power/Other Input

TESTHI6 G24 Power/Other Input

TESTHI7 F24 Power/Other Input

TESTHI8 G3 Power/Other Input

TESTHI9 G4 Power/Other Input

TESTHI10 H5 Power/Other Input

TESTHI11 P1 Power/Other Input

TESTHI12 W2 Power/Other Input

TESTHI13 L2 Asynch GTL+ Input

THERMDA AL1 Power/Other

THERMDC AK1 Power/Other

THERMTRIP# M2 Asynch GTL+ Output

TMS AC1 TAP Input

TRDY# E3 Common Clock Input

TRST# AG1 TAP Input

VCC AA8 Power/Other

VCC AB8 Power/Other

VCC AC23 Power/Other

VCC AC24 Power/Other

VCC AC25 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 49

VCC AC26 Power/Other

VCC AC27 Power/Other

VCC AC28 Power/Other

VCC AC29 Power/Other

VCC AC30 Power/Other

VCC AC8 Power/Other

VCC AD23 Power/Other

VCC AD24 Power/Other

VCC AD25 Power/Other

VCC AD26 Power/Other

VCC AD27 Power/Other

VCC AD28 Power/Other

VCC AD29 Power/Other

VCC AD30 Power/Other

VCC AD8 Power/Other

VCC AE11 Power/Other

VCC AE12 Power/Other

VCC AE14 Power/Other

VCC AE15 Power/Other

VCC AE18 Power/Other

VCC AE19 Power/Other

VCC AE21 Power/Other

VCC AE22 Power/Other

VCC AE23 Power/Other

VCC AE9 Power/Other

VCC AF11 Power/Other

VCC AF12 Power/Other

VCC AF14 Power/Other

VCC AF15 Power/Other

VCC AF18 Power/Other

VCC AF19 Power/Other

VCC AF21 Power/Other

VCC AF22 Power/Other

VCC AF8 Power/Other

VCC AF9 Power/Other

VCC AG11 Power/Other

VCC AG12 Power/Other

VCC AG14 Power/Other

VCC AG15 Power/Other

VCC AG18 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

VCC AG19 Power/Other

VCC AG21 Power/Other

VCC AG22 Power/Other

VCC AG25 Power/Other

VCC AG26 Power/Other

VCC AG27 Power/Other

VCC AG28 Power/Other

VCC AG29 Power/Other

VCC AG30 Power/Other

VCC AG8 Power/Other

VCC AG9 Power/Other

VCC AH11 Power/Other

VCC AH12 Power/Other

VCC AH14 Power/Other

VCC AH15 Power/Other

VCC AH18 Power/Other

VCC AH19 Power/Other

VCC AH21 Power/Other

VCC AH22 Power/Other

VCC AH25 Power/Other

VCC AH26 Power/Other

VCC AH27 Power/Other

VCC AH28 Power/Other

VCC AH29 Power/Other

VCC AH30 Power/Other

VCC AH8 Power/Other

VCC AH9 Power/Other

VCC AJ11 Power/Other

VCC AJ12 Power/Other

VCC AJ14 Power/Other

VCC AJ15 Power/Other

VCC AJ18 Power/Other

VCC AJ19 Power/Other

VCC AJ21 Power/Other

VCC AJ22 Power/Other

VCC AJ25 Power/Other

VCC AJ26 Power/Other

VCC AJ8 Power/Other

VCC AJ9 Power/Other

VCC AK11 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Na me Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

50 Datasheet

VCC AK12 Power/Other

VCC AK14 Power/Other

VCC AK15 Power/Other

VCC AK18 Power/Other

VCC AK19 Power/Other

VCC AK21 Power/Other

VCC AK22 Power/Other

VCC AK25 Power/Other

VCC AK26 Power/Other

VCC AK8 Power/Other

VCC AK9 Power/Other

VCC AL11 Power/Other

VCC AL12 Power/Other

VCC AL14 Power/Other

VCC AL15 Power/Other

VCC AL18 Power/Other

VCC AL19 Power/Other

VCC AL21 Power/Other

VCC AL22 Power/Other

VCC AL25 Power/Other

VCC AL26 Power/Other

VCC AL29 Power/Other

VCC AL30 Power/Other

VCC AL8 Power/Other

VCC AL9 Power/Other

VCC AM11 Power/Other

VCC AM12 Power/Other

VCC AM14 Power/Other

VCC AM15 Power/Other

VCC AM18 Power/Other

VCC AM19 Power/Other

VCC AM21 Power/Other

VCC AM22 Power/Other

VCC AM25 Power/Other

VCC AM26 Power/Other

VCC AM29 Power/Other

VCC AM30 Power/Other

VCC AM8 Power/Other

VCC AM9 Power/Other

VCC AN1 1 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

VCC AN12 Power/Other

VCC AN14 Power/Other

VCC AN15 Power/Other

VCC AN18 Power/Other

VCC AN19 Power/Other

VCC AN21 Power/Other

VCC AN22 Power/Other

VCC AN25 Power/Other

VCC AN26 Power/Other

VCC AN29 Power/Other

VCC AN30 Power/Other

VCC AN8 Power/Other

VCC AN9 Power/Other

VCC J10 Power/Other

VCC J11 Power/Other

VCC J12 Power/Other

VCC J13 Power/Other

VCC J14 Power/Other

VCC J15 Power/Other

VCC J18 Power/Other

VCC J19 Power/Other

VCC J20 Power/Other

VCC J21 Power/Other

VCC J22 Power/Other

VCC J23 Power/Other

VCC J24 Power/Other

VCC J25 Power/Other

VCC J26 Power/Other

VCC J27 Power/Other

VCC J28 Power/Other

VCC J29 Power/Other

VCC J30 Power/Other

VCC J8 Power/Other

VCC J9 Power/Other

VCC K23 Power/Other

VCC K24 Power/Other

VCC K25 Power/Other

VCC K26 Power/Other

VCC K27 Power/Other

VCC K28 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 51

VCC K29 Power/Other

VCC K30 Power/Other

VCC K8 Power/Other

VCC L8 Power/Other

VCC M23 Power/Other

VCC M24 Power/Other

VCC M25 Power/Other

VCC M26 Power/Other

VCC M27 Power/Other

VCC M28 Power/Other

VCC M29 Power/Other

VCC M30 Power/Other

VCC M8 Power/Other

VCC N23 Power/Other

VCC N24 Power/Other

VCC N25 Power/Other

VCC N26 Power/Other

VCC N27 Power/Other

VCC N28 Power/Other

VCC N29 Power/Other

VCC N30 Power/Other

VCC N8 Power/Other

VCC P8 Power/Other

VCC R8 Power/Other

VCC T23 Power/Other

VCC T24 Power/Other

VCC T25 Power/Other

VCC T26 Power/Other

VCC T27 Power/Other

VCC T28 Power/Other

VCC T29 Power/Other

VCC T30 Power/Other

VCC T8 Power/Other

VCC U23 Power/Other

VCC U24 Power/Other

VCC U25 Power/Other

VCC U26 Power/Other

VCC U27 Power/Other

VCC U28 Power/Other

VCC U29 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

VCC U30 Power/Other

VCC U8 Power/Other

VCC V8 Power/Other

VCC W23 Power/Other

VCC W24 Power/Other

VCC W25 Power/Other

VCC W26 Power/Other

VCC W27 Power/Other

VCC W28 Power/Other

VCC W29 Power/Other

VCC W30 Power/Other

VCC W8 Power/Other

VCC Y23 Power/Other

VCC Y24 Power/Other

VCC Y25 Power/Other

VCC Y26 Power/Other

VCC Y27 Power/Other

VCC Y28 Power/Other

VCC Y29 Power/Other

VCC Y30 Power/Other

VCC Y8 Power/Other

VCC_MB_

REGULATION AN5 Power/Other Output

VCC_SENSE AN3 Power/Other Output

VCCA A23 Power/Other

VCCIOPLL C23 Power/Other

VID0 AM2 Power/Other Output

VID1 AL5 Power/Other Output

VID2 AM3 Power/Other Output

VID3 AL6 Power/Other Output

VID4 AK4 Power/Other Output

VID5 AL4 Power/Other Output

VSS A12 Power/Other

VSS A15 Power/Other

VSS A18 Power/Other

VSS A2 Power/Other

VSS A21 Power/Other

VSS A24 Power/Other

VSS A6 Power/Other

VSS A9 Power/Other

VSS AA23 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Na me Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

52 Datasheet

VSS AA24 Power/Other

VSS AA25 Power/Other

VSS AA26 Power/Other

VSS AA27 Power/Other

VSS AA28 Power/Other

VSS AA29 Power/Other

VSS AA3 Power/Other

VSS AA30 Power/Other

VSS AA6 Power/Other

VSS AA7 Power/Other

VSS AB1 Power/Other

VSS AB23 Power/Other

VSS AB24 Power/Other

VSS AB25 Power/Other

VSS AB26 Power/Other

VSS AB27 Power/Other

VSS AB28 Power/Other

VSS AB29 Power/Other

VSS AB30 Power/Other

VSS AB7 Power/Other

VSS AC3 Power/Other

VSS AC6 Power/Other

VSS AC7 Power/Other

VSS AD4 Power/Other

VSS AD7 Power/Other

VSS AE10 Power/Other

VSS AE13 Power/Other

VSS AE16 Power/Other

VSS AE17 Power/Other

VSS AE2 Power/Other

VSS AE20 Power/Other

VSS AE24 Power/Other

VSS AE25 Power/Other

VSS AE26 Power/Other

VSS AE27 Power/Other

VSS AE28 Power/Other

VSS AE29 Power/Other

VSS AE30 Power/Other

VSS AE5 Power/Other

VSS AE7 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

VSS AF10 Power/Other

VSS AF13 Power/Other

VSS AF16 Power/Other

VSS AF17 Power/Other

VSS AF20 Power/Other

VSS AF23 Power/Other

VSS AF24 Power/Other

VSS AF25 Power/Other

VSS AF26 Power/Other

VSS AF27 Power/Other

VSS AF28 Power/Other

VSS AF29 Power/Other

VSS AF3 Power/Other

VSS AF30 Power/Other

VSS AF6 Power/Other

VSS AF7 Power/Other

VSS AG10 Power/Other

VSS AG13 Power/Other

VSS AG16 Power/Other

VSS AG17 Power/Other

VSS AG20 Power/Other

VSS AG23 Power/Other

VSS AG24 Power/Other

VSS AG7 Power/Other

VSS AH1 Power/Other

VSS AH10 Power/Other

VSS AH13 Power/Other

VSS AH16 Power/Other

VSS AH17 Power/Other

VSS AH20 Power/Other

VSS AH23 Power/Other

VSS AH24 Power/Other

VSS AH3 Power/Other

VSS AH6 Power/Other

VSS AH7 Power/Other

VSS AJ10 Power/Other

VSS AJ13 Power/Other

VSS AJ16 Power/Other

VSS AJ17 Power/Other

VSS AJ20 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 53

VSS AJ23 Power/Other

VSS AJ24 Power/Other

VSS AJ27 Power/Other

VSS AJ28 Power/Other

VSS AJ29 Power/Other

VSS AJ30 Power/Other

VSS AJ4 Power/Other

VSS AJ7 Power/Other

VSS AK10 Power/Other

VSS AK13 Power/Other

VSS AK16 Power/Other

VSS AK17 Power/Other

VSS AK2 Power/Other

VSS AK20 Power/Other

VSS AK23 Power/Other

VSS AK24 Power/Other

VSS AK27 Power/Other

VSS AK28 Power/Other

VSS AK29 Power/Other

VSS AK30 Power/Other

VSS AK5 Power/Other

VSS AK7 Power/Other

VSS AL10 Power/Other

VSS AL13 Power/Other

VSS AL16 Power/Other

VSS AL17 Power/Other

VSS AL20 Power/Other

VSS AL23 Power/Other

VSS AL24 Power/Other

VSS AL27 Power/Other

VSS AL28 Power/Other

VSS AL3 Power/Other

VSS AL7 Power/Other

VSS AM1 Power/Other

VSS AM10 Power/Other

VSS AM13 Power/Other

VSS AM16 Power/Other

VSS AM17 Power/Other

VSS AM20 Power/Other

VSS AM23 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

VSS A M24 Power/Other

VSS A M27 Power/Other

VSS A M28 Power/Other

VSS AM4 Power/Other

VSS AN1 Power/Other

VSS AN10 Power/Other

VSS AN13 Power/Other

VSS AN16 Power/Other

VSS AN17 Power/Other

VSS AN2 Power/Other

VSS AN20 Power/Other

VSS AN23 Power/Other

VSS AN24 Power/Other

VSS AN27 Power/Other

VSS AN28 Power/Other

VSS B1 Power/Other

VSS B11 Power/Other

VSS B14 Power/Other

VSS B17 Power/Other

VSS B20 Power/Other

VSS B24 Power/Other

VSS B5 Power/Other

VSS B8 Power/Other

VSS C10 Power/Other

VSS C13 Power/Other

VSS C16 Power/Other

VSS C19 Power/Other

VSS C22 Power/Other

VSS C24 Power/Other

VSS C4 Power/Other

VSS C7 Power/Other

VSS D12 Power/Other

VSS D15 Power/Other

VSS D18 Power/Other

VSS D21 Power/Other

VSS D24 Power/Other

VSS D3 Power/Other

VSS D5 Power/Other

VSS D6 Power/Other

VSS D9 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Na me Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

54 Datasheet

VSS E11 Power/Other

VSS E14 Power/Other

VSS E17 Power/Other

VSS E2 Power/Other

VSS E20 Power/Other

VSS E25 Power/Other

VSS E26 Power/Other

VSS E27 Power/Other

VSS E28 Power/Other

VSS E29 Power/Other

VSS E8 Power/Other

VSS F10 Power/Other

VSS F13 Power/Other

VSS F16 Power/Other

VSS F19 Power/Other

VSS F22 Power/Other

VSS F4 Power/Other

VSS F7 Power/Other

VSS G1 Power/Other

VSS H10 Power/Other

VSS H11 Power/Other

VSS H12 Power/Other

VSS H13 Power/Other

VSS H14 Power/Other

VSS H17 Power/Other

VSS H18 Power/Other

VSS H19 Power/Other

VSS H20 Power/Other

VSS H21 Power/Other

VSS H22 Power/Other

VSS H23 Power/Other

VSS H24 Power/Other

VSS H25 Power/Other

VSS H26 Power/Other

VSS H27 Power/Other

VSS H28 Power/Other

VSS H3 Power/Other

VSS H6 Power/Other

VSS H7 Power/Other

VSS H8 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

VSS H9 Power/Other

VSS J4 Power/Other

VSS J7 Power/Other

VSS K2 Power/Other

VSS K5 Power/Other

VSS K7 Power/Other

VSS L23 Power/Other

VSS L24 Power/Other

VSS L25 Power/Other

VSS L26 Power/Other

VSS L27 Power/Other

VSS L28 Power/Other

VSS L29 Power/Other

VSS L3 Power/Other

VSS L30 Power/Other

VSS L6 Power/Other

VSS L7 Power/Other

VSS M1 Power/Other

VSS M7 Power/Other

VSS N3 Power/Other

VSS N6 Power/Other

VSS N7 Power/Other

VSS P23 Power/Other

VSS P24 Power/Other

VSS P25 Power/Other

VSS P26 Power/Other

VSS P27 Power/Other

VSS P28 Power/Other

VSS P29 Power/Other

VSS P30 Power/Other

VSS P4 Power/Other

VSS P7 Power/Other

VSS R2 Power/Other

VSS R23 Power/Other

VSS R24 Power/Other

VSS R25 Power/Other

VSS R26 Power/Other

VSS R27 Power/Other

VSS R28 Power/Other

VSS R29 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 55

VSS R30 Power/Other

VSS R5 Power/Other

VSS R7 Power/Other

VSS T3 Power/Other

VSS T6 Power/Other

VSS T7 Power/Other

VSS U1 Power/Other

VSS U7 Power/Other

VSS V23 Power/Other

VSS V24 Power/Other

VSS V25 Power/Other

VSS V26 Power/Other

VSS V27 Power/Other

VSS V28 Power/Other

VSS V29 Power/Other

VSS V3 Power/Other

VSS V30 Power/Other

VSS V6 Power/Other

VSS V7 Power/Other

VSS W4 Power/Other

VSS W7 Power/Other

VSS Y2 Power/Other

VSS Y5 Power/Other

VSS Y7 Power/Other

VSS_MB_

REGULATION AN6 Power/Other Output

VSS_SENSE AN4 Power/Other Output

VSSA B23 Power/Other

VTT A25 Power/Other

VTT A26 Power/Other

VTT A27 Power/Other

VTT A28 Power/Other

VTT A29 Power/Other

VTT A30 Power/Other

VTT B25 Power/Other

VTT B26 Power/Other

VTT B27 Power/Other

VTT B28 Power/Other

VTT B29 Power/Other

VTT B30 Power/Other

VTT C25 Power/Other

Table 4-1. Alphabetical Land

Assignments

Land Name Land

#Signal Buffer

Type Direction

VTT C26 Power/Other

VTT C27 Power/Other

VTT C28 Power/Other

VTT C29 Power/Other

VTT C30 Power/Other

VTT D25 Power/Other

VTT D26 Power/Other

VTT D27 Power/Other

VTT D28 Power/Other

VTT D29 Power/Other

VTT D30 Power/Other

VTT_OUT_LEFT J1 Power/Other Output

VTT_OUT_RIGHT AA1 Power/Other Output

VTT_SEL F27 Power/Other Output

VTTPWRGD AM6 Power/Other Input

Table 4-1. Alphabetical Land

Assignments

Land Na me Land

#Signal Buffer

Type Direction

Land Listing and Signal Descriptions

56 Datasheet

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

A2 VSS Power/Other

A3 RS2# Common Clock Input

A4 D2# Source Synch Input/Output

A5 D4# Source Synch Input/Output

A6 VSS Power/Other

A7 D7# Source Synch Input/Output

A8 DBI0# Source Synch Input/Output

A9 VSS Power/Other

A10 D8# Source Synch Input/Output

A11 D9# Source Synch Input/Output

A12 VSS Power/Other

A13 COMP0 Power/Other Input

A14 D50# Source Synch Input/Output

A15 VSS Power/Other

A16 DSTBN3# Source Synch Input/Output

A17 D56# Source Synch Input/Output

A18 VSS Power/Other

A19 D61# Source Synch Input/Output

A20 RESERVED

A21 VSS Power/Other

A22 D62# Source Synch Input/Output

A23 VCCA Power/Other

A24 VSS Power/Other

A25 VTT Power/Other

A26 VTT Power/Other

A27 VTT Power/Other

A28 VTT Power/Other

A29 VTT Power/Other

A30 VTT Power/Other

B1 VSS Power/Other

B2 DBSY# Common Clock Input/Output

B3 RS0# Common Clock Input

B4 D0# Source Synch Input/Output

B5 VSS Power/Other

B6 D5# Source Synch Input/Output

B7 D6# Source Synch Input/Output

B8 VSS Power/Other

B9 DSTBP0# Source Synch Input/Output

B10 D10# Source Synch Input/Output

B11 VSS Power/Other

B12 D13# Source Synch Input/Output

B13 RESERVED

B14 VSS Power/Other

B15 D53# Source Synch Input/Output

B16 D55# Source Synch Input/Output

B17 VSS Power/Other

B18 D57# Source Synch Input/Output

B19 D60# Source Synch Input/Output

B20 VSS Power/Other

B21 D59# Source Synch Input/Output

B22 D63# Source Synch Input/Output

B23 VSSA Power/Other

B24 VSS Power/Other

B25 VTT Power/Other

B26 VTT Power/Other

B27 VTT Power/Other

B28 VTT Power/Other

B29 VTT Power/Other

B30 VTT Power/Other

C1 DRDY# Common Clock Input/Output

C2 BNR# Common Clock Input/Output

C3 LOCK# Common Clock Input/Output

C4 VSS Power/Other

C5 D1# Source Synch Input/Output

C6 D3# Source Synch Input/Output

C7 VSS Power/Other

C8 DSTBN0# Source Synch Input/Output

C9 RESERVED

C10 VSS Power/Other

C11 D11# Source Synch Input/Output

C12 D14# Source Synch Input/Output

C13 VSS Power/Other

C14 D52# Source Synch Input/Output

C15 D51# Source Synch Input/Output

C16 VSS Power/Other

C17 D STBP3# Source Synch Input/Output

C18 D54# Source Synch Input/Output

C19 VSS Power/Other

C20 DBI3# Source Synch Input/Output

C21 D58# Source Synch Input/Output

C22 VSS Power/Other

C23 VCCIOPLL Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 57

C24 VSS Power/Other

C25 VTT Power/Other

C26 VTT Power/Other

C27 VTT Power/Other

C28 VTT Power/Other

C29 VTT Power/Other

C30 VTT Power/Other

D1 RESERVED

D2 ADS# Common Clock Input/Output

D3 VSS Power/Other

D4 HIT# Common Clock Input/Output

D5 VSS Power/Other

D6 VSS Power/Other

D7 D20# Source Synch Input/Output

D8 D12# Source Synch Input/Output

D9 VSS Power/Other

D10 D22# Source Synch Input/Output

D11 D15# Source Synch Input/Output

D12 VSS Power/Other

D13 D25# Source Synch Input/Output

D14 RESERVED

D15 VSS Power/Other

D16 RESERVED

D17 D49# Source Synch Input/Output

D18 VSS Power/Other

D19 DBI2# Source Synch Input/Output

D20 D48# Source Synch Input/Output

D21 VSS Power/Other

D22 D46# Source Synch Input/Output

D23 RESERVED

D24 VSS Power/Other

D25 VTT Power/Other

D26 VTT Power/Other

D27 VTT Power/Other

D28 VTT Power/Other

D29 VTT Power/Other

D30 VTT Power/Other

E2 VSS Power/Other

E3 TRDY# Common Clock Input

E4 HITM # Common Clock Input/Output

E5 RESERVED

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

E6 RESERVED

E7 RESERVED

E8 VSS Power/Other

E9 D19# Source Synch Input/Output

E10 D21# Source Synch Input/Output

E11 VSS Power/Other

E12 DSTBP1# Source Synch Input/Output

E13 D26# Source Synch Input/Output

E14 VSS Power/Other

E15 D33# Source Synch Input/Output

E16 D34# Source Synch Input/Output

E17 VSS Power/Other

E18 D39# Source Synch Input/Output

E19 D40# Source Synch Input/Output

E20 VSS Power/Other

E21 D42# Source Synch Input/Output

E22 D45# Source Synch Input/Output

E23 RESERVED

E24 RESERVED

E25 VSS Power/Other

E26 VSS Power/Other

E27 VSS Power/Other

E28 VSS Power/Other

E29 VSS Power/Other

F2 FC5 Common Clock Input

F3 BR0# Common Clock Input/Output

F4 VSS Power/Other

F5 RS1# Common Clock Input

F6 RESERVED

F7 VSS Power/Other

F8 D17# Source Synch Input/Outpu t

F9 D18# Source Synch Input/Outpu t

F10 VSS Power/Other

F11 D23# Source Synch Input/Output

F12 D24# Source Synch Input/Output

F13 VSS Power/Other

F14 D28# Source Synch Input/Output

F15 D30# Source Synch Input/Output

F16 VSS Power/Other

F17 D37# Source Synch Input/Output

F18 D38# Source Synch Input/Output

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

Land Listing and Signal Descriptions

58 Datasheet

F19 VSS Power/Other

F20 D41# Source Synch Input/Output

F21 D43# Source Synch Input/Output

F22 VSS Power/Other

F23 RESERVED

F24 TESTHI7 Power/Other Input

F25 TESTHI2 Power/Other Input

F26 TESTHI0 Power/Other Input

F28 BCLK0 Clock Input

F29 RESERVED

G1 VSS Power/Other

G2 FC1 Power/Other Input

G3 TESTHI8 Power/Other Input

G4 TESTHI9 Power/Other Input

G5 FC7 Source Synch Output

G6 RESERVED

G7 DEFER# Common Clock Input

G8 BPRI# Common Clock Input

G9 D16# Source Synch Input/Output

G10 RESERVED

G11 DBI1# Source Synch Input/Output

G12 DSTBN1# Source Synch Input/Output

G13 D27# Source Synch Input/Output

G14 D29# Source Synch Input/Output

G15 D31# Source Synch Input/Output

G16 D32# Source Synch Input/Output

G17 D36# Source Synch Input/Output

G18 D35# Source Synch Input/Output

G19 DSTBP2# Source Synch Input/Output

G20 DSTBN2# Source Synch Input/Output

G21 D44# Source Synch Input/Output

G22 D47# Source Synch Input/Output

G23 RESET# Common Clock Input

G24 TESTHI6 Power/Other Input

G25 TESTHI3 Power/Other Input

G26 TESTHI5 Power/Other Input

G27 TESTHI4 Power/Other Input

G28 BCLK1 Clock Input

G29 BSEL0 Power/Other Output

G30 BSEL2 Power/Other Output

H1 GTLREF Power/Other Input

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

H2 FC6 Power/Other Input

H3 VSS Power/Other

H4 RSP# Common Clock Input

H5 TESTHI10 Power/Other Input

H6 VSS Power/Other

H7 VSS Power/Other

H8 VSS Power/Other

H9 VSS Power/Other

H10 VSS Power/Other

H11 VSS Power/Other

H12 VSS Power/Other

H13 VSS Power/Other

H14 VSS Power/Other

H15 DP1# Common Clock Input/Output

H16 DP2# Common Clock Input/Output

H17 VSS Power/Other

H18 VSS Power/Other

H19 VSS Power/Other

H20 VSS Power/Other

H21 VSS Power/Other

H22 VSS Power/Other

H23 VSS Power/Other

H24 VSS Power/Other

H25 VSS Power/Other

H26 VSS Power/Other

H27 VSS Power/Other

H28 VSS Power/Other

H29 GTLREF_SEL Power/Other Output

H30 BSEL1 Power/Other Output

J1 VTT_OUT_LEFT Power/Other Output

J2 FC3 Power/Other Input

J3 RESERVED

J4 VSS Power/Other

J5 REQ1# Source Synch Input/Output

J6 REQ4# Source Synch Input/Output

J7 VSS Power/Other

J8 VCC Power/Other

J9 VCC Power/Other

J10 VCC Power/Other

J11 VCC Power/Other

J12 VCC Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 59

J13 VCC Power/Other

J14 VCC Power/Other

J15 VCC Power/Other

J16 DP0# Common Clock Input/Output

J17 DP3# Common Clock Input/Output

J18 VCC Power/Other

J19 VCC Power/Other

J20 VCC Power/Other

J21 VCC Power/Other

J22 VCC Power/Other

J23 VCC Power/Other

J24 VCC Power/Other

J25 VCC Power/Other

J26 VCC Power/Other

J27 VCC Power/Other

J28 VCC Power/Other

J29 VCC Power/Other

J30 VCC Power/Other

K1 LINT0 Asynch GTL+ Input

K2 VSS Power/Other

K3 A20M# Asynch GTL+ Input

K4 REQ0# Source Synch Input/Output

K5 VSS Power/Other

K6 REQ3# Source Synch Input/Output

K7 VSS Power/Other

K8 VCC Power/Other

K23 VCC Power/Other

K24 VCC Power/Other

K25 VCC Power/Other

K26 VCC Power/Other

K27 VCC Power/Other

K28 VCC Power/Other

K29 VCC Power/Other

K30 VCC Power/Other

L1 LINT1 Asynch GTL+ Input

L2 TESTHI13 Asynch GTL+ Input

L3 VSS Power/Other

L4 A6# Source Synch Input/Output

L5 A3# Source Synch Input/Output

L6 VSS Power/Other

L7 VSS Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

L8 VCC Power/Other

L23 VSS Power/Other

L24 VSS Power/Other

L25 VSS Power/Other

L26 VSS Power/Other

L27 VSS Power/Other

L28 VSS Power/Other

L29 VSS Power/Other

L30 VSS Power/Other

M1 VSS Power/Other

M2 THERMTRIP# Asynch GTL+ Output

M3 STPCLK# Asynch GTL+ Input

M4 A7# Source Synch Input/Output

M5 A5# Source Synch Input/Output

M6 REQ2# Source Synch Input/Output

M7 VSS Power/Other

M8 VCC Power/Other

M23 VCC Power/Other

M24 VCC Power/Other

M25 VCC Power/Other

M26 VCC Power/Other

M27 VCC Power/Other

M28 VCC Power/Other

M29 VCC Power/Other

M30 VCC Power/Other

N1 PWRGOOD Power/Other Input

N2 IGNNE# Asynch GTL+ Input

N3 VSS Power/Other

N4 RESERVED

N5 RESERVED

N6 VSS Power/Other

N7 VSS Power/Other

N8 VCC Power/Other

N23 VCC Power/Other

N24 VCC Power/Other

N25 VCC Power/Other

N26 VCC Power/Other

N27 VCC Power/Other

N28 VCC Power/Other

N29 VCC Power/Other

N30 VCC Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

Land Listing and Signal Descriptions

60 Datasheet

P1 TESTHI11 Power/Other Input

P2 SMI# Asynch GTL+ Input

P3 INIT# Asynch GTL+ Input

P4 VSS Power/Other

P5 RESERVED

P6 A4# Source Synch Input/Output

P7 VSS Power/Other

P8 VCC Power/Other

P23 VSS Power/Other

P24 VSS Power/Other

P25 VSS Power/Other

P26 VSS Power/Other

P27 VSS Power/Other

P28 VSS Power/Other

P29 VSS Power/Other

P30 VSS Power/Other

R1 FC2 Power/Other Input

R2 VSS Power/Other

R3 FERR#/PBE# Asynch GTL+ Output

R4 A8# Source Synch Input/Output

R5 VSS Power/Other

R6 ADSTB0# Source Synch Input/Output

R7 VSS Power/Other

R8 VCC Power/Other

R23 VSS Power/Other

R24 VSS Power/Other

R25 VSS Power/Other

R26 VSS Power/Other

R27 VSS Power/Other

R28 VSS Power/Other

R29 VSS Power/Other

R30 VSS Power/Other

T1 COMP1 Power/Other Input

T2 FC4 Power/Other Input

T3 VSS Power/Other

T4 A11# Source Synch Input/Output

T5 A9# Source Synch Input/Output

T6 VSS Power/Other

T7 VSS Power/Other

T8 VCC Power/Other

T23 VCC Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

T24 VCC Power/Other

T25 VCC Power/Other

T26 VCC Power/Other

T27 VCC Power/Other

T28 VCC Power/Other

T29 VCC Power/Other

T30 VCC Power/Other

U1 VSS Power/Other

U2 AP0# Common Clock Input/Output

U3 AP1# Common Clock Input/Output

U4 A13# Source Synch Input/Output

U5 A12# Source Synch Input/Output

U6 A10# Source Synch Input/Output

U7 VSS Power/Other

U8 VCC Power/Other

U23 VCC Power/Other

U24 VCC Power/Other

U25 VCC Power/Other

U26 VCC Power/Other

U27 VCC Power/Other

U28 VCC Power/Other

U29 VCC Power/Other

U30 VCC Power/Other

V1 MSID1 Power/Other Output

V2 LL_ID0 Power/Other Output

V3 VSS Power/Other

V4 A15# Source Synch Input/Output

V5 A14# Source Synch Input/Output

V6 VSS Power/Other

V7 VSS Power/Other

V8 VCC Power/Other

V23 VSS Power/Other

V24 VSS Power/Other

V25 VSS Power/Other

V26 VSS Power/Other

V27 VSS Power/Other

V28 VSS Power/Other

V29 VSS Power/Other

V30 VSS Power/Other

W1 MSID0 Power/Other Output

W2 TESTHI12 Power/Other Input

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 61

W3 TESTHI1 Power/Other Input

W4 VSS Power/Other

W5 A16# Source Synch Input/Output

W6 A18# Source Synch Input/Output

W7 VSS Power/Other

W8 VCC Power/Other

W23 VCC Power/Other

W24 VCC Power/Other

W25 VCC Power/Other

W26 VCC Power/Other

W27 VCC Power/Other

W28 VCC Power/Other

W29 VCC Power/Other

W30 VCC Power/Other

Y1 BOOTSELECT Power/Other Input

Y2 VSS Power/Other

Y3 RESERVED

Y4 A20# Source Synch Input/Output

Y5 VSS Power/Other

Y6 A19# Source Synch Input/Output

Y7 VSS Power/Other

Y8 VCC Power/Other

Y23 VCC Power/Other

Y24 VCC Power/Other

Y25 VCC Power/Other

Y26 VCC Power/Other

Y27 VCC Power/Other

Y28 VCC Power/Other

Y29 VCC Power/Other

Y30 VCC Power/Other

AA2 LL_ID1 Power/Other Output

AA3 VSS Power/Other

AA4 A21# Source Synch Input/Output

AA5 A23# Source Synch Input/Output

AA6 VSS Power/Other

AA7 VSS Power/Other

AA8 VCC Power/Other

AA23 VSS Power/Other

AA24 VSS Power/Other

AA25 VSS Power/Other

AA26 VSS Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

AA27 VSS Power/Other

AA28 VSS Power/Other

AA29 VSS Power/Other

AA30 VSS Power/Other

AB1 VSS Power/Other

AB2 IERR# A synch GTL+ Output

AB3 MCERR# Common Clock Input/Output

AB4 A26# Source Synch Input/Output

AB5 A24# Source Synch Input/Output

AB6 A17# Source Synch Input/Output

AB7 VSS Power/Other

AB8 VCC Power/Other

AB23 VSS Power/Other

AB24 VSS Power/Other

AB25 VSS Power/Other

AB26 VSS Power/Other

AB27 VSS Power/Other

AB28 VSS Power/Other

AB29 VSS Power/Other

AB30 VSS Power/Other

AC1 TMS TAP Input

AC2 DBR# Power/Other Output

AC3 VSS Power/Other

AC4 RESERVED

AC5 A25# Source Synch Input/Output

AC6 VSS Power/Other

AC7 VSS Power/Other

AC8 VCC Power/Other

AC23 VCC Power/Other

AC24 VCC Power/Other

AC25 VCC Power/Other

AC26 VCC Power/Other

AC27 VCC Power/Other

AC28 VCC Power/Other

AC29 VCC Power/Other

AC30 VCC Power/Other

AD1 TDI TAP Input

AD2 BPM2# Common Clock Input/Output

AD3 BINIT# Common Clock Input/Output

AD4 VSS Power/Other

AD5 ADSTB1# Source Synch Input/Output

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

Land Listing and Signal Descriptions

62 Datasheet

AD6 A22# Source Synch Input/Output

AD7 VSS Power/Other

AD8 VCC Power/Other

AD23 VCC Power/Other

AD24 VCC Power/Other

AD25 VCC Power/Other

AD26 VCC Power/Other

AD27 VCC Power/Other

AD28 VCC Power/Other

AD29 VCC Power/Other

AD30 VCC Power/Other

AE1 TCK TAP Input

AE2 VSS Power/Other

AE3 RESERVED

AE4 RESERVED

AE5 VSS Power/Other

AE6 RESERVED

AE7 VSS Power/Other

AE8 SKTOCC# Power/Other Output

AE9 VCC Power/Other

AE10 VSS Power/Other

AE11 VCC Power/Other

AE12 VCC Power/Other

AE13 VSS Power/Other

AE14 VCC Power/Other

AE15 VCC Power/Other

AE16 VSS Power/Other

AE17 VSS Power/Other

AE18 VCC Power/Other

AE19 VCC Power/Other

AE20 VSS Power/Other

AE21 VCC Power/Other

AE22 VCC Power/Other

AE23 VCC Power/Other

AE24 VSS Power/Other

AE25 VSS Power/Other

AE26 VSS Power/Other

AE27 VSS Power/Other

AE28 VSS Power/Other

AE29 VSS Power/Other

AE30 VSS Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

AF1 TDO TAP Output

AF2 BPM4# Common Clock Input/Output

AF4 A28# Source Synch Input/Output

AF5 A27# Source Synch Input/Output

AF6 VSS Power/Other

AF7 VSS Power/Other

AF8 VCC Power/Other

AF9 VCC Power/Other

AF10 VSS Power/Other

AF11 VCC Power/Other

AF12 VCC Power/Other

AF13 VSS Power/Other

AF14 VCC Power/Other

AF15 VCC Power/Other

AF16 VSS Power/Other

AF17 VSS Power/Other

AF18 VCC Power/Other

AF19 VCC Power/Other

AF20 VSS Power/Other

AF21 VCC Power/Other

AF22 VCC Power/Other

AF23 VSS Power/Other

AF24 VSS Power/Other

AF25 VSS Power/Other

AF26 VSS Power/Other

AF27 VSS Power/Other

AF28 VSS Power/Other

AF29 VSS Power/Other

AF3 VSS Power/Other

AF30 VSS Power/Other

AG1 TRST# TAP Input

AG2 BPM3# Common Clock Input/Output

AG3 BPM5# Common Clock Input/Output

AG4 A30# Source Synch Input/Output

AG5 A31# Source Synch Input/Output

AG6 A29# Source Synch Input/Output

AG7 VSS Power/Other

AG8 VCC Power/Other

AG9 VCC Power/Other

AG10 VSS Power/Other

AG11 VCC Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 63

AG12 VCC Power/Other

AG13 VSS Power/Other

AG14 VCC Power/Other

AG15 VCC Power/Other

AG16 VSS Power/Other

AG17 VSS Power/Other

AG18 VCC Power/Other

AG19 VCC Power/Other

AG20 VSS Power/Other

AG21 VCC Power/Other

AG22 VCC Power/Other

AG23 VSS Power/Other

AG24 VSS Power/Other

AG25 VCC Power/Other

AG26 VCC Power/Other

AG27 VCC Power/Other

AG28 VCC Power/Other

AG29 VCC Power/Other

AG30 VCC Power/Other

AH1 VSS Power/Other

AH2 RESERVED

AH3 VSS Power/Other

AH4 A32# Source Synch Input/Output

AH5 A33# Source Synch Input/Output

AH6 VSS Power/Other

AH7 VSS Power/Other

AH8 VCC Power/Other

AH9 VCC Power/Other

AH10 VSS Power/Other

AH11 VCC Power/Other

AH12 VCC Power/Other

AH13 VSS Power/Other

AH14 VCC Power/Other

AH15 VCC Power/Other

AH16 VSS Power/Other

AH17 VSS Power/Other

AH18 VCC Power/Other

AH19 VCC Power/Other

AH20 VSS Power/Other

AH21 VCC Power/Other

AH22 VCC Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

AH23 VSS Power/Other

AH24 VSS Power/Other

AH25 VCC Power/Other

AH26 VCC Power/Other

AH27 VCC Power/Other

AH28 VCC Power/Other

AH29 VCC Power/Other

AH30 VCC Power/Other

AJ1 BPM1# Common Clock Input/Output

AJ2 BPM0# Common Clock Input/Output

AJ3 ITP_CLK1 TAP Input

AJ4 VSS Power/Other

AJ5 A34# Source Synch Input/Output

AJ6 A35# Source Synch Input/Output

AJ7 VSS Power/Other

AJ8 VCC Power/Other

AJ9 VCC Power/Other

AJ10 VSS Power/Other

AJ11 VCC Power/Other

AJ12 VCC Power/Other

AJ13 VSS Power/Other

AJ14 VCC Power/Other

AJ15 VCC Power/Other

AJ16 VSS Power/Other

AJ17 VSS Power/Other

AJ18 VCC Power/Other

AJ19 VCC Power/Other

AJ20 VSS Power/Other

AJ21 VCC Power/Other

AJ22 VCC Power/Other

AJ23 VSS Power/Other

AJ24 VSS Power/Other

AJ25 VCC Power/Other

AJ26 VCC Power/Other

AJ27 VSS Power/Other

AJ28 VSS Power/Other

AJ29 VSS Power/Other

AJ30 VSS Power/Other

AK1 THERMDC Power/Other

AK2 VSS Power/Other

AK3 ITP_CLK0 TAP Input

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

Land Listing and Signal Descriptions

64 Datasheet

AK4 VID4 Power/Other Output

AK5 VSS Power/Other

AK6 RESERVED

AK7 VSS Power/Other

AK8 VCC Power/Other

AK9 VCC Power/Other

AK10 VSS Power/Other

AK11 VCC Power/Other

AK12 VCC Power/Other

AK13 VSS Power/Other

AK14 VCC Power/Other

AK15 VCC Power/Other

AK16 VSS Power/Other

AK17 VSS Power/Other

AK18 VCC Power/Other

AK19 VCC Power/Other

AK20 VSS Power/Other

AK21 VCC Power/Other

AK22 VCC Power/Other

AK23 VSS Power/Other

AK24 VSS Power/Other

AK25 VCC Power/Other

AK26 VCC Power/Other

AK27 VSS Power/Other

AK28 VSS Power/Other

AK29 VSS Power/Other

AK30 VSS Power/Other

AL1 THERMDA Power/Other

AL2 PROCHOT# Asynch GTL+ Input/Output

AL3 VSS Power/Other

AL4 VID5 Power/Other Output

AL5 VID1 Power/Other Output

AL6 VID3 Power/Other Output

AL7 VSS Power/Other

AL8 VCC Power/Other

AL9 VCC Power/Other

AL10 VSS Power/Other

AL11 VCC Power/Other

AL12 VCC Power/Other

AL13 VSS Power/Other

AL14 VCC Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

AL15 VCC Power/Other

AL16 VSS Power/Other

AL17 VSS Power/Other

AL18 VCC Power/Other

AL19 VCC Power/Other

AL20 VSS Power/Other

AL21 VCC Power/Other

AL22 VCC Power/Other

AL23 VSS Power/Other

AL24 VSS Power/Other

AL25 VCC Power/Other

AL26 VCC Power/Other

AL27 VSS Power/Other

AL28 VSS Power/Other

AL29 VCC Power/Other

AL30 VCC Power/Other

AM1 VSS Power/Other

AM2 VID0 Power/Other Output

AM3 VID2 Power/Other Output

AM4 VSS Power/Other

AM5 FC11 Power/Other Output

AM7 FC12 Power/Other Output

AM8 VCC Power/Other

AM9 VCC Power/Other

AM10 VSS Power/Other

AM11 VCC Power/Other

AM12 VCC Power/Other

AM13 VSS Power/Other

AM14 VCC Power/Other

AM15 VCC Power/Other

AM16 VSS Power/Other

AM17 VSS Power/Other

AM18 VCC Power/Other

AM19 VCC Power/Other

AM20 VSS Power/Other

AM21 VCC Power/Other

AM22 VCC Power/Other

AM23 VSS Power/Other

AM24 VSS Power/Other

AM25 VCC Power/Other

AM26 VCC Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

Land Listing and Signal Descriptions

Datasheet 65

AM27 VSS Power/Other

AM28 VSS Power/Other

AM29 VCC Power/Other

AM30 VCC Power/Other

AN1 VSS Power/Other

AN2 VSS Power/Other

AN3 VCC_SENSE Power/Other Output

AN4 VSS_SENSE Power/Other Output

AN5 VCC_MB_

REGULATION Power/Other Output

AN6 VSS_MB_

REGULATION Power/Other Output

AN7 FC16 Power/Other Output

AN8 VCC Power/Other

AN9 VCC Power/Other

AN10 VSS Power/Other

AN11 VCC Power/Other

AN12 VCC Power/Other

AN13 VSS Power/Other

AN14 VCC Power/Other

AN15 VCC Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

AN16 VSS Power/Other

AN17 VSS Power/Other

AN18 VCC Power/Other

AN19 VCC Power/Other

AN20 VSS Power/Other

AN21 VCC Power/Other

AN22 VCC Power/Other

AN23 VSS Power/Other

AN24 VSS Power/Other

AN25 VCC Power/Other

AN26 VCC Power/Other

AN27 VSS Power/Other

AN28 VSS Power/Other

AN29 VCC Power/Other

AN30 VCC Power/Other

Table 4-2. Numerical Land Assignment

Land

#Land Name Signal Buffer

Type Direction

66 Datasheet

Land Listing and Signal Descriptions

4.2 Alphabetical Signals Reference

Table 4-3. Signal Description (Sheet 1 of 8)

Name Type Description

A[35:3]# Input/

Output

A[35:3]# (Address) define a 236-byte physical memory address space. In sub-

phase 1 of the address phase, these signals transmit the address of a

transaction. In sub-phase 2, these signals transmit transaction type information.

These signals must connect the appropriate pins/lands of all agents on the

processor FSB. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are

source synchronous signals and are latched into the receiving buffers by

ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processor samples a subset

of the A[35:3]# signals to determine power-on configuration. See Section 6.1 for

more details.

A20M# Input

If A20M# (Address-20 Mask) is asserted, the processor masks physical

address bit 20 (A20#) before looking up a line in any internal cache and before

driving a read/write transaction on the bus. Asserting A20M# emulates the 8086

processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is

only supported in real mode.

A20M# is an asynchronous signal. However , to ensure recognition of this signal

following an Input/Output write instruction, it must be valid along with the

TRDY# assertion of the corresponding Input/Output Write bus transaction.

ADS# Input/

Output

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the

ADS# activation to begin parity checking, protocol checking, address decode,

internal snoop, or deferred reply ID match operations associated with the new

transaction.

ADSTB[1:0]# Input/

Output

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and

falling edges. Strobes are associated with signals as shown below.

AP[1:0]# Input/

Output

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,

A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is

high if an even number of covered signals are low and low if an odd number of

covered signals are low. This allows parity to be high when all the covered

signals are high. AP[1:0]# should connect the appropriate pins/lands of all

processor FSB agents. The following table defines the coverage model of these

signals.

BCLK[1:0] Input

The differential pair BCLK (Bus Clock) determines the FSB frequency. All

processor FSB agents must receive these signals to drive their outputs and

latch their inputs.

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing VCROSS.

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB0#

A[35:17]# ADSTB1#

Request Signals Subphase 1 Subphase 2

A[35:24]# AP0# AP1#

A[23:3]# AP1# AP0#

REQ[4:0]# AP1# AP0#

Datasheet 67

Land Listing and Signal Descriptions

BINIT# Input/

Output

BINIT# (Bus Initialization) may be observed and driven by all processor FSB

agents and if used, must connect the appropriate pins/lands of all such agents.

If the BINIT# driver is enabled during power-on configuration, BINIT# is

asserted to signal any bus condition that prevents reliable future operation.

If BINIT# observation is enabled during power-on configuration, and BINIT# is

sampled asserted, symmetric agents reset their bus LOCK# activity and bus

request arbitration state machines. The bus agents do not reset their IOQ and

transaction tracking state machines upon observation of BINIT# activation.

Once the BINIT# assertion has been observed, the bus agents will re-arbitrate

for the FSB and attempt completion of their bus queue and IOQ entries.

If BINIT# observation is disabled during power-on configuration, a central agent

may handle an assertion of BINIT# as appropriate to the error handling

architecture of the system.

BNR# Input/

Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent

unable to accept new bus transactions. During a bus stall, the current bus

owner cannot issue any new transactions.

BOOTSELECT Input This input is required to determine whether the processor is installed in a

platform that supports the Pentium 4 processor in the 775-land package. The

processor will not operate if this signal is low. This input has a weak internal

pull-up to VCC.

BPM[5:0]# Input/

Output

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor

signals. They are outputs from the processor which indicate the status of

breakpoints and programmable counters used for monitoring processor

performance. BPM[5:0]# should connect the appropriate pins/lands of all

processor FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY#

is a processor output used by debug tools to determine processor debug

readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP port.

PREQ# is used by debug tools to request debug operation of the processor.

These signals do not have on-die termination. Refer to Section 2.5 for

termination requirements.

BPRI# Input

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor

FSB. It must connect the appropriate pins/lands of all processor FSB agents.

Observing BPRI# active (as asserted by the priority agent) causes all other

agents to stop issuing new requests, unless such requests are part of an

ongoing locked operation. The priority agent keeps BPRI# asserted until all of

its requests are completed, then releases the bus by de-asserting BPRI#.

BR0# Input/

Output

BR0# drives the BREQ0# signal in the system and is used by the processor to

request the bus. During power-on configuration this signal is sampled to

determine the agent ID = 0.

This signal does not have on-die termination and must be terminated.

BSEL[2:0] Output

The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the

processor input clock frequency . Table 2-6 defines the possible combinations of

the signals and the frequency associated with each combination. The required

frequency is determined by the processor, chipset and clock synthesizer. All

agents must operate at the same frequency. For more information about these

signals, including termination recommendations refer to Section 2.9.

COMP[1:0] Analog COMP[1:0] must be terminated to VSS on the system board using precision

resistors.

Table 4-3. Signal Description (Sheet 2 of 8)

Name Type Description

68 Datasheet

Land Listing and Signal Descriptions

D[63:0]# Input/

Output

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the processor FSB agents, and must connect the appropriate pins/

lands on all such agents. The dat a driver asserts DRDY# to indicate a valid dat a

transfer.

D[63:0]# are quad-pumped signals and will, thus, be driven four times in a

common clock period. D[63:0]# are latched off the falling edge of both

DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a

pair of one DSTBP# and one DSTBN#. The following table shows the grouping

of data signals to data strobes and DBI#.

Furthermore, the DBI# signals determine the polarity of the data signals. Each

group of 16 data signals corresponds to one DBI# signal. When the DBI# signal

is active, the corresponding data group is inverted and therefore sampled active

high.

DBI[3:0]# Input/

Output

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the

polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the

data on the data bus is inverted. If more than half the data bits, within a 16-bit

group, would have been asserted electrically low, the bus agent may invert the

data bus signals for that particular sub-phase for that 16-bit group.

DBR# Output

DBR# (Debug Reset) is used only in processor systems where no debug port is

implemented on the system board. DBR# is used by a debug port interposer so

that an in-target probe can drive system reset. If a debug port is implemented in

the system, DBR# is a no connect in the system. DBR# is not a processor

signal.

DBSY# Input/

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on

the processor FSB to indicate that the data bus is in use. The data bus is

released after DBSY# is de-asserted. This signal must connect the appropriate

pins/lands on all processor FSB agents.

DEFER# Input DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the

responsibility of the addressed memory or input/output agent. This signal must

connect the appropriate pins/lands of all processor FSB agents.

DP[3:0]# Input/

Output DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They

are driven by the agent responsible for driving D[63:0]#, and must connect the

appropriate pins/lands of all processor FSB agents.

Table 4-3. Signal Description (Sheet 3 of 8)

Name Type Description

Quad-Pumped Signal Groups

Data Group DSTBN#/

DSTBP# DBI#

D[15:0]# 0 0

D[31:16]# 1 1

D[47:32]# 2 2

D[63:48]# 3 3

DBI[3:0] Assignment To Data Bus

Bus Signal Data Bus Signals

DBI3# D[63:48]#

DBI2# D[47:32]#

DBI1# D[31:16]#

DBI0# D[15:0]#

Datasheet 69

Land Listing and Signal Descriptions

DRDY# Input/

Output

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

indicating valid data on the data bus. In a multi-common clock data transfer,

DRDY# may be de-asserted to insert idle clocks. This signal must connect the

appropriate pins/lands of all processor FSB agents.

DSTBN[3:0]# Input/

Output

DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.

DSTBP[3:0]# Input/

Output

DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.

FCx Other FC signals are signals that are available for compatibility with other processors.

FERR#/PBE# Output

FERR#/PBE# (floating point error/pending break event) is a multiplexed signal

and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,

FERR#/PBE# indicates a floating-point error and will be asserted when the

processor detects an unmasked floating-point error. When STPCLK# is not

asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387

coprocessor, and is included for compatibility with systems using MS-DOS*-

type floating-point error reporting. When STPCLK# is asserted, an assertion of

FERR#/PBE# indicates that the processor has a pending break event waiting

for service. The assertion of FERR#/PBE# indicates that the processor should

be returned to the Normal state. For additional information on the pending break

event functionality, including the identification of support of the feature and

enable/disable information, refer to volume 3 of the Intel Architecture Software

Developer's Manual and the Intel Processor Identification and the CPUID

Instruction application note.

GTLREF Input G TLREF determines the signal reference level for GTL+ input signals. GTLREF

is used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.

GTLREF_SEL Output GTLREF_SEL is used to select the appropriate chipset GTLREF voltage.

HIT#

HITM#

Input/

Output

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Any FSB agent may assert both HIT# and HITM# together to indicate

that it requires a snoop stall, which can be continued by reasserting HIT# and

HITM# together.

IERR# Output

IERR# (Internal Error) is asserted by a processor as the result of an internal

error . Assertion of IERR# is usually accompanied by a SHUTDOWN transaction

on the processor FSB. This transaction may optionally be converted to an

external error signal (e.g., NMI) by system core logic. The processor will keep

IERR# asserted until the assertion of RESET#.

This signal does not have on-die termination. Refer to Section 2.5 for

termination requirements.

Table 4-3. Signal Description (Sheet 4 of 8)

Name Type Description

Signals Associated Strobe

D[15:0]#, DBI0# DSTBN0#

D[31:16]#, DBI1# DSTBN1#

D[47:32]#, DBI2# DSTBN2#

D[63:48]#, DBI3# DSTBN3#

Signals Associated Strobe

D[15:0]#, DBI0# DSTBP0#

D[31:16]#, DBI1# DSTBP1#

D[47:32]#, DBI2# DSTBP2#

D[63:48]#, DBI3# DSTBP3#

70 Datasheet

Land Listing and Signal Descriptions

IGNNE# Input

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. If

IGNNE# is de-asserted, the processor generates an exception on a noncontrol

floating-point instruction if a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this

signal following an Input/Output write instruction, it must be valid along with the

TRDY# assertion of the corresponding Input/Output Write bus transaction.

INIT# Input

INIT# (Initialization), when asserted, resets integer registers inside the

processor without affecting its internal caches or floating-point registers. The

processor then begins execution at the power-on Reset vector configured

during power-on configuration. The processor continues to handle snoop

requests during INIT# assertion. INIT# is an asynchronous signal and must

connect the appropriate pins/lands of all processor FSB agents.

If INIT# is sampled active on the active to inactive transition of RESET#, then

the processor executes its Built-in Self-Test (BIST).

ITP_CLK[1:0] Input

ITP_CLK[1:0] are copies of BCLK that are used only in processor systems

where no debug port is implemented on the system board. ITP_CLK[1:0] are

used as BCLK[1:0] references for a debug port implemented on an interposer . If

a debug port is implemented in the system, ITP_CLK[1:0] are no connects in

the system. These are not processor signals.

LINT[1:0] Input

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of all

APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR,

a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable

interrupt. INTR and NMI are backward compatible with the signals of those

names on the Pentium processor. Both signals are asynchronous.

Both of these signals must be software configured via BIOS programming of the

APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the

APIC is enabled by default after Reset, operation of these signals as LINT[1:0]

is the default configuration.

LL_ID[1:0] Output The LL_ID[1:0] signals are used to select the correct loadline slope for the

processor. LL_ID[1:0] = 00 for the Pentium 4 processor in the 775-land

package.

LOCK# Input/

Output

LOCK# indicates to the system that a transaction must occur atomically. This

signal must connect the appropriate pins/lands of all processor FSB agents. For

a locked sequence of transactions, LOCK# is asserted from the beginning of

the first transaction to the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the

processor FSB, it will wait until it observes LOCK# de-asserted. This enables

symmetric agents to retain ownership of the processor FSB throughout the bus

locked operation and ensure the atomicity of lock.

MCERR# Input/

Output

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error

without a bus protocol violation. It may be driven by all processor FSB agents.

MCERR# assertion conditions are configurable at a system level. Assertion

options are defined by the following options:

• Enabled or disabled.

• Asserted, if configured, for internal errors along with IERR#.

• Asserted, if configured, by the request initiator of a bus transaction after it

observes an error.

• Asserted by any bus agent when it observes an error in a bus transactio n.

For more details regarding machine check architecture, refer to the IA-32

Software Developer’s Manual, Volume 3: System Programming Guide.

MSID[1:0] Output MSID[1:0] are provided to indicate the market segment for the processor and

may be used for future processor compatibility or for keying.

Table 4-3. Signal Description (Sheet 5 of 8)

Name Type Description

Datasheet 71

Land Listing and Signal Descriptions

PROCHOT# Input/

Output

As an output, PROCHOT# (Processor Hot) will go active when the processor

temperature monitoring sensor detects that the processor has reached its

maximum safe operating temperature. This indicates that the processor

Thermal Control Circuit (TCC) has been activated, if enabled. As an input,

assertion of PROCHOT# by the system will activate the TCC, if enabled. The

TCC will remain active until the system de-asserts PROCHOT#. See

Section 5.2.4 for more details.

PWRGOOD Input

PWRGOOD (Power Good) is a processor input. The processor requires this

signal to be a clean indication that the clocks and power supplies are stable and

within their specifications. ‘Clean’ implies that the signal will remain low

(capable of sinking leakage current), without glitches, from the time that the

power supplies are turned on until they come within specification. The signal

must then transition monotonically to a high state. PWRGOOD can be driven

inactive at any time, but clocks and power must again be stable before a

subsequent rising edge of PWRGOOD. The PWRGOOD sign al must be

supplied to the processor; it is used to protect internal circuits against voltage

sequencing issues. It should be driven high throughout boundary scan

operation.

REQ[4:0]# Input/

Output

REQ[4:0]# (Request Command) must connect the appropriate pins/lands of all

processor FSB agents. They are asserted by the current bus owner to define

the currently active transaction type. These signals are source synchronous to

ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity

checking of these signals.

RESET# Input

Asserting the RESET# signal resets the processor to a known state and

invalidates its internal caches without writing back any of their contents. For a

power-on Reset, RESET# must stay active for at least one millisecond after

VCC and BCLK have reached their proper specifications. On observing active

RESET#, all FSB agents will de-assert their outputs within two clocks. RESET#

must not be kept asserted for more than 10 ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of

RESET# for power-on configuration. These configuration options are described

in the Section 6.1.

This signal does not have on-die termination and must be terminated on the

system board.

RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins/lands of all processor FSB agents.

RSP# Input

RSP# (Response Parity) is driven by the response agent (the agent responsible

for completion of the current transaction) during assertion of RS[2:0]#, the

signals for which RSP# provides parity protection. It must connect to the

appropriate pins/lands of all processor FSB agents.

A correct parity signal is high if an even number of covered signals are low and

low if an odd number of covered signals are low . While RS[2:0]# = 000, RSP# is

also high, since this indicates it is not being driven by any agent guaranteeing

correct parity.

SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor . System

board designers may use this signal to determine if the processor is present.

SMI# Input

SMI# (System Management Interrupt) is asserted asynchronously by system

logic. On accepting a System Management Interrupt, the processor saves the

current state and enter System Management Mode (SMM). An SMI

Acknowledge transaction is issued, and the processor begins program

execution from the SMM handler.

If SMI# is asserted during the de-assertion of RESET#, the processor will tri-

state its outputs.

Table 4-3. Signal Description (Sheet 6 of 8)

Name Type Description

72 Datasheet

Land Listing and Signal Descriptions

STPCLK# Input

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low

power Stop-Grant state. The processor issues a Stop-Grant Acknowledge

transaction, and stops providing internal clock signals to all processor core units

except the FSB and APIC units. The processor continues to snoop bus

transactions and service interrupts while in S top-Grant state. When STPCLK# is

de-asserted, the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#

is an asynchronous input.

TCK Input TCK (Test Clock) provides the clock input for the processor Test Bus (also

known as the Test Access Port).

TDI Input TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO Output TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TESTHI[13:0] Input TESTHI[13:0] must be connected to the processor’s appropriate power source

(refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a

resistor for proper processor operation. See Section 2.5 for more details.

THERMDA Other Thermal Diode Anode. See Section 5.2.7.

THERMDC Other Thermal Diode Cathode. See Section 5.2.7.

THERMTRIP# Output

In the event of a catastrophic cooling failure, the processor will automatically

shut down when the silicon has reached a temperature approximately 20 °C

above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the

processor junction temperature has reached a level beyond where permanent

silicon damage may occur. Upon assertion of THERMTRIP#, the processor will

shut off its internal clocks (thus, halting program execution) in an attempt to

reduce the processor junction temperature. To pro t ect the processor, its core

voltage (VCC) must be removed following the assertion of THERMTRIP#.

Driving of the THERMTRIP# signal is enabled within 10 µs of the assertion of

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-

assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the

processor’s junction temperature remains at or above the trip level,

THERMTRIP# will again be asserted within 10 µs of the assertion of

PWRGOOD.

TMS Input TMS (Test Mode Select) is a JTAG specification support signal used by debug

tools.

TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to

receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins/lands of all FSB agents.

TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be

driven low during power on Reset.

VCC Input VCC are the power pins for the processor . The voltage supplied to these pins is

determined by the VID[5:0] pins.

VCCA Input VCCA provides isolated power for the internal processor core PLLs.

VCCIOPLL Input VCCIOPLL provides isolated power for internal processor FSB PLLs.

VCC_SENSE Output VCC_SENSE is an isolated low impedance connection to processor core power

(VCC). It can be used to sense or measure voltage near the silicon with little

noise.

VCC_MB_

REGULATION Output This land is provided as a voltage regulator feedback sense point for VCC. It is

connected internally in the processor package to the sense point land U27 as

described in the V oltage Regulator-Down (VRD) 10.1 Design Guide for Desktop

Socket 775.

Table 4-3. Signal Description (Sheet 7 of 8)

Name Type Description

Datasheet 73

Land Listing and Signal Descriptions

VID[5:0] Output

VID[5:0] (Voltage ID) signals are used to support automatic selection of power

supply voltages (VCC). These are open drain signals that are driven by the

processor and must be pulled up on the motherboard. Refer to the Voltage

Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for more

information. The voltage supply for these signals must be valid before the VR

can supply VCC to the processor. Conversely, the VR output must be disabled

until the voltage supply for the VID signals becomes valid. The VID signals are

needed to support the processor voltage specification variations. See Table 2-2

for definitions of these signals. The VR must supply the voltage that is

requested by the signals, or disable itself.

VSS Input VSS are the ground pins for the processor and should be connected to the

system ground plane.

VSSA Input VSSA is the isolated ground for internal PLLs.

VSS_SENSE Output VSS_SENSE is an isolated low impedance connection to processor core VSS. It

can be used to sense or measure ground near the silicon with little noise.

VSS_MB_

REGULATION Output This land is provided as a voltage regulator feedback sense point for VSS. It is

connected internally in the processor package to the sense point land V27 as

described in the Volt age Regulator-Down (VRD) 10.1 Design Guide for Desktop

Socket 775.

VTT Miscellaneous voltage supply.

VTT_OUT_LEFT

VTT_OUT_RIGHT Output

The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a

voltage supply for some signals that require termination to VTT on the

motherboard.

For future processor compatibility some signals are required to be pulled up to

VTT_OUT_LEFT or VTT_OUT_RIGHT. Refer to the following table for the

signals that should be pulled up to VTT_OUT_LEFT and VTT_OUT_RIGHT.

VTT_SEL Output The VTT_SEL signal is used to select the correct VTT voltage level for the

processor.

VTTPWRGD Input The processor requires this input to determine that the VTT voltages are stable

and within specification.

Table 4-3. Signal Description (Sheet 8 of 8)

Name Type Description

Pull-up Signal Signals to be Pulled Up

VTT_OUT_RIGHT VTT_PWRGOOD, VID[5:0], GTLREF, TMS, TDI,

TDO, BPM[5:0], other VRD components

VTT_OUT_LEFT RESET#, BR0#, PWRGOOD, TESTHI1, TESTHI8,

TESTHI9, TESTHI10, TESTHI11, TESTHI12

74 Datasheet

Land Listing and Signal Descriptions

Datasheet 75

Thermal Specifications and Design Considerations

5Thermal Specifications and

Design Considerations

5.1 Processor Thermal Specifications

The Pentium 4 processor in the 775-land package requires a thermal solutio n to maintain

temperatures within operati ng limits as set forth in Section 5.1.1. Any attempt to operate the

processor outside these operating limits may resu lt in perman ent damage to the processor and

potentially other componen ts within the system. As processor technology chang e s, thermal

management becomes increasingly cru cia l when building computer systems. Maintaini ng the

proper thermal environment is key to reliable, long-term system operation.

A complete thermal solution includes both componen t and sy stem level thermal management

features. Component level thermal solutions can include active or passive heatsinks attached to the

processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of

system fans combined with ducting and venting.

For more information on designing a component lev el thermal solution, refer to the Intel®

Pentium® 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Gu ideli nes.

Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on

the boxed processor.

5.1.1 Thermal Specifications

To allow for the optimal operation and long-term reliabil ity of Intel processor-based systems, the

system/processor thermal sol ution should be designed such that the processor rema ins within the

minimum and maximum case temperature (TC) specifications when operating at or below the

Thermal Design Power (TDP) value listed per frequency in Table 5-1. Thermal solut ions not

designed to provide this level of thermal capability may affect the long-term reliability of the

processor and system. For more details on thermal solution design, refer to th e appropriate

processor thermal design guidelines.

The Pentium 4 processor in the 775-land package introduces a new methodology for managing

processor temperatures which is intend ed to support acoustic noise reduction through fan speed

control. Selection of the appropriate fan speed will be based on the temperature reported by the

processor’s thermal diod e. If the diode temperature is greater than or equal to TCONTROL, the

processor case temperature must remain at or below the temperature as specified by the thermal

profile. If the diode temperature is less than TCONTROL then the case temperature is permitted to

exceed the thermal profile, but the diode temperature must remain at or below TCONTROL. Systems

that implement fan speed control must be designed to take th ese conditions into account. Systems

that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile

specifications.

To determine a processor's case temperature specification based on the thermal profile, it is

necessary to accurately measure processor power dissipation.

76  Datasheet
Thermal Specifications and Design Considerations
The case temperature is defined at the geometric top center of the processor IHS. Analysis indicates 
that real applications are unlikely to cause the processor to  consume maximum power dissipation for 
sustained periods of time. Intel recommends that complete thermal solu tion designs target the 
Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processo r po wer 
consumption. The Thermal Monitor feature is intended to help protect the processor in the unlikely 
event that an application exceeds the TDP recommendation for a sustained period of time. For more 
details on the usage of this feature, refer to Section 5.2. In all cases, the Thermal Monitor feature 
must be enabled for the processor to remain within specification.
Table 5-1. Processor Thermal Specifications
Processor 
Number Core Frequency 
(GHz) Thermal Design 
Power (W) Minimum TC 
(°C) Maximum TC (°C) Notes
520/521 2.80 (PRB = 0) 84 5 See Table 5-3 and Figure 5-2 1, 2
530/531 3 (PRB = 0) 84 5 See Table 5-3 and Figure 5-2 1, 2
540/541 3.20 (PRB = 0) 84 5 See Table 5-3 and Figure 5-2 1, 2
550/551 3.40 (PRB = 0) 84 5 See Table 5-3 and Figure 5-2 1, 2
550 3.40 (PRB = 1) 115 5 See Table 5-2 and Figure 5-1 1, 2
NOTES:
1. Thermal Design Power (TDP) should b e used for processor thermal solution de sign targets. The TDP is not the maximum pow-
er that the processor can dissipate.
2. This table shows the maximum TDP for a given f requency range . Individual pr ocessors may h ave a lower TDP. Theref ore, the
maximum TC will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table
for the allowed combinations of power and TC.
560/561 3.60 (PRB = 1) 115 5 See Table 5-2 and Figure 5-1 1, 2
570/571 3.80 (PRB = 1) 115 5 See Table 5-2 and Figure 5-1 1, 2

Datasheet 77

Thermal Specifications and Design Considerations

Table 5-2. Thermal Profile for Processors with PRB = 1

Power

(W) Maximum TC

(°C) Power

(W) Maximum TC

(°C) Power

(W) Maximum TC

(°C) Power

(W) Maximum TC

(°C)

0 44.0 30 51.5 60 59.0 90 66.5

2 44.5 32 52.0 62 59.5 92 67.0

4 45.0 34 52.5 64 60.0 94 67.5

6 45.5 36 53.0 66 60.5 96 68.0

8 46.0 38 53.5 68 61.0 98 68.5

10 46.5 40 54.0 70 61.5 100 69.0

12 47.0 42 54.5 72 62.0 102 69.5

14 47.5 44 55.0 74 62.5 104 70.0

16 48.0 46 55.5 76 63.0 106 70.5

18 48.5 48 56.0 78 63.5 108 71.0

20 49.0 50 56.5 80 64.0 110 71.5

22 49.5 52 57.0 82 64.5 112 72.0

24 50.0 54 57.5 84 65.0 114 72.5

26 50.5 56 58.0 86 65.5 115 72.8

28 51.0 58 58.5 88 66.0

Figure 5-1. Thermal Profile for Processors with PRB = 1

y = 0.25x + 44

40.0

45.0

50.0

55.0

60.0

65.0

70.0

75.0

0 10 20 30 40 50 60 70 80 90 100 110

Power (W)

Tcase (C)

78 Datasheet

Thermal Specifications and Design Considerations

Table 5-3. Thermal Profile for Processors with PRB = 0

Power

(W) Maximum Tc

(°C) Power

(W) Maximum Tc

(°C) Power

(W) Maximum Tc

(°C)

0 44.2 30 52.6 60 61.0

2 44.8 32 53.2 62 61.6

4 45.3 34 53.7 64 62.1

6 45.9 36 54.3 66 62.7

8 46.4 38 54.8 68 63.2

10 47.0 40 55.4 70 63.8

12 47.6 42 56.0 72 64.4

14 48.1 44 56.5 74 64.9

16 48.7 46 57.1 76 65.5

18 49.2 48 57.6 78 66.0

20 49.8 50 58.2 80 66.6

22 50.4 52 58.8 82 67.2

24 50.9 54 59.3 84 67.7

26 51.5 56 59.9

28 52.0 58 60.4

Figure 5-2. Thermal Profile for Proc essors with PRB = 0

y = 0.28x + 44.2

40.0

45.0

50.0

55.0

60.0

65.0

70.0

0 1020304050607080

Power (W)

Tcase (C)

Datasheet 79

Thermal Specifications and Design Considerations

5.1.2 Thermal Metrology

The maximum and minimum case temperatures (TC) are specified in Table 5-1. These temperature

specifications are meant to help ensure proper operation of the processor. Figure 5-3 illustrates

where Intel recommends TC thermal measurements should be made. For detailed guidelines on

temperature measurement methodolog y, refer to the Intel® Pentium® 4 Processor on 90 nm

Process in the 775-Land Package Thermal Design Guidelines.

5.2 Processor Thermal Features

5.2.1 Thermal Monitor

The Thermal Monitor feature helps control the processor temperature by activating the TCC when

the processor silicon reaches its maximum operating temperature. The TCC reduces processor

power consumption as needed by modulating (starting and stopping) the internal processor core

clocks. The Thermal Monitor feature must be enabled for the processor to be operating

within specifications. The temperature at which Thermal Monitor activates the thermal control

circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal

manner, and in terrupt requests are latched (and serviced during the time that the clocks are on)

while the TCC is active.

When the Thermal Monitor feature is enabled, and a high temperature situation exists (i. e., TCC i s

active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle

specific to the processor (typically 30–50%). Clocks often will not be off for more than

3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will

decrease as processor core frequencies increase. A small amount of hysteresis has been included to

prevent rapid active/inact ive transitions of the TCC when the processor temperature is near its

maximum operating temperature. Once the temperature has dropped below the maximum

operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock

modulation ceases.

Figure 5-3. Case Temperature (TC) Measurement Location

37.5 mm

Meas ure TCat this point

(geometric center of the package)

37. 5 mm

37.5 mm

Meas ure TCat this point

(geometric center of the package)

37. 5 mm

80 Datasheet

Thermal Specifications and Design Considerations

With a properly designed and characterized thermal solution, it is anticipated that the TCC would

only be activated for very short perio ds of tim e when running the most power intensive

applications. The processor performance impact due to these brief per i ods of TCC activation is

expected to be so minor that it would be immeasurable. An under-designed thermal solution that is

not able to prevent excessive activation of the TCC in the anticipated ambient environment may

cause a noticeable performance loss, and in some cases may result in a TC that exceeds the

specified maximum temperature and may affect the long-term reliability of the processor. In

addition, a thermal solution that is significantly under-designed may not be capable of cooling the

processor even when the TCC is active continuously. Refer to the Intel® Pentium® 4 Processor on

90 nm Process in the 775-Land Package Therm al Design Guidelines for information on designing

a thermal solution.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and

cannot be modified. The Thermal Monitor does no t require any additional hardware, software

drivers, or interrupt handling rou tines.

5.2.2 Thermal Monitor 2

The Pentium 4 processor in the 775-land pack age also supports a power management capability

known as Thermal Monitor 2. This mechanism provides an efficient mechanism for limiting the

processor temperature by reducing power consumption within the processor.

When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the enhanced

Thermal Control Circuit (TCC) will be activated. This enhanced TCC causes the processor to

adjust its operating frequency (bus multiplier) and input voltage (VID). This combination of

reduced frequency and VID results in a decrease in processor power consumption.

A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a

specific operating frequency and voltage. The first point represents the normal operating conditions

for the processor.

The second point consists of both a lower operating frequency and voltage. When th e enhanced

TCC is activated, the processor automatically transitions to the new frequency. This transition

occurs very rapidly (on the order of 5 µs). During the frequency transition, the processor is unable

to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts

will be latched and kept pending until the processor resumes operation at the new frequency.

Once the new operating frequency is engaged, the processor will transition to the new core

operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must

support VID transitions in order to su pport Thermal Monitor 2. During th e vo ltage change, it will

be necessary to transition through multiple VID codes to reach the target operating voltage. Each

step will be one VID table entry (i.e., 12.5 mV steps). The processor continues to execute

instructions during the voltage transition. Operation at this lower voltage reduces both the dynamic

and leakage power consumption of the processor, providing a reduction in power consumption at a

minimum performance impact.

Once the processor has sufficiently cooled, and a minimum activation time has expired, the

operating frequency and voltage transition back to the normal system operating point. T ransition of

the VID code will occur first, to insure proper operation once the processor reaches its normal

operating frequency. Refer to Figure 5-4 for an illustration of this ordering.

Datasheet 81

Thermal Specifications and Design Considerations

The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of

whether or not Thermal Monitor or Thermal Monitor 2 is enabled.

It should be noted that the Thermal Monitor 2 TCC can not be activated via the on demand mode.

The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.

5.2.3 On-Demand Mode

The Pentium 4 processor in the 775-land package provides an auxiliary mechanism that allows

system software to force the processor to reduce its power consumption. This mechanism is

referred to as "On-Demand" mode and is distinct from the Thermal Monitor feature. On-Demand

mode is intended as a means to reduce system level power consumption. Systems using the

Pentium 4 processor in the 775-land package must not rely on software usage of this mechanism to

limit the processor temperature.

If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL

MSR) is written to a '1', the processor will immediately reduce its power consumption via

modulation (starting and stopping) of the internal core clock, independent of the processor

temperature. When using On-Demand mode, the duty cycle of the clock modulati on is

programmable via bits 3:1 of the same ACPI P_CNT Control Register. In On-Demand mode, the

duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5%

increments. On-Demand mode may be used in conjunction with the Thermal Monitor . If the system

tries to enable On-Demand mode at the same ti me the TCC is engaged, the factory configured duty

cycle of the TCC will override the duty cycle selected by the On-Demand mode.

Figure 5-4. Thermal Monitor 2 Frequency and Voltage Orde ring

VID

Frequency

Temperature

TTM2

fMAX

fTM2

VID

VIDTM2

PROCHOT#

Time

82 Datasheet

Thermal Specifications and Design Considerations

5.2.4 PROCHOT# Signal

An external signal, PROCHOT# (processo r hot ), is asserted when the processor die temperature

has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the

Thermal Monitor must be enabled for the processor to be operating within specification), the TCC

will be active when PROCHOT# is asserted. The processor can be configured to generate an

interrupt upon the assertion or de-assertion of PROCHOT# . Refer to the Intel Architecture

Software Developer's Manuals for specific register and programming details.

The Pentium 4 processor in the 775-land package implements a bi-directional PROCHOT#

capability to allow system designs to protect various components from over-temperature situations.

The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached

its maximum operating temperatu re or be driven from an external source to activate the TCC. The

ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system

components.

One application is the thermal protection of voltage regulators (VR). System designers can create a

circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR

is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, th e VR can cool down

as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR

thermal designs to target maximum sustaine d curr ent instead of maximum current. Systems should

still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in

case of system cooling failure. The system thermal design should allow the power delivery

circuitry to operate within its temperature specification even while the processor is operating at its

Thermal Design Power. With a properly designed and characterized thermal solution, it is

anticipated that bi-directional PROCHOT# would only be asserted for very short pe rio ds of tim e

when running the most power intensi ve appli cations. An under-designed thermal solution that is

not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may

cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 10.1 Design

Guide for Desktop Socket 775 for details on implementing the bi-directional PROCHOT# feature.

5.2.5 THERMTRIP# Signal

Regardless of whether or not the Thermal Monitor feature is enabled, in the event of a catastrophic

cooling failure, the processor will automatically shut down when the silicon has reached an

elevated temperature (refer to the THERMTRIP# definition in Table 4-3). At this point, the FSB

signal THERMTRIP# will go active and stay active as described in Table 4-3. THERMTRIP#

activation is independent of processor activity and does not generate any bus cycles.

5.2.6 TCONTROL and Fan Speed Reduction

TCONTROL is a temperature specification based on a temperature reading from the thermal diode.

The value for TCONTROL will be calibrated in manufacturing and configured for each processor.

When Tdiode is above TCONTROL, then TC must be at or below TC-MAX as defined by the thermal

profile in Table 5-2 and Figure 5-1; otherwise, the processor temperature can be maintained at

TCONTROL (or lower) as measured by the thermal diode.

The purpose of this feature is to support acoustic optimization through fan speed control . Contact

your Intel representative for further details and documentatio n.

Datasheet 83

Thermal Specifications and Design Considerations

5.2.7 Thermal Diode

The processor incorporates an on-die thermal diode. A thermal sensor located on the system board

may monitor the di e temp erature of the proce sso r for thermal managemen t /long term die

temperature change purposes. Table 5-4 and Table 5-5 provide the diode parameter and interface

specifications. This thermal diode is separate from the Therm al Monitor’s thermal sensor and

cannot be used to predict the behavior of the Thermal Monitor.

Table 5-4. Thermal Diode Parameters

Symbol Parameter Min Typ Max Unit Notes

IFW Forward Bias Current 11 187 µA 1

NOTES:

1. Intel does not support or recommend operation of the t hermal diode under reverse bias.

n Diode Ideality Factor 1.0083 1.011 1.023 2, 3, 4, 5

2. Characterized at 75 °C.

3. Not 100% tested. Specified by design characterization.

4. The ideality factor, n, represents the de viation from ideal diode behavior as exempl ified by the diode equation:

IFW = IS * (e qVD/nkT –1)

where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann

Constant, and T = absolute temperature (Kelvin).

5. Devices found to have an ideality factor of 1.0183 to 1.023 will create a temperature error approximately 2 C° higher than

the actual tempera tur e. To minimize an y p otent ial acou st ic impact of this t emp erature error , T CONTROL will be increased by

2 C° on these parts.

RTSeries Resistance 3.242 3.33 3.594 Ω2, 3, 6

6. The series resistance, RT, is provided to allow for a more accurate measurement of the thermal diode temperature. RT, as

defined, includes the pins of the processor but does not include any socket resistance or board trace resistance between

the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic

series resistance cancellation to calibrate out this error te rm. Another application is that a temperature offset can be manu-

ally calculated and pr ogrammed into an offset register in the remote diode thermal sensors as exemplified by the equation:

Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N]

where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic

charge.

Table 5-5. Thermal Diode Interface

Signal Name Land Number Signal Description

THERMDA AL1 diode anode

THERMDC AK1 diode cathode

84 Datasheet

Thermal Specifications and Design Considerations

Datasheet 85

Features

6Features

6.1 Power-On Configuration Options

Several configuration options can be configured by hardware. The Pentium 4 processor in the 775-

land package samples the hardware configuration at reset, on the active-to-inactive transition of

RESET#. For specifications on these options, refer to Table 6-1.

The sampled information configures the processor for subsequent operation. These configuration

options cannot be changed except by another reset. All resets reconfigure the processor; for reset

purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.

Frequency determination functionality will exist on engineering sample processors which means

that samples can run at varied frequencies. Production material will have the bus to core ratio

locked and can only be operated at the rated frequency.

6.2 Clock Control and Low Power States

The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by

stopping the clock to internal sections of the processor, depend ing on each particular state. See

Figure 6-1 for a visual representation of the processor low power states.

The processor adds support for the Enhanced HALT powerd own state. Refer to Figure 6-1 and the

following sections.

Not all processors are capable of supporting the Enhanced HALT state. Refer to the Specification

Update to determine which processor stepping and frequencies will support the Enhanced HALT

state.

Table 6-1. Power-On Configuration Option Signals

Configuration Option Signal1, 2

NOTES:

1. Asserting this signal during RESET# will select the correspo nding option.

2. Address signals not identified in this table as configuration options should not be asserted during RESET#.

Output tristate SMI#

Execute BIST INIT#

In Order Queue pipelining (set IOQ depth to 1) A7#

Disable MCERR# observation A9#

Disable BINIT# observation A10#

APIC Cluster ID (0-3) A[12:11]#

Disable bus parking A15#

Disable Hyper-Threading Technology A31#

Symmetric agent arbitration ID BR0#

RESERVED A[6:3]#, A8#, A[14:13]#, A[16:30]#, A[32:35]#

86 Datasheet

Features

6.2.1 Normal State

This is the normal operating state for the processor.

6.2.2 HALT and Enhanced HALT Powerdown States

The Prescott processor supports the HALT or Enhanced HALT powerdown state. The Enhanced

HALT powerdown state is configured and enabled via the BIOS.

The Enhanced HALT state is a lower power state as compared to the Stop Grant State.

If Enhanced HALT is not enabled, the default powerdown state entered will be HALT. Refer to the

sections below for details about the HALT and Enhanced HALT states.

6.2.2.1 HALT Powerdown State

HALT is a low power state entered when all the logical processors have executed th e HALT or

MWAIT instructions. When one of the logical processors executes the HALT instruction, that

logical processor is halted, however , the other processor continues normal operation. The processor

will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0]

(NMI, INTR). RESET# will cause the processor to immediately initialize itself.

The return from a System Management In terrupt (SMI) handler can be to either Normal Mode or

the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III:

System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in th e HALT Power Down state. When

the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT Power Down state, the processor will process bus snoops.

6.2.2.2 Enhanced HALT Powerdown State

Enhanced HALT is a low power state entered when all logical processors have executed the HALT

or MWAIT instructions and Enhanced HALT has been enabled via the BIOS. When one of the

logical processors executes the HALT instruction, that logical processor is halted ; ho wever, the

other processor continues normal operation.

The processor will automatically transition to a lower frequency and voltage operating point before

entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; onl y the

internal core frequency is changed. When entering the lo w power state, the processor will first

switch to the lower bus ratio and then transition to the lower VID.

While in Enhanced HALT state, the processor will process bus snoops.

The processor exits the Enhanced HALT state when a break event occurs. When the processor exits

the Enhanced HALT state, it will first transition the VID to the original value and then change the

bus ratio back to the original value.

Datasheet 87

Features

6.2.3 Stop-Grant State

When the STPCLK# signal is asserted, the Stop-Grant state of the processor is entered 20 bus

clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.

Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing

the level to return to VTT) for minimum power drawn by the termination resistors in this state. In

addition, all other in put signals on the FSB should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched

and can be serviced by software upon exit from the Stop Grant state.

RESET# will cause the processor to immediately initialize itself, but the processo r wil l stay in

Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the

STPCLK# signal.

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the

FSB (see Section 6.2.3).

While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the

processor, and only serviced when the processor returns to the Normal State. Only one occurrence

of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process a FSB snoop.

Figure 6-1. Processor Low Power State Machine

Enhanced HALT or HALT State

BCLK running

Snoops and interrupts allowed

Normal State

Normal execution

HALT Snoop State

BCLK running

Service snoops to caches

Stop-Grant State

BCLK running

Snoops and interrupts allowed

Snoop

Event

Occurs

Snoop

Event

Serviced

INIT#, BINIT#, INTR, NMI, SMI#,

RESET#, FSB interrupts

STPCLK#

Asserted STPCLK#

De-asserted

STPCLK#

Asserted

STPCLK#

De-asserted

Snoop Event Occurs

Snoop Event Serviced

HALT or MWAIT Instruction and

HALT Bus Cycle Generated

Grant Snoop State

BCLK running

Service snoops to caches

88 Datasheet

Features

6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop

State

The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If

Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the

HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop

State and Enhanced HALT Snoop State.

6.2.4.1 HALT Snoop State, Grant Snoop State

The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT

Power Down state. During a snoop transaction, the processor enters the HALT:Grant Snoop state.

The processor will stay in this state until the snoop on the FSB has been serviced (whether by the

processor or another agent on the FSB). After the snoop is serviced, the processor will return to the

Stop-Grant state or HALT Power Down state, as appropriate.

6.2.4.2 Enhanced HALT Snoop State

The Enhanced HALT Snoop State is the default Snoop State when the Enhanced HALT state is

enabled via the BIOS. The processor will remain in the lower bus ratio and VID operating point of

the Enhanced HALT state.

While in the Enhanced HALT Snoop State, snoops are handled the same way as in the HALT

Snoop State. After the snoop is serviced the processor will return to the Enhanced HALT Power

Down state.

Datasheet 89

Boxed Processor Specifications

7Boxed Processor Specifications

The Pentium 4 processor on 90 nm process in the 775-land package will also be offered as a boxed

Intel processor. Boxed Intel processors are intended for system integrators who build systems from

baseboards and standard components. The boxed Pentium 4 processor in the 775-land package will

be supplied with a cooling solution. This chapter docum ents baseboard and system requirements

for the cooling solution that will be supplied with the boxed Pentium 4 processor in the 775-land

package. This chapter is particularly important for OEMs that manufacture baseboards for system

integrators. Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and

inches [in brackets]. Figure 7-1 shows a mechanical representation of a boxed Pentium 4 processor

in the 775-land package.

Note: Drawings in this section reflect only the specifications on the boxed Intel processor product. These

dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system

designers’ responsibility to consider their proprietary cooling solution when designing to the

required keep-out zone on their system platforms and chassis. Refer to the Intel® Pentium® 4

Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines for further

guidance. Contact your local Intel Sales Represen tative for this document.

NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

Figure 7-1. Mechanical Representation of the Boxed Processor

90 Datasheet

Boxed Processor Specifications

7.1 Mechanical Specifications

7.1.1 Boxed Processor Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed Pentium 4 processor on 90 nm

process in the 775-land package. The boxed processor will be shipped with an unatt ached fan

heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium 4 processor in the

775-land package.

Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The

physical space requirements and dimensions for the boxed processor with assembled fan heatsink

are shown in Figure 7-2 (side view), and Figure 7-3 (top view). The airspace requirements for the

boxed processor fan heatsink must also be incorporated into new baseboard and system designs.

Airspace requirements are shown in Figure 7-7 and Figure 7-8. Note th at some figures have

centerlines shown (marked with alphabetic designations) to clarify relat ive dim e nsioning.

NOTES:

1. Diagram does not show the attached hardware for the clip design and is provided on ly as a mechanical

representation.

Figure 7-2. Space Requirements for the Boxed Processor (Side View)

Figure 7-3. Space Requirements for the Boxed Processor (Top View)

3.74

[95.0]

3.2

[81.3]

0.39

[10.0] 0.98

[25.0]

3.74

[95.0]

3.74

[95.0]

Datasheet 91

Boxed Processor Specifications

7.1.2 Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the

Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land Package Thermal Design

Guidelines for details on the processor weig ht and heatsink requirements.

7.1.3 Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly

The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the

processor an d fan heatsink in the bas eboard socket. The boxed processor will ship with the heatsink

attach clip assembly.

7.2 Electrical Requirements

7.2.1 Fan Heatsink Power Supply

The boxed processor's fan heatsink requires a +12 V pow er suppl y. A fan power cable will be

shipped with the boxed processor to draw power from a power header on the baseboard. The power

cable connector and pinout are shown in Figure 7-5. Baseboard s must provid e a matched power

header to support the boxed processor. Table 7-1 contains specifications for the input and output

signals at the fan heatsink connector.

Figure 7-4. Space Requirements for the Boxed Processor (Overall View)

92 Datasheet

Boxed Processor Specifications

The fan heatsink outputs a SENSE signal that is an open-collector output that pulses at a rate of

2 pulses per fan revolution. A baseboard pu ll-up resist or provides VOH to match the system board-

mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the

SENSE signal is not used, pin 3 of the connector should be tied to GND.

The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connecto r

labeled as CONTROL.

The boxed processor's fan heatsink requires a constant +12 V supplied to pin 2 and does not

support variable voltage control or 3-pin PWM cont rol .

The power header on the baseboard must be positioned to allow the fan heatsink power cable to

reach it. The power header identification and location should be documented in the platform

documentation, or on the system board itsel f. Figure 7-6 shows the locat ion of the fan power

connector relative to the processor socket. The baseboard power header should be posi t io n ed

within 110 mm [4.33 inches] from the center of the processor socket.

Figure 7-5. Boxed Processor Fa n Heatsink Power Cable Connector Description

Table 7-1. Fan Heatsink Power and Signal Spe cifications

Description Min Typ Max Unit Notes

+12 V: 12 volt fan power supply 10.2 12 13.8 V -

IC:

Peak Fan current draw

Fan start-up current draw

Fan start-up current draw maximum duration

—1.1

—

1.5

2.2

1.0

Second

SENSE: SENSE frequency — 2 — pulses per fan

revolution 1

NOTES:

1. Baseboard should pull this pin up to 5V with a resistor.

CONTROL 21 25 28 kHz 2, 3

2. Open drain type, pulse width modulated.

3. Fan will have pull-up resistor to 4.75 V maximum of 5.25 V.

Boxed_Proc_PwrCable

Pin Signal

1234

GND

+12 V

SENSE

CONTROL

Straight square pi n, 4-pi n terminal housing with

polar izing ribs and f r icti on lock ing ramp.

0.100" pitc h, 0.025" square pin width.

Matc h with straight pin, fric ti on lock header on

mainboard.

Datasheet 93

Boxed Processor Specifications

7.3 Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution used by the boxed

processor.

7.3.1 Boxed Processor Cooling Requirements

The boxed proc essor may be direct ly cool ed wit h a fan heatsink. However, meeting the processor's

temperature specification is also a function of the thermal design of the entire system, and

ultimately the responsibility of the system integrator. The processor temperature specification is in

Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature within the

specifications (see Table 5-1) in chassis that provide good thermal management. For the boxed

processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink

is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

Airspace is required around the fan to ensure that the airflow through the fan heatsink is not

blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan

life. Figure 7-7 and Figure 7-8 illustrate an acceptable airspace clearance for the fan heatsink. The

air temperature entering the fan should be kept below 38 ºC. Again, meeting the processor's

temperature specification is the responsibility of the system integrator.

Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket

R4.33

[110]

94 Datasheet

Boxed Processor Specifications

Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)

Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side View)

Datasheet 95

Boxed Processor Specifications

7.3.2 Variable Speed Fan

If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin m otherboard header it

will operate as follows:

The boxed processor fan will operate at different speeds over a short range of internal chassis

temperatures. This allows the processor fan to operate at a lower speed and noise level, while

internal chassis temperatures are low. If internal chassis temperature increases beyond a lower

set point, the fan speed will rise linearly with the internal temperature until the higher set point

is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan

noise levels. Systems should be designed to provi de adequate air around the boxed processor

fan heatsink that remains cooler then lo wer set point. These set points, represented in

Figure 7-9 and Table 7-2, can vary by a few degrees from fan heatsink to fan heatsink. The

internal chassis temperature should be kept below 38 ºC. Meeting the processor's temperature

specification (see Chapter 5) is the responsibility of the system integrat or.

The motherboard must supply a constant +12 V to the processor's power header to ensure proper

operation of the variable speed fan for the boxed processor. Refer to Table 7-1 for the specific

requirements.

Figure 7-9. Boxed Processor Fan Heatsink Set Points

Lower Set Point

Lowest Noi se Level

Inter nal Chassis Tem per ature (Degrees C)

XYZ

Incr easi ng F an

Speed & Noise

Higher S et Point

Highest Noi se Level

96 Datasheet

Boxed Processor Specifications

If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and

the motherboard is designed with a fan speed controller with PWM output (CONTROL see

Table 7-1) and remote thermal diode measurement capability the boxed processor will operate as

follows:

As processor power has increased the required thermal solutions have generated increasingly more

noise. Intel has added an option to the boxed processor that allows system integrators to have a

quieter system in the most common usage.

The 4th wire PWM solution provides better control ov er chassis acoustics. This is achieved by

more accurate measurement of processor die temperature through the processor's temperature

diode (Tdiode). Fan RPM is modulated through the use of an ASIC located on the motherboard that

sends out a PWM control signal to the 4th pin of the con nector labeled as CONTROL. The fan

speed is based on actual processor temperature instead of internal ambient chassis temperatures.

If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan

header, it will default back to a thermistor controlled mode, allowing compatibility with existing 3-

pin baseboard designs. Under thermist or controlled mode, the fan RPM is automatically varied

based on the Tinlet temperature measured by a thermistor located at the fan inlet.

For more details on specific motherboard requirements for 4-wire based fan speed control see the

Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land Package Thermal Desi gn Guide.

Table 7-2. Fan Heatsink Power and Signal Spe cifications

Boxed Processor Fan

Heatsink Set Point (ºC) Boxed Processor Fan Speed Notes

X ≤ 30 When the internal chassis temperature is below or equal to this set point,

the fan operates at its lowest speed. Recommended maximum internal

chassis temperature for nominal operating environment. 1

NOTES:

1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.

Y = 34 When the internal chassis temperature is at this point, the fan operates

between its lowest and highest speeds. Recommended maximum

internal chassis temperature for worst-case operating environment. -

Z ≥ 38 When the internal chassis temperature is above or equal to this set point,

the fan operates at its highest speed. -

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Product Specs Intel

Processors Intel

Pentium

4 Processo

Intel

Pentium

4 Processor 500 Series

supporting Hyper-Threading Technology

530

Intel® Pentium® 4 Processor 530/530J supporting HT Technology

(1M Cache, 3.00 GHz, 800 MHz FSB) Compare Now (0)Add to Compare

dditional Information

Quick Links

PCN/MDDS Information

Products formerly Prescott

Download Datasheet

Support Overview >

Specifications

Essentials

Package Specifications

Advanced Technologies

Ordering / sSpecs / Steppings

Retired and Discontinued

Compatible Products

Chipsets

Block Diagrams

Specifications

Essentials

Status EOIS

Launch Date Q2'04

Processor Number 530

# of Cores 1

# of Threads 2

Clock Speed 3 GHz

L2 Cache 1 MB

Bus/Core Ratio 15

FSB Speed 800 MHz

Instruction Set 32-bit

Embedded Options Available No

Supplemental SKU No

Lithography 90 nm

Max TDP 84 W

VID Voltage Range 1.200V-1.425V

Recommended Channel Price $70 - $97

Package Specifications

CASE 67.7°C

Package Size 37.5mm x 37.5mm

Processing Die Size 112 mm2

# of Processing Die Transistors 125 million

Sockets Supported PLGA775, PPGA478

Low Halogen Options Available No

Advanced Technologies

Intel® Turbo Boost Technology No

Intel® Hyper-Threading Technology Yes

Intel® Virtualization Technology (VT-x) No

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Intel® Trusted Execution Technology No

Intel® 64 No

Idle States No

Enhanced Intel SpeedStep® Technology No

Intel® Demand Based Switching No

Execute Disable Bit No

Ordering and Spec Information

Retired and Discontinued

Intel® Pentium® 4 Processor 530 supporting HT Technology (1M Cache, 3.00 GHz, 800 MHz FSB) mPGA 478, Tray

Intel® Pentium® 4 Processor 530 supporting HT Technology (1M Cache, 3.00E GHz, 800 MHz FSB) mPGA 478, Tray

Boxed Intel® Pentium® 4 Processor 530 supporting HT Technology (1M Cache, 3.00E GHz, 800 MHz FSB) mPGA 478

Boxed Intel® Pentium® 4 Processor 530/530J supporting HT Technology (1M Cache, 3.00 GHz, 800 MHz FSB) LGA775

Boxed Intel® Pentium® 4 Processor 530 supporting HT Technology (1M Cache, 3.00 GHz, 800 MHz FSB) LGA775

Intel® Pentium® 4 Processor 530/530J supporting HT Technology (1M Cache, 3.00 GHz, 800 MHz FSB) LGA775, Tray

Boxed Pentium® 4 Processor 530/530J supporting HT Technology, Balanced Technology Extended (BTX) Type 1, LGA775

Socket Step Step TDP Ordering Code Spec Code Low Halogen VT-x Recommended Channel Price

PPGA478 G1 65 W RK80546PG0801M SL8JZ No No N/A

PPGA478 65 W RK80546PG0801M SL79L No No N/A

PPGA478 65 W RK80546PG0801M SL7E4 No No N/A

Socket Step Step TDP Ordering Code Spec Code Low Halogen VT-x Recommended Channel Price

PPGA478 G1 84 W NE80546PG0801M SL8JZ No No $70

PPGA478 E1 84 W RK80546PG0801M SL88J No No N/A

PPGA478 115 W RK80546PG0801M SL7KB No No N/A

PPGA478 84 W RK80546PG0801M SL7PM No No $97

Socket Step Step TDP Ordering Code Spec Code Low Halogen VT-x Recommended Channel Price

PPGA478 G1 84 W BX80546PG3000E SL8JZ No No N/A

PPGA478 E1 84 W BX80546PG3000E SL7PM No No N/A

PPGA478 C1 95 W BX80546PG3000E SL79L No No N/A

PPGA478 95 W BX80546PG3000E SL7E4 No No N/A

PPGA478 95 W BX80546PG3000E SL7KB No No N/A

PPGA478 115 W BX80546PG3000E SL88J No No N/A

Socket Step Step TDP Ordering Code Spec Code Low Halogen VT-x Recommended Channel Price

PLGA775 G1 84 W BX80547PG3000E SL9CB No No N/A

Socket Step Step TDP Ordering Code Spec Code Low Halogen VT-x Recommended Channel Price

PLGA775 D1 95 W BX80547PG3000E SL7J6 No No N/A

PLGA775 D1 95 W BX80547PG3000E SL7KK No No N/A

Socket Step Step TDP Ordering Code Spec Code Low Halogen VT-x Recommended Channel Price

PLGA775 84 W JM80547PG0801M SL7J6 No No N/A

Socket Step Step TDP Ordering Code Spec Code Low Halogen VT-x Recommended Channel Price

PLGA775 84 W BX80547PG3000ET SL7KK No No N/A

PLGA775 95 W BX80547PG3000ET SL7PU No No N/A

Compatible Products

Chipsets Intel® 865G Chipset (embedded) (Configurations: 2)

Embedded Intel® 865G chipset with 82801EB Embedded Intel® 865G chipset with 82801ER

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Intel®

910GL

Express

Chipset

(Configurations: 2)

Intel® 915G Express Chipset (Configurations: 2)

Intel® 915GL Express Chipset (Configurations: 2)

Intel® 915GV Express Chipset (Configurations: 2)

Intel® 915P Express Chipset (Configurations: 2)

Intel® 915PL Express Chipset (Configurations: 2)

Intel® 945G Express Chipset (Configurations: 2)

Intel® 945GZ Express Chipset (Configurations: 2)

Intel® 945P Express Chipset (Configurations: 2)

Intel® 945PL Express Chipset (Configurations: 2)

I/O Controller Hub 5 (ICH5)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 99.3W

I/O Controller Hub 5 R (ICH5R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 99.3W

Intel® 910GL Express Chipset with 82801FB

I/O Controller Hub 6 (ICH6)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 100.3W

Intel® 910GL Express Chipset with 82801FR

I/O Controller Hub 6 (ICH6R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915G Express Chipset with 82801FB

I/O Controller Hub 6 (ICH6)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915G Express Chipset with 82801FR

I/O Controller Hub 6 (ICH6R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915GL Express Chipset with 82801FB

I/O Controller Hub 6 (ICH6)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915GL Express Chipset with 82801FR

I/O Controller Hub 6 (ICH6R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915GV Express Chipset with 82801FB

I/O Controller Hub 6 (ICH6)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915GV Express Chipset with 82801FR

I/O Controller Hub 6 (ICH6R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915P Express Chipset with 82801FB I/O

Controller Hub 6 (ICH6)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915P Express Chipset with 82801FR

I/O Controller Hub 6 (ICH6R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915PL Express Chipset with 82801FB

I/O Controller Hub 6 (ICH6)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 915PL Express Chipset with 82801FR

I/O Controller Hub 6 (ICH6R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 104.1W

Intel® 945G Express Chipset with 82801GB

I/O Controller Hub 7 (ICH7)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 109.5W

Intel® 945G Express Chipset with 82801GR

I/O Controller Hub 7 (ICH7R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 109.5W

Intel® 945GZ Express Chipset with 82801GB

I/O Controller Hub 7 (ICH7)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 109.5W

Intel® 945GZ Express Chipset with 82801GR

I/O Controller Hub 7 (ICH7R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 109.5W

Intel® 945P Express Chipset with 82801GB

I/O Controller Hub 7 (ICH7)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 102.5W

Intel® 945P Express Chipset with 82801GR

I/O Controller Hub 7 (ICH7R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 102.5W

Intel® 945PL Express Chipset with 82801GB

I/O Controller Hub 7 (ICH7)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 102.5W

Intel® 945PL Express Chipset with 82801GR

I/O Controller Hub 7 (ICH7R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 102.5W

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Intel®

946GZ Express Chipset (Configurations: 3)

Intel® 946PL Express Chipset (Configurations: 3)

Intel® G965 Express Chipset (Configurations: 3)

Intel® P965 Express Chipset (Configurations: 3)

Intel® Q963 Express Chipset (Configurations: 2)

Intel® Q965 Express Chipset (Configurations: 3)

Intel® 946GZ Express Chipset with 82801GB

I/O Controller Hub 7 (ICH7)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 113.3W

Intel® 946GZ Express Chipset with 82801GDH

I/O Controller Hub 7 (ICH7DH)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 113.3W

Intel® 946GZ Express Chipset with 82801GR

I/O Controller Hub 7 (ICH7R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 113.3W

Intel® 946PL Express Chipset with 82801GB

I/O Controller Hub 7 (ICH7)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 103.3W

Intel® 946PL Express Chipset with 82801GDH

I/O Controller Hub 7 (ICH7DH)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 103.3W

Intel® 946PL Express Chipset with 82801GR

I/O Controller Hub 7 (ICH7R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 103.3W

Intel® G965 Express Chipset with 82801HB

I/O Controller Hub (ICH8)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 115.7W

Intel® G965 Express Chipset with 82801HH

I/O Controller Hub (ICH8DH)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 115.7W

Intel® G965 Express Chipset with 82801HR

I/O Controller Hub (ICH8R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 115.7W

Intel® P965 Express Chipset with 82801HB

I/O Controller Hub 8 (ICH8)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 106.7W

Intel® P965 Express Chipset with 82801HH

I/O Controller Hub 8 (ICH8DH)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 106.7W

Intel® P965 Express Chipset with 82801HR

I/O Controller Hub 8 (ICH8R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 106.7W

Intel® Q963 Express Chipset with 82801HB

I/O Controller Hub (ICH8)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 115.7W

Intel® Q963 Express Chipset with 82801HR

I/O Controller Hub (ICH8R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 115.7W

Intel® Q965 Express Chipset with 82801HB

I/O Controller Hub 8 (ICH8)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 115.7W

Intel® Q965 Express Chipset with 82801HO

I/O Controller Hub 8 (ICH8DO)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 115.7W

Intel® Q965 Express Chipset with 82801HR

I/O Controller Hub 8 (ICH8R)

# of CPUs: 1

Embedded: No

System Price: N/A

System TDP: 115.7W

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Block Diagrams

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Disclaimers

“

Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC

manufacturer on whether your system delivers Execute Disable Bit functionality.

64-bit computing on Intel® architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel®

64 architecture. Processors will not operate (including 32-bit operation) without an Intel 64 architecture-enabled BIOS. Performance will vary depending on your hardware

and software configurations. Consult with your system vendor for more information.

Hyper-Threading Technology (HT Technology) requires a computer system with an Intel® processor supporting HT Technology and an HT Technology enabled chipset,

BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See www.intel.com/products/ht/hyperthreading_more.htm for

more information including details on which processors support HT Technology.

Intel® Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software,

enabled for it. Functionality, performance or other benefit will vary depending on hardware and software configurations. Intel Virtualization Technology-enabled VMM

applications are currently in development.

Note: Prices subject to change without notice. Prices are for direct Intel customers in 1000-unit bulk quantities and, unless specified, represent the latest technolo

y versions

of the products. Taxes and shipping, etc. not included. Prices may vary for other package types and shipment quantities, and special promotional arrangements may apply.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families.

See http://www.intel.com/products/processor_number for details.

System and Maximum TDP is based on worst case scenarios. Actual TDP may be lower if not all I/Os for chipsets are used.

ll information provided is sub

ect to chan

e at any time, withou

notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any

time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever re

ardin

accuracy of the information,

nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or

systems.

Low Halogen implies the following:

Bromine and/or chlorine in materials that may be used during processing, but do not remain within the final product are not included in this definition. The halogens fluorine

(F), iodine (I), and astatine (At) are not restricted by this standard.

“

BFR/CFR and PVC-Free” Definition: :

ll PCB laminates must meet Br and Cl requirements for low halogen as defined in IPC-4101B

For components other than PCB laminates, all homogeneous materials must contain < 900 ppm (0.09%) of Bromine [if the Bromine (Br) source

is from BFRs] and < 900 ppm (0.09%) of Chlorine [if the Chlorine (Cl) source is from CFRs or PVC. Higher concentrations of Br and Cl are

allowed in homogenous materials of components other than PCB laminates as long as their sources are not BFRs, CFRs, PVC.

lthough the elemental analysis for Br and Cl in homogeneous materials can be performed by any analytical method with sufficient sensitivity

and selectivity, the presence or absence of BFRs, CFRs or PVC must be verified by any acceptable analytical techniques that allow for the

unequivocal identification of the specific Br or Cl compounds, or by appropriate material declarations agreed to between customer and supplier.

Max Turbo Frequency refers to the maximum single-core frequency that can be achieved with Intel® Turbo Boost Technology, which requires a PC with a processor with

Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software, and overall system configuration. Check with

your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. See www.intel.com/technology/turboboost/ for more information.

Some products can support AES New Instructions with a Processor Configuration update, in particular, i7-2630QM/i7-2635QM, i7-2670QM/i7-2675QM, i5-2430M/i5-2435M,

i5-2410M/i5-2415M. Please contact OEM for the BIOS that includes the latest Processor configuration update.

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