1. General description
The 74LVC1G99 provides a low voltage, ultra-configurable, multiple function gate with
3-state output. The device can be configured as one of several logic functions including,
AND, OR, NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components
are required to configure the device as all inputs can be connected directly to VCC or
GND. The 3-state output is controlled by the output enable input (OE). A HIGH level at OE
causes the outp u t (Y) to assume a high-im ped a nce OFF-state. When OE is LOW, the
output stat e is determ ined by the signals applied to the Schmitt trig ger input s (A, B, C and
D).
Due to the use of Schm itt trig g er inpu ts the device is tolerant of slowly changing input
signals, transforming them into sharply defined, jitter free output signals. By eliminating
leakage current paths to VCC and GND, the inputs and disabled output are also
over-voltage tolerant, making the device suitable for mixed-voltage applications.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the outp u t, pr eve n tin g the damaging backflow current through
the device when it is powered down.
The 74LVC1G99 is fully specified over the supply range from 1.65 V to 5.5 V.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -A ex ce ed s 200 V
±24 mA output drive (VCC =3.0V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °Cto+85 °C and −40 °C to +125 °C.
74LVC1G99
Ultra-configurable multiple function gate; 3-state
Rev. 7 — 22 June 2012 Product data sheet
74LVC1G99 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 22 June 2012 2 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC1G99DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm SOT505-2
74LVC1G99GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1
74LVC1G99GF −40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 ×1×0.5 mm SOT1089
74LVC1G99GD −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm SOT996-2
74LVC1G99GM −40 °C to +125 °C XQFN8 plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 ×1.6 ×0.5 mm SOT902-2
74LVC1G99GN −40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2 ×1.0 ×0.35 mm SOT1116
74LVC1G99GS −40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 ×1.0 ×0.35 mm SOT1203
Table 2. Mark ing codes
Type number Marking code[1]
74LVC1G99DP V99
74LVC1G99GT V99
74LVC1G99GF YF
74LVC1G99GD V99
74LVC1G99GM V99
74LVC1G99GN YF
74LVC1G99GS YF
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Product data sheet Rev. 7 — 22 June 2012 3 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
5. Functional diagram
6. Pinning information
6.1 Pinning
Fig 1. Logic symbol
001aah322
OE
A
BY
C
D
Fig 2. Pin configuration SOT505-2 Fig 3. Pin configuration SOT833-1, SOT1089,
SOT111 6 and SOT1203
74LVC1G99
OE VCC
AY
BD
GND C
001aah323
1
2
3
4
6
5
8
7
74LVC1G99
D
Y
V
CC
C
B
A
OE
GND
001aah324
36
27
18
45
Transparent top view
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Product data sheet Rev. 7 — 22 June 2012 4 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
6.2 Pin description
Fig 4. Pin configuration SOT996-2 Fig 5. Pin configuration SOT902 -2
001aal775
74LVC1G99
Transparent top view
8
7
6
5
1
2
3
4
OE
A
B
GND
VCC
Y
D
C
001aah325
AD
OE
VCC
B
Y
GND
C
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74LVC1G99
Table 3. Pin description
Symbol Pin Description
SOT505-2, SOT833-1, SOT1089,
SOT111 6, SOT1203 and SOT996-2 SOT902-2
OE 1 7 output enable inpu t OE (active LOW)
A 2 6 data input
B 3 5 data input
GND 4 4 ground (0 V)
C 5 3 data input
D 6 2 data input
Y 7 1 data output
VCC 8 8 supply voltage
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Product data sheet Rev. 7 — 22 June 2012 5 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Table 4. Function table[1]
Input Output
OE DCBAY
LLLLLL
LLLLHH
LLLHLL
LLLHHH
LLHLLL
LLHLHL
LLHHLH
LLHHHH
LHLLLH
LHLLHL
LHLHLH
LHLHHL
LHHLLH
LHHLHH
LHHHLL
LHHHHL
HXXXXZ
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Product data sheet Rev. 7 — 22 June 2012 6 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
7.1 Logic configurations
7.2 3-state buffer functions available
[1] H = HIGH voltage level;
L = LOW voltage level.
Table 5. Function selection table
Primary function Complementary function
3-state buffer
3-state inverter
3-state 2-input multiplexer
3-state 2-input multiplexer with inverting output
3-state 2-input AND 3-state 2-input NOR with two inverting inputs
3-state 2-input AND with one inverting input 3-state 2-input NOR with one inverting input
3-state 2-input AND with two inverting inputs 3-state 2-input NOR
3-state 2-input NAND 3-state 2-input OR with two inverting inputs
3-state 2-input NAND with one inverting input 3-state 2-input OR with one inverting input
3-state 2-input NAND with two inverting inputs 3-state 2-input OR
3-state 2-input XOR
3-state 2-input XNOR 3-state 2-input XOR with one inverting input
Table 6. Function table[1]
See Figure 6.
Function Input
OE ABCD
3-state buffer L input H or L L L
L H or L input H L
LLHinputL
LHLinputH
L H H or L L input
L H or L L H input
LLLH or Linput
Fig 6. 3-state buffer fun ction
001aah326
OE
input Y
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Product data sheet Rev. 7 — 22 June 2012 7 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
7.3 3-state inverter functions availa ble
[1] H = HIGH voltage level;
L = LOW voltage level.
X = don’t care.
7.4 3-state multiplexer functions available
[1] H = HIGH voltage level;
L = LOW voltage level.
Table 7. Function table[1]
See Figure 7.
Function Input
OE ABCD
3-state inverter L input H or L L H
L X input H H
LLHinputH
LHLinputL
L H H or L L input
L H or L H H input
L H H H or L input
Fig 7. 3-state inver ter fun ction
001aah327
OE
input Y
Table 8. Function table[1]
See Figure 8.
Function Input
OE ABCD
3-state 2-input
multiplexer L input 1 input 2 input 1 or input 2 L
L input 2 input 1 input 2 or input 1 L
L input 1 input 2 input 1 or input 2 H
L input 2 input 1 input 2 or input 1 H
Fig 8. 3-state 2-input m ultiplexer functio n
OE
input 1
input 2
A/B
Y
OE
input 1
001aah328
input 2
A/B
Y
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Product data sheet Rev. 7 — 22 June 2012 8 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
7.5 3-state AND/NOR functions available
[1] H = HIGH voltage level;
L = LOW voltage level.
[1] H = HIGH voltage level;
L = LOW voltage level.
Table 9. Function table[1]
See Figure 9.
Number of inputs Function Input
AND/NAND OR/NOR OE ABCD
2 3-state AND 3-state NOR L L input 1 input 2 L
2 3-state AND 3-state NOR L L input 2 input 1 L
Fig 9. 3-state AND/NOR function
Table 10 . Function table[1]
See Figure 10.
Number of inputs Function Input
AND/NAND OR/NOR OE ABCD
2 3-state AND 3-state NOR L input 2 L input 1 L
2 3-state AND 3-state NOR L H input 1 input 2 H
Fig 10. 3-state AND/NOR function
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Product data sheet Rev. 7 — 22 June 2012 9 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
[1] H = HIGH voltage level;
L = LOW voltage level.
[1] H = HIGH voltage level;
L = LOW voltage level.
Tabl e 11. Function table[1]
See Figure 11.
Number of inputs Function Input
AND/NAND OR/NOR OE ABCD
2 3-state AND 3-state NOR L input 1 L input 2 L
2 3-state AND 3-state NOR L H input 2 input 1 H
Fig 11. 3-state AND/NOR function
Table 12 . Function table[1]
See Figure 12.
Number of inputs Function Input
AND/NAND OR/NOR OE ABCD
2 3-state AND 3-state NOR L input 1 H input 2 L
2 3-state AND 3-state NOR L input 2 H input 1 L
Fig 12. 3-state AND/NOR function
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Product data sheet Rev. 7 — 22 June 2012 10 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
7.6 3-state NAND/OR functions available
[1] H = HIGH voltage level;
L = LOW voltage level.
[1] H = HIGH voltage level;
L = LOW voltage level.
Table 13 . Function table[1]
See Figure 13.
Number of inputs Function Input
AND/NAND OR/NOR OE ABCD
2 3-state NAND 3-state OR L L input 1 input 2 H
2 3-state NAND 3-state OR L L input 2 input 1 H
Fig 13. 3-state NAND/OR function
Table 14 . Function table[1]
See Figure 14.
Number of inputs Function Input
AND/NAND OR/NOR OE ABCD
2 3-state NAND 3-state OR L input 2 L inp ut 1 H
2 3-state NAND 3-state OR L H input 1 input 2 L
Fig 14. 3-state NAND/OR function
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Product data sheet Rev. 7 — 22 June 2012 11 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
[1] H = HIGH voltage level;
L = LOW voltage level.
[1] H = HIGH voltage level;
L = LOW voltage level.
Table 15 . Function table[1]
See Figure 15.
Number of inputs Function Input
AND/NAND OR/NOR OE ABCD
2 3-state NAND 3-state OR L input 1 L inp ut 2 H
2 3-state NAND 3-state OR L H input 2 input 1 L
Fig 15. 3-state AND/NOR function
Table 16 . Function table[1]
See Figure 16.
Number of inputs Function Input
AND/NAND OR/NOR OE ABCD
2 3-state NAND 3-state OR L input 1 H inp ut 2 L
2 3-state NAND 3-state OR L input 2 H inp ut 1 L
Fig 16. 3-state AND/NOR function
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Product data sheet Rev. 7 — 22 June 2012 12 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
7.7 3-st ate XOR/XNOR functions available
[1] H = HIGH voltage level;
L = LOW voltage level.
[1] H = HIGH voltage level;
L = LOW voltage level.
Table 17 . Function table[1]
See Figure 17.
Function Input
OE ABCD
3-state XOR L input 1 H or L L input 2
L input 2 H or L L input 1
L H or L input 1 H input 2
L H or L input 2 H input 1
L L H input 1 input 2
L L H input 2 input 1
Fig 17. 3-state XOR function
001aah337
OE
input 1
input 2
Y
Table 18 . Function table[1]
See Figure 18.
Function Input
OE ABCD
3-state XOR L H L input 1 input 2
Fig 18. 3-state XOR function
001aah338
OE
input 1
input 2
Y
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Product data sheet Rev. 7 — 22 June 2012 13 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
[1] H = HIGH voltage level;
L = LOW voltage level.
[1] H = HIGH voltage level;
L = LOW voltage level.
Table 19 . Function table[1]
See Figure 19.
Function Input
OE ABCD
3-state XOR L H L input 1 input 2
Fig 19. 3-state XOR function
001aah339
OE
input 1
input 2
Y
Table 20 . Function table[1]
See Figure 20.
Function Input
OE ABCD
3-state XNOR L H L input 1 input 2
L H L input 2 input 1
Fig 20. 3-state XNOR function
001aah340
OE
input 1
input 2
Y
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Product data sheet Rev. 7 — 22 June 2012 14 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in nor mal operation.
[3] For TSSOP8 package: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 21. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +6.5 V
IIK input clamping current VI < 0 V −50 - mA
VIinput voltage [1] −0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - ±50 mA
VOoutput voltage Active mode [1][2] −0.5 VCC + 0.5 V
Power-down mode [1][2] −0.5 +6.5 V
IOoutput current VO = 0 V to VCC -±50 mA
ICC supply current - 100 mA
IGND ground current −100 - mA
Ptot total power dissipation Tamb =−40 °C to +125 °C[3] - 250 mW
Tstg storage temp erature −65 +150 °C
Tabl e 22. Operating con ditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 1.65 5.5 V
VIinput voltage 0 5.5 V
VOoutput voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 5.5 V
Tamb ambient temperature −40 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V
VCC = 2.7 V to 4.5 V - 10 ns/V
VCC = 4.5 V to 5.5 V - 5 ns/V
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Product data sheet Rev. 7 — 22 June 2012 15 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
10. Static characteristics
Table 23 . Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb =−40 °C to +85 °C
VOH HIGH-level output voltage VI=V
T+ or VT−
IO=−100 μA; VCC = 1.65 V to 5.5 V VCC −0.1 - - V
IO=−4mA; V
CC = 1.65 V 1.2 - - V
IO=−8mA; V
CC = 2.3 V 1.9 - - V
IO=−12 mA; VCC = 2.7 V 2.2 - - V
IO=−24 mA; VCC = 3.0 V 2.3 - - V
IO=−32 mA; VCC = 4.5 V 3.8 - - V
VOL LOW-level output voltage VI=V
T+ or VT−
IO=100μA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO=4mA; V
CC = 1.65 V - - 0.45 V
IO=8mA; V
CC = 2.3 V - - 0.3 V
IO=12mA; V
CC = 2.7 V - - 0.4 V
IO=24mA; V
CC = 3.0 V - - 0.55 V
IO=32mA; V
CC = 4.5 V - - 0.55 V
IIinput leakage current VCC = 0 V to 5.5 V; VI=5.5VorGND - ±0.1 ±5μA
IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL;
VO= 5.5 Vor GND -±0.1 ±10 μA
IOFF power-off leakage current VCC = 0 V; VIor VO=5.5V - ±0.1 ±10 μA
ICC supply current VCC = 1.65 V to 5.5 V;
VI= 5.5 Vor GND; IO=0A -0.110μA
ΔICC additional supply current per pin; VCC = 2.3 V to 5.5 V;
VI=V
CC −0.6 V; IO=0 A -5500μA
CIinput capacitance VCC = 3.3 V; VI = GND to VCC -2.5-pF
Tamb =−40 °C to +125 °C
VOH HIGH-level output voltage VI=V
T+ or VT−
IO=−100 μA; VCC = 1.65 V to 5.5 V VCC −0.1 - - V
IO=−4mA; V
CC = 1.65 V 0.95 - - V
IO=−8mA; V
CC = 2.3 V 1.7 - - V
IO=−12 mA; VCC = 2.7 V 1.9 - - V
IO=−24 mA; VCC = 3.0 V 2.0 - - V
IO=−32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-level output voltage VI=V
T+ or VT−
IO=100μA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO=4mA; V
CC = 1.65 V - - 0.70 V
IO=8mA; V
CC = 2.3 V - - 0.45 V
IO=12mA; V
CC = 2.7 V - - 0.60 V
IO=24mA; V
CC = 3.0 V - - 0.80 V
IO=32mA; V
CC = 4.5 V - - 0.80 V
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Product data sheet Rev. 7 — 22 June 2012 16 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
[1] All typical values are measured at VCC = 3.3 V and Tamb =25°C.
11. Dynamic characteristics
IIinput leakage current VCC = 0 V to 5.5 V; VI=5.5VorGND - - ±100 μA
IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL;
VO= 5.5 Vor GND --±200 μA
IOFF power-off leakage current VCC = 0 V; VIor VO=5.5V - - ±200 μA
ICC supply current VCC = 1.65 V to 5.5 V;
VI= 5.5 Vor GND; IO=0A --200μA
ΔICC additional supply current per pin; VCC = 2.3 V to 5.5 V;
VI=V
CC −0.6 V; IO=0 A - - 5000 μA
Table 23 . Static characteristics …continued
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Table 24. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 23.
Symbol Parameter Conditions 25 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
(85 °C) Max
(125 °C)
tpd propagation delay A to Y; see Figure 21 [2]
VCC = 1.65 V to 1.95 V - 7.5 - 2.8 30.8 38.5 ns
VCC = 2.3 V to 2.7 V - 5.0 - 2.0 11.7 14.6 ns
VCC = 2.7 V - 5.4 - 2.0 9.0 11.3 ns
VCC = 3.0 V to 3.6 V - 4.5 - 1.8 8.4 10.5 ns
VCC = 4.5 V to 5.5 V - 3.8 - 1.8 5.5 6.9 ns
B to Y; see Figure 21 [2]
VCC = 1.65 V to 1.95 V - 7.5 - 2.8 28.9 36.2 ns
VCC = 2.3 V to 2.7 V - 5.0 - 2.0 11.3 14.2 ns
VCC = 2.7 V - 5.4 - 2.0 9.0 11.3 ns
VCC = 3.0 V to 3.6 V - 4.5 - 1.8 8.2 10.3 ns
VCC = 4.5 V to 5.5 V - 3.8 - 1.8 5.4 6.8 ns
C to Y; see Figure 21 [2]
VCC = 1.65 V to 1.95 V - 7.8 - 3.2 29.8 37.3 ns
VCC = 2.3 V to 2.7 V - 5.2 - 2.3 12.3 15.4 n s
VCC = 2.7 V - 5.3 - 2.3 9.6 12.0 ns
VCC = 3.0 V to 3.6 V - 4.6 - 2.3 8.6 10.8 ns
VCC = 4.5 V to 5.5 V - 3.8 - 1.8 5.7 7.2 ns
D to Y; see Figure 21 [2]
VCC = 1.65 V to 1.95 V - 7.0 - 2.8 25.7 32.2 ns
VCC = 2.3 V to 2.7 V - 4.6 - 2.0 10.7 13.4 n s
VCC = 2.7 V - 4.8 - 2.0 9.2 11.5 ns
VCC = 3.0 V to 3.6 V - 4.1 - 1.8 7.6 9.5 ns
VCC = 4.5 V to 5.5 V - 3.4 - 1.6 5.2 6.5 ns
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Product data sheet Rev. 7 — 22 June 2012 17 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] ten is the same as tPZH and tPZL.
[4] tdis is the same as tPHZ and tPLZ.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of the outputs.
ten enable time OE to Y; see Figure 22 [3]
VCC = 1.65 V to 1.95 V - 5.7 - 2.0 25.2 32.0 ns
VCC = 2.3 V to 2.7 V - 3.8 - 1.4 11.3 14.0 ns
VCC = 2.7 V - 4.2 - 1.4 8.6 11.0 ns
VCC = 3.0 V to 3.6 V - 3.5 - 1.4 7.0 9.0 ns
VCC = 4.5 V to 5.5 V - 2.7 - 1.4 4.7 6.0 ns
tdis disable time OE to Y; see Figure 22 [4]
VCC = 1.65 V to 1.95 V - 5.7 - 3.0 15.0 19.0 ns
VCC = 2.3 V to 2.7 V - 3.6 - 2.0 5.8 7.3 ns
VCC = 2.7 V - 4.5 - 2.0 6.6 8 .2 ns
VCC = 3.0 V to 3.6 V - 4.5 - 2.1 5.9 7.4 ns
VCC = 4.5 V to 5.5 V - 3.4 - 1.0 4.5 5.6 ns
CPD power dissipation
capacitance per buffer (output enabled);
fi = 10 MHz; CL = 50 pF;
VI= GND to VCC
[5]
VCC = 1.65 V to 1.95 V - 14 - - - - pF
VCC = 2.3 V to 2.7 V - 1 6 - - - - pF
VCC = 2.7 V - 18 - - - - pF
VCC = 3.0 V to 3.6 V - 25 - - - - pF
VCC = 4.5 V to 5.5 V - 30 - - - - pF
Table 24. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 23.
Symbol Parameter Conditions 25 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
(85 °C) Max
(125 °C)
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Product data sheet Rev. 7 — 22 June 2012 18 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
12. Waveforms
Measurement points are given in Table 25.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 21. The data input (A, B, C, D) to output (Y) propagation delays
001aah341
t
PLH
t
PHL
t
PHL
V
M
V
M
V
M
V
M
V
M
V
I
GND
A, B, C, D input
Y output
Y output
V
OH
V
OL
V
OH
V
OL
V
M
t
PLH
Measurement points are given in Table 25.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 22. 3-st ate enable and disable times
mna644
t
PLZ
t
PHZ
outputs
disabled outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
I
V
OL
V
OH
V
CC
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
Table 25 . Mea surement points
Supply voltage Input Output
VCC VMVMVXVY
1.65 V to 1.95 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V
2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V
2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V
3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V
4.5 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V
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Product data sheet Rev. 7 — 22 June 2012 19 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
13. Transfer characteristics
Test data is given in Table 26.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 23. Test circuit for measuring switching times
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Table 26 . Test data
Supply voltage Input Load VEXT
VItr = tfCLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
1.65 V to 1.95 V VCC ≤2.0 ns 30 pF 1 kΩopen GND 2VCC
2.3 V to 2.7 V VCC ≤2.0 ns 30 pF 500 Ωopen GND 2VCC
2.7 V 2.7 V ≤2.5 ns 50 pF 500 Ωopen GND 6 V
3.0 V to 3.6 V 2.7 V ≤2.5 ns 50 pF 500 Ωopen GND 6 V
4.5 V to 5.5 V VCC ≤2.5 ns 50 pF 500 Ωopen GND 2VCC
Table 27 . Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 23
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
VT+ positive-going
threshold voltage see Figure 24, Figure 25,
Figure 26, Figure 27 and
Figure 28
VCC = 1.8 V 0.70 1.02 1.20 0.67 1.20 V
VCC = 2.3 V 1.11 1.42 1.60 1.08 1.60 V
VCC = 3.0 V 1.50 1.79 2.00 1.47 2.00 V
VCC = 4.5 V 2.16 2.52 2.74 2.13 2.74 V
VCC = 5.5 V 2.61 2.99 3.33 2.58 3.33 V
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Product data sheet Rev. 7 — 22 June 2012 20 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
[1] All typical values are measured at Tamb = 25 °C
14. Waveforms transfer characteristics
VT−negative-going
threshold voltage see Figure 24, Figure 25,
Figure 26, Figure 27 and
Figure 28
VCC = 1.8 V 0.30 0.53 0.72 0.30 0.75 V
VCC = 2.3 V 0.58 0.77 1.00 0.58 1.03 V
VCC = 3.0 V 0.80 1.04 1.30 0.80 1.33 V
VCC = 4.5 V 1.21 1.55 1.90 1.21 1.93 V
VCC = 5.5 V 1.45 1.86 2.29 1.45 2.32 V
VHhysteresis voltage (VT+ −VT−); see Figure 24,
Figure 25, Figure 26,
Figure 27 and Figure 28
VCC = 1.8 V 0.30 0.48 0.62 0.23 0.62 V
VCC = 2.3 V 0.40 0.64 0.80 0.34 0.80 V
VCC = 3.0 V 0.50 0.75 1.00 0.44 1.00 V
VCC = 4.5 V 0.71 0.97 1.20 0.65 1.20 V
VCC = 5.5 V 0.71 1.13 1.40 0.65 1.40 V
Table 27 . Transfer characteristics …continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 23
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
Fig 24. Transfer characteristic Fig 25. Definition of VT+, VT− and VH
mna207
VO
VI
VHVT+
VT−
mna208
V
O
V
I
V
H
V
T+
V
T−
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Product data sheet Rev. 7 — 22 June 2012 21 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
Fig 26. Transfer characteristic Fig 27. Definition of VT+, VT− and VH
mnb154
VO
VHVI
VT+
VT−
mnb155
V
O
V
I
V
H
V
T+
V
T−
Fig 28. Typical 74LVC1G99 transfer characteristic; VCC =3.0V
001aab594
VI (V)
0321
8
4
12
16
ICC
(mA)
0
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Product data sheet Rev. 7 — 22 June 2012 22 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
15. Package outline
Fig 29. Package outline SOT505-2 (TSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.95
0.75 0.38
0.22 0.18
0.08 3.1
2.9 3.1
2.9 0.65 4.1
3.9 0.70
0.35 8°
0°
0.13 0.10.20.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2 - - - 02-01-16
wM
bp
D
Z
e
0.25
14
85
θ
A2A1
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
1.1
pin 1 index
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Product data sheet Rev. 7 — 22 June 2012 23 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
Fig 30. Package outline SOT833-1 (XSON8)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT833-1 - - -
MO-252
- - -
SOT833-1
07-11-14
07-12-07
DIMENSIONS (mm are the original dimensions)
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17 2.0
1.9 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
8
2
7
3
6
4
5
8×
(2)
4×
(2)
A
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Product data sheet Rev. 7 — 22 June 2012 24 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
Fig 31. Package outline SOT1089 (XSON8)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1089 MO-252
sot1089_po
10-04-09
10-04-12
Unit
mm max
nom
min
0.5 0.04 1.40
1.35
1.30
1.05
1.00
0.95 0.55 0.35 0.35
0.30
0.27
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm SOT1089
A1bL
1
0.40
0.35
0.32
0.20
0.15
0.12
DEee
1L
0 0.5 1 mm
scale
terminal 1
index area
E
D
detail X
A
A1
L
L1
b
e1
e
terminal 1
index area
1
4
8
5
(4×)(2)
(8×)(2)
X
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Product data sheet Rev. 7 — 22 June 2012 25 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
Fig 32. Package outline SOT996-2 (XSON8U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT996-2 - - -- - -
SOT996-2
07-12-18
07-12-21
UNIT A
max
mm 0.5 0.05
0.00 0.35
0.15 3.1
2.9 0.5 1.5 0.5
0.3 0.6
0.4 0.1 0.05
A1
DIMENSIONS (mm are the original dimensions)
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
0 1 2 mm
scale
b D
2.1
1.9
E e e1L L1
0.15
0.05
L2v w
0.05
y y1
0.1
C
y
C
y1
X
b
14
85
e1
eAC B
vMCw M
L2
L1
L
terminal 1
index area
B A
D
E
detail X
AA1
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Product data sheet Rev. 7 — 22 June 2012 26 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
Fig 33. Package outline SOT902-2 (XQFN8)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT902-2 - - -
MO-255
- - -
sot902-2_po
10-11-02
11-03-31
Unit(1)
mm max
nom
min
0.5 0.05
0.00
1.65
1.60
1.55
1.65
1.60
1.55 0.55 0.5 0.15
0.10
0.05 0.1 0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2
A1b
0.25
0.20
0.15
DEee
1L
0.35
0.30
0.25
L1vw
0.05
yy
1
0.05
0 1 2 mm
scale
terminal 1
index area
BA
D
E
X
C
y
C
y1
terminal 1
index area
3
L
L1
b
e1
eAC B
vCw
2
1
5
6
7
metal area
not for soldering
8
4
A1
A
detail X
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Product data sheet Rev. 7 — 22 June 2012 27 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
Fig 34. Package outline SOT1116 (XSON8)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1116
sot1116_po
10-04-02
10-04-07
Unit
mm max
nom
min
0.35 0.04 1.25
1.20
1.15
1.05
1.00
0.95 0.55 0.3 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2) A1A
e1e1e1
e
L
L1
b
4321
5678
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Product data sheet Rev. 7 — 22 June 2012 28 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
Fig 35. Package outline SOT1203 (XSON8)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1203
sot1203_po
10-04-02
10-04-06
Unit
mm max
nom
min
0.35 0.04 1.40
1.35
1.30
1.05
1.00
0.95 0.55 0.35 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2)
A
A1
e
L
L1
b
e1e1e1
1
8
2
7
3
6
4
5
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Product data sheet Rev. 7 — 22 June 2012 29 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
16. Abbreviations
17. Revision history
Table 28 . Abbreviation s
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Dis charge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 29. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC1G99 v. 7 20120622 Product data sheet - 74LVC1G99 v.6
Modifications: •For type number 74LVC1G99GM the SOT code has changed to SOT902-2.
74LVC1G99 v. 6 20111201 Product data sheet - 74LVC1G99 v.5
Modifications: •Legal pages updated.
74LVC1G99 v. 5 20101021 Product data sheet - 74LVC1G99 v.4
74LVC1G99 v.4 20100416 Product data sheet - 74LVC1G99 v.3
74LVC1G99 v.3 20091203 Product data sheet - 74LVC1G99 v.2
74LVC1G99 v.2 20080208 Product data sheet - 74LVC1G99 v.1
74LVC1G99 v.1 20080103 Product data sheet - -
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Product data sheet Rev. 7 — 22 June 2012 30 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semicondu ctors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
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to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the applicatio n or use by custo mer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specif ication for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
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Product data sheet Rev. 7 — 22 June 2012 31 of 32
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automo tive use. It i s neit her qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC1G99
Ultra-configurable multiple function gate; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 June 2012
Document identifier : 74L VC1G99
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
20. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Logic configurations . . . . . . . . . . . . . . . . . . . . . 6
7.2 3-state buffer functions available . . . . . . . . . . . 6
7.3 3-state inverter functions avai lable. . . . . . . . . . 7
7.4 3-state multiplexer functions available . . . . . . . 7
7.5 3-state AND/NOR functions availab le. . . . . . . . 8
7.6 3-state NAND/OR functions available. . . . . . . 10
7.7 3-state XOR/XNOR functions available . . . . . 12
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
9 Recommended operating cond itions. . . . . . . 14
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 15
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 16
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13 Transfer characteristics . . . . . . . . . . . . . . . . . 19
14 Waveforms transfer charac teristics. . . . . . . . 20
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 29
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
19 Contact information. . . . . . . . . . . . . . . . . . . . . 31
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32