SC16C850IET,151 - NXP SEMICONDUCTORS

1. General description

The SC16C850 is a 2.5 V to 3.3 V, low power, single channel Universal Asynchronous

Receiver and Transmitter (UART) used for serial data communications. Its principal

function is to convert par allel data into serial data and vice versa. The UART can handle

serial data rates up to 5 Mbit/s. The SC16C850 is functionally (software) compatible with

the SC16C650B. SC16C85 0 can be programmed to operate in extended mode (see

Section 6.2) where additional advanced UART features are available. The SC16C850

UART provide s enhanced UAR T functions with 128-by te FIFOs, modem control interface ,

and IrDA encoder/decoder. On-board status registers provide the user with error

indications and oper ational st atus. System interrupts and modem control features may be

tailored by software to meet specific user requirements. An internal loopback capability

allows on-board diagnostics.

The SC16C850IBS with Intel (16 mode) or Motorola (68 mode) bus host interface

operates at 2.5 V to 3.3 V and is available in a very small (Micro-UART) HVQFN32

package.

The SC16C850IET with Intel (16 mode) bus host interface operates at 2.5 V to 3.3 V and

is available in a very small TFBGA36 package.

2. Features and benefits

Single channel high performance UART

Intel or Motorola bus inter fac e se lectable using 16/68 pin

2.5 V to 3.3 V operation

Up to 5 Mbit/s data rate

128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

128-byte receive FIFO with error flags to reduce the bandwidth requirement of the

external CPU

128 programmable Receive and Transmit FIFO interrupt trigger levels

128 Receive and Transmit FIFO reporting levels (level counters)

Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control

Industrial temperature range (−40 °C to +85 °C)

128 hardware and software trigger levels

Automatic 9-bit mode (RS-485) address detection

Automatic RS-485 driver turn-around with programmable delay

UART software reset

High resolution clock prescaler, from 0 to 15 with granularity of 1⁄16 to allow

non-st andard UART clock to be used

SC16C850

2.5 V to 3.3 V UART, 5 Mbit/s (max.) with 128-byte FIFOs,

infrared (IrDA), and 16 mode or 68 mode p arallel bus interface

Rev. 2 — 11 November 2010 Product data sheet

Product data sheet Rev. 2 — 11 November 2010 2 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Programmable Xon/Xoff characters

Software selectable baud rate generator

Support IrDA version 1.0 (up to 115.2 kbit/s)

Standard modem interface or infrared IrDA encoder/decoder interface

Enhanced Sleep mode and low power feature

Modem control functions (CTS, RTS, DSR, DTR, RI, CD)

Independent tran smitter and receiver enable/disable

Pb-free, RoHS compliant package offered

3. Ordering information

[1] SC16C850IBS/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.

Table 1. Ordering information

Type number Package

Name Description Version

SC16C850IBS HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 ×5×0.85 mm SOT617-1

SC16C850IBS/Q900 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 ×5×0.85 mm SOT617-1

SC16C850IET TFBGA36 plastic thin fine-pitch ball grid array package; 36 balls;

body 3.5 ×3.5 ×0.8 mm SOT912-1

Product data sheet Rev. 2 — 11 November 2010 3 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

4. Block diagram

Fig 1. Block diagram of SC16C850 (16 mode)

SC16C850

XTAL2XTAL1

D0 to D7

IOR

IOW

RESET

002aad020

DATA B U S

AND

CONTROL

LOGIC

SELECT

LOGIC

A0 to A2

INTERRUPT

CONTROL

LOGIC

INT CLOCK AND

BAUD RATE

GENERATOR

INTERCONNECT BUS LINES

AND

CONTROL SIGNALS

MODEM

CONTROL

LOGIC

DTR

RTS

CTS

DSR

RECEIVE

SHIFT

RECEIVE

FIFO

FLOW

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

TRANSMIT

SHIFT

TRANSMIT

FIFO

DECODER

ENCODER

POWER-DOWN

CONTROL

LOWPWR

Product data sheet Rev. 2 — 11 November 2010 4 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Fig 2. Block diagram of SC16C850 (68 mode)

SC16C850

XTAL2XTAL1

D0 to D7

R/W

RESET

002aad021

DATA B U S

AND

CONTROL

LOGIC

SELECT

LOGIC

A0 to A2

INTERRUPT

CONTROL

LOGIC

IRQ

CLOCK AND

BAUD RATE

GENERATOR

INTERCONNECT BUS LINES

AND

CONTROL SIGNALS

MODEM

CONTROL

LOGIC

DTR

RTS

CTS

DSR

RECEIVE

SHIFT

RECEIVE

FIFO

FLOW

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

TRANSMIT

SHIFT

TRANSMIT

FIFO

DECODER

ENCODER

POWER-DOWN

CONTROL

LOWPWR

Product data sheet Rev. 2 — 11 November 2010 5 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

5. Pinning information

5.1 Pinning

Fig 3. Pin configura tio n for TFBG A3 6

Transparent top view.

Fig 4. Ball mapping for TFBGA36

002aad02

SC16C850IET

Transparent top view

246135

ball A1

index area

VDD n.c. n.c. XTAL2

12345

A2 n.c. n.c. IOW LOWPWR

A0 VSS A1 VSS TXC

INT CTS VDD D7D

DTR n.c. CD D1 D3E

RESET DSR D0 D2F

RTS

002aad02

XTAL1

IOR

Product data sheet Rev. 2 — 11 November 2010 6 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

5.2 Pin description

a. 16 mode b. 68 mode

Fig 5. Pin configuration for HVQFN32

002aad02

Transparent top view

RX A0

D7 INT

D5 DTR

D4 CTS

LOWPWR

XTAL1

XTAL2

IOW

VSS

IOR

n.c.

VDD

DSR

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

RTS

RESET

SC16C850IBS

SC16C850IBS/Q900

(16 mode)

002aad02

Transparent top view

RX A0

D7 IRQ

D5 DTR

D4 CTS

LOWPWR

XTAL1

XTAL2

R/W

VSS

VDD

n.c.

VDD

DSR

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

RTS

RESET

SC16C850IBS

SC16C850IBS/Q900

(68 mode)

Table 2. Pin description

Symbol Pin Type Description

TFBGA36 HVQFN32

16/68 -2IBus select. Intel or Motorola bus select.

When 16/6 8 pin is at logic 1 or left unconnected (internally pulled-up) the

device will operate in Intel bus (16 mode) type of interface.

When 16/68 pin is at logic 0, the device will operate in Motorola bus (68 mode)

type of interface.

A0 C1 19 I Address 0 select bit. Internal register address selection.

A1 C3 18 I Address 1 select bit. Internal register address selection.

A2 B1 17 I Address 2 select bit. Internal register address selection.

CD E3 26 I Carrier Detect (active LOW). A logic 0 on this pin indicates that a carrier has

been detected by the modem. Status can be tested by reading MSR[7].

CS B6 8 I Chip Select (active LOW). In 16 mode or 68 mode, this input is chip select for

the UART.

CTS D3 24 I Clear to Send (active LOW). A logic 0 on the CTS pin indicates the modem

or data set is ready to accept transmit data from the SC16C850. S t atus can be

tested by read i n g MSR [4 ].

DSR F2 25 I Data Set Ready (active LOW). A logic 0 on this pin indicates the modem or

data set is powered-on and is ready for data exchange with the UART. Status

can be tested by reading MSR[5].

DTR E1 22 O Data Terminal Ready (active LOW). A logic 0 on this pin indicates that the

SC16C850 is powered-on and ready. This pin can be controlled via the

modem control register. Writing a logic 1 to MCR[0] will set the DTR output to

logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to

MCR[0], or after a reset.

Product data sheet Rev. 2 — 11 November 2010 7 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

D0 F4 29 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least

significant bit and the first data bit in a transmit or receive serial data stream.

D1 E4 30 I/O

D2 F5 31 I/O

D3 E5 32 I/O

D4 F6 1 I/O

D5 E6 3 I/O

D6 D6 4 I/O

D7 D5 5 I/O

INT

(IRQ)- 20 O When 16/6 8 pin is at logic 1 or unconnected, this output becomes active HIGH

interrupt output. The output state is defined by the user through the software

setting of MCR[5]. INT is set to the active mode when MCR[5] is set to a

logic 1. INT is set to the open-source mode when MCR[5] is set to a logic 0 .

When 16/6 8 pin is at logic 0, this output becomes device interrupt output

(active LOW, open-drain). An external pull-up resistor to VDD is required.

INT D1 - O Interrupt output (active HIGH). The output state is defined by the user

through the software setting of MCR[5]. INT is set to the active mode when

MCR[5] is set to a logic 1. INT is set to the open-source mode when MCR[5] is

set to a logic 0.

IOR

(VDD)-14IWhen 16/68 pin is at logic 1, this input becomes the read strobe (active LOW).

When 16/6 8 pin is at logic 0, this input pin is not used and should be

connected to VDD.

IOR A3 - I Read strobe (active LOW).

IOW

(R/W)- 1 2 I When 16 /68 pin is at logic 1 or unconnected, this input becomes the write

strobe (active LOW).

When 16/68 pin is at logic 0, this input becomes read strobe when it is at logic

HIGH, and write strobe when it is at logic LOW.

IOW B4 - I Write strobe (active LOW).

LOWPWR B5 9 I Low Power. When asserted (active HIGH), the device immediately goes into

low power mode. The oscillator is shut-off and some host interface pins are

isolated from the host’s bus to reduce power consumption. The device only

returns to normal mode when the LOWPWR pin is de-asserted . On the

negative edge of a de-asserting LOWP WR signal, the device is automatically

reset and all registers return to their default reset states. This pin has a 22 kΩ

internal pull-down resistor, therefore, it can be left unconnected (refer to

Section 6.12 “ Low power feature”).

RESET

(RESET)-23IMaster Reset. When 16/68 pin is at logic 1 or unconnected, this input

becomes the RESET pin (active HIGH).

When 16/68 pin is at logic LOW , this input pin becomes RESET (active LOW).

(See Section 7.23 “SC16C850 external reset condition and software reset” for

initialization details.)

RESET F1 - I Reset input (active HIGH). See Section 7.23 “SC16C850 external reset

condition and software reset” for initialization details.

RI F3 27 I Ring Indicator (active LOW). A logic 0 on this pin indicates the mo de m ha s

received a ringing signal from the telephone line. A logic 1 transition on this

input pin will generate an interrupt if modem status interrupt is enabled. S t atus

can be tested by reading MCR[6].

Table 2. Pin description …continued

Symbol Pin Type Description

TFBGA36 HVQFN32

Product data sheet Rev. 2 — 11 November 2010 8 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

[1] HVQFN32 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

RTS D2 21 O Request to Send (active LOW). A logic 0 on the RTS pin indicates the

transmitter has data ready and waiting to send. Writing a logic 1 in the modem

control register MCR[1] will set this pin to a logic 0, indicating data is available.

After a reset this pin will be set to a logic 1.

RX C6 6 I UART receive data. The RX signal will be a logic 1 during reset, idle (no

data), or when not receiving data. During the local loopback mode, the RX

input pin is disabled and TX data is connected to the UART RX input,

internally.

TX C5 7 O UART transmit data. The TX signal will be a logic 1 during reset, idle (no

data), or when the transmitter is disabled. During the local loopback mode, the

TX output pin is disabled and TX data is internally connected to the UART RX

input.

VDD A1, D4 28 I Power supply input.

VSS C2, C4 13[1] ISignal and power gro und.

XTAL1 A6 10 I Cryst al or external clock input. Functions as a crystal input or as an external

clock input. A crystal can be connected between this pin and XT AL2 to form an

internal oscillator circuit. Alternatively, an external clo ck can be connected to

this pin to provide custom data rates (see Section 6.9 “Programmable baud

rate generator”). See Figure 8.

XTAL2 A5 11 O Output of the crystal oscillator or buffered clock. (See al so XTAL1.)

Crystal oscillator output or buffered clock output. Should be left open if an

external clock is connected to XTAL1.

Table 2. Pin description …continued

Symbol Pin Type Description

TFBGA36 HVQFN32

Product data sheet Rev. 2 — 11 November 2010 9 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

6. Functional description

The SC16C850 provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orient ated protocol). Dat a integrity is ensured by att aching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex, especially

when manufactured on a single integrated silicon chip. The SC16C850 represents such

an integration with greatly enhanced features. The SC16C850 is fabricated with an

advanced CMOS process.

The SC16C850 is an upward solution to the SC16C650B that provides a single UART

capability with 128 bytes of transmit and receive FIFO memory, instead of 32 bytes for the

SC16C650B and 16 bytes in the SC16C550B. The SC16C850 is designed to work with

high speed modem s and shared network environments that require fast data processing

time. Increased performance is realized in the SC16C850 by the transmit and receive

FIFOs. This allows the external processor to ha ndle more networking tasks within a given

time. In addition, the four selectable receive and transmit FIFO trigger interrupt levels are

provided in 16C650 mode, or 128 programmable levels are provid ed in the extended

mode for maximum data throughput performance especially when operating in a

multi-channel en vironment (see Section 6.2 “Extended mode (128-byte FIFO)”). The FIFO

memory greatly reduces the bandwidth requirement of the external controlling CPU and

increases performance. A low power pin (LOWPWR) is provided to further reduce powe r

consumption by isolating the host bus interface.

The SC16C850 is cap able of operation up to 5 Mbit/s with a n external 80 MHz clock. With

a crystal, the SC16C850 is capable of operation up to 1.5 Mbit/s.

The rich feature set of the SC16C850 is available through internal re gisters. These

features are: selectable and programmable receive and transmit FIFO trigger levels,

selectable TX and RX baud rates, and modem interface controls, and are all standard

features. Following a power-on reset, an external reset, or a software reset, the

SC16C850 is software compatible with the previous generation, SC16C550B, and

SC16C650B.

6.1 UART selection

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC16C850 package, and an external serial device. A

logic 0 (LOW) on chip select pin CS allows the user to configure, send data, and/or

receive data via the UART. Refer to Table 3 and Table 4.

Table 3. Serial port selection (Intel interfac e)

H = HIGH; L = LOW.

Chip Select Function

CS = H none

CS = L UART select

Product data sheet Rev. 2 — 11 November 2010 10 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

6.2 Extended mode (128-byte FIFO)

The device is in the extended mode when any of these four registers contains any value

other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.

6.3 Internal registers

The SC16C850 provides a set of 25 internal registers for monitoring and controlling the

functions of the UART. These registers are shown in Table 5.

Table 4. Serial port selection (Motorola interface)

H = HIGH; L = LOW.

Chip Select Function

CS = H none

CS = L UART select

Table 5. Internal registers decoding

A2 A1 A0 Read mode Wr ite mod e

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, EFCR, SPR)[1]

000Receive Holding Register Transmit Holding Register

001Interrupt Enable Register Interrupt Enable Register

010Interrupt Status Register FIFO Control Register

011Line Control Register Line Control Register

100Modem Control Register Modem Control Register

101Line Status Register Extra Feature Control Register (EFCR)

110Modem Status Register n/a

111Scratchpad Register Scratchpad Register

Baud rate register set (DLL /DLM)[2]

000LSB of Divisor Latch LSB of Divisor Latch

001MSB of Divisor Latch MSB of Divisor Latch

Second special register set (TXLVLCNT/RXLVLCNT)[3]

011Transmit FIFO Level Count n/a

100Receive FIFO Level Count n/a

Enhanced feature register set (EFR, Xon1/Xon2, Xoff1/Xoff2)[4]

010Enhanced Feature Register Enhanced Feature Registe r

100Xon1 word Xon1 word

101Xon2 word Xon2 word

110Xoff1 word Xoff1 word

111Xoff2 word Xoff2 word

First extra feature reg is te r set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)[5]

010Transmit FIFO Interrupt Level Transmit FIFO Interrupt Level

100Receive FIFO Interrupt Level Receive FIFO Interrupt Level

110Flow Control Count High Flow Control Count High

111Flow Control Count Low Flow Control Count Low

Product data sheet Rev. 2 — 11 November 2010 11 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Second Special registers are accessible only when EFCR[0] = 1.

[4] Enhanced Feature Registers are only accessible when LCR = 0xBF.

[5] First Extra Feature Registers are only accessible when EFCR[2:1] = 01b.

[6] Second Extra Feature Registers are only accessible when EFCR[2:1] = 10b.

6.4 FIFO operation

6.4.1 32-byte FIFO mode

When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the

‘first extra feature register set’ are empty (0x00 ) the transmit and r eceive trigger levels a re

set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward

compatible to the SC16C650B (see Table 6), and the FIFO sizes are 32 entries. The

transmit and receive dat a FIF Os are enab led by th e FIFO Control Reg ister bit 0 (FCR[0]).

It should be noted that the user can set the transmit trigger levels by writing to the FCR,

but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section

includes a time-out function to ensure data is delivered to the external CPU (see

Section 6.8). Please refer to Table 11 and Table 12 for the setting of FCR[7:4].

6.4.2 128-byte FIFO mode

When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature

set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the

transmit FIFO , an d th e tra n s m it trigger levels can be set to any value between 1 and 128

with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive

trigger levels can be set to any value between 1 and 128 with granularity of 1.

When the effective FIFO size changes (that is, when FCR[0] toggles or when the

combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between

equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will

be lost).

Second extra feature reg ister set (CLKPRES, RS485TIME, AFCR2, AFCR1 )[6]

0 1 0 Clock Prescaler Clock Prescaler

100RS-485 turn-around Timer RS-485 turn-around Timer

110Additional Feature Contro l Register 2 Additional Feature Control Register 2

111Additional Feature Contro l Register 1 Additional Feature Control Register 1

Table 5. Internal registers decoding …continued

A2 A1 A0 Read mode Wr ite mod e

Table 6. Interrupt trigger level and flo w contro l mechanism

FCR[7:6] FCR[5:4] INT pin activation Negate R T S or

send Xoff Assert RTS or

send Xon

RX TX

00 00 8 16 8 0

01 01 16 8 16 7

10 10 24 24 24 15

11 11 28 30 28 23

Product data sheet Rev. 2 — 11 November 2010 12 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

6.5 Hardware flow control

When automatic hardware flow control is enabled, the SC16C850 monitors the CTS pin

for a remote buffer overflow indication and controls the RTS pin for local buffer overflo ws.

Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7 ] (CTS) to

a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow control request,

ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C850 will suspend TX

transmissions as soon as the stop bit of the character in process is shifted out.

Transmission is resumed after the CTS input returns to a logic 0, indicating more data

may be sent.

When AFCR1[2] is set to logic 1 then the function of CTS pin is mapped to the DSR pin,

and the function of RTS is mapped to DTR pin. DSR and DTR pins will behave as

described above for CTS and RTS.

With the automatic hardware flow control function en abled, an interrupt is generated wh en

the receive FIFO reaches the pr ogram med trigger level. Th e RTS (or DTR) pin will not be

forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level.

However, the RTS (or DTR) pin will return to a logic 0 after the receive buffer (FIFO) is

unloaded to the next trigger level below the programmed trigger level. Under the above

described conditions, the SC16C850 will continue to accept data until the receive FIFO is

full.

When the TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the ‘first extra feature

FCR[7:4]; see Table 6.

When the TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature

trigger levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines

how many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is

sent. The content in FLWCNTL determines how many bytes are in the receive FIFO

before RTS (or DTR) is asserted, or Xon is sent.

In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to

any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always

be greater than FLWCNTL. The UAR T does not check for this condition au tomatically, and

if this condition is not met, spurious operation of the device might occur. When using

FLWCNTH and FLWCNTL, these registers must be initialized to proper values before

hardware or software flow control is enabled via the EFR register.

6.6 Software flow control

When software flow control is enabled, the SC16C850 compares one or two sequentially

received data characters with the programmed Xon or Xoff character value(s). If the

received character(s) match the programmed Xoff values, the SC16C850 will halt

transmission (TX) as soon as the curren t character(s) has completed tran smission. When

a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if

receive interrupt is enabled) will be activated. Following a sus pension due to a match of

the Xoff characters’ values, the SC16C850 will monitor the receive data stream for a

match to the Xon1/Xon2 character value(s). If a match is found, the SC16C850 will

resume operation and clear the flags (I SR[4 ]) .

Product data sheet Rev. 2 — 11 November 2010 13 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software flow control.

Different conditions can be set to detect Xon/Xoff char acters and suspend/resume

transmissions (see Table 24). When double 8-bit Xon/Xoff characters are selected, the

SC16C850 compares two cons ecu tiv e re ce ive ch ar ac te rs with two so ftware flow control

8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under

the above described flow contr ol mechanisms, flow control characters are no t placed

(stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters

cannot be used for data transfer.

In the event that the receive buffer is overfilling, the SC16C850 automatically sends an

Xoff character (when enabled) via the serial TX output to the remote UART. The

SC16C850 sends the Xoff1/Xoff2 characters as soon as the number of received dat a in

the receive FIFO passes the programmed trigger level. To clear this cond ition, the

SC16C850 will transmit the programmed Xon1/Xon2 characters as soon as the number of

characters in the receive FIFO drops below the programmed trigger level.

6.7 Special character detect

A special character detect feature is provided to detect an 8-bit character when EFR[5] is

set. When an 8-bit character is detected, it will be placed on the user-accessible data

stack along with normal incoming RX data. This condition is selected in conjunction with

EFR[3:0] (see Table 24). Note that software flo w control should be turned off when using

this special mode by setting EFR[3:0] to all zeroes.

The SC16C850 compares each incoming receive character with Xoff2 data. If a match

occurs, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate

detection of a special character. Although Table 8 “SC16C850 internal registers” shows

Xon1, Xon2, Xof f1, Xof f2 with eight bit s o f char acter information, the actua l number of bits

is dependent on the programmed word length. Line Control Register bits LCR[1:0] define

the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length

selected by LCR[1:0] also determines the number of bits that will be used for the special

character comparison. Bit 0 in Xon1, Xon2, Xoff1, Xoff2 corresponds with the LSB bit for

the received character.

6.8 Interrupt priority and time-out interrupts

The interrupts are enabled by IER[7:0]. Care must be taken when handling these

interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C850

will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to

continuing operations. The ISR indicates the current singular highest priority interrupt

only. A condition can exist where a higher priority interrupt masks the lower priority

interrupt(s) (see Table 13). Only after servicing the higher pending interrupt will the lower

priority interrupt(s) be r eflected in the status register. Servicing the interrupt without

investigating further interrupt conditions can result in data errors.

Receive Data Ready and Receive Time-Out have the same interrupt priority (when

enabled by IER[0]), and it is important to serve th ese inte rr up ts correct ly. The receive r

issues an interrupt after the number of characters have reached the programmed trigger

level. In this case, the SC16C850 FIFO may hold more characters than the programmed

trigger level. Following the removal of a data byte, the user should re-check LSR[0 ] to see

if there are any additional characters. A Receive Time-Out will not occur if the receive

FIFO is empty. The time-out counter is reset at the cente r of eac h sto p bit receive d or

Product data sheet Rev. 2 — 11 November 2010 14 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

each time the Receive Holding Register (RHR) is read. The actual time-out value is

4 character time, including d at a informatio n lengt h, st art bit, p arity b it, and the size of stop

bit, that is, 1×, 1.5×, or 2× bit times.

6.9 Programmable baud rate generator

The SC16C850 UART contains a programmable rational baud rate generator that takes

any clock input and divides it by a divisor in the range between 1 and (216 −1). The

SC16C850 offers the capability of dividing the input frequency by rational divisor. The

fractional part o f the divisor is controlled by the CLKPRES registe r in the ‘first extra feature

(1)

where:

N is the integer part of the divisor in DLL and DLM registers;

M is the fractional part of the divisor in CLKPRES register;

fXTAL1 is the clock frequency at XTAL1 pin.

Prescaler = 1 when MCR[7] is set to 0.

Prescaler = 4 when MCR[7] is set to 1.

A single baud rate generator is provided for the transmitter and receiver. The

programmable Baud Rate Gener ator is capable of operating with a frequency of up to

80 MHz. To obta in maximum data rate, it is necessary to use full rail swing on the clock

input. The SC16C850 can be configured for internal or external clock operation. For

internal clock operation, an industry standard crystal is connected externally between the

XTAL1 and XTAL2 pins (see Figure 7). Alternatively, an external clock can be connected

to the XTAL1 pin (see Figure 8) to clock the internal baud rate generator for standard or

custom rates (see Table 7).

The generator divides the input 16× clock by any divisor from 1 to (216 −1). The

SC16C850 divides the basic external clock by 16. The baud rate is configured via the

CLKPRES, DLL and DLM internal register functions. Custom ized baud rates can be

achieved by selecting the proper divisor values for the MSB and LSB sections of the baud

rate generator.

Fig 6. Prescalers and baud rate generator block diagram

baud rate fXTAL1

MCR 7[] 16 N M

------

⎝⎠

⎛⎞

××

-------------------------------------------------------------------

002aac64

OSCILLATOR

XTAL1

XTAL2

DIVIDE-BY-1

DIVIDE-BY-4

CLKPRES

[3:0]

BAUD RATE

GENERATOR

(DLL, DLM)

transmitter and

receiver clock

MCR[7] = 0

MCR[7] = 1

Product data sheet Rev. 2 — 11 November 2010 15 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB)

provides a user capa bility for selecting the desired final baud rate. The example in Table 7

shows the selectable baud rate table available when using a 1.8432 MHz external clock

input when MCR[7] = 0, and CLKPRES = 0x00.

Fig 7. Crystal oscillator connection

If fXTAL1 frequency is greater than 50 MHz, then a DC blocking capacitor is required.

XTAL2 pin should be left unconnected when an external clock is used.

Fig 8. External clock connection

Table 7. Baud rate generator pr ogramming table using a 1.8432 MHz clo ck when

MCR[7] = 0 and CLKPRES[3:0] = 0

Output

baud rate

(bit/s)

Output

16×clock divisor

(decimal)

Output

16×clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

50 2304 900 09 00

75 1536 600 06 00

110 1047 417 04 17

150 768 300 03 00

300 384 180 01 80

600 192 C0 00 C0

1.2 k 96 60 00 60

2.4 k 48 30 00 30

3.6 k 32 20 00 20

4.8 k 24 18 00 18

7.2 k 16 10 00 10

9.6 k 12 0C 00 0C

19.2 k 6 06 00 06

002aaa87

47 pF

XTAL1 XTAL2

1.8432 MHz

22 pF

33 pF

XTAL1 XTAL2

1.5 kΩ

1.8432 MHz

22 pF

002aac63

XTAL1 XTAL2

100 pF

XTAL1

Product data sheet Rev. 2 — 11 November 2010 16 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

6.10 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconfigured for loopback internally

(see Figure 9). MCR[3:0] register bits are used for controlling loopback diagnostic testing.

In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are

disconnected from their associated interface pins, and instead are connected together

internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control

input pins, and instead ar e co nnected in tern ally to RTS, DTR, MCR[3] (OP2) and MCR[2]

(OP1). Loopback test data is entered into the transmit holding register via the user data

bus interface, D[7:0]. The transmit UART serializes the da ta and passe s the ser ial d ata to

the receive UART via the internal loopback connection. The receive UART converts the

serial data back into parallel data that is then made available at the user data interface

D[7:0]. The user optionally compares the received data to the initial transmitted data for

verifying error-free operation of the UART TX/RX circuits.

In this mode, the interrupt pin is 3-stated, therefore, the software must use the polling

method (see Section 7.2.2) to send and receive da ta.

38.4 k 3 03 00 03

57.6 k 2 02 00 02

115.2 k 1 01 00 01

Table 7. Baud rate generator pr ogramming table using a 1.8432 MHz clo ck when

MCR[7] = 0 and CLKPRES[3:0] = 0 …continued

Output

baud rate

(bit/s)

Output

16×clock divisor

(decimal)

Output

16×clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

Product data sheet Rev. 2 — 11 November 2010 17 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Fig 9. Internal Loopback mode diagra m

CTS

TRANSMIT

FIFO

REGISTERS

RECEIVE

SHIFT

RECEIVE

FIFO

REGISTERS RX

INTERCONNECT BUS LINES

AND

CONTROL SIGNALS

SC16C850

TRANSMIT

SHIFT

XTAL2XTAL1

002aad026

FLOW

CONTROL

LOGIC

DATA B U S

AND

CONTROL

LOGIC

SELECT

LOGIC

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

MODEM

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

RTS

DSR

DTR

OP2

MCR[4] = 1

ENCODER

DECODER

INT

(IRQ)

D0 to D7

IOR

IOW

RESET

A0 to A2

OP1

POWER-

DOWN

CONTROL

LOWPWR

Product data sheet Rev. 2 — 11 November 2010 18 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

6.11 Sleep mode

Sleep mode is an enhanced feature of the SC16C850 UART. It is enabled when EFR[4],

the enhanced fu nct ion s bit, is set and when IER[4] bit is set.

6.11.1 Conditions to enter Sleep mode

Sleep mode is entered when:

•Modem input pins are not toggling.

•The serial data input line, RX, is idle for 4 character time (logic HIGH) and AFCR1[4]

is logic 0. When AFCR1[4] is logic 1 the device will go to sleep regardless of the state

of the RX pin (see Section 7.21 for the description of AFCR1 bit 4).

•The TX FIFO and TX shift register are empty.

•There are no interrupts pending.

•The RX FIFO is empty.

In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are

clocked using these clocks, the power co nsumption is greatly reduced.

Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, mu st not be

done during Sleep mode. The refore, it is advisable to disable Sleep mode using IER[4]

before writing to DLL or DLM.

6.11.2 Conditions to resume normal operation

SC16C850 resumes normal operation by any of the following:

•Receives a start bit on RX pin.

•Data is loaded into transmit FIFO.

•A change of state on any of the modem input pins

If the device is awakened by one of the conditions described above, it will return to the

Sleep mode automatically a fter all th e conditions described in Section 6.11.1 are met. The

device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a

logic 0.

When the SC16C850 is in Sleep mode and the host data bus (D[7:0], A[2:0], IOW, IOR,

CS) remains in steady state, either HIGH or LOW, the Sleep mode supply current will be

in the μA range as specified in Table 36 “Static characteristics”. If any of these signals is

toggling or floating then the sleep current will be higher.

6.12 Low power feature

A low power feature is provided by the SC16C850 to prevent the switching of the host

data bus from influencing the sleep current. When the pin LOWPWR is activa ted (logic

HIGH), the device immediately and unconditionally goes into Low power mode. All clocks

are stopped and most host interface pins are isolated to reduce power consumption. The

device only returns to normal mode when the LOWPWR pin is de-asserted. The pin can

be left unconnected because it has an internal pull-down resistor.

Product data sheet Rev. 2 — 11 November 2010 19 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

6.13 RS-485 features

6.13.1 Auto RS-485 RTS control

Normally the RTS pin is controlled by MCR[1], or if hardware flow control is enabled, the

logic state of the RTS pin is controlled by the hardware flow control circuitry . AFCR2[4] will

take the precedence over the other two modes; once this bit is set, the transmitter will

control the state of the RTS pin. The tr an sm itte r auto matically asserts the RTS pin

(logic 0) once the host writes data to the transmit FIFO, and de-asserts RTS pin (logic 1)

once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode the software would have to disable the hardware

flow control function.

6.13.2 RS-485 RTS inversion

AFCR2[5] reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.

When the transmitter has data to be sent it will de-asserts the R TS pin (logic 1), and when

the last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).

6.13.3 Auto 9-bit mode (RS-485)

AFCR2[0] is used to enable the 9-bit mode (Multi-drop or RS-485 mode). In this mode of

operation, a ‘master’ station transmits an address character followed by data characters

for the addressed ‘slave’ stations. The slave stations examine the received data and

interrupt the controller if the received character is an address character (parity bit = 1).

To use the automatic 9-bit mode, the software would have to disable the hardware and

software flow control functions.

6.13.3.1 Normal Multi-drop mode

The 9-bit Mode in AFCR2[0] is enabled, but not Special Character Detect (EFR[5]). The

receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an

address byte is received (parity bit = 1). This address byte wi ll cause the UART to set the

parity error. The UART will generate a line status interrupt (IER[2] must be set to ‘1’ at this

time), and at the same time puts this address byte in the RX FIFO. After the controller

examines the byte it must make a decision whether or not to enable the receiver; it should

enable the receiver if the a ddress byte ad dresses it s ID address, a nd must n ot enable the

receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until

being disabled by the controller after the controller has received a complete message

from the ‘master’ station. If the controller does not disable the receiver after receiving a

message from the ‘master’ station, the receiver will generate a parity error upon receiving

another address byte. The contro ller then determ ines if the address byte addresses it s ID

address, if it is not, the controller then can disable the receiver. If the address byte

addresses the ‘slave’ ID address, the controller takes no further action, and the receiver

will receive the subsequent data.

Product data sheet Rev. 2 — 11 November 2010 20 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

6.13.3.2 Auto address detection

If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the

address byte) the receiver will try to detect an address byte that matches the programmed

character in the Xoff2 register. If the received byte is a data byte or an address byte that

does not match the programmed character in the Xoff2 register, the receiver will discard

these data. Upon receiving an address byte that matches the Xoff2 character , the receiver

will be automatically enabled if not already enabled, and the address character is pushed

into the RX FIFO along with the parity bit (in place of the par ity error bit). Th e receiver also

generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will

then receive the subsequent data from the ‘master’ station until being disabled by the

controller after having received a message from the ‘master’ station.

If another address byte is received and this address byte does not match the Xoff2

character, the receiver will be automatically disabled and the address byte is ignored. If

the address byte matches the Xoff2 character, the receiver will put this byte in the RX

FIFO along with the parity bit in the parity error bit (LSR bit 2).

7. Register descriptions

Table 8 details the assigned bit functions for th e SC16C850 internal registers. The

assigned bit functions are more fully defined in Section 7.1 through Section 7.23.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 2 — 11 November 2010 21 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Table 8. SC16C850 internal registers

A2 A1 A0 Register Default[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

General register set[2]

0 0 0 RHR 0xXX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R

0 0 0 THR 0xXX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W

0 0 1 IER 0x00 CTS

interrupt[3] RTS

interrupt[3] Xoff

interrupt[3] Sleep

mode[3] modem

status

interrupt

receive line

status

interrupt

transmit

holding

interrupt

receive

holding

interrupt

R/W

0 1 0 FCR 0x00 RCVR

trigger

(MSB)

RCVR

trigger (LSB) TX trigger

(MSB)[3] TX trigger

(LSB)[3] reserved XMIT FIFO

reset RCVR FIFO

reset FIFOs

enable W

0 1 0 ISR 0x01 FIFOs

enabled FIFOs

enabled INT priority

bit 4 INT priority

bit 3 INT priority

bit 2 INT priority

bit 1 INT priority

bit 0 INT status R

0 1 1 LCR 0x00 divisor latch

enable set break set parity even parity parity

enable stop bits word length

bit 1 word length

bit 0 R/W

1 0 0 MCR 0x00 clock

select[3] IrDA enable INT type loopback OP2 OP1 RTS DTR R/W

1 0 1 LSR 0x60 FIFO data

error THR and

TSR empty THR empty break

interrupt framing

error parity error overrun

error receive data

ready R

1 0 1 EFCR 0x00 reserved reserved reserved reserved reserved Enable extra

feature bi t 1 Enable extra

feature bi t 0 Enable

TXLVLCNT/

RXLVLCNT

1 1 0 MSR 0xX0 CD RI DSR CTS ΔCD ΔRI ΔDSR ΔCTS R

1 1 1 SPR 0xFF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

Special register set[4]

0 0 0 DLL 0xXX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0 0 1 DLM 0xXX bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W

Second special register set[6]

0 1 1 TXLVLCNT 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R

1 0 0 RXLVLCNT 0x0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 2 — 11 November 2010 22 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

[1] The value shown represents the register’s initialized HEX value; X = not applicable.

[2] Accessible only when LCR[7] is logic 0, and EFCR[2:0] are logic 000b.

[3] This bit is only accessible when EFR[4] is set.

[4] Baud rate registers accessible only when LCR[7] is logic 1.

[5] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic 0.

[6] Second Special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0.

[7] First extra feature register set is only accessible when EFCR[2:1] = 01b.

[8] Second extra feature register set is only accessible when EFCR[2:1] = 10b.

Enhanced feature register set[5]

0 1 0 EFR 0x00 Auto CTS Auto RTS special

character

select

Enable

IER[7:4],

ISR[5:4],

FCR[5:4],

MCR[7:5]

Cont-3 TX,

RX Control Cont-2 TX,

RX Control C ont-1 TX,

RX Control Cont-0 TX,

RX Control R/W

1 0 0 Xon1 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 0 1 Xon2 0x00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W

1 1 0 Xoff1 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 1 1 Xoff2 0x00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W

First extra feature register set[7]

0 1 0 TXINTLVL 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 0 0 RXINTLVL 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 1 0 FLWCNTH 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 1 1 FLWCNTL 0x00 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 R/W

Second extra feature register set[8]

0 1 0 CLKPRES 0x00 reserved reserved reserved reserved bit 3 bit 2 bit 1 bit 0 R/W

1 0 0 RS485TIME 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 1 0 AFCR2 0x00 reserved reserved RS485 RTS

Invert Auto RS485

RTS RS485

RTS/DTR Transmitter

Disable Receiver

Disable 9-bit Enable R/W

1 1 1 AFCR1 0x00 reserved reserved reserved Sleep

RXLow reserved RTS/CTS

mapped to

DTR/DSR

Software

Reset TSR

Interrupt R/W

Table 8. SC16C850 internal registers …continued

A2 A1 A0 Register Default[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

Product data sheet Rev. 2 — 11 November 2010 23 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

transmit FIFO. The THR empty flag in the LSR will be set to a logic 1 when the transmit

FIFO is empty or when data is transferred to the TSR.

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC16C850

receive FIFO by readin g the RHR . Th e re ce ive se ctio n pr ov ide s a me ch an ism to pr ev en t

false starts. On the falling edge of a start or false start bit, an internal receiver counter

starts counting clocks at the 16× clock rate. After 71⁄2 clocks, the start bit time should be

shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a

logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from

assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INT output pin.

Table 9. Interrupt Enable Register bits description

Bit Symbol Description

7 IER[7] CTS interrupt.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC16C850 issues an interrupt when

the CTS pin transitions from a logic 0 to a logic 1 .

6 IER[6] RTS interrupt.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC16C850 issues an interru pt when

the RTS pin transitions from a logic 0 to a logic 1.

5 IER[5] Xoff interrupt.

logic 0 = disable the software flow control, receive Xoff interrupt (normal default

condition)

logic 1 = enable the receive Xoff interrupt

4 IER[4] Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode

3 IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a modem

status change as reflected in MSR[3:0].

logic 0 = disable the modem status register interrupt (normal default condition)

logic 1 = enable the modem status register interrupt

2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a receive

data error condition exists as reflected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

Product data sheet Rev. 2 — 11 November 2010 24 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts

(IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the

following:

•The receive RXRDY interr upt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

•Receive FIFO status will also be reflected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

•The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

•When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by th e TSR and UART for

transmission via the tran smission media. The inter rupt is cleared either by r eading the

ISR, or by loading the THR with new dat a characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, setting IER[3:0] puts the SC16C850 in the FIFO polled mode of

operation. In this mode, interrupts are not generated and the user must poll the LSR

bits in the LSR either or both can be used in the polled mod e by selecting respective

transmit or receiv e control bit(s).

•LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

•LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.

•LSR[5] will indicate when the transmit FIFO is empty.

•LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

•LSR[7] will show if any FIFO data errors occurred.

1 IER[1] Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be

issued whenever the THR is empty, and is associated with LSR[5 ]. In the FIFO

modes, this interrupt will be issued whenever the FI FO is empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

0 IER[0] Receive Holding Registe r interrupt. In the non-FIFO mode, this interrupt will be

issued when the RHR has data, or is cleared when the RHR is empty. In the FIFO

mode, this interrupt will be issued when the FIFO has reached the programmed

trigger le ve l or i s cle are d wh en th e FI FO drops belo w th e tri g ge r level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal

default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

Table 9. Interrupt Enable Register bits description …continued

Bit Symbol Description

Product data sheet Rev. 2 — 11 November 2010 25 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear th e FI FO s, and set the receive FIFO

trigger levels.

7.3.1 FIFO mode

[1] For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18.

[2] For 128-byte FIFO mode, refer to Section 7.15, Section 7.17, Section 7.18.

[1] When RXINTLVL, TXINTLVL, FLWCNTL or F LWCNTH contains any value other than 0x00, receive and

transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”).

Table 10. FIFO Cont rol Register bits description

Bit Symbol Description

7:6 FCR[7:6] Receive trigger level in 32-byte F IF O mode[1].

These bits are used to set the trigger levels for receive FIFO interrupt and flow

control. The SC16C850 will issue a receive ready interrupt when the number of

characters in the receive FIFO reaches the selected trigger level. Refer to

Table 11.

5:4 FCR[5:4] Tr ansmit trigger level in 32-by te FIFO mode[2].

These bits are used to set the trigger level for the transmit FIFO interrupt and

flow control. The SC16C850 will issue a tra nsmit empty interrup t whe n the

number of characters in FIFO drop s be l ow th e se le cted trigger level. Ref e r to

Table 12.

3 FCR[3] reserved

2 FCR[2] XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic. This bit will return to a logic 0 after clearing the FIFO.

1 FCR[1] RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO counter

logic. This bit will re turn to a logic 0 after clearing the FIFO.

0 FCR[0] FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO

Table 11. RCVR trigger levels

FCR[7] FCR[6] RX FIFO trigger level (bytes) in 32-b yte FIFO mode[1]

008

0116

1024

1128

Product data sheet Rev. 2 — 11 November 2010 26 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

[1] When RXINTLVL, TXINTLVL, FLWCNTL or F LWCNTH contains any value other than 0x00, receive and

transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”).

7.4 Interrupt Status Register (ISR)

The SC16C850 provides six levels of pr ioritized interrupts to min imize external software

interaction. The Interrupt Status Register (ISR) provides the user with six interrupt st atus

bits. Performing a read cycle on the ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are acknowledged until the pending

interrupt is serviced. A lower level interrupt may be seen after servicing the higher level

interrupt and re-reading the interrupt status bits. Table 13 “Interrupt source” shows the

data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources

associated with each of these interrupt levels.

Table 12. TX FIFO trigger levels

FCR[5] FCR[4] TX FIFO trigger level (bytes) in 32-byte FIFO mode[1]

0016

018

1024

1130

Table 13. Interr upt source

Priority

level ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

1 000110LSR (Receiver Line Status

2 000100RXRDY (Received Data Ready)

2 001100RXRDY (Receive Data time-out)

3 000010TXRDY (Transmitter Holding

4 000000MSR (Modem Status Register)

5 010000RXRDY (Received Xoff signal)/

Specia l character

6 100000CTS, RTS change of state

Table 14. Interrupt Status Register bits description

Bit Symbol Description

7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being

used in the non-FIFO mode. They are set to a logic 1 when the FIFOs a re

enabled in the SC16C850 mode.

logic 0 or cleared = default condition

5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.

ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]

indicates that CTS, RTS have been generated. Note that once set to a

logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.

logic 0 or cleared = default condition

3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending interrupt at

interrupt priority levels 1, 2, and 3 (see Table 13).

logic 0 or cleared = default condition

Product data sheet Rev. 2 — 11 November 2010 27 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchron ous data communication

format. The word length, the number of stop bit s, and the par ity are selected by writing the

appropriate bits in this register .

0 ISR[0] INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as a

pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

Table 14. Interrupt Status Register bits description …continued

Bit Symbol Description

Ta ble 15. Line Control Register bits description

Bit Symbol Description

7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced

Featur e mo de enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to

be transmitted (the TX output is forced to a logic 0 state). This condition

exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5:3 LCR[5:3] Programs the parity conditions (see Table 16).

2 LCR[2] S top bits. The length of stop bit is specified by this bit in conjunction with the

programmed word length (see Table 17).

logic 0 or cleared = default condition

1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 18).

logic 0 or cleared = default condition

Table 16. LCR[5:3] parity selection

LCR[5] LCR[4] LCR[3] Parity selection

XX0no parity

001odd parity

011even parity

1 0 1 forced parity ‘1’

1 1 1 forced parity ‘0’

Table 17. LCR[2] stop bit length

LCR[2] Word length (bits) Stop bit length (bit times)

0 5, 6, 7, 8 1

15 1

1⁄2

16, 7, 8 2

Product data sheet Rev. 2 — 11 November 2010 28 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 18. LCR[1:0] word length

LCR[1] LCR[0] Word length (bits)

00 5

01 6

10 7

11 8

Table 19. Modem Control Register bits description

Bit Symbol Description

7 MCR[7] Clock select

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

6 MCR[6] IR enable (see Figure 22).

logic 0 = enable the standard modem receive and transmit input/output

interface (normal default condition)

logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While

in this mode, the TX/RX output/inputs are routed to the infrared

encoder/decoder. The data input and output levels will conform to the

IrDA infrared interface requirement. As such, while in this mode, the

infrared TX output will be a logic 0 during idle data conditions.

5 MCR[5] Interrupt type (In te l mode only). In Intel mode (16/68 = 1), this pin

determines the interrupt outp ut pin configuration.

logic 0 = CMOS output

logic 1 = open-source. A 300 Ω to 500 Ω pull-down resistor is requi red.

In Motorola mode (16/68 = 0), the output is always open-drain.

4 MCR[4] Loopback. Enable the local loopback mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI

are disconnected from the SC16C850 I/O pins. Internally the modem data

and control pins are connected into a loopback data configuration (see

Figure 9). In this mode, the receiver and transmitter interrupts remain fully

operational. The Mo dem Control Interrupts are also operational, but the

interrupts’ sources are switched to the lower four bits of the Modem Control.

Interrupts continue to be controlled by the IER register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

3MCR[3]OP2

. This bit is used for internal Loopback mode on ly. In Loopback mode,

this bit is used to write the state of the modem CD interface signal.

2MCR[2]OP1

. This bit is used for internal Loopback mode on ly. In Loopback mode,

this bit is used to write the state of the modem RI interface signal.

1MCR[1]RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

0MCR[0]DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

Product data sheet Rev. 2 — 11 November 2010 29 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C850 and the CPU.

Table 20. Line Status Register bits descriptio n

Bit Symbol Description

7 LSR[7] FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when there are no remaining error flags

associated with the remaining data in the FIFO.

6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the transmit holding register and the transmit shift register are

both empty. It is reset to logic 0 whenever either the THR or TSR contains a data

character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and

transmit shift register are both empty.

5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register.

The bit is reset to a logic 0 concurrently with the loading of the transmitter

holding register by the CPU. In the FIFO mode, this bit is set when the transmit

FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4 LSR[4] Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

3 LSR[3] Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s).

In the FIFO mode, this error is associated with the character at the top of the

FIFO.

2LSR[2]Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error. The receive character does not have correc t parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

1 LSR[1] Overrun error.

logic 0 = no overrun error (normal default cond ition)

logic 1 = overrun error. A data overrun error occurred in the Receive Shift

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the Receive Shift Register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the erro r.

0 LSR[0] Receive data ready.

logic 0 = no data in Receive Holding Register or FIFO (normal default

condition)

logic 1 = data has been received and is saved in the Receive Holding Register

or FIFO

Product data sheet Rev. 2 — 11 November 2010 30 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.8 Modem Status Register (MSR)

This register shares the same addres s as EFCR register. This is a read-only register and

it provides the current state of the control interface signals from the modem, or other

peripheral device to which the SC16C850 is connected. Four bits of this register are used

to indicate the changed information. These bits are set to a logic 1 whenever a control

input from the modem changes state. These bits are set to a logic 0 whenever the CPU

reads this register.

When write, the data will be written to EFCR register.

[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.

Table 21. Mod em Status Register bits description

Bit Symbol Description

7 MSR[7] CD. During normal operation, this bit is the complement of the CD input.

Reading this bit in the loopback mode produces the state of MCR[3] (OP2).

6 MSR[6] RI. During normal operation, this bit is the complement of the RI input.

Reading this bit in the loopback mode produces the state of MCR[2] (OP1).

5 MSR[5] DSR. During normal operation, this bit is the complement of the DSR input.

During the loopback mode, this bit is equivalent to MCR[0 ] (DTR).

4 MSR[4] CTS. During normal operation, this bit is the complement of the CTS input.

During the loopback mode, this bit is equivalent to MCR[1 ] (RTS).

3MSR[3]ΔCD [1]

logic 0 = no CD change (normal default condition)

logic 1 = the CD input to the SC16C850 has changed state since the last

time it was read. A modem Status Interrupt will be generated.

2MSR[2]ΔRI [1]

logic 0 = no RI change (normal default co ndition)

logic 1 = the RI input to the SC16C850 has changed from a logic 0 to a

logic 1. A modem Status Interrupt will be generated.

1MSR[1]ΔDSR [1]

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C850 has changed state since the

last time it was read. A modem Status Interrupt will be generated.

0MSR[0]ΔCTS [1]

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C850 has changed state since the last

time it was read. A modem Status Interrupt will be generated.

Product data sheet Rev. 2 — 11 November 2010 31 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.9 Extra Feature Control Register (EFCR)

This is a write-only register , and it allows the software access to these registers: ‘first extra

feature register se t’, ‘second extra feature register set’, Transmit FIFO Level Counter

(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).

Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can

only be accessed if EFCR[ 2:1 ] ar e ze ro es .

7.10 Scratchpad Register (SPR)

The SC16C850 provides a tempor ary data register to sto re 8 bits of user information.

7.11 Divisor Latch (DLL and DLM)

These are two 8-bit registe rs which store the 16-bit divisor for generation of the baud clock

in the baud rate genera tor. DLM, stores the most significant p art of the divisor. DLL stores

the least significant part of the divisor.

7.12 Transmit FIFO Level Count (TXLVLCNT)

This register is a read-only register. It reports the number of spa ces available in the

transmit FIFO .

7.13 Receive FIFO Level Count (RXLVLCNT)

This register is a read-only register . It report s the fill level of the receive FIFO (the number

of characters in the RX FIFO).

Table 22. Extra Featu re Control Register bits description

Bit Symbol Description

7:3 EFCR[7:3] reserved

2:1 EFCR[2: 1 ] Enable Extra Feat ure Control bits

00 = General register set is accessible

01 = First extra feature register set is accessible

10 = Second extra feature register set is accessible

11 = reserved

0 EFCR[0] Enable TXLVLCNT and RXLVLCNT access

0 = TXLVLCNT and RXLVLCNT are disabled

1 = TXLVLCNT and RXLVLCNT are enabled and can be read.

Product data sheet Rev. 2 — 11 November 2010 32 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.14 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 pr ovide single or dual characte r software flow control selection. When the

Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential numbers.

[1] Enhanced function control bits IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].

Table 23. Enhanced Feature Register bits description

Bit Symbol Description

7 EFR[7] Automatic CTS flow control.

logic 0 = automatic CTS flow control is disabled (normal defaul t condition)

logic 1 = enable automatic CTS flow control. Tr ansmission will stop when

CTS goes to a logical 1. Transmission will resume when the CTS pin returns

to a logical 0.

6 EFR[6] Automatic RTS flow control. Automatic RTS may be used for hardware flow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be

generated when the receive F IF O is filled to the programmed trigger level and

RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when

data is unloaded below the next lower trigger level (programmed trigger level 1).

The state of this register bit changes with the status of the hardware flow

control. RTS functions normally when hardware flow control is disabled.

logic 0 = automatic RTS flow control is disabled (normal default condition)

logic 1 = enable automatic RTS flow control

5 EFR[5] Special Character Detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C850 compares each

incoming receive character with Xoff2 data. If a match exists, the received

data will be transferred to FIFO and ISR[4] will be set to indicate detection of

special character . Bit 0 in the X-registers corresponds with the LSB bit for the

receive character. When this feature is enabled, the normal softw ar e fl o w

control must be disabled (EFR[3:0] must be set to a logic 0).

4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] can be modified and latched. After modifying any bits in the enhanced

registers, EFR[4] can be set to a logic 0 to latch the new values. This feature

prevents existing software from altering or overwriting the SC16C850 enhanced

functions.

logic 0 = disable/latch enhanced features[1]. (Normal default condition.)

logic 1 = enables the enhanced functions[1].

3:0 EFR[3:0] Cont-3:0 TX, RX control. Logic 0 or cleared is the default conditio n.

Combinations of software flow control can be selected by programming these

bits. See Table 24.

Product data sheet Rev. 2 — 11 November 2010 33 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

[1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer.

7.15 Transmit Interrupt Level Register (TXINTLVL)

This 8-bit register is used to store the transmit FIFO trigger levels used for interrupt

generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.

Table 25 shows the TXINTLVL register bit settings.

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.16 Receive Interrupt Level Register (RXINTLVL)

This 8-bit register is used store the receive FIFO trigger levels used for interrupt

generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.

Table 26 shows the RXINTLVL register bit settings.

Table 24. Software flow control functions[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls

0 0 X X No transmit flow control

1 0 X X Transmit Xon1/Xoff1

0 1 X X Transmit Xon2/Xoff2

1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2

X X 0 0 No receive flow control

X X 1 0 Receiver compares Xon1/Xoff1

X X 0 1 Receiver compares Xon2/Xoff2

1 0 1 1 Transmit Xon1/Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0 1 1 1 Transmit Xon2/Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Table 25. TXINTLVL register bits description

Bit Symbol Description

7:0 TXINTLVL[7:0] This register stores the pro g r am mable transmit interr up t tri g ge r levels

for 128-byte FIFO mode[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

Table 26. RXINTLVL register bits description

Bit Symbol Description

7:0 RXINTLVL[7:0] This register store s the programmable receive interrupt trigger levels

for 128-byte FIFO mode[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

Product data sheet Rev. 2 — 11 November 2010 34 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.17 Flow Control Trigger Level High (FLWCNTH)

This 8-bit register is used to store the receive FIFO high threshold levels to start/stop

transmission during hardware/software flow control. Table 27 shows the FLWCNTH

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.18 Flow Control Trigger Level Low (FLWCNTL)

This 8-bit register is used to store the receive FIFO low threshold levels to start/stop

transmission during hardware/software flow control. Table 28 shows the FLWCNTL

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.19 Clock Prescaler (CLKPRES)

This register hold values for the clock prescaler.

Table 27. FLWCNTH reg ister bits description

Bit Symbol Description

7:0 FLWCNTH[7:0] This register stores the programmable HIGH threshold level for

hardware and software flow control for 128-byte FIFO mode[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

Table 28. FLWCNTL register bits description

Bit Symbol Description

7:0 FLWCNTL[7:0] This register stores the programmable LOW threshold level for

hardware and software flow control for 128-byte FIFO mode[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

Table 29. Clock Prescaler register bits description

Bit Symbol Description

7:4 CLKPRES[7:4] reserved

3:0 CLKPRES[3:0] Clock Prescaler value. Reset to 0.

Product data sheet Rev. 2 — 11 November 2010 35 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.20 RS-485 Turn-around time delay (RS485TIME)

The value in this register controls the turn-around time of the external line transceiver in

bit time. In automatic 9-bit mode RTS or DTR pin is used to control the direction of the line

driver, after the la st bit of d at a h as been sh ifted out of the transmit shif t re gister th e UART

will count down the value in this register. When the count value reaches zero, the UART

will assert RTS or DTR pin (logic 0) to turn the external RS-485 transceiver around for

receiving.

7.21 Advanced Feature Control Register 2 (AFCR2)

Table 30. RS-485 programmable turn-around time register bits description

Bit Symbol Description

7:0 RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value

represents the bit time at the programmed baud rate.

Table 31. Advanced Feature Control Register 2 register bits description

Bit Symbol Description

7:6 AFCR2[7:6] reserved

5 AFCR2[5] RTSInvert. Invert RTS or DTR signal in automatic 9-bit mode.

logic 0 = RTS or DTR is set to 0 by the UART during transmission,

and to 1 during reception

logic 1 = RTS or DTR is set to 1 by the UART during transmission,

and to 0 during reception

4 AFCR2[4] RTSCon. Enable the transmitter to control RTS or DTR pin in

automatic 9-bit mode.

logic 0 = transmitter does not control RTS or DTR pin

logic 1 = transmitter controls RTS or DTR pin

3 AFCR2[3] RS485 RTS/DTR. Select RTS or DTR pin to control the external

transceiver.

logic 0 = RTS pin is used to control the external transceiver

logic 1 = DTR pin is used to control the external transceiver

2 AFCR2[2] TXDisable. Disable transmitter

logic 0 = transmitter is enabled

logic 1 = transmitter is disabled

1 AFCR2[1] RXDisable. Disable receiver

logic 0 = receiver is enabled

logic 1 = receiver is disabled

0 AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode

logic 0 = normal RS-232 mode

logic 1 = enable 9-bit mode

Product data sheet Rev. 2 — 11 November 2010 36 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.22 Advanced Feature Control Register 1 (AFCR1)

[1] It takes 4 XTAL1 clocks to reset the device.

Table 32. Advanced Feature Control Register 1 register bits description

Bit Symbol Description

7:5 AFCR1[7:5] reserved

4 AFCR1[4] Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.

logic 0 = RX input is level-sensitive. If RX pin is LOW, the UART will

not go to sleep. Once the UART is in Sleep mode, it will wake up if RX

pin goes LOW.

logic 1 = RX input is edge-sensitive. UART will go to sleep even if RX

pin is LOW, and will wake up whe n RX pin toggles.

3 AFCR1[3] reserved

2 AFCR1[2] RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to

DTR/DSR.

logic 0 = RTS and CTS signals are used for hardware flow control.

logic 1 = DTR and DSR signals are used for hardware flow control.

RTS and CTS retain their functionality.

1 AFCR1[1] SReset. Software Reset. A write to this bit will reset the UART. Once the

UART is reset this bit is automatically set to 0.[1]

0 AFCR1[0] TSR Interrupt. Select TSR interrupt mode

logic 0 = transmit empty interrupt occurs when transmit FIFO falls

below the trigger level or becomes empty.

logic 1 = transmit empty interrupt occurs when transmit FIFO falls

below the trigger level, or be comes empty and the last stop bit has

been shifted out of the Transmit Shift Register.

Product data sheet Rev. 2 — 11 November 2010 37 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.23 SC16C850 external reset condition and software reset

These two reset methods are identical and will reset the internal registers as indicated in

Table 33.

Table 33. Reset state for registers

IER IER[7:0] = 0

FCR FCR[7:0] = 0

ISR ISR[7:1] = 0; ISR[0] = 1

LCR LCR[7:0] = 0

MCR MCR[7:0] = 0

LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR MSR[7:4] = input signals; MSR[3:0] = 0

EFCR EFCR[7:0] = 0

SPR SPR[7:0] = 1

DLL undefined

DLM undefined

TXLVLCNT TXLVLCNT[7:0] = 0

RXLVLCNT RXLVLCNT[7:0] = 0

EFR EF R [7:0] = 0

Xon1 undefined

Xon2 undefined

Xoff1 undefined

Xoff2 undefined

TXINTLVL TXINTLVL[7:0] = 0

RXINTLVL RXINTLVL[7:0] = 0

FLWCNTH FLWCNTH[7:0] = 0

FLWCNTL FLWCNTL[7:0] = 0

CLKPRES CLKPRES[7:0] = 0

RS485TIME RS485TIME[7:0] = 0

AFCR2 AFCR2[7:0] = 0

AFCR1 AFCR1[7:0] = 0

Table 34. Reset state for outputs

Output Reset state

TX logic 1

RTS logic 1

DTR logic 1

INT logic 0

IRQ open-drain

Product data sheet Rev. 2 — 11 November 2010 38 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

8. Limiting values

9. Static characteristics

[1] Hysteresis input.

[2] Except XTAL2; XTAL2 VOL is 1 V typical.

[3] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.

[4] Activated by LOWPWR pin.

Table 35. Limiting va lues

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage - 7 V

Vnvoltage on any other pin VSS −0.3 VDD +0.3 V

Tamb ambient temperature o perating in free air −40 +85 °C

Tstg storage temperature −65 +150 °C

Ptot/pack tot al po w e r dissipation per

package - 500 mW

Table 36. Static characteristics

Tamb =

−

C to +85

C; tolerance of VDD

10 %; unless otherwise specified.

Symbol Parameter Conditions VDD =2.5V VDD =3.3V Unit

Min Max Min Max

VIL(clk) clock LOW-le vel input voltage XTAL1 pin −0.3 0.45 −0.3 0.6 V

VIH(clk) clock HIGH-level input voltage XTAL1 pin 1.8 VDD 2.4 VDD V

VIL LOW-level input voltage except XTAL1 clock,

LOWPWR pin −0.3 0.65 −0.3 0.8 V

LOWPWR pin [1] −0.3 0.65 −0.3 0.8 V

VIH HIGH-level input voltage except XTAL1 clock,

LOWPWR pin 1.6-2.0-V

LOWPWR pin [1] 1.6 VDD 2.2 VDD V

VOL LOW-level output voltage IOL =4mA [2] ---0.4V

IOL =2mA [2] -0.4- -V

VOH HIGH-level output voltage IOH =−4mA [2] --2.2-V

IOH =−800 μA[2] 1.85 - - - V

ILIL LOW-level input leakage current - 10 - 10 μA

ILIH HIGH-level input leakage current - 10 - 10 μA

IL(clk) clock leakage current LOW-level - 30 - 30 μA

HIGH-level - 30 - 30 μA

IDD supply current f = 5 MHz - 3 - 3 mA

IDD(sleep) sleep mode supply current [3] -50-50μA

IDD(lp) low-power mode supply current [4] -50-50μA

Ciinput capacitance - 5 - 5 pF

Product data sheet Rev. 2 — 11 November 2010 39 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

10. Dynamic characteristics

[1] Applies to external clock, crystal oscillator max 24 MHz.

[2] Maximum frequency =

[3] 10 % of the data bus output voltage level.

[4] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

Table 37. Dy namic characteristics - Intel or 16 mode

Tamb =

−

C to +85

C; tolerance of VDD

10 %; unless otherwise specified.

Symbol Parameter Conditions VDD =2.5V VDD =3.3V Unit

Min Max Min Max

tWH pulse width HIGH 6 - 6 - ns

tWL pulse width LOW 6 - 6 - ns

tw(clk) clock pulse width 12.5 - 12.5 - ns

fXTAL1 frequency on pin XTAL1 [1][2] -80-80MHz

tsu(A) address set-up time 10 - 5 - ns

th(A) address hold time 10 - 5 - ns

td(CS-IOR) delay time from CS to IOR 10 - 5 - ns

tw(IOR) IOR pulse width time 35 - 26 - ns

th(IOR-CS) hold time from IOR to chip select 0 - 0 - ns

td(IOR) IOR delay time 10 - 10 - ns

td(IOR-Q) delay time from IOR to data output 25 pF load - 35 - 26 ns

tdis(IOR-QZ) disable time from IOR to

high-impedance data output[3] 25 pF load - 17 - 15 ns

td(CSL-IOWL) d e l ay ti me from CS LOW to

IOW LOW 10 - 5 - ns

tw(IOW) IOW pulse width time 15 - 20 - ns

th(IOW-CS) hold time from IOW to CS 0-0-ns

td(IOW) IOW delay time 15 - 20 - ns

tsu(D-IOWH) set-up time from data input to

IOW HIGH 10 - 5 - ns

th(IOWH-D) data input hold time after IOW HIGH 10 - 5 - ns

td(IOW-Q) delay time from IOW to data output 25 pF load - 40 - 33 ns

td(modem-INT) delay time from modem to INT 25 pF load - 35 - 24 ns

td(IOR-INTL) delay time from IOR to INT LOW 25 pF load - 35 - 24 ns

td(stop-INT) delay time from stop to INT 25 pF load [4] -1T

RCLK -1T

RCLK s

td(start-INT) delay time from start to INT 25 pF load [4] -1T

RCLK -1T

RCLK s

td(IOW-TX) delay time from IOW to TX 25 pF load [4] 8TRCLK 24TRCLK 8TRCLK 24TRCLK s

td(IOW-INTL) delay time from IOW to INT LOW 25 pF load - 55 - 45 ns

tw(RESET) pulse width on pin RESET 10 - 10 - ns

N baud rate divisor 1 (216 −1) 1 (216 −1)

twclk()

---------------

Product data sheet Rev. 2 — 11 November 2010 40 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

[1] Applies to external clock, crystal oscillator max 24 MHz.

[2] Maximum frequency =

[3] 1 kΩ pull-up resistor on IRQ pin.

[4] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

Table 38. Dynamic characteristics - Motorola or 68 mode

Tamb =

−

C to +85

C; tolerance of VDD

10 %; unless otherwise specified.

Symbol Parameter Conditions VDD =2.5V VDD =3.3V Unit

Min Max Min Max

tWH pulse width HIGH 6 - 6 - ns

tWL pulse width LOW 6 - 6 - ns

tw(clk) clock pulse width 12.5 - 12.5 - ns

fXTAL1 frequency on pin XTAL1 [1][2] -80-80MHz

tsu(A) address set-up time 10 - 10 - ns

th(A) address hold time 15 - 15 - ns

tsu(RWL-CSL) set-up time from R/W LOW to CS LOW 10 - 10 - ns

tsu(RWH-CSL) set-up time from R/W HIGH to CS LOW 10 - 10 - ns

tw(CS) CS pulse width 25 pF load 50 - 20 - ns

td(CS) CS delay time 25 pF load 20 - 10 - ns

td(CS-Q) delay time from CS to data output 25 pF load - 50 - 20 ns

tdis(CS-QZ) di sa bl e time from CS to

high-impedance data output 25 pF load - 20 - 20 ns

th(CS-RWH) hold time from CS to R/W HIGH 10 - 10 - ns

td(RW) R/W delay time 10 - 10 - ns

tsu(D-CSH) set-up time from data input to CS HIGH 15 - 15 - ns

th(CSH-D) data input hold time after CS HIGH 15 - 15 - ns

td(modem-IRQL) delay time from modem to IRQ LOW [3] - 40 - 30 ns

td(CS-IRQH)R read delay time from CS to IRQ HIGH [3] - 40 - 30 ns

td(stop-IRQL) delay time from stop to IRQ LOW [4] -1T

RCLK -1T

RCLK s

td(CS-TX)W write delay time from CS to TX [4] 8TRCLK 24TRCLK 8TRCLK 24TRCLK s

td(start-IRQL) delay time from start to IRQ LOW [3][4] -1T

RCLK -1T

RCLK s

td(CS-IRQH)W write delay time from CS to IRQ HIGH [3] - 55 - 45 ns

td(CS-Q)W write delay time from CS to data output - 40 - 33 ns

tw(RESET_N) pulse width on pin RESET 10 - 10 - ns

N baud rate divisor 1 (216 −1) 1 (216 −1)

twclk()

---------------

Product data sheet Rev. 2 — 11 November 2010 41 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

10.1 T iming diagrams

Fig 10. General write timing (16 mode)

data

active

valid

address

002aac69

A0 to A2

IOW

D0 to D7

tsu(D-IOWH)

th(IOWH-D)

td(CSL-IOWL) tw(IOW) td(IOW)

th(A)

th(IOW-CS)

tsu(A)

Fig 11. General write timing (68 mode)

002aac40

A0 to A4

D0 to D7

R/W

tsu(RWL-CSL)

tsu(D-CSH)

th(CSH-D)

th(CS-RWH)

td(RW)

th(A)

tw(CS)

tsu(A)

Product data sheet Rev. 2 — 11 November 2010 42 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Fig 12. General read timing (16 mode)

data

active

valid

address

002aac69

A0 to A2

IOR

D0 to D7

td(IOR-Q) tdis(IOR-QZ)

td(CS-IOR) tw(IOR) td(IOR)

th(A)

th(IOR-CS)

tsu(A)

Fig 13. General read timing (68 mode)

002aac40

tsu(A)

A0 to A4

R/W

D0 to D7

tw(CS)

th(A)

td(CS)

tdis(CS-QZ)

tsu(RWH-CSL)

td(CS-Q)

Fig 14. External clock timing

external clock

002aac35

tw(clk)

tWL tWH

XTAL 1

twclk()

---------------

Product data sheet Rev. 2 — 11 November 2010 43 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Fig 15. Mode m input/output timing (16 mode)

td(IOW-Q)

change of state

td(modem-INT)

td(IOR-INTL)

002aac409

change of state

change of state change of state

active

active active active

change of state

RTS

DTR

IOW

CTS

DSR

INT

IOR

td(modem-INT)

(1) CS timing during a write cycle. See Figure 11.

(2) CS timing during a read cycle. See Figure 13.

Fig 16. Mode m input/output timing (68 mode)

td(CS-Q)W

change of state

td(modem-IRQL) td(modem-IRQL)

td(CS-IRQH)R

002aac63

td(modem-IRQL)

change of state

change of state change of state

active

active active active

change of state

RTS

DTR

CS (write)(1)

CTS

DSR

IRQ

CS (read)(2)

Product data sheet Rev. 2 — 11 November 2010 44 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

(1) INT is active when RX FIFO fills up to trigger level or a time-out condition happens (see Section 6.8).

(2) INT is cleared when RX FIFO drops below trigger level.

Fig 17. Receive timing in 16 mode

D0 D1 D2 D3 D4 D5 D6 D7

active

16 baud rate clock

002aac41

INT(1)(2)

IOR

td(IOR-INTL)

td(stop-INT)

5 data bits

6 data bits

7 data bits

stop

bit

parity

bit

start

bit data bits (0 to 7)

next data

start

bit

(1) IRQ is active when RX FIFO fills up to trigger level or time-out condition happens (see Section 6.8).

(2) IRQ is cleared when RX FIFO drops below trigger level.

Fig 18. Receive timing in 68 mode

D0 D1 D2 D3 D4 D5 D6 D7

active

16 baud rate clock

002aac63

td(CS-IRQH)R

next data

start

bit

stop

bit

parity

bit

start

bit

td(stop-IRQL)

IRQ(1)(2)

CS (read)

data bits (0 to 7)

5 data bits

6 data bits

7 data bits

Product data sheet Rev. 2 — 11 November 2010 45 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

(1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level.

(2) INT is cleared when ISR is read or TX FIFO fills up to trigger level.

Fig 19. Transmit timing in 16 mode

active

transmitter ready

active

16 baud rate clock

002aac41

td(IOW-INTL)

INT(1)(2)

IOW active

D0 D1 D2 D3 D4 D5 D6 D7

5 data bits

6 data bits

7 data bits

stop

bit

parity

bit

start

bit data bits (0 to 7)

next data

start

bit

td(start-INT)

td(IOW-TX)

(1) IRQ is active when TX FIFO is empty or TX FIFO drops below trigger level.

(2) IRQ is cleared when ISR is read or TX FIFO fills up to trigger level.

Fig 20. Transmit timing in 68 mode

D0 D1 D2 D3 D4 D5 D6 D7

active

TX ready

active

16 baud rate clock

002aac63

td(CS-IRQH)W

start

bit

td(start-IRQL)

IRQ(1)(2)

CS (write)

data bits (0 to 7)

active

td(CS-TX)W

5 data bits

6 data bits

7 data bits

parity

bit

stop

bit

next data

start

bit

Product data sheet Rev. 2 — 11 November 2010 46 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Fig 21. Infrare d transmit timing

Fig 22. Infrared receive timing

01010011 10

UART frame

TX data

1/2 bit time

002aaa21

data bitsstart stop

bit

time

IrDA TX data

3/16 bit time

01010011 10

UART frame

RX data

IrDA RX data

bit

time

002aaa21

start data bits stop

0 to 1 16× clock delay

Product data sheet Rev. 2 — 11 November 2010 47 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

11. Package outline

Fig 23. Package outline SOT617-1 (HVQFN32)

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

3.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT617-1 MO-220- - - - - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT617

-1

VQFN32: plastic thermal enhanced very thin quad flat package; no leads;

2 terminals; body 5 x 5 x 0.85 mm

A(1)

max.

detail X

y1C

916

32 25

terminal 1

index area

terminal 1

index area

01-08-08

02-10-18

1/2 e

1/2 e AC

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 2 — 11 November 2010 48 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Fig 24. Package outline SOT912-1 (TFBGA36)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT912-1

SOT912-

05-08-09

05-09-01

UNIT A

max

mm 1.15 0.25

0.15

0.90

0.75

0.35

0.25

3.6

3.4

3.6

3.4

DIMENSIONS (mm are the original dimensions)

FBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm

0 2.5 5 mm

scale

A2b D E e2

2.5

0.5

2.5

0.1

0.15

0.05

0.08

- - - - - -- - -

1/2 e

AC B

Cw M

ball A1

index area

246135

ball A1

index area

B A

detail X

Product data sheet Rev. 2 — 11 November 2010 49 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 2 — 11 November 2010 50 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

12.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 25) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 39 and 40

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 25.

Table 39. SnPb eutec t ic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 40. Lead-free process (from J-ST D-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 2 — 11 November 2010 51 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

13. Abbreviations

MSL: Moisture Sensitivity Level

Fig 25. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 41. Abbreviations

Acronym Description

CPU Central Processing Unit

DLL Di visor Latch LSB

DLM Divisor Latch MSB

FIFO First In, First Out

IrDA Infrared Data Association

ISDN Integrated Service Digital Network

LSB Least Significant Bit

MSB Most Significant Bit

PCB Printed-Circuit Board

RoHS Restriction of Hazardous Substances directive

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 2 — 11 November 2010 52 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

14. Revision history

Table 42. Revision history

Document ID Release d ate Data sheet status Change notice Supersedes

SC16C850 v.2 20101111 Product data sheet - SC16C850 v.1

Modifications: •Table 1 “Ordering information”:

–added Type number SC16C 850IBS/Q900

–added Table note [1]

•Figure 5 “Pin configuration for HVQFN32”: added Type number SC16C850IBS/Q900

•Table 2 “Pin description”, description of pin LOWPWR changed from “This pin has an internal

pull-down resistor, ...” to “This pin has a 22 kΩ internal pull-down resistor, ...”

•Table 8 “SC16C850 internal registers”, Table note [2] changed from “... and EFCR[2:1] are logic 0.”

to “... and EFCR2:0] are logic 000b.”

•Table 16 “LCR[5:3] parity selection”:

–second row changed from “X 0 1” to “0 0 1”

–fourth row changed from “0 0 1” to “1 0 1”

•Table 36 “Static characteristics”:

–VIL(clk): added condition “XTAL1 pin”

–VIH(clk): added condition “XTAL1 pin”

–VIL, condition “except XTAL1 clock”: appended “L OWPWR pin”

–VIL: added condition “LOWPWR pin”

–VIH, condition “except XTAL1 clock”: appended “LOWPWR pin”

–VIH: added condition “LOWPWR pin”

–VOH Min value for condition IOH =−4 mA and under column VDD = 3.3 V is changed from “2.0 V” to

“2.2 V”

–IDD Max value (for both VDD = 2.5 V and VDD = 3.3 V) changed from “2 mA” to “3 mA”

–added (new) Table note [1]

SC16C850 v.1 20080 110 Product data sheet - -

Product data sheet Rev. 2 — 11 November 2010 53 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed be tween

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whethe r or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reaso nably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the applicatio n or use by custo m er’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby exp ressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 11 November 2010 54 of 55

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automo tive use. It i s neither qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 11 November 2010

Document identifier: SC 16C8 50

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . . 9

6.1 UART selection. . . . . . . . . . . . . . . . . . . . . . . . . 9

6.2 Extended mode (128-byte FIFO) . . . . . . . . . . 10

6.3 Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10

6.4 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11

6.4.1 32-byte FIFO mode . . . . . . . . . . . . . . . . . . . . 11

6.4.2 128-byte FIFO mode . . . . . . . . . . . . . . . . . . . 11

6.5 Hardware flow control. . . . . . . . . . . . . . . . . . . 12

6.6 Software flow control . . . . . . . . . . . . . . . . . . . 12

6.7 Special character detect. . . . . . . . . . . . . . . . . 13

6.8 Interrupt priority and time-out interrupts . . . . . 13

6.9 Programmable baud rate generator . . . . . . . . 14

6.10 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 16

6.11 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.11.1 Conditions to enter Sleep mode . . . . . . . . . . . 18

6.11.2 Conditions to resume normal operation . . . . . 18

6.12 Low power feature . . . . . . . . . . . . . . . . . . . . . 18

6.13 RS-485 features . . . . . . . . . . . . . . . . . . . . . . . 19

6.13.1 Auto RS-485 RTS control. . . . . . . . . . . . . . . . 19

6.13.2 RS-485 RTS inversion . . . . . . . . . . . . . . . . . . 19

6.13.3 Auto 9-bit mode (RS-485). . . . . . . . . . . . . . . . 19

6.13.3.1 Normal Multi-drop mode. . . . . . . . . . . . . . . . . 19

6.13.3.2 Auto address detection. . . . . . . . . . . . . . . . . . 20

7 Register descriptions . . . . . . . . . . . . . . . . . . . 20

7.1 Transmit (THR) and Receive (RHR)

Holding Registers. . . . . . . . . . . . . . . . . . . . . . 23

7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 23

7.2.1 IER versus Tr ansmit/Receive FIFO

interrupt mode operation . . . . . . . . . . . . . . . . 24

7.2.2 IER versus Receive/Transmit FIFO

polled mode operation . . . . . . . . . . . . . . . . . . 24

7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 25

7.3.1 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 26

7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 27

7.6 Modem Control Register (MCR). . . . . . . . . . . 28

7.7 Line Status Register (LSR). . . . . . . . . . . . . . . 29

7.8 Modem Status Register (MSR). . . . . . . . . . . . 30

7.9 Extra Feature Control Register (EFCR) . . . . . 31

7.10 Scratchpad Register (SPR) . . . . . . . . . . . . . . 31

7.11 Divisor Latch (DLL and DLM). . . . . . . . . . . . . 31

7.12 Transmit FIFO Leve l Count (TXLVLCNT) . . . 31

7.13 Receive FIFO Level Count (RXLVLCNT). . . . 31

7.14 Enhanced Feature Register (EFR) . . . . . . . . 32

7.15 Transmit Interrupt Level Register (TXINTLVL) 33

7.16 Receive Interrupt Level Register (RXINTLVL) 33

7.17 Flow Control Trigger Level High (FLWCNTH) 34

7.18 Flow Control Trigger Level Low (FLWCNTL) . 34

7.19 Clock Prescaler (CLKPRES) . . . . . . . . . . . . . 34

7.20 RS-485 Turn-around time delay (RS485T IME) 35

7.21 Advanced Feature Control Register 2

(AFCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.22 Advanced Feature Control Register 1

(AFCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.23 SC16C850 external reset condition and

software reset . . . . . . . . . . . . . . . . . . . . . . . . 37

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Static characteristics . . . . . . . . . . . . . . . . . . . 38

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 39

10.1 Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 41

11 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 47

12 Soldering of SMD packages. . . . . . . . . . . . . . 49

12.1 Introduction to soldering . . . . . . . . . . . . . . . . . 49

12.2 Wave and reflow soldering. . . . . . . . . . . . . . . 49

12.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 49

12.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 50

13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 52

15 Legal information . . . . . . . . . . . . . . . . . . . . . . 53

15.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 53

15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 53

15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 54

16 Contact information . . . . . . . . . . . . . . . . . . . . 54

17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55