© 1999 Fairchild Semiconductor Corporation DS01 1603 www.fairchildsemi.com
March 1993
Revised December 1999
74LVX14 Low Voltage Hex Inverter with Schmitt Trigger Input
74LVX14
Low Voltage Hex Inverter with Schmitt Trigger Input
General Descript ion
The LVX14 contains six inverter gates each with a Schmitt
trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free out-
put signals. In addition, they have a greater noise margin
than conventional inverters.
The LVX14 has hy steresis betw een the posi tive-going a nd
negative-going input thresholds (typically 1.0V) which is
determi ned internally by transi stor ratios and is essen tially
insensitive to temperature and supply voltage variations.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
■Input voltage level translation from 5V to 3V
■Ideal for low power/low noise 3.3V applications
■Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Devices also ava ilable in Tape and R eel. Speci fy by append ing suffix lette r “X” to the ord ering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
Order Number Package Number Package Description
74LVX14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74LVX14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
InInputs
OnOutputs
Input Output
AO
LH
HL
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74LVX14
Absolute Maximum Ratings(No te 1) Recommended Operating
Conditions (Note 2)
Note 1: The “A bsolute Maxim um Ratin gs” are those valu es beyond w hich
the saf ety of the device cannot be guarante ed. The device should n ot be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not gua rant eed at the absolute maximum rati n gs.
The “Re comme nded Operat ing Co ndition s” table will define the cond itions
for actu al device op eration.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics (Note 3)
Note 3: Input tr = tf = 3ns
Supply Voltage (VCC)−0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V −20 mA
DC In put Voltage (VI)−0.5V to 7V
DC Output Diode Current (IOK)
VO = −0.5V −20 mA
VO = VCC + 0.5V +20 mA
DC Output Voltage (VO)−0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)±25 mA
DC VCC or Ground Current
(ICC or IGND)±50 mA
Storage Temperature (TSTG)−65°C to +150°C
Power Dissipation 180 mW
Supply Voltage (VCC) 2.0V to 3.6V
Input Voltage (VI)0V to 5.5V
Output Voltage (VO) 0V to VCC
Operating Temperature (TA)−40°C to +85°C
Symbol Parameter VCC TA = +25°CT
A = −40°C to +85°CUnits Conditions
Min Typ Max Min Max
Vt+Positive Threshold 3.0 2.2 2.2 V
Vt−Negative Threshold 3.0 0.9 0.9 V
VHHysteresis 3.0 0.3 1.2 0.3 1.2 V
VOH HIGH Level 2.0 1.9 2.0 1.9 IOH = −50 µA
Output Voltage 3.0 2.9 3.0 2.9 V VIN = VIL or VIH IOH = −50 µA
3.0 2.58 2.48 IOH = −4 mA
VOL LOW Level 2.0 0.0 0.1 0.1 IOL = 50 µA
Output Voltage 3.0 0.0 0.1 0.1 V VIN = VIL or VIH IOL = 50 µA
3.0 0.36 0.44 IOL = 4 mA
IIN Input Leakage Current 3.6 ±0.1 ±1.0 µAV
IN = 5.5V or GND
ICC Qui escent Supply Current 3.6 2.0 20 µAV
IN = VCC or GND
Symbol Parameter VCC
(V)
TA = 25°CUnits CL (pF)
Typ Limit
VOLP Quiet Output Maximum Dynamic VOL 3.3 0.3 0.5 V 50
VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.3 −0.5 V 50
VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50
VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50
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74LVX14
AC Electrical Characteristics
Note 4: Paramete r guarant eed by des ign. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|
Capacitance
Note 5: CPD is defined as t he v alue of the int ernal equivalent c apacitan c e w hic h is calculated fro m th e operating current co ns umptio n w it ho ut load.
Symbol Parameter VCC
(V)
TA = +25°CT
A = −40°C to +85°CUnits CL (pF)
Min Typ Max Min Max
tPLH Propagation 2.7 8.7 16.3 1.0 19.5
ns
15
tPHL Delay Time 11.2 19.8 1.0 23.0 50
3.3 ± 0.3 6.8 10.6 1.0 12.5 15
9.3 14.1 1.0 16.0 50
tOSLH Output to Output 2.7 1.5 1.5 ns 50
tOSHL Skew (Note 4) 3.3 1.5 1.5
Symbol Parameter TA = +25°CT
A = −40°C to +85°CUnits
Min Typ Max Min Max
CIN Input Capacitance 4 10 10 pF
CPD Power Dissipation 21 pF
Capacitance (Note 5)
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74LVX14
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
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74LVX14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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74LVX14 Low Voltage Hex Inverter with Schmitt Trigger Input
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does no t assume any responsibility for use of any circuitry de scribed, no circuit patent licenses ar e implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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