© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1Publication Order Number:
74HC574/D
74HC574
Octal 3−State Noninverting
D Flip−Flop
High−Performance Silicon−Gate CMOS
The 74HC574 is identical in pinout to the LS574. The device inputs
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
Data meeting the set−up time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip−flops but when Output Enable is high, all device
outputs are forced to the high−impedance state. Thus, data may be
stored even when the outputs are not enabled.
The HC574 is identical in function to the HC374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1.0 mA
•In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•ESD Performance: HBM > 2000 V; Machine Model > 200 V
•Chip Complexity: 266 FETs or 66.5 Equivalent Gates
•This is a Pb−Free Device
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1
20
MARKING
DIAGRAMS
HC
574
ALYW G
G
TSSOP−20
DT SUFFIX
CASE 948E
1
20
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
HC574 = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
74HC574
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2
Figure 1. Pin Assignment
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
VCC
CLOCK
Q7
Q6
Q5
Q4
FUNCTION TABLE
Inputs Output
OE Clock D Q
LHH
LLL
L L,H, X No Change
HXXZ
X = Don’t Care
Z = High Impedance
Figure 2. Logic Diagram
DATA
INPUTS
D0 219
Q0
D1
D2
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
3
4
5
6
7
8
9
11
1
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
Design Criteria Value Units
Internal Gate Count* 66.5 ea.
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0 mW
Speed Power Product 0.0075 pJ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
*Equivalent to a two−input NAND gate.
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage *0.5 to )7.0 V
VIDC Input Voltage *0.5 to VCC )0.5 V
VODC Output Voltage (Note 1) *0.5 to VCC )0.5 V
IIK DC Input Diode Current $20 mA
IOK DC Output Diode Current $35 mA
IODC Output Sink Current $35 mA
ICC DC Supply Current per Supply Pin $75 mA
IGND DC Ground Current per Ground Pin $75 mA
TSTG Storage Temperature Range *65 to )150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds 260 _C
TJJunction Temperature under Bias )150 _C
qJA Thermal Resistance TSSOP 128 _C/W
PDPower Dissipation in Still Air at 85_C TSSOP 450 mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
VESD ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
>2000
>200
V
ILatchup Latchup Performance Above VCC and Below GND at 85_C (Note 4) $300 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to EIA/JESD78.
5. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VI, VODC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types *55 )125 _C
tr, tfInput Rise and Fall Time (Figure 3) VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
ORDERING INFORMATION
Device Package Shipping†
74HC574DTR2G TSSOP−20* 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
(V)
Guaranteed Limit
Symbol Parameter Test Conditions *55 to 25_Cv85_Cv125_CUnit
VIH Minimum High−Level Input
Voltage
Vout = VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL Maximum Low−Level Input
Voltage
Vout = 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH Minimum High−Level Output
Voltage
Vin = VIH
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VOH Minimum High−Level Output
Voltage
Vin = VIH |Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
V
VOL Maximum Low−Level Output
Voltage
Vin = VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIL |Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Iin Maximum Input Leakage
Current
Vin = VCC or GND 6.0 $0.1 $1.0 $1.0 mA
IOZ Maximum Three−State
Leakage Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0 $0.5 $5.0 $10 mA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0 4.0 40 40 mA
7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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5
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns)
VCC
(V)
Guaranteed Limit
Symbol Parameter *55 to 25_Cv85_Cv125_CUnit
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 3 and 6)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
160
105
32
27
200
145
40
34
240
190
48
41
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
2.0
3.0
4.5
6 0
140
90
28
24
175
120
35
30
210
140
42
36
ns
tTLH,
tTHL
Maximum Output Transition Time, any Output
(Figures 3 and 6)
2.0
3.0
4.5
6.0
60
27
12
10
75
32
15
13
90
36
18
15
ns
Cin Maximum Input Capacitance 10 10 10 pF
Cout Maximum Three−State Output Capacitance, Output in High−Impedance
State
15 15 15 pF
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Enabled Output)* 24 pF
*Used to determine the no−load dynamic power consumption: PD = CPD V
CC2f + ICC V
CC. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (CL = 50 pF; Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC – 55 to 25_Cv 85_Cv 125_C
Symbol Parameter Figure (V) Min Max Min Max Min Max Unit
tsu Minimum Setup Time, Data to Clock 5 2.0
3.0
4.6
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
thMinimum Hold Time, Clock to Data 5 2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
twMinimum Pulse Width, Clock 3 2.0
3.0
4.5
6.0
75
60
15
13
95
80
19
16
110
90
22
19
ns
tr, tfMaximum Input Rise and Fall Times 3 2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
74HC574
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6
Figure 3. Figure 4.
CLOCK
Q
trtf
VCC
GND
90%
50%
10%
90%
50%
10%
tPLH tPHL
tTLH tTHL
tw
1/fmax Q
Q
1.3 V
1.3 V
90%
10%
tPZL tPLZ
tPZH tPHZ
3.0 V
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
SWITCHING WAVEFORMS
Figure 5. Figure 6.
Figure 7. Test Circuit
Figure 8. Expanded Logic Diagram
50%CLOCK
VCC
VALID
GND
VCC
GND
tsu th
50%DATA
*Includes all probe and jig capacitance.
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance.
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
C
DQ
2
D0
19 Q0
C
DQ
3
D1
18 Q1
C
DQ
4
D2
17 Q2
C
DQ
5
D3
16 Q3
C
DQ
6
D4
15 Q4
C
DQ
7
D5
14 Q5
C
DQ
8
D6
13 Q6
C
DQ
9
D7
12 Q7
11
CLOCK
1
OUTPUT ENABLE
74HC574
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7
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
110
1120
PIN 1
IDENT
A
B
−T−
0.100 (0.004)
C
DGH
SECTION N−N
K
K1
JJ1
N
N
M
F
−W−
SEATING
PLANE
−V−
−U−
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
−−− −−−
S
U0.15 (0.006) T
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
74HC574/D
LITERATURE FULFILLMENT:
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P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
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