TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32,768-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC55257DPL/DFL/DFTL/DTRL is a 262,144-bit static random access memory (SRAM) organized as 32,768 words by 8 bits. Fabricated using Toshibas CMOS Silicon gate process technology, this device operates from a single 2.7 to 5.5 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 5 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.3 A standby current (typ) when chip enable (CE) is asserted high. There are two control inputs. CE is used to select the device and for data retention control, and output enable (OE) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. The TC55257DPL/DFL/DFTL/DTRL is available in a standard plastic 28-pin dual-in-line package (DIP), plastic 28-pin small-outline package (SOP) and normal and reverse pinout plastic 28-pin thin-small-outline package (TSOP). FEATURES @ Low-power dissipation @ Access Times (maximum): Operating: 27.5 mW/MHz (typical) 5V + 10% 2.7 to 5.5V @ Standby current of 2 A (maximum) at -55V | -70V | -85V | -55V/4-70V | -85V Ta = 25C Access Time 55ns | 70ns | 85ns 120 ns 150 ns e Single power Supply voltage of 2.7t05.5 V CE Access Time | 55ns | 70ns | 85ns 120 ns 150 ns @ Power down features using CK. = : Data retention supply voltage of 2 to 5.5 V OE Access Time] 30ns | 35ns | 45ns 70 ns 75 ns Direct TTL compatibility for all inputs and @ Packages: outputs DIP28-P-600-2.54(DPL) (Weight: 4.42 g typ) SOP28-P-450-1.27 (DFL) (Weight: 0.79 g typ) TSOP I 28-P-0.55(DFTL) (Weight: 0.22 g typ) TSOP I 28-P-0.55A (DTRL) (Weight: 0.22 g typ) PIN ASSIGNMENT (TOP VIEW) o 28 PIN DIP & SOP o 28 PIN TSOP (Normal pinout) (Reverse pinout) > aia (1 28 1] Vop AMUN TAA ai2Q2 27 Ll Rw na 1 1 4 a7 [3 26 1 ai3 a6 La 25 [as as U5 24 [ag aalle 23 fan a3 7 22 [OE azls 21 [1 ato ail 20 1 ce ao [10 19 [1 vos vor 11 18 [1 vo7 vo2 [12 17 [1 vos vo3 013 16 [1 vos eno [14 15 [I oa hs 28 28 19 PIN NAMES AO to A14_ | Address Inputs PIN NO. 1/2;)3)]4 5 6 7 8 9 | 10} 11] 12] 13) 14 Raw Reac/Write Control PIN NAME] OE |Ay1] Ag | Ag | A13 [RW] Vpp| Ara | A12| Az | As | As | Aa | Aa OE utput Enable PIN NO. [15/16] 17] 18 | 19 | 20] 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 CE Chip Enable 701 to /08 | Data Input/Output PIN NAME] Azo | Aq | Ao |1/01 11/02} 1/03 |GND} 1/04 |1/05 | 1/06] 1/07/1/08) CE |Ai Vop Power GND Ground 961001EBA1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-08-05 1/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V BLOCK DIAGRAM Ee ao Vv AS wn n op AG now n ~o GND A7 ce | foe ws MEMORY CELL nN aL) |oa ARRAY Alt =! si 512 x 64x 8 we a (262144) Al3 S S SENSE AMP COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER DATA CONTROL os GENERATOR CLOCK AO A1 A2 A3 A4A10 OPERATION MODE MODE CE 01 to /O8 Read Dout Write Din Outputs Disabled High-Z Stand High-Z Note: x = dontcare. H = logic high. L = logic low. ABSOLUTE MAXIMUM _ RATINGS SYMBOL RATING VALUE UNIT Vop Power Supply Voltage - 0.3 to 7.0 Vv Vin Input Voltage 0.3* to 7.0 Vv Vio Input/Output Voltage - 0.5* to Vpp + 0.5 Vv Pp Power Dissipation 1.0/0.6 ** Ww Tsolder Soldering Temperature (10s) 260 C Tstrg Storage Temperature - 55 to 150 C Topr Operating Temperature 0 to 70 C * 3.0 V when measured at a pulse width of 50 ns ** SOP 1998-08-05 2/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V DC RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70C) SYMBOL PARAMETER MIN 10% MAX MIN 27 te 5-5 V MAX UNIT Vop Power Supply Voltage 4.5 - 5.5 2.7 - 5.5 Vin Input High Voltage 2.2 - Vpp + 0.3 | Vpp - 0.2 - Vpp + 0.3 y Vi Input Low Voltage - 0.3* - 0.8 - 0.3* - 0.2 Vou Data Retention Supply Voltage 2.0 - 5.5 2.0 - 5.5 * 3.0 V when measured at a pulse width of 50 ns DC CHARACTERISTICS (Ta = 0 to 70C, Vpp = 3V + 10%) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT lit Input Leakage Current Vin = OV to Vpp - - + 1.0 LA lou Output High Current Vou = 2.4V - 1.0 - - mA lot Output Low Current VoL = 0.4V 4.0 - - mA CE = Vin or RAW = Vi_ or OE = Viy lLo Output Leakage Current - - + 1.0 pA Vout = 0V to Vpp CE = Vin teycle = 1 48 - 10 - RW = Vin Ippo1 Other Inputs = Viy/ViL teyele = min - - 70 mA lour = OMA Operating Current CE = 0.2V toycle = 14S - 5 - RW = Vpp - 0.2V Ippo2 Other Inputs tole = min - - 0 mA = Vpp 0.2 V/0.2V lour = OmA Ipps1 Standby Current CE = Vin - - 3 mA CE = Vpp - 0.2V Ta=0 to 7oc}] - - 20 pA Ipps2 Standby Current Vop = 2.0 to 5.5V Ta = 25C - 0.3 2 pA 1998-08-05 3/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V DC CHARACTERISTICS (Ta = 0 to 70C, Vpp = 5V + 10%) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT li Input Leakage Current Vin = OV to Vpp - - + 1.0 rN lou Output High Current Vou = Vpp - 0.2V - 0.1 - - mA lot Output Low Current Vot = 0.2V 0.1 - - mA CE = Viy or RAW = Vi, or lLo Output Leakage Current | __ IH IL - - + 1.0 vA OE = Vin, Vout = OV to Vop CE = 0.2V : RIW = Vpp - 0.2V mm - 20 Ippo2 | Operating Current = DD , Tcycle mA lout = OMA 1 Other Inputs = Vpp 0.2 V/0.2 V us ~ ~ 5 Vpp = Ta = 25C - 1 1.5 3V 410% |Ta=0to 70C] - - 15 Ipps2__- | Standby Current CE = Vpp - 0.2V Ta = 25C - - 1 vA Vpp = 3.0V |Ta = 0 to 40C - - 2 Ta = 0 to 70C - - 10 CAPACITANCE (Ta = 25C, f = 1 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT Cin Input Capacitance Vin = GND 10 c : Pp Cout Output Capacitance Vout = GND 10 Note: This parameter is periodically sampled and is not 100% tested. 1998-08-05 4/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0 to 70C, Vpp = 5V + 10%) READ CYCLE TC55257DPL/DFL/DFTL/DTRL SYMBOL PARAMETER -55V -70V -85V UNIT MIN MAX MIN MAX MIN MAX tre Read Cycle Time 55 - 70 - 85 - tacc Address Access Time - 55 - 70 - 85 tco Chip Enable Access Time - 55 - 70 - 85 tor Output Enable Access Time - 30 - 35 - 45 tcoe Chip Enable Low to Output Active 10 - 10 - 10 - ns toceE Output Enable Low to Output Active 5 - 5 - 5 - top Chip Enable High to Output High-Z - 20 - 25 - 30 topo Output Enable High to Output High-Z - 20 - 25 - 30 tou Output Data Hold Time 10 - 10 - 10 - WRITE CYCLE TC55257DPL/DFL/DFTL/DTRL SYMBOL PARAMETER -55V -70V -85V UNIT MIN MAX MIN MAX MIN MAX twe Write Cycle Time 55 - 70 - 85 - twp Write Pulse Width 45 - 50 - 60 - tow Chip Enable to End of Write 50 - 60 - 65 - tas Address Setup Time 0 - 0 - 0 - twr Write Recovery Time 0 - 0 - 0 - ns topw RAW Low to Output High-Z - 20 - 25 - 30 toew RAW High to Output Active 5 - 5 - 5 - tos Data Setup Time 25 - 30 - 40 - toy Data Hold Time 0 - 0 - 0 - AC TEST CONDITIONS Output load: 30 pF + one TTL gate (-55V) 100 pF + one TTL gate (-70L, -85L) Input pulse level: 0.6 V, 2.4 V Timing measurements: 1.5 V Reference level: 1.5 V tr, te: 5 ns 1998-08-05 5/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0 to 70C, Vpp = 2.7 to 5.5 V) READ CYCLE TC55257DPL/DFL/DFTL/DTRL SYMBOL PARAMETER -55V/-70V -B5V UNIT MIN MAX MIN MAX tre Read Cycle Time 120 - 150 - tacc Address Access Time - 120 - 150 tco Chip Enable Access Time - 120 - 150 toe Output Enable Access Time - 70 - 75 tcoe Chip Enable Low to Output Active 10 - 10 - ns tore Output Enable Low to Output Active 5 - 5 - top Chip Enable High to Output High-Z - 50 - 50 topo Output Enable High to Output High-Z - 50 - 50 ton Output Data Hold Time 10 - 10 - WRITE CYCLE TC55257DPL/DFL/DFTL/DTRL SYMBOL PARAMETER -55V/-70V -85V UNIT MIN MAX MIN MAX twe Write Cycle Time 120 - 150 - twe Write Pulse Width 80 - 100 - teow Chip Enable to End of Write 100 - 120 - tas Address Setup Time 0 - 0 - twr Write Recovery Time 0 - 0 - ns topw RAW Low to Output High-Z - 50 - 50 toew RAW High to Output Active 5 - 5 - tos Data Setup Time 50 - 60 - toy Data Hold Time 0 - 0 - AC TEST CONDITIONS Output load: 100 pF (including jig) Input pulse level: 0.2 V, Vpp 0.2 V Timing measurements: 1.5 V Reference level: 1.5 V tr, tr: 5 ns 1998-08-05 6/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V TIMING DIAGRAMS tre ADDRESS Dour VALID DATA OUT INDETERMINATE WRITE CYCLE 1 (R/W CONTROLLED) See Note 4) twe ADDRESS RAW CE Dout tou Din Note 5) VALID DATA IN 1998-08-05 7/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V WRITE CYCLE 2 (GE CONTROLLED) (ee Note 4) twe ADDRESS R/AW CE Dout toy Din Note 5) VALID DATA IN Note 5) Note: (1) R/W remains HIGH for the read cycle. (2) If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OF is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 1998-08-05 8/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V DATA RETENTION CHARACTERISTICS (Ta = 0 to 70C) SYMBOL PARAMETER MIN TYP MAX UNIT VoH Data Retention Supply Voltage 2.0 - 5.5 v | Standby Vou = 3.0V 1 A tan urrent DDS2 y Vou = 5.5V _ _ 20 a Chip Deselect to Data Retention tcpr ; 0 - - Mode Time ns tr Recovery Time tre (See Note) - = * 2 vA(max) at Ta = 0 to 40C Note: Read cycle time. CE CONTROLLED DATA RETENTION MODE Vpp DATA RETENTION MODE 4a5V --SSoo STN rrr srsrcscs (See Note) (See Note) Viq TTT \ CE Vop - 0.2V tepr GND Note: When CE is operating at the Vyq level (2.2 V), the standby current is given by Ippsi during the transition of Vpp from 4.5 to 2.4 V. 1998-08-05 9/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V PACKAGE DIMENSIONS (DIP28-P-600-2.54) Units in mm fa 28 15 Y Cod od) od) od od od Od dd od dd oO N st +! N o wn vf = +8, aq CIreroerocrcey cy Cy er CI CI Cy CIC Co ao 4 14 =f 37.5 MAX 37.040.2 3.5403 1.99 Typ Weight: 4.42 g (typ) 1998-08-05 10/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V PACKAGE DIMENSIONS (SOP28-P-450-1.27) Units in mm TOOORRBAAggeot 47 ) me CUUCHUGHoh 0.995TYP 0.43+0.1 510.25 Gi) 8.840.2 11.840.3 (450mil) 1.27] L 19,0MAx _. 18.520.2 8 i eo 0 770.11 S L Weight: 0.79 g (typ) 1998-08-05 11/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V PACKAGE DIMENSIONS (TSOP I 28-P-0.55) 0.08 ' 0 14 : j 11.8+0.2 | 18 > " . in - 13.440.2 - S . . 3 a \ IX Ps, Weight: 0.22 g (typ) Units in mm Coy 8.2MAX 7.9+0.1 1.040.1 |_0-140.05 1998-08-05 12/13TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-70V,-85V PACKAGE DIMENSIONS (TSOP I 28-P-0.55A) Units in mm 0.08 8.2MAX 7.9+0.1 HOB BAR REBAR OE 15 | | 14 1.0+0.1 | || 0.1+0.05 7 0.375TYP Weight: 0.22 g (typ) 1998-08-05 13/13