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SCLS559 − JANUAR Y 2004
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DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product-Change Notification
DQualification Pedigree
DWide Operating Voltage Range of 2 V to 6 V
DOutputs Can Drive Up To 10 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 13 ns
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D±4-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
DSynchronous Load
DDirect Overriding Clear
DParallel-to-Serial Conversion
description/ordering information
This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding
clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high,
SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock
(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on
the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
−40°C to 85°C
SOIC − D Tape and reel SN74HC166AIDREP SHC166IEP
−40
°
C to 85
°
C
TSSOP − PW Tape and reel SN74HC166AIPWREP§SHC166IEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
§Product Preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SER
A
B
C
D
CLK INH
CLK
GND
VCC
SH/LD
H
QH
G
F
E
CLR
D OR PW PACKAGE
(TOP VIEW)
Copyright 2004, Texas Instruments Incorporated
   ! "#$ !  %#&'" ($)
(#"! "  !%$""! %$ *$ $!  $+! !#$!
!(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($
$!.  '' %$$!)
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SCLS559 − JANUAR Y 2004
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FUNCTION TABLE
INPUTS
OUTPUTS
INPUTS
INTERNAL
CLR SH/LD CLK INH CLK SER PARALLEL
A...H QAQBQH
L X X X X X L L L
HXLLX XQ
A0 QB0 QH0
HLLX a...h a bh
HHLHXHQAn QGn
HHLLXLQAn QGn
H X H X X QA0 QB0 QH0
logic diagram (positive logic)
1D
C1
15
9
7
6
13
SH/LD
CLR
CLK
CLK INH
Q
H
234510111214
SER
ABCDEFGH
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1
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typical clear, shift, load, inhibit, and shift sequence
Clear Load
Inhibit
H
H
H
H
H
H HHHH
LLL
L
L
L
CLK
CLK INH
SER
A
B
C
D
E
F
G
H
SH/LD
CLR
QH
Parallel
Inputs
Serial Shift Serial Shift
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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SCLS559 − JANUAR Y 2004
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recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 V
VIH
High-level input voltage
VCC = 6 V 4.2
V
VCC = 2 V 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 V
VIL
Low-level input voltage
VCC = 6 V 1.8
V
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
VCC = 2 V 1000
t/vInput transition rise/fall time VCC = 4.5 V 500 ns
t/v
Input transition rise/fall time
VCC = 6 V 400
ns
TAOperating free-air temperature −40 85 °C
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX
MIN
MAX
UNIT
2 V 1.9 1.998 1.9
I
OH
= −20 µA4.5 V 4.4 4.499 4.4
V
OH
V
= V
or V
IOH = −20 µA
6 V 5.9 5.999 5.9 V
VOH
IOH = −4 mA 4.5 V 3.98 4.3 3.84
V
IOH = −5.2 mA 6 V 5.48 5.8 5.34
2 V 0.002 0.1 0.1
I
OL
= 20 µA4.5 V 0.001 0.1 0.1
V
OL
V
= V
or V
IOL = 20 µA
6 V 0.001 0.1 0.1 V
VOL
IOL = 4 mA 4.5 V 0.17 0.26 0.33
V
IOL = 5.2 mA 6 V 0.15 0.26 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 8 80 µA
Ci2 V to 6 V 3 10 10 pF
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SCLS559 − JANUAR Y 2004
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timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C
MIN
MAX
UNIT
V
CC MIN MAX
MIN
MAX
UNIT
2 V 6 5
f
clock
Clock frequency 4.5 V 31 25 MHz
fclock
Clock frequency
6 V 36 29
MHz
2 V 100 125
CLR low 4.5 V 20 25
tw
Pulse duration
CLR low
6 V 17 21
ns
twPulse duration 2 V 80 100 ns
CLK high or low 4.5 V 16 20
CLK high or low
6 V 14 17
2 V 145 180
SH/LD high before CLK4.5 V 29 36
SH/LD high before CLK
6 V 25 31
2 V 80 100
SER before CLK4.5 V 16 20
SER before CLK
6 V 14 17
2 V 100 125
t
su
Setup time CLK INH low before CLK4.5 V 20 25 ns
tsu
Setup time
CLK INH low before CLK
6 V 17 21
ns
2 V 80 100
Data before CLK4.5 V 16 20
Data before CLK
6 V 14 17
2 V 40 50
CLR inactive before CLK4.5 V 8 10
CLR inactive before CLK
6 V 7 9
2 V 0 0
SH/LD high after CLK4.5 V 0 0
SH/LD high after CLK
6 V 0 0
2 V 5 5
SER after CLK4.5 V 5 5
th
Hold time
SER after CLK
6 V 5 5
ns
t
h
Hold time
2 V 0 0
ns
CLK INH high after CLK4.5 V 0 0
CLK INH high after CLK
6 V 0 0
2 V 5 5
Data after CLK4.5 V 5 5
Data after CLK
6 V 5 5
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SCLS559 − JANUAR Y 2004
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX
MIN
MAX
UNIT
2 V 611 5
f
max
4.5 V 31 36 25 MHz
fmax
6 V 36 45 29
MHz
2 V 62 120 150
t
PHL
CLR Q
H
4.5 V 18 24 30 ns
tPHL
CLR
QH
6 V 13 20 26
ns
2 V 75 150 190
t
pd
CLK Q
H
4.5 V 15 30 38 ns
tpd
CLK
QH
6 V 13 26 32
ns
2 V 38 75 95
t
t
Any 4.5 V 8 15 19 ns
tt
Any
6 V 6 13 16
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 50 pF
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SCLS559 − JANUAR Y 2004
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PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50% VCC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74HC166AIDREP ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/04690-01XE ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74HC166A-EP :
Automotive: SN74HC166A-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC166AIDREP SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Nov-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC166AIDREP SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Nov-2008
Pack Materials-Page 2
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