CD74HC541EE4 - Texas Instruments High-Performance Analog

Data sheet acquired from Harris Semiconductor

SCHS189C

Features

• ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting

• ’HC541, ’HCT541. . . . . . . . . . . . . . . . . . . . . . Non-In verting

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capability

• Typical Propagation Delay = 9ns at VCC = 5V,

CL = 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC540 and CD74HCT540 are Inverting Octal Buffers

and Line Drivers with Three-State Outputs and the capability

to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are Non-

Inverting Octal Buffers and Line Drivers with Three-State Out-

puts that can drive 15 LSTTL loads. The Output Enables

(OE1) and (OE2) control the Three-State Outputs. If either

OE1 or OE2 is HIGH the outputs will be in the high imped-

ance state. For data output OE1 and OE2 both must be LOW.

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC540F3A -55 to 125 20 Ld CERDIP

CD54HC541F3A -55 to 125 20 Ld CERDIP

CD54HCT541F3A -55 to 125 20 Ld CERDIP

CD74HC540E -55 to 125 20 Ld PDIP

CD74HC540M -55 to 125 20 Ld SOIC

CD74HC540M96 -55 to 125 20 Ld SOIC

CD74HC541E -55 to 125 20 Ld PDIP

CD74HC541M -55 to 125 20 Ld SOIC

CD74HC541M96 -55 to 125 20 Ld SOIC

CD74HC541PW -55 to 125 20 Ld TSSOP

CD74HC541PWR -55 to 125 20 Ld TSSOP

CD74HCT540E -55 to 125 20 Ld PDIP

CD74HCT540M -55 to 125 20 Ld SOIC

CD74HCT540M96 -55 to 125 20 Ld SOIC

CD74HCT541E -55 to 125 20 Ld PDIP

CD74HCT541M -55 to 125 20 Ld SOIC

CD74HCT541M96 -55 to 125 20 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

January 1998 - Revised July 2004

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC540, CD74HCT540,

CD54/74HC541, CD54/74HCT541

High-Speed CMOS Logic

Octal Buffer and Line Drivers, Three-State

[ /Title

(CD74

HC540

CD74

HCT54

CD74

HC541

CD74

HCT54

Functional Diagram

Pinouts CD54HC540

(CERDIP)

CD74HC540, CD74HCT540

(PDIP, SOIC)

TOP VIEW

CD54HC541, CD54HCT541

(CERDIP)

CD74HC541

(PDIP, SOIC, TSSOP)

CD74HCT541

(PDIP, SOIC)

TOP VIEW

GND

VCC

OE2

OE1

GND

VCC

OE2

D0Y0

OEAOEB

540 541

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

TRUTH TABLE

INPUTS OUTPUTS

OE1 OE2 An 540 541

LLHLH

HXXZZ

XHXZZ

LLLHL

H = HIGH Voltage Level

L = LOW Voltage Level

X= Don’t Care

Z = High Impedance

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, IO

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - -V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - -V

6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

Three-State Leakage

Current IOZ VIL or VIH VO =

VCC or

GND

6--±0.5 - ±5.0 - ±10 µA

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-6 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

6 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC and

GND 0 5.5 - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Three-State Leakage

Current IOZ VIL or VIH VO =

VCC or

GND

5.5 - - ±0.5 - ±5.0 - ±10 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC

(Note 2) VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT

UNIT LOADS

HCT540 HCT541

A0 - A7 1 0.4

OE2 0.75 0.75

OE1 1.15 1.15

NOTE: UnitLoadis∆ICC limitspeciﬁcinDCElectrical Speciﬁcations

Table, e.g., 360µA max. at 25oC.

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Switching Speciﬁcations CL = 50pF, Input tr, tf= 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay tPLH, tPHL CL = 50pF

Data to Outputs (540) 2 - - 110 - 140 - 165 ns

4.5 - - 22 - 28 - 33 ns

CL = 15pF 5 - 9 - - - - - ns

CL = 50pF 6 - - 19 - 24 - 28 ns

Data to Outputs (541) tPLZ,t

PHZ CL = 50pF 2 - - 115 - 145 - 175 ns

4.5 - - 23 - 29 - 35 ns

CL = 15pF 5 - 9 - - - - - ns

CL = 50pF 6 - - 20 - 25 - 30 ns

Output Enable and Disable

to Outputs (540) tPLZ,t

PHZ CL = 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns

CL = 15pF 5 - 13 - - - - - ns

CL = 50pF 6 - - 27 - 34 - 41 ns

Output Enable and Disable

to Outputs (541) tPLZ,t

PHZ CL = 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns

CL = 15pF 5 - 14 - - - - - ns

CL = 50pF 6 - - 23 - 29 - 35 ns

Output Transition Time tTHL, tTLH CL = 50pF 2 - - 60 - 75 - 90 ns

4.5 - - 12 - 15 - 18 ns

6 - - 10 - 13 - 15 ns

Input Capacitance CICL = 50pF - 10 - 10 - 10 - 10 pF

Three-State Output

Capacitance CO- - 20 - 20 - 20 - 20 pF

Power Dissipation Capacitance

(Notes 3, 4) (540) CPD CL = 15pF 5 - 50 - - - - - pF

Power Dissipation Capacitance

(Notes 3, 4) (541) CPD CL = 15pF 5 - 48 - - - - - pF

HCT TYPES

Propagation Delay tPHL, tPLH

Data to Outputs (540) CL = 50pF 4.5 - - 24 - 30 - 36 ns

CL = 15pF 5 - 9 - - - - - ns

Data to Outputs (541) tPHL, tPLH CL = 50pF 4.5 - - 28 - 35 - 42 ns

CL = 15pF 5 - 11 - - - - - ns

Output Enable and Disable

to Outputs (540, 541) tPLZ,t

PHZ CL = 50pF 4.5 - - 35 - 44 - 53 ns

CL = 15pF 5 - 14 - - - - - ns

Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 12 - 15 - 18 ns

Input Capacitance CICL = 50pF - 10 - 10 - 10 - 10 pF

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Three-State Output

Capacitance CO- - 20 - 20 - 20 - 20 pF

Power Dissipation Capacitance

(Notes 3, 4) (540, 541) CPD CL = 15pF 5 - 55 - - - - - pF

NOTES:

3. CPD is used to determine the dynamic power consumption, per channel.

4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Switching Speciﬁcations CL = 50pF, Input tr, tf= 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 3. HC THREE-STATE PROPAGATION DELAY

WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

50% 10%

90%

VCC

10%

90% 50%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

UTPUT HIGH

TO OFF

OUTPUTS

ENABLED OUTPUTS

DISABLED OUTPUTS

ENABLED

6ns 6ns

tPZH

tPHZ

tPZL

tPLZ

0.3

2.7

10%

90%

1.3V

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

UTPUT HIGH

TO OFF

OUTPUTS

ENABLED OUTPUTS

DISABLED OUTPUTS

ENABLED

tr6ns

tPZH

tPHZ

tPZL

tPLZ

6ns tf

1.3

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

Test Circuits and Waveforms (Continued)

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

IED HIGH

OR LOW

OUTPUT

DISABLE

VCC FOR tPLZ AND tPZL

GND FOR tPHZ AND tPZ

OUTPUT

RL = 1kΩ

50pF

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CD54HC540F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type

CD54HC541F ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type

CD54HC541F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type

CD54HCT541F ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type

CD54HCT541F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type

CD74HC540E ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HC540EE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HC540M ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC540M96 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC540M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC540M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC540ME4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC540MG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541E ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HC541EE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HC541M ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541M96 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541MG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541PW ACTIVE TSSOP PW 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541PWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC541PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT540E ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

PACKAGE OPTION ADDENDUM

www.ti.com 11-Nov-2009

Addendum-Page 1

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CD74HCT540EE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT540M ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT540M96 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT540M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT540M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT540MG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT541E ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT541EE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT541M ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT541M96 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT541M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT541M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT541ME4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT541MG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

PACKAGE OPTION ADDENDUM

www.ti.com 11-Nov-2009

Addendum-Page 2

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Nov-2009

Addendum-Page 3

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CD74HC540M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

CD74HC541M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

CD74HC541PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

CD74HCT540M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

CD74HCT541M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC540M96 SOIC DW 20 2000 367.0 367.0 45.0

CD74HC541M96 SOIC DW 20 2000 367.0 367.0 45.0

CD74HC541PWR TSSOP PW 20 2000 367.0 367.0 38.0

CD74HCT540M96 SOIC DW 20 2000 367.0 367.0 45.0

CD74HCT541M96 SOIC DW 20 2000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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