LP3892EMR-1.2/NOPB - Texas Instruments

LP3892

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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

LP3892 1.5A Fast-Response Ultra Low Dropout Linear Regulators

Check for Samples: LP3892

1FEATURES DESCRIPTION

The LP3892 is a high current, fast response regulator

2• Ultra Low Dropout Voltage (140 mV at 1.5A which can maintain output voltage regulation with

typ) minimum input to output voltage drop. Fabricated on

• Low Ground Pin Current a CMOS process, the device operates from two input

• Load Regulation of 0.04%/A voltages: Vbias provides voltage to drive the gate of

the N-MOS power transistor, while Vin is the input

• 60 nA Typical Quiescent Current in Shutdown voltage which supplies power to the load. The use of

• 1.5% Output Accuracy (25°C) an external bias rail allows the part to operate from

• TO-220, DDPAK/TO-263 and SO PowerPAD-8 ultra low Vin voltages. Unlike bipolar regulators, the

Packages CMOS architecture consumes extremely low

quiescent current at any output load current. The use

• Over Temperature/Over Current Protection of an N-MOS power transistor results in wide

•−40°C to +125°C Junction Temperature Range bandwidth, yet minimum external capacitance is

required to maintain loop stability.

APPLICATIONS The fast transient response of these devices makes

• DSP Power Supplies them suitable for use in powering DSP,

Microcontroller Core voltages and Switch Mode

• Server Core and I/O Supplies Power Supply post regulators. The parts are available

• PC Add-in-Cards in TO-220, DDPAK/TO-263 and SO PowerPAD-8

• Local Regulators in Set-Top Boxes packages.

• Microcontroller Power Supplies Dropout Voltage:140mV (typ) at 1.5A load current.

• High Efficiency Power Supplies Ground Pin Current: 3 mA (typ) at full load.

• SMPS Post-Regulators Shutdown Current: 60 nA (typ) when S/D pin is low.

Precision Output Voltage: 1.5% room temperature

accuracy.

TYPICAL APPLICATION CIRCUIT

At least 10 µF of input and output capacitance is required for stability.

*Tantalum capacitors are recommended. Aluminum electrolytic capacitors may be used for restricted temperature

range. See application hints.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

GND

VIN

S/D

VBIAS

GND

VOUT N/C

GND

VOUT

LP3892

SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAM

Figure 1. TO-220, Top View Figure 2. DDPAK/TO-263, Top View

Figure 3. SO PowerPAD-8, Top View

white space

BLOCK DIAGRAM

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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

ABSOLUTE MAXIMUM RATINGS (1)

VALUE / UNITS

Storage Temperature Range −65°C to +150°C

Lead Temp. (Soldering, 5 seconds) 260°C

ESD Rating

Human Body Model (2) 2 kV

Machine Model (3) 200V

Power Dissipation (4) Internally Limited

VIN Supply Voltage (Survival) −0.3V to +6V

VBIAS Supply Voltage (Survival) −0.3V to +7V

Shutdown Input Voltage (Survival) −0.3V to +7V

IOUT (Survival) Internally Limited

Output Voltage (Survival) −0.3V to +6V

Junction Temperature −40°C to +150°C

(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For specifications, see Electrical

Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.

(2) The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.

(3) The machine model is a 220 pF capacitor discharged directly into each pin. The machine model ESD rating of pin 5 is 100V.

(4) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values.

θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be

assumed. θJ-A for DDPAK/TO-263 devices is approximately 40°C/W if soldered down to a copper plane which is at least 1.5 square

inches in area. θJ-A value for typical SO PowerPAD-8 PC board mounting is 166°C/W. If power dissipation causes the junction

temperature to exceed specified limits, the device will go into thermal shutdown.

RECOMMENDED OPERATING CONDITIONS VALUE / UNITS

VIN (VOUT + VDO) to 5.5V

Shutdown 0 to +6V

IOUT 1.5A

Junction Temperature −40°C to +125°C

VBIAS 4.5V to 6V

Product Folder Links: LP3892

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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

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ELECTRICAL CHARACTERISTICS

Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL= 10 mA, CIN = COUT = 10µF, VS/D = VBIAS.

Typical

Symbol Parameter Conditions MIN (1) MAX (1) Units

(2)

VOOutput Voltage Tolerance 10 mA ≤IL≤1.5A, 1.198 1.234

1.216

VO(NOM) + 1V ≤VIN ≤5.5V, 1.186 1.246

4.5V ≤VBIAS ≤6V 1.478 1.522

1.5 V

1.455 1.545

1.773 1.827

1.8

1.746 1.854

ΔVO/ΔVIN Output Voltage Line Regulation(3) (4) VO(NOM) + 1V ≤VIN ≤5.5V 0.01 %/V

ΔVO/ΔILOutput Voltage Load Regulation (5) 10 mA ≤IL≤1.5A 0.04 %/A

0.06

VDO Dropout Voltage (6) IL= 1.5A (TO-220 and DDPAK/TO-263 320

140

only) 500 mV

IL= 1.5A (SO PowerPAD only) 340

155 550

IQ(VIN) Quiescent Current Drawn from VIN 10 mA ≤IL≤1.5A 7

3 mA

Supply 8

VS/D ≤0.3V 1

0.03 µA

IQ(VBIAS) Quiescent Current Drawn from VBIAS 10 mA ≤IL≤1.5A 2

1 mA

Supply 3

VS/D ≤0.3V 1

0.03 µA

ISC Short-Circuit Current VOUT = 0V 4.3 A

Shutdown Input

VSDT Output Turn-off Threshold Output = ON 1.3 0.7 V

Output = OFF 0.7 0.3

Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 µs

Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15

IS/D S/D Input Current VS/D =1.3V 1 µA

VS/D ≤0.3V −1

AC Parameters

PSRR Ripple Rejection for VIN Input Voltage VIN = VOUT +1V, f = 120 Hz 80

(VIN)VIN = VOUT + 1V, f = 1 kHz 65 dB

PSRR Ripple Rejection for VBIAS Voltage VBIAS = VOUT + 3V, f = 120 Hz 70

(VBIAS)VBIAS = VOUT + 3V, f = 1 kHz 65

Output Noise Density f = 120 Hz µV/root−

1Hz

enOutput Noise Voltage BW = 10 Hz −100 kHz, VOUT = 1.8V 150 µV (rms)

BW = 300 Hz −300 kHz, VOUT = 1.8V 90

(1) Limits are specified through testing, statistical correlation, or design.

(2) Typical numbers represent the most likely parametric norm for 25°C operation.

(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to

ground.

(4) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

(5) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load

to full load.

(6) Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. The SO

PowerPAD-8 package devices have a slightly higher dropout voltage due to increased band wire resistance.

Product Folder Links: LP3892

0.60

0.80

1.00

1.20

1.40

1.60

IBIAS (mA)

00.5 1.0 1.5

LOAD CURRENT (A)

VBIAS = 5V

VIN = 2.3V

25oC

-40oC

125oC

LP3892

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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise specified: TJ= 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.

IGND vs VSD VOUT vs Temperature

Figure 4. Figure 5.

DC Load Regulation Line Regulation vs VIN

Figure 6. Figure 7.

Line Regulation vs VBIAS IBIAS vs IL

Figure 8. Figure 9.

Product Folder Links: LP3892

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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified: TJ= 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.

IGND vs VSD Noise Measurement

Figure 10. Figure 11.

VOUTStartup Waveform VOUTStartup Waveform

Figure 12. Figure 13.

Line Regulation vs VBIAS Line Regulation vs VBIAS

Figure 14. Figure 15.

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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified: TJ= 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.

VIN PSRR VIN PSRR

Figure 16. Figure 17.

VBIAS PSRR

Figure 18.

Product Folder Links: LP3892

LOAD CURRENT (A)

1 2

COUT ESR (:)

COUT > 10 PF

STABLE REGION

.001

.01

0.1

1.0

LP3892

SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

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Application Hints

EXTERNAL CAPACITORS

To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit.

OUTPUT CAPACITOR

At least 10µF of output capacitance is required for stability (the amount of capacitance can be increased without

limit). The output capacitor must be located less than 1 cm from the output pin of the IC and returned to a clean

analog ground. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" range

as shown in Figure 19 over the full operating temperature range for stable operation.

Figure 19. Minimum ESR vs Output Load Current

Tantalum capacitors are recommended for the output as their ESR is ideally suited to the part's requirements

and the ESR is very stable over temperature. Aluminum electrolytics are not recommended because their ESR

increases very rapidly at temperatures below 10°C. Aluminum caps can only be used in applications where lower

temperature operation is not required.

A second problem with Al caps is that many have ESR's which are only specified at low frequencies. The typical

loop bandwidth of a linear regulator is a few hundred kHz to several MHz. If an Al cap is used for the output cap,

it must be one whose ESR is specified at a frequency of 100 kHz or more.

Because the ESR of ceramic capacitors is only a few milliohms, they are not suitable for use as output capacitors

on LP389X devices. The regulator output can tolerate ceramic capacitance totaling up to 15% of the amount of

Tantalum capacitance connected from the output to ground.

INPUT CAPACITOR

The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low

source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very

good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be

used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application

where temperatures go below about 10°C.

BIAS CAPACITOR

The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended).

BIAS VOLTAGE

The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage

must be in the range of 4.5 - 6V to assure proper operation of the part.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage

is below approximately 4V.

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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

SHUTDOWN OPERATION

Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a

pull-up resistor (10 kΩto 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high

and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin

if not used.

POWER DISSIPATION/HEATSINKING

A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of

the application. Under all possible conditions, the junction temperature must be within the range specified under

operating conditions. The total power dissipation of the device is given by:

PD= (VIN−VOUT)IOUT+ (VIN)IGND (1)

where IGND is the operating ground current of the device.

The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the

application, and the maximum allowable junction temperature (TJmax):

TRmax = TJmax−TAmax (2)

The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the

formula:

θJA = TRmax / PD(3)

These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount

of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥60 °C/W

for TO-220 package and ≥60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can

dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat

sink is required.

HEATSINKING TO-220 PACKAGE

The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on

a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for

DDPAK/TO-263 package.

The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θHA≤ θJA − θCH

− θJC.

In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal

resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for

θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value

is unknown, 2°C/W can be assumed.

HEATSINKING DDPAK/TO-263 PACKAGE

The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are

soldered to the copper plane for heat sinking. The graph below shows a curve for the θJA of DDPAK/TO-263

package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the

copper area for heat sinking.

Figure 20. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 Package

Product Folder Links: LP3892

130

180

QJA (oC/W)

0 0.5 1.5

COPPER AREA (sq. in.)

LP3892

SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

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As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement.

The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W.

Figure 22 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient

temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.

Figure 21. Maximum Power Dissipation vs Ambient Temperature for DDPAK/TO-263 Package

HEATSINKING SO PowerPAD PACKAGE

Heatsinking for the SO PowerPAD-8 package is accomplished by allowing heat to flow through the ground slug

on the bottom of the package into the copper on the PC board. The heat slug must be soldered down to a

copper plane to get good heat transfer. It can also be connected through vias to internal copper planes. Since

the heat slug is at ground potential, traces must not be routed under it which are not at ground potential. Under

all possible conditions, the junction temperature must be within the range specified under operating conditions.

Figure 22 shows a curve for the θJA of the SO PowerPAD package for different copper area sizes using a typical

PCB with one ounce copper in still air.

Figure 22. θJA vs Copper (1 ounce) Area for SO PowerPAD Package

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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision C (April 2013) to Revision D Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 10

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PACKAGE OPTION ADDENDUM

www.ti.com 13-Sep-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3892EMR-1.2/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 3892E

MR1.2

LP3892EMR-1.5/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 3892E

MR1.5

LP3892EMR-1.8/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 3892E

MR1.8

LP3892EMRX-1.2/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 3892E

MR1.2

LP3892EMRX-1.5/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 3892E

MR1.5

LP3892ES-1.2/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3892ES

-1.2

LP3892ES-1.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3892ES

-1.5

LP3892ESX-1.2/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3892ES

-1.2

LP3892ESX-1.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3892ES

-1.5

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

PACKAGE OPTION ADDENDUM

www.ti.com 13-Sep-2014

Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3892EMRX-1.2/NOPB SO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LP3892EMRX-1.5/NOPB SO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LP3892ESX-1.2/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3892ESX-1.5/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3892EMRX-1.2/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

LP3892EMRX-1.5/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

LP3892ESX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3892ESX-1.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 2

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PACKAGE OUTLINE

6X 1.27

8X 0.51

0.31

3.81

TYP

0.25

0.10

0 - 8 0.15

0.00

2.71

2.11

3.4

2.8 0.25

GAGE PLANE

1.27

0.40

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MS-012.

PowerPAD is a trademark of Texas Instruments.

0.25 C A B

PIN 1 ID

AREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.400

EXPOSED

THERMAL PAD

TYP

6.2

5.8

1.7 MAX

NOTE 3

5.0

4.8

B4.0

3.8

www.ti.com

EXAMPLE BOARD LAYOUT

(5.4)

(1.3) TYP

( ) TYP

VIA

0.2

(R ) TYP0.05

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

8X (1.55)

8X (0.6)

6X (1.27)

(2.95)

NOTE 9

(4.9)

NOTE 9

(2.71)

(3.4)

SOLDER MASK

OPENING

(1.3)

TYP

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-8

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(R ) TYP0.05

8X (1.55)

8X (0.6)

6X (1.27)

(5.4)

(2.71)

(3.4)

BASED ON

0.125 THICK

STENCIL

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

2.29 X 2.870.175 2.47 X 3.100.150 2.71 X 3.40 (SHOWN)0.125 3.03 X 3.800.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

SYMM

BASED ON

0.125 THICK

STENCIL

BY SOLDER MASK

METAL COVERED SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

MECHANICAL DATA

KTT0005B

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