Output Current (A)
Efficiency (%)
1E-5 0.0001 0.001 0.01 0.1 1 2
0
10
20
30
40
50
60
70
80
90
100
D002
VIN = 2.8 V
VIN = 3.6 V
VIN = 4.2 V
VIN
EN
GND
GND
PG
SW
VOS
FB
TLV62084
POWER GOOD
180 kΩ
VOUT
22 µF
R1
R2
10 µF
VIN
2.7 V to 6 V
1 µH
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intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV62080
,
TLV62084
,
TLV62084A
SLVSAK9H –OCTOBER 2011–REVISED JANUARY 2017
TLV6208x 1.2-A and 2-A High-Efficiency Step-Down Converter in 2-mm × 2-mm WSON
Package
1
1 Features
1• DCS-Control™ Architecture for Fast Transient
Regulation
• 2.5 to 6-V Input Voltage Range (TLV62080)
• 2.7 to 6-V Input Voltage Range (TLV62084,
TLV62084A)
• 100% Duty Cycle for Lowest Dropout
• Power Save Mode for Light Load Efficiency
• Output Discharge Function
• Power Good Output
• Thermal Shutdown
• Available in 2 mm × 2 mm 8-Terminal WSON
Package
• For Improved Features Set, see the TPS62080
• Create a Custom Design Using the TLV6208x
With the WEBENCH®Power Designer
2 Applications
• Battery-Powered Portable Devices
• Point-of-Load Regulators
• PC, Notebook, Server
• Set Top Box
• Solid State Drive (SSD), Memory Supply
3 Description
The TLV6208x family devices are small buck
converters with few external components, enabling
cost effective solutions. They are synchronous step-
down converters with an input voltage range of 2.5
and 2.7 (2.5 V for TLV62080, 2.7 V for TLV62084x)
to 6 V. The TLV6208x devices focus on high-
efficiency step-down conversion over a wide output
current range. At medium to heavy loads, the
TLV6208x converters operate in PWM mode and
automatically enter power save mode operation at
light-load currents to maintain high efficiency over the
entire load current range.
To address the requirements of system power rails,
the internal compensation circuit allows a wide range
of external output capacitor values. With the DCS-
Control™ (Direct Control with Seamless transition
into Power save mode) architecture excellent load
transient performance and output voltage regulation
accuracy are achieved. The devices are available in
2-mm × 2-mm WSON package with Thermal Pad.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TLV62080 WSON (8) 2.00 mm × 2.00 mm
TLV62084,
TLV62084A
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
Typical Application Schematic Efficiency vs Output Current, VOUT = 1.2V
space space
2
TLV62080
,
TLV62084
,
TLV62084A
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions......................... 4
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Typical Characteristics.............................................. 7
8 Detailed Description.............................................. 9
8.1 Overview................................................................... 9
8.2 Functional Block Diagram......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application.................................................. 12
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
11.3 Thermal Considerations........................................ 19
12 Device and Documentation Support................. 20
12.1 Device Support...................................................... 20
12.2 Documentation Support ........................................ 20
12.3 Related Links ........................................................ 20
12.4 Trademarks........................................................... 20
12.5 Electrostatic Discharge Caution............................ 20
12.6 Receiving Notification of Documentation Updates 21
12.7 Community Resources.......................................... 21
12.8 Glossary................................................................ 21
13 Mechanical, Packaging, and Orderable
Information........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (September 2016) to Revision H Page
• Added WEBENCH®information to Features, Detailed Design Procedure, and Device Support sections............................. 1
• Added SW (AC, less than 10 ns) to the Absolute Maximum Rating table ............................................................................. 5
Changes from Revision F (January 2015) to Revision G Page
• Added TLV62084A device and Applications ......................................................................................................................... 1
• Added Power Good Pin Logic Table (TLV62080/84) and Power Good Pin Logic Table (TLV62084A) ............................. 10
• Added scale factors in Figure 14 ......................................................................................................................................... 16
• Changed PCB Layout Image ............................................................................................................................................... 18
• Added Receiving Notification of Documentation Updates and Community Resources sections......................................... 21
Changes from Revision E (February 2014) to Revision F Page
• Changed Device Information table. ....................................................................................................................................... 1
• Renamed the Configuration and Functions section .............................................................................................................. 4
• Added new TI-Legal note to Application and Implementation section. ................................................................................ 12
• Renamed "Thermal Information" to Thermal Considerations............................................................................................... 19
Changes from Revision D (June 2013) to Revision E Page
• Added the Device Information table, Power Supply Recommendations,Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections................................................................................................ 1
• Clarified the input voltage ranges of 2.5 V to 5.5 V for the TLV62080 device and 2.7 V to 5.5 V for the TLV62084 device 1
• Changed the Ordering Information table to the Device Comparison table and removed the Package Marking, TA,
and Package columns from the table .................................................................................................................................... 4
3
TLV62080
,
TLV62084
,
TLV62084A
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• Changed the word pin to terminal in most cases throughout the document ......................................................................... 4
• Added the Handling Ratings table which now contains the storage temperature range and ESD ratings ........................... 5
• Added ILIM range for TLV62084 in Electrical Characteristics table......................................................................................... 6
• Added the higher output voltage graphs "Output Voltage vs Load Current", Figure 6,Figure 7 in the Typical
Characteristics section............................................................................................................................................................ 7
• Replaced the "Switching Frequency vs Load Current" graph to the new "Switching Frequency vs Output Current"
graph in the Typical Characteristics section........................................................................................................................... 7
• Replaced the TLV62080 typical application circuit with the circuit for the TLV62084.......................................................... 12
• Deleted the Parameter Measurement Information Section and moved image and list of components to Typical
Application section................................................................................................................................................................ 12
• Added Table 4 to the Design Requirements section ........................................................................................................... 12
• Added Moved Waveforms from the Typical Characteristics section into the Application Curves section. Changed
LCOIL (coil inductance) to ICOIL (coil current) in the Typical Application (PWM Mode and PFM Mode),Load Transient,
Line Transient, and Startup waveforms................................................................................................................................ 15
• Added the output capacitance and inductance conditions to the first (original) Load Transient graph................................ 16
• Added the second Load Transient graph (Figure 14) .......................................................................................................... 16
Changes from Revision C (May 2013) to Revision D Page
• Deleted TLV62084 device number from datasheet.............................................................................................................. 19
Changes from Revision B (July 2012) to Revision C Page
• Changed the Thermal Information table values ..................................................................................................................... 5
Changes from Revision A (November 2011) to Revision B Page
• Changed QFN to SON in ORDERING INFORMATION......................................................................................................... 4
• Changed QFN to SON in DEVICE INFORMATION............................................................................................................... 4
• Changed Thermal Pad description in Pin Functions.............................................................................................................. 4
• Changed TJin the Absolute Maximum Ratings(1) From: –40 to 125°C To: -40 to 150°C...................................................... 5
• Changed several instances of DSC to DCS in DEVICE OPERATION section...................................................................... 9
• Changed DSC to DCS in Functional Block Diagram.............................................................................................................. 9
Changes from Original (October 2011) to Revision A Page
• Changed pin VSNS to VOS in Figure 9 ............................................................................................................................... 12
• Changed pin VSNS to VOS in Figure 10 ............................................................................................................................. 15
1
2
3
4
8
7
6
5
EN
GND
GND
FB
VIN
PG
SW
VOS
Exposed
Thermal
Pad
4
TLV62080
,
TLV62084
,
TLV62084A
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(1) For detailed ordering information please check the Mechanical, Packaging, and Orderable Information section at the end of this
datasheet.
5 Device Comparison Table
PART NUMBER(1) INPUT VOLTAGE OUTPUT CURRENT Power Good Logic Level (EN=Low)
TLV62080 2.5 V to 6 V 1.2 A High Impedance
TLV62084 2.7 V to 6 V 2 A High Impedance
TLV62084A 2.7 V to 6 V 2 A Low
6 Pin Configuration and Functions
space
8-Pin WSON With Thermal Pad
DSG Package
(Top View)
space
space
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 EN IN Device enable logic input. Do not leave floating.
Logic HIGH enables the device, logic LOW disables the device and turns it into shutdown.
2, 3 GND PWR Power and signal ground.
4 FB IN Feedback terminal for the internal control loop.
Connect this terminal to the external feedback divider to program the output voltage.
5 VOS IN Output voltage sense terminal for the internal control loop. Must be connected to output.
6 PG OUT Power Good open drain output.
This terminal is pulled to low if the output voltage is below regulation limits. This terminal can be left floating if not
used.
7 SW PWR Switch terminal connected to the internal MOSFET switches and inductor terminal.
Connect the inductor of the output filter here.
8 VIN PWR Power supply voltage input.
Exposed
Thermal Pad — Must be connected to GND. Must be soldered to achieve appropriate power dissipation and mechanical
reliability.
5
TLV62080
,
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,
TLV62084A
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(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
7 Specifications
7.1 Absolute Maximum Ratings(1)
MIN MAX UNIT
Voltage range(2)
VIN, PG, VOS – 0.3 7 V
SW – 0.3 VIN + 0.3 V
SW (AC, less than 10 ns)(3) – 3.0 10 V
FB – 0.3 3.6 V
EN – 0.3 VIN + 0.3 V
Power Good Sink Current PG 1 mA
Operating junction temperature range, TJ– 40 150 °C
Storage temperature range, Tstg – 65 150 °C
(1) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process.
(2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
7.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic
discharge Human body model (HBM) ESD stress voltage(1) ±2000 V
Charged device model (CDM) ESD stress voltage(2) ±500 V
(1) Refer to the Application Information section for further information.
7.3 Recommended Operating Conditions(1)
MIN TYP MAX UNIT
VIN Input voltage range, TLV62080 2.5 6 V
VIN Input voltage range, TLV62084, TLV62084A 2.7 6 V
TJOperating junction temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Thermal Information
THERMAL METRIC(1) TLV6208x
DSG
(8 PINS) UNITS
θJA Junction-to-ambient thermal resistance 59.7 °C/W
θJCtop Junction-to-case (top) thermal resistance 70.1 °C/W
θJB Junction-to-board thermal resistance 30.9 °C/W
ψJT Junction-to-top characterization parameter 1.4 °C/W
ψJB Junction-to-board characterization parameter 31.5 °C/W
θJCbot Junction-to-case (bottom) thermal resistance 8.6 °C/W
6
TLV62080
,
TLV62084
,
TLV62084A
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7.5 Electrical Characteristics
Over recommended free-air temperature range, TA= –40°C to 85°C, typical values are at TA= 25°C (unless otherwise noted),
VIN= 3.6 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range,TLV62080 2.5 6 V
VIN Input voltage range,TLV62084, TLV62084A 2.7 6 V
IQQuiescent current into VIN IOUT = 0 mA, Device not switching 30 uA
ISD Shutdown current into VIN EN = LOW 1 µA
VUVLO Under voltage lock out Input voltage falling 1.8 2 V
Under voltage lock out hysteresis Rising above VUVLO 120 mV
TJSD Thermal shutdown Temperature rising 150 °C
Thermal shutdown hysteresis Temperature falling below TJSD 20 °C
LOGIC INTERFACE (EN)
VIH High level input voltage 2.5 V ≤VIN ≤6 V 1 V
VIL Low level input voltage 2.5 V ≤VIN ≤6 V 0.4 V
ILKG Input leakage current 0.01 0.5 µA
POWER GOOD
VPG Power good threshold VOUT falling referenced to VOUT nominal –15 –10 –5 %
Power good hysteresis 5 %
VOL Low level voltage Isink = 500 µA 0.3 V
IPG,LKG PG Leakage current VPG = 5.0 V 0.01 0.1 µA
OUTPUT
VOUT Output voltage range 0.5 4 V
VFB Feedback regulation voltage VIN ≥2.5 V and VIN ≥VOUT + 1 V 0.438 0.45 0.462 V
IFB Feedback input bias current VFB = 0.45 V 10 100 nA
RDIS Output discharge resistor EN = LOW, VOUT = 1.8 V 1 kΩ
RDS(on) High side FET on-resistance ISW = 500 mA 120 mΩ
Low side FET on-resistance ISW = 500 mA 90 mΩ
ILIM High side FET switch current-limit,
TLV62080 Rising inductor current 1.6 2.8 4 A
ILIM High side FET switch current-limit,
TLV62084, TLV62084A Rising inductor current 2.3 2.8 4 A
Input Voltage (V)
Output Voltage (V)
2.5 3 3.5 4 4.5 5 5.5 6
0.88
0.885
0.89
0.895
0.9
0.905
0.91
D004
IOUT = 10 mA, TA = 25qC
IOUT = 1 A, TA = 25qC
IOUT = 2 A, TA = 25qC
IOUT = 10 mA, TA = 40qC
IOUT = 1 A, TA = 40qC
IOUT = 2 A, TA = 40qC
IOUT = 10 mA, TA = 85qC
IOUT = 1 A, TA = 85qC
IOUT = 2 A, TA = 85qC
Output Current (A)
Efficiency (%)
1E-5 0.0001 0.001 0.01 0.1 1 2
0
10
20
30
40
50
60
70
80
90
100
D001
VIN = 2.8 V
VIN = 3.6 V
VIN = 4.2 V
7
TLV62080
,
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,
TLV62084A
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7.6 Typical Characteristics
See Typical Application for characterization setup.
space Table 1. Table of Graphs
FIGURE
Efficiency Load current, VOUT = 0.9 V Figure 1
Load current, VOUT = 1.2 V Figure 2
Load current, VOUT = 2.5 V Figure 3
Output Voltage
Accuracy
Input Voltage, VOUT = 0.9 V Figure 4
Input Voltage, VOUT = 2.5 V Figure 5
Load current, VOUT = 0.9 V Figure 6
Load current, VOUT = 2.5 V Figure 7
Switching Frequency Load current, VOUT = 2.5 V Figure 8
VOUT = 0.9 V
Figure 1. Efficiency vs Load Current
VOUT = 1.2 V
Figure 2. Efficiency vs Load Current
VOUT = 2.5 V
Figure 3. Efficiency vs Load Current
VOUT = 0.9 V
Figure 4. Output Voltage vs Input Voltage
Output Current (A)
Output Voltage (V)
1E-5 0.0001 0.001 0.01 0.1 1 2
2.46
2.48
2.5
2.52
2.54
D007
TA = 40qC
TA = 25qC
TA = 85qC
Output Current (A)
Switching Frequency (MHz)
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0
1
2
3
4
5
D008
VIN = 3.3 V
VIN = 4.2 V
VIN = 5 V
Input Voltage (V)
Output Voltage (V)
2.5 3 3.5 4 4.5 5 5.5 6
2.42
2.44
2.46
2.48
2.5
2.52
2.54
D005
IOUT = 10 mA, TA = 25qC
IOUT = 1 A, TA = 25qC
IOUT = 2 A, TA = 25qC
IOUT = 10 mA, TA = 40qC
IOUT = 1 A, TA = 40qC
IOUT = 2 A, TA = 40qC
IOUT = 10 mA, TA = 85qC
IOUT = 1 A, TA = 85qC
IOUT = 2 A, TA = 85qC
Output Current (A)
Output Voltage (V)
1E-5 0.0001 0.001 0.01 0.1 1 2
0.88
0.888
0.896
0.904
0.912
0.92
D006
TA = 40qC
TA = 25qC
TA = 85qC
8
TLV62080
,
TLV62084
,
TLV62084A
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VOUT = 2.5 V
Figure 5. Output Voltage vs Input Voltage
VIN = 3.6 V
Figure 6. Output Voltage vs Load Current
VIN = 3.6 V
Figure 7. Output Voltage vs Load Current
VOUT = 2.5 V
Figure 8. Switching Frequency vs Output Current
Gate
Driver
Control
Logic Low Side
N-MOS
High Side
N-MOS
Thermal
Shutdown
Softstart
Under
Voltage
Shutdown
direct control
&
compensation
VIN
SW
GND
PG
EN
VOS
REF
Active
Output
Discharge
Power
Good
FB
ramp
minimum
on-timer
DCS-CONTROLTM
error
amplifier
comparator
50
Copyright © 2016, Texas Instruments Incorporated
9
TLV62080
,
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,
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8 Detailed Description
8.1 Overview
The TLV62080 and TLV62084x synchronous switched-mode converters are based on DCS-Control™. DCS-
Control™ is an advanced regulation topology that combines the advantages of hysteretic and voltage mode
control.
The DCS-Control™ topology operates in PWM (pulse width modulation) mode for medium to heavy load
conditions and in power save mode at light load currents. In PWM mode, the TLV6208x converter operates with
the nominal switching frequency of 2 MHz, having a controlled frequency variation over the input voltage range.
As the load current decreases, the converter enters power save mode, reducing the switching frequency and
minimizing the IC quiescent current to achieve high efficiency over the entire load current range. DCS-Control™
supports both operation modes (PWM and PFM) using a single building block with a seamless transition from
PWM to power save mode without effects on the output voltage. The TLV62080 and TLV62084x devices offer
both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple,
minimizing interference with RF circuits.
8.2 Functional Block Diagram
space
space
8.3 Feature Description
8.3.1 100% Duty-Cycle Low-Dropout Operation
The devices offer low input-to-output voltage difference by entering the 100% duty-cycle mode. In this mode the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This mode is
particularly useful in battery powered applications to achieve the longest operation time by taking full advantage
of the whole battery voltage range. Equation 1 calculates the minimum input voltage to maintain regulation based
on the load current and output voltage.
IN,MIN OUT OUT,MAX DS(on) L
V V I (R + R )= + ´
10
TLV62080
,
TLV62084
,
TLV62084A
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Feature Description (continued)
space
With:• VIN,MIN = Minimum input voltage
• IOUT,MAX = Maximum output current
• RDS(on) = High-side FET on-resistance
• RL= Inductor ohmic resistance (1)
space
8.3.2 Enabling and Disabling the Device
The device is enabled by setting the EN input to a logic HIGH. Accordingly, a logic LOW disables the device. If
the device is enabled, the internal power stage starts switching and regulates the output voltage to the
programmed threshold. The EN input must be terminated and not left floating.
8.3.3 Output Discharge
The output gets discharged through the SW terminal with a typical discharge resistor of RDIS whenever the
device shuts down (by disable, thermal shutdown or UVLO).
8.3.4 Soft Start
When EN is set to start device operation, the device starts switching after a delay of about 40 μs and VOUT rises
with a slope of about 10mV/μs (See Figure 16 and Figure 17 for typical startup operation). Soft start avoids
excessive inrush current and creates a smooth output voltage rise slope. Soft start also prevents excessive
voltage drops of primary cells and rechargeable batteries with high internal impedance.
If the output voltage is not reached within the soft start time, such as in the case of heavy load, the converter
enters standard operation. Consequently, the inductor current limit operates as described in Inductor Current-
Limit. The TLV62080 and TLV62084x devices are able to start into a pre-biased output capacitor. The converter
starts with the applied bias voltage and ramps the output voltage to the nominal value.
8.3.5 Power Good
The TLV62080 and TLV62084x devices have a power-good output going low when the output voltage is below
the nominal value. The power good maintains high impedance once the output is above 95% of the regulated
voltage, and is driven to low once the output voltage falls below typically 90% of the regulated voltage. The PG
terminal is an open drain output and is specified to sink typically up to 0.5 mA. The power good output requires a
pull-up resistor which is recommended connecting to the device output. When the device is off because of
disable, UVLO, or thermal shutdown, the PG terminal is at high impedance. TLV62084A features PG=Low in
these cases. Table 2 and Table 3 show the different PG operation for the TLV6208x and TLV62084A. The PG
output can be left floating if unused.
space
Table 2. Power Good Pin Logic Table (TLV62080/84)
Device Information PG Logic Status
High Z Low
Enable (EN=High) VFB ≥VPG √
VFB ≤VPG √
Shutdown (EN=Low) √
UVLO 0.7V < VIN < VUVLO √
Thermal Shutdown TJ> TJSD √
Power Supply Removal VIN < 0.7V √
11
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,
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space
Table 3. Power Good Pin Logic Table (TLV62084A)
Device Information PG Logic Status
High Z Low
Enable (EN=High) VFB ≥VPG √
VFB ≤VPG √
Shutdown (EN=Low) √
UVLO 0.7V < VIN < VUVLO √
Thermal Shutdown TJ> TJSD √
Power Supply Removal VIN < 0.7V √
space
The PG signal can be used for sequencing of multiple rails by connecting to the EN terminal of other converters.
Leave the PG terminal unconnected when not in use.
8.3.6 Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout is implemented which shuts
down the device at voltages lower than VUVLO with a VHYS_UVLO hysteresis.
8.3.7 Thermal Shutdown
The device goes into thermal shutdown once the junction temperature exceeds typically TJSD. Once the device
temperature falls below the threshold, the device returns to normal operation automatically.
8.3.8 Inductor Current-Limit
The Inductor current-limit prevents the device from high inductor current and drawing excessive current from the
battery or input voltage rail. Excessive current can occur with a shorted or saturated inductor, a heavy load, or
shorted output circuit condition.
The incorporated inductor peak-current limit measures the current during the high-side and low-side power
MOSFET on-phase. Once the high-side switch current-limit is tripped, the high-side MOSFET is turned off and
the low-side MOSFET is turned on to reduce the inductor current. When the inductor current drops down to the
low-side switch current-limit, the low-side MOSFET is turned off and the high-side switch is turned on again. This
operation repeats until the inductor current does not reach the high-side switch current-limit. Because of an
internal propagation delay, the real current-limit value exceeds the static-current limit in the Electrical
Characteristics table.
8.4 Device Functional Modes
8.4.1 Power Save Mode
As the load current decreases, the TLV62080 and TLV62084x devices enter power save mode operation. During
power save mode, the converter operates with a reduced switching frequency in PFM mode and with a minimum
quiescent current maintaining high efficiency. Power save mode occurs when the inductor current becomes
discontinuous. Operation in power save mode is based on a fixed on time architecture. The typical on time is
given by ton = 400 ns × (VOUT / VIN). The switching frequency over the whole load current range is shown in
Figure 8.
VIN
EN
GND
GND
PG
SW
VOS
FB
TLV62084
POWER GOOD
R3
VOUT
C2
R1
R2
C1
VIN
2.7 V to 6 V
L1
C3
+
Copyright © 2016, Texas Instruments Incorporated
12
TLV62080
,
TLV62084
,
TLV62084A
SLVSAK9H –OCTOBER 2011–REVISED JANUARY 2017
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Product Folder Links: TLV62080 TLV62084 TLV62084A
Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The devices are designed to operate from an input voltage supply range between 2.5 V (2.7 V for the TLV62084x
devices) and 6 V with a maximum output current of 2 A (1.2 A for the TLV62080 device). The TLV6208x devices
operate in PWM mode for medium to heavy load conditions and in power save mode at light load currents.
In PWM mode the TLV6208x converters operate with the nominal switching frequency of 2 MHz which provides a
controlled frequency variation over the input voltage range. As the load current decreases, the converter enters
power save mode, reducing the switching frequency and minimizing the IC quiescent current to achieve high
efficiency over the entire load current range.
The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design. See the Documentation Support section for additional documentation.
9.2 Typical Application
Figure 9. Typical Application Schematic
9.2.1 Design Requirements
Use the following typical application design procedure to select external components values for the TLV62084
device.
Table 4. Design Parameters
DESIGN PARAMETERS EXAMPLE VALUES
Input Voltage Range 2.8 V to 4.2 V
Output Voltage 1.2 V
Transient Response ±5% VOUT
Input Voltage Ripple 400 mV
Output Voltage Ripple 30 mV
Output Current Rating 2 A
Operating frequency 2 MHz
13
TLV62080
,
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,
TLV62084A
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(1) See Third-party Products Disclaimer
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62080 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
Table 5. List of Components
REFERENCE DESCRIPTION MANUFACTURER(1)
C1 10 μF, Ceramic Capacitor, 6.3 V, X5R, size 0603 Std
C2 22 μF, Ceramic Capacitor, 6.3 V, X5R, size 0805,
GRM21BR60J226ME39L Murata
C3 47 μF, Tantalum Capacitor, 8 V, 35 mΩ, size 3528,
T520B476M008ATE035 Kemet
L1 1μH, Power Inductor, 2.2 A, size 3 mm × 3 mm × 1.2 mm,
XFL3012-102MEB Coilcraft
R1 65.3 kΩ, Chip Resistor, 1/16 W, 1%, size 0603 Std
R2 39.2 kΩ, Chip Resistor, 1/16 W, 1%, size 0603 Std
R3 178 kΩ, Chip Resistor, 1/16 W, 1%, size 0603 Std
9.2.2.2 Output Filter Design
The inductor and the output capacitor together provide a low pass frequency filter. To simplify this process
Table 6 outlines possible inductor and capacitor value combinations for the most application.
(1) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by
+20% and –50%. Inductor tolerance and current de-rating is anticipated. The effective inductance can
vary by +20% and –30%.
(2) Plus signs (+) indicates recommended filter combinations.
(3) Filter combination in typical application.
Table 6. Matrix of Output Capacitor and Inductor Combinations
L [µH](1) COUT [µF](1)
10 22 47 100 150
0.47
1+ +(2)(3) + +
2.2 + + + +
4.7
SW
IN
OUT
OUTL
L
MAX,OUTMAX,L
fL
V
V
1
VI
2
I
II
´
-
´=D
D
+=
14
TLV62080
,
TLV62084
,
TLV62084A
SLVSAK9H –OCTOBER 2011–REVISED JANUARY 2017
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Product Folder Links: TLV62080 TLV62084 TLV62084A
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(1) See Third-party Procucts Disclaimer
(2) Recommended for TLV62080 only due to limited current rating
9.2.2.3 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 2 is given.
Where
• IOUT,MAX = Maximum output current
•ΔIL= Inductor current ripple
• fSW = Switching frequency
• L = Inductor value (2)
space
TI recommends choosing the saturation current for the inductor 20% to approximately 30% higher than the IL,MAX,
out of Equation 2. A higher inductor value is also useful to lower ripple current, but increases the transient
response time as well. The following inductors are recommended to be used in designs (see Table 7).
Table 7. List of Recommended Inductors
INDUCTANCE
[µH] CURRENT RATING
[mA] DIMENSIONS
L x W x H [mm3]DC RESISTANCE
[mΩtyp] TYPE MANUFACTURER(1)
1 2500 3 × 3 × 1.2 35 XFL3012-102ME Coilcraft
1 1650(2) 3 × 3 × 1.2 40 LQH3NPN1R0NJ0 Murata
2.2 2500 4 × 3.7 × 1.65 49 LQH44PN2R2MP0 Murata
2.2 1600(2) 3 × 3 × 1.2 81 XFL3012-222ME Coilcraft
(1) See Third-party Products Disclaimer
9.2.2.4 Capacitor Selection
The input capacitor is the low impedance energy source for the converter which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and must be placed between
VIN and GND as close as possible to those terminals. For most applications 10 μF is sufficient though a larger
value reduces input current ripple.
The architecture of the TLV6208x device allows use of tiny ceramic-type output capacitors with low equivalent-
series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep the
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends use
of the X7R or X5R dielectric. The TLV62080 and TLV62084x devices are designed to operate with an output
capacitance of 10 to 100 µF and beyond, as listed in Table 6. Load transient testing and measuring the bode plot
are good ways to verify stability with larger capacitor values.
Table 8. List of Recommended Capacitors
CAPACITANCE
[µF] TYPE DIMENSIONS
L x W x H [mm3]MANUFACTURER(1)
10 GRM188R60J106M 0603: 1.6 × 0.8 × 0.8 Murata
22 GRM188R60G226M 0603: 1.6 × 0.8 × 0.8 Murata
22 GRM21BR60J226M 0805: 2 × 1.2 × 1.25 Murata
SW
(2 V/div)
Time (200 ns/div)
V
(20 mV/div)
OUT
I
(0.5 A/div)
COIL
SW
(2 V/div)
Time (2 s/div)µ
V
(20 mV/div)
OUT
I
(0.2 A/div)
COIL
÷
ø
ö
ç
è
æ+´=
÷
ø
ö
ç
è
æ+´= 2R
1R
1V45.0
2R
1R
1VV FBOUT
VIN
EN
GND
GND
PG
SW
VOS
FB
TLV62084
POWER GOOD
180 kΩ
VOUT
22 µF
R1
R2
10 µF
VIN
2.7 V to 6 V
1 µH
Copyright © 2016, Texas Instruments Incorporated
15
TLV62080
,
TLV62084
,
TLV62084A
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9.2.2.5 Setting the Output Voltage
By selecting R1and R2, the output voltage is programmed to the desired value. Use Equation 3 to calculate R1
and R2.
Figure 10. Typical Application Circuit
space
(3)
For best accuracy, R2must be kept smaller than 40 kΩto ensure that the current flowing through R2is at least
100-times larger than IFB. Changing the sum towards a lower value increases the robustness against noise
injection. Changing the sum towards higher values reduces the current consumption.
9.2.3 Application Curves
VIN = 3.3 V VOUT = 1.2 V ILOAD = 500 mA
Figure 11. Typical Application (PWM Mode)
VIN = 3.3 V VOUT = 1.2 V ILOAD = 10 mA
Figure 12. Typical Application (PFM Mode)
Time (100 s/div)µ
V
(50 mV/div)
OUT
3.3 V
4.2 V
V
(1 V/div)
IN
EN
(5 V/div)
Time (20 s/div)µ
V
(1 V/div)
OUT
I
(0.5 A/div)
COIL
PG
(1 V/div)
LOAD
(1 A/div)
Time (50 s/div)µ
V
(20 mV/div)
OUT
I
(1 A/div)
COIL
1 A
50 mA
Time (20 s/div)µ
V
OUT
I
COIL
LOAD
(1A/div)
(50mV/div)
(2A/div)
16
TLV62080
,
TLV62084
,
TLV62084A
SLVSAK9H –OCTOBER 2011–REVISED JANUARY 2017
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Product Folder Links: TLV62080 TLV62084 TLV62084A
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L = 1 µH COUT = 22 µF VIN = 3.3 V
VOUT = 1.2 V ILOAD = 50 mA to 1 A
Figure 13. Load Transient
L = 1 µH COUT = 22 µF VIN = 3.3 V
VOUT = 1.2 V ILOAD = 200 mA to 1.8 A
Figure 14. Load Transient
VIN = 3.3 to 4.2 V VOUT = 1.2 V ILOAD = 2.2 Ω
Figure 15. Line Transient
VIN = 3.3 V VOUT = 1.2 V ILOAD = 2.2 Ω
Figure 16. Startup
EN
(5 V/div)
Time (20 s/div)µ
V
(1 V/div)
OUT
I
(0.2 A/div)
COIL
PG
(1 V/div)
17
TLV62080
,
TLV62084
,
TLV62084A
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VIN = 3.3 V VOUT = 1.2 V
Figure 17. Startup (No Load)
VIN
SW
PG
VOS
EN
GND
FB
GND
L1
C1
C2
R2
R1
VIN
GND
VOUT
GND
18
TLV62080
,
TLV62084
,
TLV62084A
SLVSAK9H –OCTOBER 2011–REVISED JANUARY 2017
www.ti.com
Product Folder Links: TLV62080 TLV62084 TLV62084A
Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated
10 Power Supply Recommendations
The input power supply's output current needs to be rated according to the supply voltage, output voltage and
output current of the TLV6208x.
11 Layout
11.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TLV62080 and TLV62084x devices.
• Place input and output capacitors, along with the inductor, as close as possible to the IC which keeps the
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance.
• Use a common-power GND.
• Properly connect the low side of the input and output capacitors to the power GND to avoid a GND potential
shift.
• The sense traces connected to FB and VOS terminals are signal traces. Keep these traces away from SW
nodes.
• Use care to avoid noise induction. By a direct routing, parasitic inductance can be kept small.
• Use GND layers for shielding if needed.
11.2 Layout Example
space
space
space
Figure 18. PCB Layout Suggestion
19
TLV62080
,
TLV62084
,
TLV62084A
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SLVSAK9H –OCTOBER 2011–REVISED JANUARY 2017
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11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design.
• Improving the thermal coupling of the component to the PCB by soldering the Thermal Pad.
• Introducing airflow in the system.
For more details on how to use the thermal parameters, see the Thermal Characteristics application notes
SZZA017 and SPRA953.
20
TLV62080
,
TLV62084
,
TLV62084A
SLVSAK9H –OCTOBER 2011–REVISED JANUARY 2017
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Product Folder Links: TLV62080 TLV62084 TLV62084A
Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62080 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
For related documentation see the following:
• TLV62080EVM-756 User's Guide, TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm
SON Package,SLVU640
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9. Related Links
PARTS PRODUCT FOLDER BUY NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
TLV62080 Click here Click here Click here Click here Click here
TLV62084 Click here Click here Click here Click here Click here
TLV62084A Click here Click here Click here Click here Click here
12.4 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
21
TLV62080
,
TLV62084
,
TLV62084A
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SLVSAK9H –OCTOBER 2011–REVISED JANUARY 2017
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Submit Documentation FeedbackCopyright © 2011–2017, Texas Instruments Incorporated
12.6 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.7 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.8 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV62080DSGR ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 RAU
TLV62080DSGT ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 RAU
TLV62084ADSGR ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 14M
TLV62084ADSGT ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 14M
TLV62084DSGR ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SLO
TLV62084DSGT ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SLO
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2016
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV62080DSGR WSON DSG 8 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2
TLV62080DSGR WSON DSG 8 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TLV62080DSGT WSON DSG 8 250 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2
TLV62084ADSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV62084ADSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV62084DSGR WSON DSG 8 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2
TLV62084DSGT WSON DSG 8 250 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jul-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV62080DSGR WSON DSG 8 3000 205.0 200.0 33.0
TLV62080DSGR WSON DSG 8 3000 195.0 200.0 45.0
TLV62080DSGT WSON DSG 8 250 205.0 200.0 33.0
TLV62084ADSGR WSON DSG 8 3000 210.0 185.0 35.0
TLV62084ADSGT WSON DSG 8 250 210.0 185.0 35.0
TLV62084DSGR WSON DSG 8 3000 205.0 200.0 33.0
TLV62084DSGT WSON DSG 8 250 205.0 200.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jul-2018
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
SEE OPTIONAL
TERMINAL 8X 0.3
0.2
1.6 0.1
2X
1.5
0.9 0.1
6X 0.5
8X 0.4
0.2
0.05
0.00
0.8 MAX
A2.1
1.9 B
2.1
1.9
0.3
0.2
0.4
0.2
(0.2) TYP
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/B 09/2017
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
9
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 5.500
OPTIONAL TERMINAL
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.25)
(1.6)
(1.9)
6X (0.5)
(0.9) ( 0.2) VIA
TYP
(0.55)
8X (0.5)
(R0.05) TYP
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/B 09/2017
SYMM
1
45
8
LAND PATTERN EXAMPLE
SCALE:20X
SYMM 9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
8X (0.25)
8X (0.5)
(0.9)
(0.7)
(1.9)
(0.45)
6X (0.5)
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/B 09/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
SYMM
1
45
8
METAL
SYMM 9
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