Megafunctions: Processors & Peripherals - Altera Corporation

Altera Corporation 1

Simula ting the a6402 Mod el

with the Visual IP Software

J une 2000, ver. 1 User Guide

A-UG-A6402VIS-01

Introduction Altera® int ellectual property (IP) MegaCore™ functions are developed

and pre-t e sted by Alte ra, and are opt i mi zed for speci fic Altera device

architectures . You can test-dr ive these functions f or free via the

OpenCore™ feature by downloading the functions from the Altera web

site and inst alling them on your PC or UNIX workst ation. To help in your

ev alua tion , Al ter a also prov id e s Vis ual IP sim ula ti on mod e ls for thes e

functions.

Th e V isu al IP soft war e fr om In n ov eda lets y ou crea te sim u la ti on mo d el s

that can be used in third-party VHDL and Verilog HDL s imulation tools.

Altera distributes the Visual IP software for the end user along with

Visual IP models of Altera IP functions.

Alter a’s Visual IP models are pa rame teriz abl e , RTL level, funct i onal

simulation models. The models let you instantiate Altera IP in your design

and simulate it in y our choice of simula tion tool. This user guide describes

how to install and use the Visual IP simulation model for the Altera

a6402 univer sal asynchronous receiver/transmitter (UART).

1Before using the a6402 model, you must download and install

the Visual IP sof tware, which is available for free from the Altera

IP MegaStore s i te at http://www.altera.com/IPmegastore.

Follow the instructions in the Installing the Visual IP Software User

Guide.

Altera recommends that you also obtain the a6402 Universal

Asynchr onous Receiver /Transmitt er Data She et from the Altera web

site. This data shee t desc ribes t he t echnical specifications of the

a6402 fu n ction.

2Altera Corporation

Simulating the a6402 Model with the Visual IP Software User Guide

The a6402 Visual IP model contains the following elements:

Download the

Models

If you have not already done so, download Visual IP models from Altera’s

web site at http://www.altera.com by following the instructions below.

1. Point your w e b browse r to http://www.altera.com/IPmegastore.

2. Sear ch in the IP MegaStore for the function/model you wish to

obtain.

3. On the search r esults pa ge, click the name of th e functi on/model

you wish t o ob ta i n.

4. Click the Free Test Drive icon and follow the on-line instructions to

downlo ad the f unction and/or model.

P C Installation Execute the a6402_vip_pc.exe file and follow the on-lin e inst ruc ti ons to

install th e model. The following files are installed :

<installation path>\vip_simulation\A6402\

doc\

a6402_vipug.pdf

verilog\

A6402.v

A6402_vectors.v

A6402_top.v

vhdl\

mti\A6402.vhd

A6402_vectors.vhd

A6402_top.vhd

leapfrog\

A6402.vhd

A6402_vectors.vhd

A6402_top.vhd

Table 1. a6402 Visual I P Mo del Elements

Element Description

a6402.* The VHDL or Verilog HDL a6402 UART MegaCore function

model file.

A6402_vectors.* A set of VHDL o r Ver ilog HDL test vectors.

A6402_top.* Top-level VHDL or Verilog HDL file that references the

a6402 function and test ve ctors.

Altera Corporation 3

Simulating the a6402 Model with the Visual IP Software User Guide

vss\A6402.vhd

A6402_vectors.vhd

A6402_top.vhd

<installation path>\vip_models\a6402\*

Befor e using the Visua l IP mo del, set t he VIP_MODELS_DIR en viron ment

variable to <installa tion pa th>/vip_models. The instal lation process se ts all

other required environment var iables in the system registry.

1All Altera Visual IP models use the VIP_MODELS_DIR

enviro nment variable. If you only wish to use one Visual IP

model, you can install the model into any directory and set up

the variable to point to that directory. However, if you wish to

use several models (e.g., both the a6402 and a8259 models) you

should install all Visual IP models into the same directory.

Solaris

Installation

The a6402 model is a tape archive file (.tar) that has been compressed

using the gzip utility. To extract the files, move the

a6402_vip_solaris.tar.gz file to the locati on in which you would like to

install the models and type the following commands at a UNIX prompt:

gunzip a6402_vip_solaris.tar.gz r

tar xvf a6 402 _vip _s olar is .tar r

The following directories and files are created:

<instal la tion pa th >/vip_simulation/A6402/

setup.csh

doc/a6402_vipug.pdf

verilog/

A6402.v

A6402_vectors.v

A6402_top.v

vhdl/

mti/A6402.vhd

A6402_vectors.vhd

A6402_top.vhd

leapfrog/

A6402.vhd

A6402_vectors.vhd

A6402_top.vhd

vss/ A6402.vhd

4Altera Corporation

Simulating the a6402 Model with the Visual IP Software User Guide

A6402_vectors.vhd

A6402_top.vhd

<i n st alla ti on path>/vip_models/a6402/*

Befor e using the Visual IP models, performperform the following steps:

1. Se t the VIP_MODELS_DIR environment variable to <installation

path>/vip_models.

1All Altera Visual IP models use the VIP_MODELS_DIR

enviro nment variable. If you only wish to use one Visual IP

model, you can install the model into any directory and set

up the variable to point to that directory. However, if you

wish to use several models (e.g., both the a6402 and a8259

models) you should install a ll Visual IP models into the

same direc tory.

2. Se t the VIP_EU_ROOT e n vironmen t varia ble to th e root directory in

which you installed the Visual IP software.

3. Source the setup.csh file to complete the configuration of the

Visual IP environment.

Running Test

Vectors

This section describes how to use the test vecto rs provided with the

a6402 simulation model.

Verilog HDL

If you are using Verilog HDL, perform the following steps:

1. Set up the Visual IP PLI i nterface as describe d in Installing the Visual

IP software User Guide.

2. Make sur e the VIP_MODELS_DIR environment variable is set

properly.

3. Change to the <installation path>/vip_simulation/A6402/verilog

directory.

4. Compile the A6402.v and A6402_vectors.v files. These modules

attach to the appro priate Visual IP models using the Verilog-XL PLI

interface.

5. Compile the A6402_top.v file .

6. Simulate A6402_top.

Altera Corporation 5

Simulating the a6402 Model with the Visual IP Software User Guide

VHDL

If you are using VHDL, perform the following steps:

1. Set up th e Visual I P C lan guage int erface as d e scribed in Installing the

Visual IP software User Guide.

2. Make sur e the VIP_MODELS_DIR environment variable is set

properly.

3. Change to the directory <installation

path>/vip_simulation/A6402/vhdl/<simulator>, where <simulator> is

to the VHDL simulation tool you are using.

4. Compile the A6402.vhd and A6402_vectors.vhd files into your work

library. These c omponen ts at t ach to th e ap propri at e Visual IP models

using th e C language i nt e rface of your VHDL simulator.

5. Compile the A6402_top.vhd file into your work libra ry.

6. Simulate work.A6402_top(struct).

Using the

a6402 Model

This section describes how to use the a6402 simulatio n model in your

designs.

Verilog HDL

If you are using Verilog HDL, perform the following steps:

1. Set up the Visual IP PLI interface as described in Inst alling the Visual

IP software User Guide.

2. Make sur e the VIP_MODELS_DIR environment variable is set

properly.

3. Go to th e <in st alla ti on pa th>/vip_simulation/A6402/verilog dir ectory

4. Compile A6402. This module attachs to the appropriate Visual IP

model using the Verilog-XL PLI interface.

5. Instantiate A6402 in your Verilog HDL design.

6Altera Corporation

Simulating the a6402 Model with the Visual IP Software User Guide

Printed on Recycled Paper.

Altera, MegaCore, and OpenCore are trademarks and/or service marks of Altera Corporation in the United

States and other countries. Altera acknowledges the trademarks of other organizations for their respective

products or services mentioned in this document. Altera products are protected under numerous U.S. and

foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of

its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no

responsibility or liability arising out of the application or use of any information, product,

or service described herein except as expressly agreed to in writing by Altera Corporation.

Altera customers are advised to obtain the latest version of device specifications before

relying on any published information and before placing orders for products or services.

101 Innovation Drive

San Jose, C A 95134

(408) 544-7000

http://www.altera.com

A p p lications Hotline:

(800) 800-EPLD

Cust omer Marketi ng:

(408) 544-7104

Literature Services:

lit_req@altera.com

VHDL

If you are using VHDL, perform the following steps:

1. Set up th e Visual I P C lan guage int erface as d e scribed in Installing the

Vi su a l IP softw a re U s er Gu id e .

2. Make sur e the VIP_MODELS_DIR envir onment variable is set

properly.

3. Go to the< instal lation path>/vip_simulation/A6402/vhdl/<simulator>

directory, where <simulator> is the VHDL simulation tool you are

using.

4. Compile A6402.vhd into your work library. This co mponent att ach es

to the appropriate Visual IP model using the C language interface of

your VHDL simulato r.

5. Instantiate work.A6402(behave) in your VHDL design.

Known Issues Visual IP models do not support chec kpoint/restart . Therefore, you must

reload the simulation model to restart the simulation.