IRF630N/IRF630NS/IRF630NL N-Channel Power MOSFETs 200V, 9.3A, 0.30 Features * Peak Current vs Pulse Width Curve * Ultra Low On-Resistance - rDS(ON) = 0.200 (Typ), VGS = 10V * UIS Rating Curve * Simulation Models - Temperature Compensated PSPICE(R) and SABER(c) Electrical Models - Spice and SABER(c) Thermal Impedance Models DRAIN (FLANGE) SOURCE DRAIN GATE SOURCE DRAIN GATE DRAIN (FLANGE) D GATE G SOURCE DRAIN (FLANGE) TO-263 TO-262 S TO-220 MOSFET Maximum Ratings TA = 25C unless otherwise noted Symbol VDSS Drain to Source Voltage Parameter Ratings 200 Units V VGS Gate to Source Voltage 20 V Continuous (TC = 25oC, VGS = 10V) 9.3 A Continuous (TC = 100oC, VGS = 10V) 6.5 A Figure 4 A 94 mJ 82 0.55 W W/oC Drain Current ID Pulsed EAS Single Pulse Avalanche Energy (Note 1) PD Power dissipation Derate above 25 oC TJ, TSTG Operating and Storage Temperature o -55 to 175 C Thermal Characteristics RJC Thermal Resistance Junction to Case TO-220, TO-262, TO-263 RJA Thermal Resistance Junction to Ambient TO-220, TO-262, TO-263 RJA oC/W 1.83 2 Thermal Resistance Junction to Ambient TO-263, 1in copper pad area 62 o C/W 40 o C/W Package Marking and Ordering Information Device Marking 630N Device IRF630NS Package TO-263AB Reel Size 330mm Tape Width 24mm Quantity 800 units 630N IRF630NL TO-262AA Tube N/A 50 630N IRF630N TO-220AB Tube N/A 50 (c)2002 Fairchild Semiconductor Corporation Rev. B IRF630N/IRF630NS/IRF630NL January 2002 IRF630N/IRF630NS/IRF630NL Electrical Characteristics TA = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current 200 - - VDS = 200V ID = 250A, VGS = 0V VGS = 0V - - 25 VDS = 160V TC = 150o - - 250 VGS = 20V - - 100 A nA On Characteristics VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250A 2 - 4 V rDS(ON) Drain to Source On Resistance ID = 5.4A, VGS = 10V - 0.200 0.300 gfs Forward Transconductance VDS = 50V, ID = 5.4A (Note 2) 49 - - S - 1030 - pF - 120 - pF - 50 - pF 59 78 nC - 32 42 nC - 2.0 3.2 nC Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance VDS = 25V, VGS = 0V, f = 1MHz Qg(TOT) Total Gate Charge at 20V VGS = 0V to 20V Qg(10) Total Gate Charge at 10V VGS = 0V to 10V Qg(TH) Threshold Gate Charge Qgs Gate to Source Gate Charge - 4.0 - nC Qgd Gate to Drain "Miller" Charge - 11 - nC Switching Characteristics VDD = 100V ID = 11A VGS = 0V to 2V Ig = 1.0mA (VGS = 10V) tON Turn-On Time - - 32 ns td(ON) Turn-On Delay Time - 9 - ns tr Rise Time - 12 - ns td(OFF) Turn-Off Delay Time - 71 - ns tf Fall Time - 19 - ns tOFF Turn-Off Time - - 135 ns V VDD = 100V, ID = 5.4A VGS = 10V, RGS = 13 Drain-Source Diode Characteristics VSD Source to Drain Diode Voltage ISD = 5.4A - - 1.3 trr Reverse Recovery Time ISD = 5.4A, dISD/dt = 100A/s - - 176 ns QRR Reverse Recovered Charge ISD = 5.4A, dISD/dt = 100A/s - - 813 nC Notes: 1: Starting TJ = 25C, L = 6.5mH, IAS = 5.4A. 2: Pulse width 400s; duty cycle 2%. (c)2002 Fairchild Semiconductor Corporation Rev. B 1.2 12 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 9 VGS = 10V 6 3 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZJC, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x R JC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 200 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK IDM, PEAK CURRENT (A) 100 CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 10V 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 5 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability (c)2002 Fairchild Semiconductor Corporation Rev. B IRF630N/IRF630NS/IRF630NL Typical Characteristic 100 10 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 100s OPERATION IN THIS AREA MAY BE LIMITED BY r DS(ON) 1 1ms 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 150oC 1 0.001 0.1 1 10 500 100 STARTING TJ = 25oC 10 0.01 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.1 1 10 tAV, TIME IN AVALANCHE (ms) Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching Capability 20 20 15 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 10 TJ = 175oC 5 TJ = -55oC 15 VGS = 10V VGS = 5V VGS =4.5V 10 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC o TJ = 25 C 0 0 2 3 4 0 5 1 VGS, GATE TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics 4 5 1.2 VGS = VDS, ID = 250A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 3 Figure 8. Saturation Characteristics 3.5 3.0 2 VDS, DRAIN TO SOURCE VOLTAGE (V) 2.5 2.0 1.5 1.0 1.0 0.8 0.5 VGS = 10V, ID = 9.3A 0.6 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature (c)2002 Fairchild Semiconductor Corporation 200 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature Rev. B IRF630N/IRF630NS/IRF630NL Typical Characteristic (Continued) 1.3 3000 VGS = 0V, f = 1MHz 1000 CISS = CGS + CGD 1.2 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.1 1.0 COSS CDS + CGD 100 CRSS = CGD 0.9 -80 -40 0 40 80 120 160 10 0.1 200 1 TJ , JUNCTION TEMPERATURE (oC) 10 100 200 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature Figure 12. Capacitance vs Drain to Source Voltage 10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 100V 8 6 4 WAVEFORMS IN DESCENDING ORDER: 2 ID = 9.3A ID = 5A 0 0 5 10 15 20 25 30 35 Qg, GATE CHARGE (nC) Figure 13. Gate Charge Waveforms for Constant Gate Currents Test Circuits and Waveforms VDS BVDSS tP VDS L IAS VDD VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDD - VGS DUT tP 0V IAS 0 0.01 tAV Figure 14. Unclamped Energy Test Circuit (c)2002 Fairchild Semiconductor Corporation Figure 15. Unclamped Energy Waveforms Rev. B IRF630N/IRF630NS/IRF630NL Typical Characteristic (Continued) IRF630N/IRF630NS/IRF630NL Test Circuits and Waveforms (Continued) VDS VDD Qg(TOT) RL VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS - VGS = 2V DUT 0 Ig(REF) Qg(TH) Qgs Qgd Ig(REF) 0 Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 0 Figure 18. Switching Time Test Circuit (c)2002 Fairchild Semiconductor Corporation 10% Figure 19. Switching Time Waveforms Rev. B P ( T JM - T A ) DM = ----------------------------Z JA (EQ. 1) In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 80 RJA = 26.51+ 19.84/(0.262+Area) 60 RJA (oC/W) The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. 40 20 0.1 1 10 AREA, TOP COPPER AREA (in2) Figure 20. Thermal Resistance vs Mounting Pad Area 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. 19.84 ( 0.262 + Area ) R JA = 26.51 + ------------------------------------- (c)2002 Fairchild Semiconductor Corporation (EQ. 2) Rev. B IRF630N/IRF630NS/IRF630NL Thermal Resistance vs. Mounting Pad Area IRF630N/IRF630NS/IRF630NL PSPICE Electrical Model .SUBCKT IRF630N 2 1 3 ; rev May 2001 CA 12 8 1.6e-9 CB 15 14 1.75e-9 CIN 6 8 9.3e-8 LDRAIN DPLCAP DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 5 51 - IT 8 17 1 LGATE GATE 1 ESLC 11 + 50 17 EBREAK 18 - RDRAIN 6 8 ESG DBREAK + RSLC2 EVTHRES 16 21 + 19 8 + EVTEMP RGATE + 18 22 9 20 6 DBODY MWEAK MMED MSTRO RLGATE LSOURCE CIN 8 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD SOURCE 3 7 RSOURCE RLSOURCE S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.98e-1 RGATE 9 20 1.61 RLDRAIN 2 5 10 RLGATE 1 9 51.2 RLSOURCE 3 7 42.4 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B RLDRAIN RSLC1 51 EBREAK 11 7 17 18 227 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 LDRAIN 2 5 1e-9 LGATE 1 9 5.12e-9 LSOURCE 3 7 4.24e-9 DRAIN 2 5 S2A 13 8 S1B CA RBREAK 15 14 13 17 18 RVTEMP S2B 13 CB 6 8 EGS 5 8 EDS - 19 VBAT + IT 14 + + - 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*19),2.5))} .MODEL DBODYMOD D (IS = 1e-12 N=1.02 RS = 7.75e-3 TRS1 = 2.5e-3 TRS2 = 2e-5 CJO = 8.5e-10 TT = 9.6e-6 M = 0.61 XTI=5.5) .MODEL DBREAKMOD D (RS = 4. 2TRS1 = 1e- 3TRS2 = -8.9e-6) .MODEL DPLCAPMOD D (CJO = 1.15e- 9IS = 1e-30 N = 10 M = 0.86) .MODEL MMEDMOD NMOS (VTO = 3.25 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.61) .MODEL MSTROMOD NMOS (VTO = 3.65 KP = 28 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.8 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 16.1 RS=.1) .MODEL RBREAKMOD RES (TC1 =1.3e- 3TC2 = 2e-6) .MODEL RDRAINMOD RES (TC1 = 1e- 2TC2 = 3.7e-5) .MODEL RSLCMOD RES (TC1 = 4e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -1.3e-5) .MODEL RVTEMPMOD RES (TC1 = -3e- 3TC2 = 1.9e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.5 VOFF= -.5) VON = -.5 VOFF= -7.5) VON = -0.1 VOFF= 0.2) VON = 0.2 VOFF= -0.1) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2002 Fairchild Semiconductor Corporation Rev. B IRF630N/IRF630NS/IRF630NL SABER Electrical Model REV May 2001 template IRF630N n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 1e-12, rs = 7.75e-3, xti = 5.5, trs1 = 2.5e-3, trs2 = 2e-5, cjo = 8.5e-10, tt = 9.6e-6, m = 0.61) dp..model dbreakmod = (rs = 4.2, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 1.15e-9, isl = 10e-30, nl=10, m = 0.86) m..model mmedmod = (type=_n, vto = 3.25, kp = 5, isl = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.65, kp = 28, isl = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.8, kp = 0.05, isl = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.5, voff = -.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -.5, voff = -7.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.2) LDRAIN sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.1) DPLCAP 5 DRAIN RLDRAIN RSLC1 51 RSLC2 ISCL dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod RDRAIN 6 8 ESG LGATE 11 DBODY EVTHRES 16 21 + 19 8 + GATE 1 DBREAK 50 - i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.12e-9 l.lsource n3 n7 = 4.24e-9 2 10 c.ca n12 n8 = 1.6e-9 c.cb n15 n14 = 1.75e-9 c.cin n6 n8 = 9.3e-8 EVTEMP RGATE + 18 22 9 20 6 MWEAK EBREAK + MMED MSTRO RLGATE m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u CIN 17 18 - 8 LSOURCE SOURCE 3 7 RSOURCE RLSOURCE res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = 2e-6 res.rdrain n50 n16 = 1.98e-5, tc1 = 1e-2, tc2 =3.7e-5 res.rgate n9 n20 = 1.61 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51.2 res.rlsource n3 n7 = 42.4 res.rslc1 n5 n51= 1e-6, tc1 = 4e-3, tc2 = -1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 10e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2e-3, tc2 = -1.3e-5 res.rvthres n22 n8 = 1, tc1 = -3e-3, tc2 = 1.9e-6 S1A 12 S2A 13 8 15 14 13 S1B CA RBREAK 17 18 RVTEMP S2B 13 CB 6 8 EGS - 19 IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 227 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6*19))** 2.5)) } } (c)2002 Fairchild Semiconductor Corporation Rev. B th IRF630N/IRF630NS/IRF630NL SPICE Thermal Model JUNCTION REV May 2001 IRF630N CTHERM1 th 6 8.0e-4 CTHERM2 6 5 2.6e-3 CTHERM3 5 4 3.5e-3 CTHERM4 4 3 5.2e-3 CTHERM5 3 2 7.0e-3 CTHERM6 2 tl 3.3e-2 RTHERM1 th 6 1.0e-3 RTHERM2 6 5 4.5e-3 RTHERM3 5 4 4.2e-2 RTHERM4 4 3 2.5e-1 RTHERM5 3 2 3.9e-1 RTHERM6 2 tl 5.0e-1 RTHERM1 CTHERM1 6 CTHERM2 RTHERM2 5 SABER Thermal Model SABER thermal model IRF630N template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 8.0e-4 ctherm.ctherm2 6 5 = 2.6e-3 ctherm.ctherm3 5 4 = 3.5e-3 ctherm.ctherm4 4 3 = 5.2e-3 ctherm.ctherm5 3 2 = 7.0e-3 ctherm.ctherm6 2 tl = 3.3e-2 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 rtherm.rtherm1 th 6 = 1.0e-3 rtherm.rtherm2 6 5 = 4.5e-3 rtherm.rtherm3 5 4 = 4.2e-2 rtherm.rtherm4 4 3 = 2.5e-1 rtherm.rtherm5 3 2 = 3.9e-1 rtherm.rtherm6 2 tl = 5.0e-1 } RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl (c)2002 Fairchild Semiconductor Corporation CASE Rev. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4