bLE D WM 449be03 OOee?74 508 MBHITe HM514400A/AL/ASL Series 1,048,576-word x 4-bit Dynamic RAM The Hitachi HM514400A/AL/ASL is a CMOS dynamic RAM organized 1,048,576-word x 4-bit. HMS514400A/AL/ASL has realized higher density, higher performance and various functions by employing 0.8 um CMOS process technology and some new CMOS circuit design technologies. The HMSI4400A/AL/ASL offers fast page mode as a high speed access mode. Multiplexed address input permits the HMS514400A/AL/ASL to be packaged in standard 20-pin plastic SOJ, 20-pin plastic ZIP, 20-pin TSOP, and 20-pin ST-ZIP. Features Single 5 V (10%) + High speed Access time 60 ns/70 ns/80 ns (max) * Low power dissipation - Active mode 605 mW/550 mW/495 mW (max) Standby mode 11 mW (max) 0.83 mW (L-version) 0.55 mW (SL-version) Fast page mode capability * 1,024 refresh cycles: 16 ms 1,024 refresh cycles: 128 ms (L-version) * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * Test function * Battery back up operation (L-version) Data retention operation (SL-version) Ordering Information T~ 46-23-12 HITACHI/ LOGIC/ARRAYS/MEM Access Type No. time Package HM514400AJ/ALU/ASLJ-6 60 ns 350-mil HM514400AJ/ALJ/ASLJ-7 70 ns 20-pin HM514400AJ/ALJ/ASLJ-8 80 ns plastic SOJ (CP-20DA) HM514400AS/ALS/ASLS-6 60 ns 300-mil HM514400AS/ALS/ASLS-7 70 ns 20-pin HM514400AS/ALS/ASLS-8 80 ns plastic SOJ (CP-20D) HM514400AZ/ALZ/ASLZ-6 60 ns 400-mil HM514400AZ/ALZ/ASLZ-7 70 ns 20-pin HM514400AZ/ALZ/ASLZ-8 80 ns plastic ZIP (ZP-20) HM514400AT/ALT/ASLT-6 60 ns 20-pin HM514400AT/ALT/ASLT-7 70 ns plastic HM514400AT/ALT/ASLT-8 80 ns TSOP |! (TFP-20DA) HM514400AR/ALR/ASLR-6 60 ns 20-pin HM514400AR/ALR/ASLA-7 70 ns plastic HM514400AR/ALR/ASLA-8 80 ns TSOP I raverse type (TFP-20DAR) HM514400ATT/ALTT/ASLTT-6 60 ns 20-pin HM514400ATT/ALTT/ASLTT-7 70 ns plastic HM514400ATT/ALTT/ASLTT-8 80 ns TSOP Ii (TTP-20D} HM514400ARR/ALRA/ASLRR-6 60 ns 20-pin HM514400ARR/ALRR/ASLRR-7 = 70. ns plastic HMS514400ARR/ALRR/ASLRA-8 = 80 ns. TSOP I reverse type (TTP-200R) HM514400ATZ/ALTZ-6 60 ns 20-pin HM514400ATZ/ALTZ-7 70 ns plastic HM514400ATZ/ALTZ-8 80 ns ST-ZIP (ZP-20S) 363bLE D MM 4496203 OOee?75 444 MBHITe2 HMS514400A/AL/ASL Series HITACHI/ LOGIC/ARRAYS/MEM Pin Arrangement HM514400AJ / ALJ / ASLJ Series HM514400AZ / ALZ / ASLZ Series HM514400AS / ALS / ASLS Series HM514400ATZ/ALTZ Series Hitachi pin No. JEDEC pin No. __ | 1 OE CAS 2 7 3 403 vor 1[ |] 1 26|{ 20 Veg vO4 4 J 5 voz 2[ |j2 25{| |19 vo4 VO1 6 s __ 7 woe We 3[ |/3 24|[] 18 vos WE 8 _ ane 9 RAS RAS 4[ || 4 23|[_|17 CAS Ag 10 GE 11 AO ao 5[ |i5 22 || ]16 OE AL 12 13 A2 A3 14 ao 6[ |l9 18 || ]15 As 15 Voc A4 16 Ai 7[_|/10 17|[_ ]14 a7 17 AS AG 18 a2 8[_|li1 16|{ ]13 Ae 19 AT as 9[_ |i12 15], ]12 As AB 20 i Voc 10[ |} 13 14][ J 41 a4 (Top View) (Bottom View) HM514400AT / ALT / ASLT Series OF 1774 O [1 20 A8 CAS 2174 [T] 19 A7 VO3 3074 LT] 18 A6 VO4 4CC4 [1 17 AS Vsg 5 C7] C16 A4 vO1 6C FT] 15 Vcc vo2 704 I") 14 A3 WE 80) [1 13 A2 RAS 907 [tT] 12 Al AQ 100. [T1111 AO (Top View) 364bB1E D MM 4496203 O02277b 360 MBHIT2 HMS514400A/AL/ASL Series Pin Arrangement (cont) HITACHI/ LOGIC/ARRAYS/MENM HM514400AR / ALR / ASLR Series Ag 10 L111 AQ RAS 9 CI [1112 Al WE 8 C1 P1113 A2 Vo2 7 (4 [1914 A3 voi 6 14 O E115 Voc Vss 5 CO [T1116 A4 vO4 4 (Lo [1317 AS VO3 3 (7 [1118 AG CAS 2 OJ Q [1119 A7 OE 107 20 A8& (Top View) HM514400ATT / ALTT / ASLTT Series HM514400ARR / ALRR / ASLRR Series vor 1 |C) | ]20 Vgg Vsg 20[ _| QC) [1 vor voz 2[_ | | ]19 vos vos 19[ | | |2 voe we 3[_| |] 18 vos vos 18[_ | | |3 We RAS 4[ | Bac CAS 17[_| |] 4 RAS ao 5 [| | ]16 OF OE i6[ | | |s5 as ao 6[_| |] 15 a8 as 15[_| | ]6 Ao ar 7[_| | ]14 a7 a7 i4[_| [7 at a2 [| | ]13 a6 as 13[_ | | |s a2 as o[_ | | | 12 As As 12[_ | | |9@ a3 Voc 10[ | [at Aa aa it [| | }10 Vgc (Top View) (Top View) 965bLE D MM 4456203 0022777? 217 MMHIT2 HM514400A/AL/ASL Series HITACHI/ LOGIC/ARRAYS/MEM Pin Description Pin name Function Pin name Function Ao Ag Address input WE Read/write enable Ao - AQ Refresh address input OE Output enabie VO1 - 1/04 Data-in/data-out Veco Power (+5 V) RAS RoW address strobe Vsg Ground CAS Column address strobe 366367 dury asuas Y>-d dwry asuas Y>-d Aeiry jap Kowa 1957 dwiy asuas 4>-N Japorag ULUNJOD F $Ng Ost dury asuas Y2-N Control Circuit | Aesry Jap owayy 4967 duy asuas y-d AY} Aeasy |\a> Nowa 4952 duny asuas YN Japorag ULUNIOD 8 SNg Of Column Address Buffer j HMS514400A/AL/ASL Series Control Circuit duny asuas y>-N pe} Keasy [18> Aiowayy 1 9S2 dusy asues 42-4 wa pae epee ~ fp --b- 4 tp eed ee dwry asuas yo-d )Y Control Circuit dury asuas yo-d dury asuas 4>-d > Aesny 1189 Lowayy 4 9SZ duwiy asuas Uo-N Address AQ ~ AQ saporag UWN}OD 3 $Ng O/ diy asuas Y2-N Row Decoder & Peripheral Circuit RAS Control Circuit V/O2 Buffer >| Aeisy }jap Awa 1957 dwiy asuas y>-d KL Kearny 99 Aowayw 1 9SZ bLE D MM 4496203 0022778 153 MBHITe HITACHI/ LOGIC/ARRAYS/MEM Block Diagram dwiy asuas Y>-N saporag UWNIOD 8 5Ng OA dury asuas 4-N Aewiy 1a Lowa 4 9SZ dwiy asuas 4-d dury asuas y>-d Row Address Buffer V/O1 Buffer | LfGLE D MM 4496203 0022779 O9T MEHIT2 HMS514400A/AL/ASL Series HITACHI/ LOGIC/ARRAYS/MENM Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to Vgg Vr 1.0 to +7.0 ai Supply voltage relative to Vgg Voc -1.0 to +7.0 V Short circuit output current lout 50 mA Power dissipation Pr 1.0 w Operating temperature Topr 0 to +70 C Operating temperature (SL-version) Topr 0 to +60 C Storage temperature Tstg 55 to +125 C Recommended DC Operating Conditions (Ta = 0 to +70C) (Ta = 0 to +60C (SL-version)) Parameter Symbol Min Typ Max Unit Notes Supply voltage Vss 0 0 0 V Voc 4.5 5.0 5.5 V 1 4.0 _ 5.5 Vv 1,2 Input high voltage Vin 2.4 _ 6.5 Vv 1 input low voltage VIL 1.0 0.8 V 1 Notes: 1. All voltage referenced to Vgg 2. Only for data retention operation (SL-version) 368BLE D MM 4456203 0022780 401 MEHITe HITACHI/ LOGIC/ARRAYS/MEM HMS514400A/AL/ASL Series DC Characteristics (Ta = 0 to +70C, Voc = 5 V t 10%, Vsg = 0 V) (Ta = 0 to +60C, Voc = 5 V + 10%, Vgg = 0 V (SL-version)) HM514400A HM514400A HM514400A 6 7 8 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Operating lect 360 -ia100s ss 100 2S =3 90s mAs RAS, TAS cycling 1,2 current tro = min Standby current Icco 2 2 2 mA TTL interface RAS, CAS = Vin Dout = High-Z _ 1 _ 1 _ 1 mA CMOS interface RAS, CAS > Voc -0.2V Dout = High-Z Standby current _ 150 150 150 pA CMOS interface 4 (L-version) RAS, CAS = Vin WE, OE, address, Standby current _ 100 100 100 pA Din=Vyyor Vii (SL-version) Dout = High-Z RAS-only refresh Ioc3 10 100 90 mA tag =min 2 current Standby current Ioc5 5 5 5 mA RAS =Vin 1 CAS = VIL Dout = enable CAS-before-RAS = Iocg _ 10 0 100 90 mA tag = min refresh current Fastpage mode Icc7 10 100 90 mA tpc=min 1,3 current Batterybackup Iccig 200 200 200 WA tag = 125 ps 4 operation current tras 1 HS (CBR refresh) WE = Vin CAS = Vit (L-version) OE, address, Din = Vin or VIL Dout = High-Z Data retention _ 150 150 150 pA trac = 250 us 4 current (CBR refresh) (SL-version) tras = 200 ns WE = Vin, CAS = Vit OE, address, Din = Vin or Vit Dout = High-Z 40V<Voo 85.5V 369 eeebLE D MM 4496203 0022781 748 MBHITe M HM514400A/AL/ASL Series HITACHT/ LOGIC/ARRAYS/ME DC Characteristics (Ta = 0 to +70C, Voc =5 V+ 10%, Vsg =0 V) (Ta = 0 to +60C, Voc= SVE 10%, Vss = 0 V (SL-version)) (cont) HM514400A HM514400A HM514400A -6 7 8 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Input leakage lo -10 10 -10 10 -10 10 pA OV<SVins7V current Output leakage = Ito -10 10 -10 10 -10 10 HA OV<Vout<s7V current Dout = disable Output high Vou 24 Veco 24 Veco 24 Veo V High lout = -5 mA voltage Output low VoL 0 04 #0 04 0 04 V Low lout = 4.2 mA voltage Notes: 1. Ig depends on output load condition when the device is selected. loc max is specified at the output open condition. 2. Address can be changed twice or less while RAS = Vi. 3. Address can be changed once or less while CAS = Vip. 4. Voo-0.2V< Vi <6.5V,0Vs Vy <0.2V. Capacitance (Ta = 25C, Voc =5 V+ 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) Cy _ 5 pF 1,3 Input capacitance (Clocks) Cio _ 7 pF 1 Output capacitance (Data-in, data-out) Cyo 10 pF 1,2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = Vi to disable Dout 3. Ciy (max) = 7 pF for HM514100ATZ/ALTZ Series. 370BLE D MM 4496203 OO22782 644 MBHIT2 HITACHI/ LOGIC/ARRAYS/MEN HM514400A/AL/ASL Series AC Characteristics (Ta = 0C to +70C, Voc = 5 V + 10%, Vgg = 0 V)*!. #14, #15. *16 (Ta = 0C to +60C, Voc = 5 V t 10%, Vgg = 0 V (SL-version)) Test Conditions Input rise and fall times: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output load: 2 TTL gate + Cy (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM514400A HM514400A HM514400A 6 7 8 Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time tac W000 130 150 ns RAS precharge time tae 40 50 60 ns RAS pulse width tras 60 10000 70 10000 80 =: 10000 ns 19 CAS pulse width toas 15 1000020 1000020 10000ns 20 Row address setup time tasr 0 - oO 0 _ ns Row address hold time tRAH 10 10 10 = ns Column address setup time tasc 0 a - oOo ns Column address hold time tcAH 5 6 6 ns RAS to CAS delay time tacb 20 45 20 50 20 60 ons 8 RAS to column address delay time trap 15 30 15 35 15 40 ns 9 RAS hold time tasH 15 20 - 2 = as CAS hold time tosH 60 70 80 = ns CAS to RAS precharge time torP 10 10 10 = ns OE to Din delay time topp 156 2 - 2 = ns OE delay time from Din tpzo 0 - 9a 0 ns CAS setup time from Din tpzc 0 oO oO ons Transition time (rise and fail) tr 3 50 3 50 3 50 ns 7 371BLE D MM 4496203 0022783 510 MBHIT2 HMS514400A/AL/ASL Series HITACHI/ LOGIC/ARRAYS/MEN Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) (cont) HM514400A HM514400A HM514400A -6 -7 - Parameter Symbol Min Max Min Max Min Max Unit Notes Refresh period tREF _ 6 146 16 ms Refresh period (L-version) tREF _ 128 128 128 ms Refresh period (SL-version) tREF _ 256 256 256 ms 21 Read Cycle HM514400A HM514400A HM514400A 6 7 -8 Parameter - Symbol Min Max Min Max Min Max Unit Notes Access time from RAS trac - 60 - 7O ~ 80 rs 2,3,17 Access time from CAS tcac - 56 20 j- 20 ns 3,4,13,17 Access time from address tag - 3s 3 40 ns 3,5,13,17 Access time from OE toac - 6&6 ~ 2 20 ns 3,17 Read command setup time tres 0 _ 0 _ 0 _ ns Read command hold time to CAS tacy =O o - oO ons 18 Read command hold time to RAS tapy 0 - 0 ~ oO on 18 Column address to RAS lead time tray 30 )638606UC SCHOO Sots Output buffer turn-off time torr4 0 15 0 20 20 20 ons 6 Output buffer turn-off to OE forF2 0 156 0 20 =O 20 ns 6 CAS to Din delay time tcpp 15 - 2 2 os OE pulse width toep 15 ~- 20 20 os 372BLE D MM 4496203 0022784 4S? MBHIT2 HMS514400A/AL/ASL Series Write Cycl ycle HITACHI/ LOGIC/ARRAYS/MEM HM514400A HM514400A HM514400A 6 7 8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time twes 0 _ 0 _ 0 _ ns 10 Write command hold time twou 5 156 15 - ns Write command pulse width twe 10 10 10 ns Write command to RAS lead time tay. 15 2 20 = ns Write command to CAS lead time tow. 15 2 20 = ns Data-in setup time tos 0 - oO - a ns 11 Data-in hold time tbH 56 6&8 15 ns 11 Read-Modify-Write Cycle HM514400A HM514400A HM514400A 6 7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time trwe 160 180 200 = ons RAS to WE delay time tRwp so 98 105 ns 10 CAS to WE delay time two 3 45 j 45 ns 10 Column address to WE delay time tawp 50 60 6 ns 10 OE hold time from WE ; toEH 165 20 20 _ ns 373BLE D MM 4446203 0022785 393 MBHITe ; HITACHI/ HMS514400A/AL/ASL Series LOGIC/ARRAYS/MEM Refresh Cycle HM514400A HM514400A HM514400A 6 7 8 Parameter Symbol Min Max Min Max Min Max Unit Notes CAS setup time tosr 10 - 10 - 110 ns (CAS-before-RAS refresh cycle) CAS hold time tour 10 10 - 10 = os (CAS-before-RAS refresh cycle) RAS precharge to CAS hold time tapc 10 10 10 ns CAS precharge time in normal topn 10 10 - 10 ns mode Fast Page Mode Cycle HM514400A HM514400A HM514400A 6 7 8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time tec 40 _ 45 _ 50 _ ns Fast page mode CAS precharge tcp 10 10 10 ns time Fast page mode RAS pulse width tpasc 100000 100000 100000ns 12 Access time from CAS precharge tacp - 3 40 45 ns 3,13,17 RAS hold time from CAS taucp 35 40 45 ns precharge Fast Page Mode Read-Modify-Write Cycle HM514400A HM514400A HM514400A 6 7 8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode read-modify-write tpoy 80 9 100 ns cycle time TAS precharge to WE delay time tcpy 55 6 7 ns 10 374b1E D MM 4496203 0022786 2eT MBHITC Test Mode Cycle HM514400A HM514400A HM514400A 6 7 8 Parameter Symbol Min Max Min Max Min Max Unit Notes Test mode WE setup time tws 0 oO oOo ons Test mode WE hold time twH 1 0 10 = ns Counter Test Cycle HM514400A HM514400A HM514400A 6 7 8 Parameter Symbol Min Max Min Max Min Max Unit Notes CAS precharge time in counter tcpt 40 40 40 as test cycle Notes: 1. AC measurements assume ty = 5 ns. np OuPpo ~ 10. 15. Assumes that tacp $ tacp (max) and tgap < trap (max). If tacp or taap is greater than the maximum recommended value shown in this table, trac exceeds the value shown. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. Assumes that tacp 2 tacp (max) and trap < trap (max). Assumes that tacp < tacp (max) and trap > trap (max). torr (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. Vin (min) and Vy (max) are reference levels for measuring timing of input signals. Also, transition times are measured between Vj, and V),. Operation with the tacp (max) limit insures that tpac (max) can be met, tacp (max) is specified as a reference point only, if tacp is greater than the specified tacp (max) limit, then access time is controlled exclusively by tcac- Operation with the trap (max) limit insures that trac (max) can be met, tap (max) is specified as a reference point only, if trap is greater than the specified taap (max) limit, then access time is controlled exclusively by taa. twos. tawp- tewp: tawp and tcpy are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twos 2 twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tawp 2 tawp (min), tewp 2 tewp (min), tawp 2 tawp (min) and tcpw 2 tcpyw (min) the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. . These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. . taasc defines RAS pulse width in fast page mode cycles. . Access time is determined by the longest of tag or tcac Or tacp- . An initial pause of 100 ps is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. In delayed write or read-modify-write cycles, OE must disable output buffers prior to applying data to the device. 375BLE D MM 4496203 0022787 bb MBHITA2 HM514400A/AL/ASL Series HITACHT/ LOGIC/ARRAYS/MEM 16. Test mode operation specified in this data sheet is 2-bit test function controlled by contro! address bits CAO. This test mode operation can be performed by WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. In order to end this test mode operation, perform a RAS-only refresh cycle or a CAS-before-RAS refresh cycle. 17. In a test mode read cycle, the value of trac. toac. tan, toac and tacp is delayed for 2 ns to ns for the specified value. These parameters should be specified in test mode cycies by adding the above value to the specified value in this data sheet. 18. Either tac} or tap must be satisfied. 19. tras (min) = tawp (min) + taw_ (min) + ty in read-modify-write cycle. 20. tcas (min) = town (min) + tow (min) + ty in read-modify-write cycle. 21. taer is 16 ms without data retention. 3761 BIE D MB 4496203 00227848 OT2 MEHITe2 HMS514400A/AL/ASL Series Timing Waveforms Read Cycle HITACHT/ LOGIC/ARRAYS/MEt Address Dout Din trap traH tase Column * : Don't care 377BLE D MM 4496203 0022749 139 MHIT2 HMS514400A/AL/ASL Series HITACHI/ LOGIC/ARRAYS/MEN. Early Write Cycle a tre tras . ash RAS N fi tT P tesu . i treo vie teas . "tere tes . __ N CAS A tea t {7 Address G ZY} twes tweu we __ tou High-z** * Ui : Dont carebLE D MM 4496203 0022790 750 MBHITe HM514400A/AL/ASL Series Delayed Write Cycle HITACHI/ LOGIC/ARRAYS/MEM . tre > tras p| [qth 4! \ \ RAS k 7 Di tes ol te tore tu. . taco ale trsn > 4 t CAS Ni as > RY 4 tow. > tasRy | tascplte tawe > lgtRAH __tcan | Address Row Columa IZ tres a WE High-Z Din 4 tbzc > tozo, Invalid Dout ea Dout** __ y OE na torr2 * : Don't care ** Invalid Dout comes out, when OE is low level. 379bLE D MM 449u203 OO22791 697 MBHITe /MEM HMS514400A/AL/ASL Series HITACHI/ LOGIC/ARRAYS Read-Modify-Write Cycle CAS Address Column Din Dout * : Don't care 380BLE D MM 4496203 0022792 S23 MEHIT2 HMS514400A/AL/ASL Series CAS-Before-RAS Refresh Cycle HITACHI/ LOGIC/ARRAYS/MEM tre High-Z * : Don't care sh Cycle < tre > tr | [q_ tS! Lg tap > > RAS N \ . Llcre Pile Kn AS = High-Z * Refresh Address AO ~ AQ (AX0 ~ AX9) * yy > Dont care *** WE : Don't care , 381bLE D MM 4496203 0022793 4bT MBHITe HMS514400A/AL/ASL Series HITACHT/ LOGIC/ARRAYS/MEM Hidden Refresh Cycle tac wt tre . tre _ tras tre tras tap | tras tre. t > | >| << (Read) (Refresh) (Refresh) 7 *Y 3 YN RAS N \ tere | \ t_ | tp ae tasty _ ag __tCHR x ig _tRCD teas ~ CAS - x i 4 7 t, tasr | ASS trap traL RAY teay y Address Row K at tRcH t RCS >| tery we i teas {CAC | taa t torr RAC oo | y Dout __}+{ Dout K torr2 . t t DZC coo, Din High-Z tpzo) |Ltoa top * YY} : Don't care 382b1E D MM 4496203 0022794 3Tb MBHIT2 HMS514400A/AL/ASL Series Fast Page Mode Read Cycle HITACHT, LOGIC /ARRAYS/M EM) 4 trasc _, __tRHCP >| be tre, 1 yt~CSC=stsSN mas N y \ tr + toy i Ly tec > SH dcr treo gigteas | 1 tor sy igteas, |, tee 1, TAS 4 y A oR L ot NUL, KJ 4 RAD _y tase trau tean ef trat > tase| | Wea tasc| le >| | taschen) UA Address Row 1D Col. Cal. Xt Col. | 7 K K. tacs 1 tacs I _ traRH > L tres trace) trey] vr gts tcoo| |, t tozc te | DD , tozc tozc teoo Lo >] High-z High-2 High-Z Din topo t tea Lo CAC . tcac - oo > . > tan . tan ty le trac tacr > tace > - - torrs | ford tozo torr y > yy Dout __+____{ Bout b 4 Dout ) {oout - ton 4225, OE. y WL * YH : Don't care 3831 GLE D MM 4y4yguag3 0022795 23a MBHIT2 HMS514400A/AL/ASL Series Fast Page Mode Early Write Cycle HITACHI/ LOGIC/ARRAYS/MEF trasc ! |e tre , Fas K A * K A < test >| I tee ~ gtRSH tr mq RCO teas te tee | |e tcas | tce | | teas tore id } N } toaH Dout E : Don't care ** : Dont care 384BLE D MM 4496203 0022796 179 MMHIT2 HMS514400A/AL/ASL Series Fast Page Delayed Write Cycle HITACHT/ LOGIC/ARRAYS/MEM ___ 4 tras > qth yt | RAS \ \ K. 7 tr_.| i *sH > I tec > 85H v| fe taco |. teas tor. tras top tea tere < < >) |< rite S | N / N KT A toan toay tasc tase | teow H Col. Col. Col. tcwL Py tow. t twe twe twa, | RCS + > RW WE ton tacs tou tres tou tos tos tos Din Din Din Din tocn High-z Dout tooo * Ly : Don't care 385bLE D MM 4496203 002279? O05 MBHITe HMS514400A/AL/ASL Series HITACHI/ LOGIC/ARRAYS/MEM Fast Page Mode Read-Modify-Write Cycle . GY : Don't care 386bLE D MM 4496203 0022798 TH) MBHITe HMS514400A/AL/ASL Series Test Mode Cycle HITACHI, LOGIC/ARRAYS/MEM cle) Normal Mode Me 2 @ 4 L \ a 4 g s 2 a o a Me a a = 4 4 L w a e tec . _ trp al le. al te tre aS f 1 K dnc, tcsr CHR, tepy aq thPC tcrp t>}] |<} | > <?+-__ ty > ten j torr1 Dout Y//7 . : Don't care gIbLE D MM 4496203 0022799 964 MBHITe HITACHI/ LOGIC/ARRAYS/MEM HM514400A/AL/ASL Series CAS-Before-RAS Refresh Counter Check Cycle (Read4 BLE D MM 4496203 0022800 4eT MMHITe HMS514400A/AL/ASL Series CAS-Before- RAS Refresh Counter Check Cycle (Write) HITACHI/ LOGIC/ARRAYS/ME} High-Z [Ai Dout OE . : Dont care