8284A/8284A-1 Clock Generator and Driver for 8086, 8088 Processors DISTINCTIVE CHARACTERISTICS @ Generates the System Clock for the 8086, 8088 Proces- @ Generates system reset output from Schmitt trigger sors: 5MHz, 8MHz with 8284A; 10MHz with 8284A-1 input @ Uses a crystal or a TTL signal for frequency source Capable of clock synchronization with other 8284As @ Provides local READY and Multibus* READY synchroni- zation GENERAL DESCRIPTION The 82844 is a single chip clock generator/driver for the trolled oscillator, a divide-by-three counter, complete 8086, 8088 processors. The chip contains a crystal-con- MULTIBUS* "Ready" synchronization and reset logic. BLOCK DIAGRAM RES [>_/> _ Qf RESET L-W8Z8/VPszcs maqick xy XTAL %;$~J osciiarorn [7] > osc Ae +3 +2 COUNT fb @| COUNT f pcLK fr SYNC SYNC sync _| RADY, t + >- cLK ER, ROY, l cKY cK} KEN, D a D @;-~ READY FF, FF2 ASYRC BD001440 RELATED AMD PRODUCTS Part No. Description Ams086 | 16-Bit Microprocessor 8288 | Bus Controller *MULTIBUS is a registered trademark of Intel Corp. Publication # Rev, Amendment 03359 D /0 3-389 Issue Date: April 19878284A/8284A-1 DIPs CONNECTION DIAGRAMS Top View CD001582 Note: Pin 1 is marked for orientation. cb009272 3-390ORDERING INFORMATION Commodity Products AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type c. Device Number d. Speed Option e. Optional Processing T | L OPTIONAL PROCESSING Blank = Standard Processing B = Bum-in d. SPEED OPTION Blank = For 5-MHz & 8-MHz Applications -1=For 10-MHz Applications c, DEVICE NUMBER/DESCRIPTION 8284A Clock Generator and Driver for 8086, 8088 Processors b. PACKAGE TYPE P= 18-Pin Plastic DIP (PD 018) O = 18-Pin Ceramic DIP (CD 018) N = 20-Pin Plastic Leaded Chip Carrier (PL 020) a. TEMPERATURE RANGE Blank = Commercial (0 to + 70C} M = Military* (55 to + 125C) Valid Combinations Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device. Consult the local AMD MD, D, P, N 8284A sales office to confirm availability of specific valid MD, D, P 8284AB combinations, to check on newly released valid combinations, 82B4A-1 and to obtain additional data on AMD's standard military D 8284A-1B grade products. *Military temperature range products are NPL (Non- Compliant Praducts List) or Non-MIL-STD-883C Compliant products only. 3-391 L-Veezs/vPrecs8284A/8284A-1 PIN DESCRIPTION Pin No. |Name 1/0 | Description 3,7 AEN. I Address Enable. The AEN signal is used to qualify the Bus Ready signal (RDY4 or RDY2). AEN} validates ARDY while AEN2 AENp validates RDYo:. It is possible for the processor to access two Multi-Master System Busses if you use both signals. Both signals are tied LOW in non Multi-Master Systems. 4,6 RADY, l Bus Ready. These signals are indications from a device located on the system bus that it is available or data has been RDY2 feceived. RDY; and RDY2 are qualified by AEN; and AEN respectively. 15 ASYNC | Ready Synchronous Select. The ASYNC signal defines the synchronization mode of the READY logic. When ASYNG is Nn (internal pull-up resistor is provided) or pulled HIGH, there is one stage of READY Synchronization. When is LOW, there are two stages of READY Synchronization. 5 READY oO Ready. READY is the synchronized RDY signal input. After the guaranteed hold time to the processor has been met, the READY signat is cleared. 7, 16 X1.X2 i Crystal In. These are the input pins for the attached crystal. The crystal frequency is 3 times the desired process clock frequency. 13 F/T l Frequency/Crystal Select. When F/T is strapped HIGH, CLK is generated from the EFI input. When strapped LOW, the F/T allows the processor clock to be generated by the crystal. 14 EFI | External Frequency. Used in conjunction with a HIGH signal on F/T, CLK is generated from the input frequency appearing on this pin. The input signal is a square wave 3 times the frequency of the desired CLK output. B CLK 0 Processor Clock. CLK is the clock output used by the processor and all devices which directly connect to the processor's local bus (including bipolar support chips and other MOS devices). An output HIGH of 4.5V (Voc = 5V) is provided on this pin to drive MOS devices. The output frequency of CLK is 1/3 of the crystal on EFI input frequency and a 1/3 duty cycle. 2 PCLK 0 Peripheral Clock. This signal is a TTL evel peripheral clock signal whose output frequency is 1/2 that of CLK and has a 50% duty cycle. 12 Osc Oscillator Output. This signal is the TTL level output of the internal oscillator circuitry. Its frequency is equal to that of the crystal. "1 RES { Reset In. This signat is used to generate a RESET. The 8284A provides a Schmitt trigger input so that an AC connection can be used to establish the power-up reset of proper duration. 10 RESET oO Reset. This signal is used to reset the 8086 family processors. 1 CSYNC | Clock Synchronization. This signal is designed to allow multiple 8284As to be synchronized to provide clocks that are in phase. CSYNC HIGH will reset the internal counters, when CSYNC goes LOW the counters will resume counting. CSYNC needs to be externally synchronized to EFI. When used with the internal oscillator, CSYNC should be hard wired to ground. DETAILED DESCRIPTION OSCILLATOR The oscillator circuit of the 8284A is designed primarily for use with a fundamental mode, series resonant crystal from which the operating frequency is derived. The crystal frequency should be selected at three times the required CPU clock. X; and Xg are the two crystal input crystal connections, The output of the oscillator is buffered and brought out on OSC sc that other system timing signals can be derived from this stable, crystal-controlled source. Two 5102 series resistors are optional for systems which have a Vcc ramp time greater than (or equal to) 1V/ms and/or inherent board capacitance between X1 or Xo exceeding 10pF. This capacitance value should not include the 8284A's pin capacitance. By limiting the stray capacitance to less than 10pF on X; or Xa, the deviation from the desired fundamental frequency is minimized. CLOCK GENERATOR The clock generator consists of a synchronous divide-by-three counter with a special clear input that inhibits the counting. This clear input, (CSYNC), allows the output clock to be synchronized with an external event (such as another 8284A clock). It is necessary to synchronize the CSYNC input to the EFI clock external to the 8284A (see Figure 1). This is accomplished with two Schottky flip-flops. The counter output is a 33% duty cycle clock at one-third the input frequency. The F/C input is a strapping pin that selects either the EFI input or the crystal oscillator as the clock for the +3 counter. If the EFI input is selected as the clock source, the oscillator section can be used independently for another clock source. Output is taken from OSC. CLOCK OUTPUTS The CLK output is a 33% duty cycla MOS clock driver designed to drive the 8086 or 8088 processors directly. PCLK is a TTL level peripheral clock signal whose output frequency is Y2 that of CLK. PCLK has a 50% duty cycle. RESET LOGIC Reset logic for the 8284A is provided by a Schmitt trigger input (RES) and a synchronizing flip-flop to generate the reset timing. The reset signal is synchronized to the falling edge of CLK. A simple RC network can be used to provide power-on reset by utilizing this function of the 8284A. READY SYNCHRONIZATION Two READY inputs (RDY1, RDY2) are provided to accommo- date two Multi-Master system busses. Each input has a qualifier (AEN, and AENp, respectively). The AEN signals validate their respective RDY signals. If a Multi-Master system is not being used the AEN pin should be tied LOW. To assure RDY setup and hold times are met, synchronization is required for all asynchronous active going edges of either RDY input. Inactive-going edges of RDY (in normally ready systems) do not require synchronization, but must satisfy RDY setup and hold as a matter of proper system design. The two modes of RDY synchronization operation are defined by the ASYNC input. When ASYNC is LOW, two stages of synchronization ara provided for active RDY input signals. Positive-going asyn- chronous RDY inputs will first be synchronized to flip-flop one at the rising edge of CLK and then synchronized to flip-flop two at the next falling edge of CLK; after which time the READY output will go active (HIGH). Negative-going asynchro- 3-392nous RDY inputs will be synchronized directly to flip-flop two at the falling edge of CLK, after which time the READY output will go inactive. This mode of operation is intended for use by asynchronous, (normally not ready), devices in the system which cannot be guaranteed by design to meet the required RADY setup timing tRivc_ on each bus cycle. When ASYNC is high or left open, the first READY flip-flop is bypassed in the READY synchronization logic. RDY inputs are synchronized by flip-flop two on the falling edge of CLK before they are presented to the processor. This mode is available for synchronous devices that can be guaranteed to meet the required RDY setup time. ASYNC can be changed on every bus cycle to select the appropriate mode of synchronization for each device in the system. Figure 1. CSYNC Synchronization EFI B284n CLOCK SYNCHRONIZE @ > csync EFI >_+_Do >| >| (TO OTHER 8284Aa) DF000270 CLOCK HIGH AND LOW TIME (USING X4, X2) LOAD mF x, CLK (SEE NOTE 1) 2ametz [=] % Fe Ry 3 Ae cSYNC AFO000631 Ry = Re=5102. CLOCK HIGH AND LOW TIME (USING EFI) PULSE GENERATOR En LOAD cuk (SEE NOTE 1) AFO00620 3-393 L-V828/VPsSzs8284A/8284A-1 READY TO CLOCK (USING Xj, Xo) cc LOAD AEN, CLK (SEE NOTE 1) 30 pF T x _[ 1 READY LOAD 24MHz FJ] (SEE NOTE 2) Tot, 2 Pulse Generator RDY, osc Trigger FC s > 2 AEN, CSYNC 7 AFO04680 Ry =Re = 5102. READY TO CLOCK (USING EFI) PULSE LOAD EFI GENERATION 7 cLK (SEE NOTE 1) oc f F/C TRIGGER AEN, PULSE RDY2 GENERATION AEN LOAD CSYNC READY (SEE NOTE 2) AF00061 1 Notes: 1. CL = 100pF 2. CL =30pF 3-394ABSOLUTE MAXIMUM RATINGS Storage Temperature ............. eee -69C to + 150C Ambient Temperature with Powers Applied (COML, A-1) oo... ee cecee ec eee cece eeeeneeeneee 0S to +70C (MIL) 56C to +125C All Output and Supply Voltages .............. -0.5V to +7.0V All Input Voltage.............. eee eens -1.0V to +5.5V Power Dissipation ...........:c.cccccsecseeeereenteetaeeeenennes iW Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (CG) Devices Temperature 0.00.00... ccc eee cee n tween eeee ens oC to +70C Supply Voltage .............cceeeeeee eens +4,75V to +5.25V Military (M) Devices Temperature ...... .- 55C to +125C Supply Voltage .......... cece essere enee +4.5V to +5.5V Operating ranges define those limits between which the functionality and parameters of the device are guaranteed. DC CHARACTERISTICS over operating ranges unless otherwise specified Parameters Description Test Conditions Min Max Units Forward Input Current (ASYNC) Ve = 0.45V -13 lr Other Inputs VF = 0.45V -05 mA Reverse Input Current (ASYNC) Va = Voc 50 IR Other Inputs Vp = 5.25V 50 HA Vc input Forward Clamp Voltage Io =-5mA -1.0 Volts joc Power Supply Current 162 mA Vit Input LOW Voltage 0.8 Volts Vin Input HIGH Voltage 2.0 Volts VIHR Reset Input HIGH Voltage 26 Volts VoL Output LOW Voltage 5mA es 0.45 Volts Output HIGH Voltage CLK -1mA 4.0 26 VOH Other Outputs =1mA 2.4 Volts Vinr-VitR_ | RES Input Hysteresis (Note 1) 0.25 Volts Note 1. This specification is provided for reference only. 3-395 L-VP8ze/ipecs8284A/8234A-1 SWITCHING TESTING CIRCUIT (CLK, READY) Vy, = 2.08v A, = 9280 DEVICE UNCER TEST T TCO00670 CL = 100pF for CLK CL = 30pF for READY SWITCHING TESTING CIRCUIT (CLK, READY) SL vest T C, = 100pF Teo00680 CL = 100pF SWITCHING TESTING WAVEFORM (input, output) aa 1.5 = TEST POWTS = 4.5 o4s WF001870 AC testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Timing measurements are made at 1.5V for both a logic ''1"' and "0". SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified TIMING REQUIREMENTS Parameters Description Test Conditions Min Typ | Max | Units tEHEL External Frequency HIGH Time 80% - 90%Vin 13 ns tELEH External Frequency LOW Time 10% - 10%Viy 13 ns . MIL (Note 4) tener + teLeH + 6 tELEL EFI Period COM'L, Ad 33 ns XTAL Frequency 12 25 MHz tRIVeL RDY1, RDY2 Active Setup to CLK ASYNC = HIGH 35 ns. tRIVCH RDY;, RDY2 Active Setup to CLK ASYNC = LOW 35 ns tRIVCL ROY1, RDY2 Inactive Setup to CLK 35 ns tcLRix RDY;, RDY2 Hold to CLK 0 ns tayvcL ASYNC Setup to CLK 50 ns tCLAYX ASYNC Hold to CLK 0 ns tAIVAIV AEN}, AEN2 Setup to RDY;, RDY2 15 ns tcLa1x AEN,, AEN2 Hold to CLK 0 ns tVHEH CSYNC Setup to EFI 20 ns MIL 20 tEHYL CSYNC Hold to EFI COM'L, Ad 10 ns tYHYL CSYNC Width 2-tELeL ns tHe RES Setup to CLK (Note 2) 65 ns toLiiH RES Hold to CLK (Note 2) 20 ns tiLIH Input Rise Time From 0.8V to 2.0V 20 ns TLL Input Fall Time From 2.0V to 0.BV 12 ns 3-396TIMING RESPONSES Parameters Description Test Conditions Min Typ | Max | Units MIL, COM'L 125 CLK Cycle Period tcLeL Cy An 700 ns MIL, COM'L + toHoL CLK HIGH Time S (1/8 teucw) +2 ns A-1 39 MIL, IM - toLcH CLK LOW Time GOM'L (2/3 tcicL) - 15 ns A-1 3 tcHicHe CLK Rise or Fall Time 4.0V to 3.5V 10 | ns tCLacLi tPHPL PCLK HIGH Time tect - 20 ns tPLPH PCLK LOW Time toto. - 20 ns tRYLCL Ready Inactive to CLK (See Note 4) -8 ns MIL, COM'L / - tRYHCH Ready Active to CLK (See Note 3} A es sougd 8 ns tou CLK to Reset Delay 40 a tcLPH CLK to PGLK HIGH Delay 22 ns foLPL. CLK to PCLK LOW Delay 22 ns. tOLCH OSC to CLK HIGH Delay -5 22 ns tOLCL OSC to CLK LOW Delay 2 a5 ns tOLOH Output Rise Time (except CLK) From 0.8V to 2.0V 20 ns tOHOL Output Fall Time (except CLK) From 2.0V to 0.8V 12 ns Notes: 1. = EFI rise (5ns max) + EF} fall (5ns max). 2. Setup and hold necessary only to guarantee recognition at next clock. 3. Applies only to Tz and Ty states. 4. Applies only to Tg states. SWITCHING WAVEFORMS CLOCKS AND RESET SIGNALS D cnyena tory e] L ame} tere foun ean, b teen leneL + te tYHER ave, ey jo tour Hh tance ~ Res ' \ / teu reser 0 L__ WF002530 Note: All timing requirements are made at 1.5 volts, unless otherwise noted. 3-397 L-vreze/veszee8284A/8284A-1 READY SIGNALS (FOR ASYNCHRONOUS DEVICES) oh oa ron ADy, 2 t tarmw Ata "cunt 7 f\S ye Sf he jo SAIVEL el r TAvvee 7 REYNE teuaix f AEACY tryncn ee teearx trLeL i WF002520 READY SIGNALS (FOR SYNCHRONOUS DEVICES) [4 = aver ~| j See) ROY, j 4 tainiv 7 teLaix -- TEN \ tovaix 4 ScLayK Pt] lave, t WF002510