intel 8284A/8284A-1 CLOCK GENERATOR AND DRIVER FOR iAPX 86, 88 PROCESSORS = Generates the System Clock for the = Single +5V Power Supply iAPX 86, 88 Processors: 5 MHz, 8 MHz with 8284A u Generates System Reset Output from 10 MHz with 8284A-1 Schmitt Trigger Input u Uses a Crystal or a TTL Signal for Frequency Source ' . T = Provides Local READY and Multibus = Available in EXPRESS READY Synchronization - Standard Temperature Range = 18-Pin Package - Extended Temperature Range = Capable of Clock Synchronization with Other 8284As RES > D Gt RESET XTAL OSCILLATOR x2 | p> ose _ csync(1 18 [ec FIC __-_1 PoLk C2 vox +3 +4 +2 pe PCLK | AENI(] 3 16 |_] x2 EFI SYNC SYNC ADVICE KSYNC CSYNC | reapy (15 14 EFI RDy2(] 6 CFIC ROY) KENG (]7 12[lose t > + | > cik __ ___ cLKCs 14 REN Cc RES GNDL]9 10 |) RESET ADY2 l CKt CKt REN? D Q D Qt READY FFA FF2 ASYNG 8284A/8284A-1 Pin 8284A/8284A-1 Block Diagram Configuration 3-5678284A/8284A-1 Table 1. Pin Description HIGH, CLK is generated from the input fre- quency appearing on this pin. The input signal is a square wave 3 times the frequency Symbol | Type Name and Function Symbol | Type Name and Function AENt, | | Address Enable: AEN is an active LOW CLK O |} Pracessor Clock: CLK is the clock output AEN2 signal. AEN serves to quality its respective used by the processor and alt devices which Bus Ready Signal (ROY1 or RDY2). AEN1 directly connect to the processor's local bus validates RDY1 while AEN2 validates ROY2 (i.e., the bipolar support chips and other MOS Two AEN signal inputs are useful in system devices). CLK has an output frequency which configurations which permit the processor to is 4 of the crystal or EFI input frequency anda access two Multi-Master System Busses_ In % duty cycle. An output HIGH of 4.5 volts non Multi-Master configurations the AEN (Vcc= 5V)} is provided on this pin to drive MOS signal inputs are tied true (LOW). devices. RDY1, | | Bus Ready: (Transfer Complete). ROY is an PCLK O | Peripheral Clock: PCLK is a TTL level pe- RDY2 active HIGH signal which is an indication from ripheral clock signal whose output frequency a device located on the system data bus that is Ye that of CLK and has a 50% duty cycle. ie qualified by pa aaed ROY? aualifiod osc | Oscillator Output: OSC is the TTL level out- by AENS put of the internal oscillator circuitry. Its fre- : quency is equal to that of the crystal ASYNC | | | Ready Synchronization Select: ASYNC is an RES | | Reset In: RES is an active LOW signal which input which defines the synchronization is used to generate RESET. The 8284A mode of the READY logic. When ASYNC is provides a Schmitt trigger input so that an RC low, two stages of READY synchronization connection can be used to establish the are provided. When ASYNC 1s feft open power-up reset of proper duration. (internal pull-up resistor is provided) or HIGH a single stage of READY synchronization is RESET | O | Reset: RESET is an active HIGH signal which provided. : is used to reset the 8086 family processors. Its timing characteristics are determined by READY | O | Ready: READY is an active HIGH signal RES. which is the synchronized RDY signal input. 7 ; READY is cleared after the guaranteed hold CSYNC | | Clock Synchronization: CSYNC is an active time 10 the processor has been met. HIGH signal which allows multiple 8284As to be synchronized to provide clocks that are in M1, X2 | | Crystal in: X1 and X2 are the pins to which a phase. When CSYNC is HIGH the internal crystal is attached. The crystal frequency is 3 counters are reset. When CSYNC goes LOW times the desired processor clock frequency. the internal counters are allowed to resume FIC 1 | Frequency/Crystal Select: F/Cis astrapping counting. CSYNC needs to be externally syn- option. When strapped LOW, F/C permits the | chronized to EFI. When using the internal os- processor's clock to be generated by the crys- i cillator CSYNC should be hardwired to tal. When F/C is strapped HIGH, CLK is gener- | | ground. ated from the EFI input. | GND Ground. EFI | | External Frequency: When F/C ts strapped | Vee Power: +5V supply. ' of the desired CLK output. FUNCTIONAL DESCRIPTION General The 8284A is a single chip clock generator/driver for the iAPX 86, 88 processors. The chip contains a crystal- controled oscillator. a divide-by-three counter, com- plete MULTIBUS Ready synchronization and reset logic. Refer to Figure 1 for Block Diagram and Figure 2 for Pin Configuration. Oscillator The oscillator circuit of the 8284A is designed primarily for use with an external series resonant, fundamental mode, crystal from which the basic operating frequency is derived. 3-568 The crystal frequency snouid be selected at three times the required CPU clock. X1 and X2 are the two crystal input crystal connections. For the most stable operation of the oscillator (OSC) output circuit, two series resistors (R, = Ro = 510 2) as shown in the waveform figures are recommended. The output of the oscillator is buffered and brought out on OSC so that other system timing signals can be derived from this stable, crystal-contralled source. For systems which have aVcc ramp time = 1V/ms and/or have inherent board capacitance between X1 or X2, ex- ceeding 10 pF (not including 8284A pin capacitance), the two 5100 resistors should be used. This circuit provides optimum stability for the oscillator in such extreme condi- tions. It is advisable to limit stray capacitances to less than 10 pF on X1 and X2 to minimize deviation from operating at the fundamenta! frequency AFN-91472Dintel 8284A/8284A-1 Clock Generator The clock generator consists of a synchronous divide- by-three counter with a special clear input that inhibits the counting. This clear input (CSYNC) allows the out- put clock to be synchronized with an external event (such as another 8284A clock). It is necessary to syn- chronize the CSYNC input to the EFI clock external to the 8284A. This is accomplished with two Schottky flip- flops. The counter output is a 33% duty cycle clock at one-third the input frequency. The F/C input is a strapping pin that selects either the crystal oscillator or the EF! input as the clock for the +3 counter. If the EFI input is selected as the clock source, the oscillator section can be used independently for another clock source. Output is taken from OSC. Clock Outputs The CLK output is a 33% duty cycle MOS clogk driver designed to drive the iAPX 86, 88 processors directly. PCLK is a TTL level peripheral clock signal whose out- put frequency is V2 that of CLK. PCLK has a 50% duty cycle. Reset Logic The reset logic provides a Schmitt trigger input (RES) and a synchronizing flip-flop to generate the reset timing. The reset signal is synchronized to the falling edge of CLK. A simple RC network can be used to provide power-on reset by utilizing this function of the 8284A. READY Synchronization Two READY inputs (RDY1, RDY2) are provided to accom- modate two Multi-Master system busses. Each input has a qualifier (AEN1 and AEN2, respectively). The AEN signals validate their respective RDY signals. If a Multi- Master system fs not being used the AEN pin should be tied LOW. Synchronization is required for all asynchronous active- going edges of either RDY input to guarantee that the RDY setup and hoid times are met. Inactive-going edges of RDY in normally ready systems do not require syn- Chronization but must Satisfy RDY setup and hold as a matter of proper system design. The ASYNC input defines two modes of READY syn- chronization operation. When ASYNC is LOW, two stages of synchronization are provided for active READY input signals. Positive- going asynchronous READY inputs will first be syn- chronized to flip-flop one at the rising edge of CLK and then synchronized to flip-flop two at the next falling edge of CLK, after which time the READY output will go active (HIGH). Negative-going asynchronous READY in- puts will be synchronized directly to flip-flop two at the falling edge of CLK, after which time the READY output will go inactive. This mode of aperation is intended for use by asynchronous (normally not ready) devices in tne sys- tem which cannot be guaranteed by design to meet the required RDY setup timing, TrivcLt, on each bus cycle. When ASYNC is high or left open, the first READY flip- flop is bypassed in the READY synchronization logic. READY inputs are synchronized by flip-flop two on the falling edge of CLK before they are presented to the processor. This mode is available for synchronous devices that can be guaranteed to meet the required RDY setup time. ASYNC can be changed on every bus cycle to select the appropriate mode of synchronization for each device in the system. CLOCK D SYNCHRONIZE EFI _p- >| {TO OTHER 8284As) Figure 3. CSYNC Synchronization 3-569 APNO147205intel 8284A/8284A-1 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias Storage Temperature All Output and Supply Voltages All Input Voltages Power Dissipation 0C to 70C 65C to + 150C -0.5V to +7V NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operational sections of this speciti- cation is not implied. Exposure to absolute maximum tating conditions for extended periods may affect device reliability. D.C. CHARACTERISTICS (7, =0C to 70C, Voc = 5V + 10%) Symbol Parameter Min. Max. Units | Test Conditions te Forward Input Current (ASYNG) -1.3 mA Ve=0.45V Other inputs -0.5 mA Vrp=0.45V lq Reverse Input Current (ASYNC) 50 pA Vr= Voc Other Inputs 50 pA Va=5.25V Vo input Forward Ciamp Voltage -1.0 Vv Ic=~-5mA lec Power Supply Current 162 mA Vin Input LOW Voltage 0.8 Vv Vin Input HIGH Voltage 2.0 Vv VinR Reset Input HIGH Voltage 2.6 v Vor Output LOW Voltage 0.45 v 5mA Vou Output HIGH Voltage CLK 4 v 1mA Other Outputs 2.4 v -imA Vina Vier RES Input Hysteresis 0.25 v A.C. CHARACTERISTICS (7,=0C to 70C, Vog= 5V + 10%) TIMING REQUIREMENTS Symbol Parameter Min. Max. Units Test Conditions teHeL External Frequency HIGH Time 13 ns 90% -90% Vin tELEH External Frequency LOW Time 13 ns 10% ~10% Vin teLeL EFI Period 33 ns (Note 1) XTAL Frequency 12 25 MHz tarvet RDY1, RDY2 Active Setup to CLK 35 ns ASYNC = HIGH trivcH RDY1, RDY2 Active Setup to CLK 35 ns ASYNC = LOW triveL RDY1, RDY2 Inactive Setup to CLK 35 ns teLrix RDY1, RDY2 Hold to CLK 0 ns tayveL ASYNC Setup to CLK 50 ns toLayx ASYNC Hold to CLK 0 ns taivriv AENT, AEN2 Setup to RDY1, RDY2 15 ns toLaix AEN1, AENZ Hold to CLK 0 ns tVvHEH CSYNC Setup to EFI 20 ns tenye CSYNC Hold to EFI 10 ns tyHYL CSYNC Width 2: teLeL ns tHe RES Setup to CLK 65 ns (Note 1) tout RES Hold to CLK 20 ns (Note 1) 3-570 AFN-01472Dintel 8284A/8284A-1 A.C. CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter Min. 8284A Min. 8284A-1 Max Units Test Conditions tore. CLK Cycle Period 125 100 ns tone CLK HIGH Time (% tere) +2 39 ns teicn CLK LOW Time (% tere.) - 15 53 ns mene CLK Rise or Fall Time 10 ns 1.0V to 3.5V tpype PCLK HIGH Time tore. 20 tere. 20 ns tetpH PCLK LOW Time tere. ~ 20 tere. -20 ns trytee Ready Inactive to CLK (See Note 3) -8 ns tryucn Ready Active to CLK (See Note 2) (4 teici}~-15 53 ns tour CLK to Reset Delay 40 ns toupH CLK to PCLK HIGH DELAY 22 ns toceL CLK to PCLK LOW Delay 22 ns toicH OSC to CLK HIGH Delay - -5 22 ns toree OSC to CLK LOW Delay 2 35 ns toron Output Rise Time (except CLK) 20 ns From 0.8V to 2.0V tonor T Output Fall Time (except CLK) 12 ns From 2.0V to 0.8V NOTES: 1. Setup and hold necessary only to guarantee recognition at next clock. 2. Applies only to T3 and TW states. 3. Applies only to T2 states. A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT INPUT/OUTPUT 24 1.5 <& TEST POINTS ~- 1.5 AC. TESTING: INPUTS ARE DRIVEN AT 2 4V FORALOGIC 1 AND 0 45V FOR A LO 0. ANOS MEASUREMENTS ARE MADE AT + SV FOR BOTHA oan 1 AND 0 ' INPUT RISE AND FALL TIMES (MEASURED BETWEEN 0.8V AND 2.0V) ARE 22NS DEVICE c= Cy, = 100pF FOR CLK 30pF FOR READY th | iba \ = 2.08V > 3269 a 3-571 AFN-O14721intel 8284A/8284A-1 WAVEFORMS CLOCKS AND RESET SIGNALS je SELEL fELEH - -tEHeEL NAME EFt A ty osc , touch m jw loL2cut be- loc >} ttcHe., CLK >| : \ | \ _ tote | ton1cH2 | ] force f fcLPH| [et aa jefciPe PCLK O j \ Y a t . | {}~t tp ppy_--}wae- oun, lo tenyL 4 ~- + be tYHEH | csync i rae tt t >| a | Cr HCL: WES 1 \ | teu >| RESET O | J NOTE: ALL TIMING MEASUREMENTS ARE MADE AT 1.5 VOLTS, UNLESS OTHERWISE NOTED. READY SIGNALS (FOR ASYNCHRONOUS DEVICES) | trivee re a PY FLD. 7 om y 4 ROY1,2 j pat tainty SENTS t AEN1,2 Le em) teLax ~ tayven he ASYNC \ , { m} tcLayx lL READY t , + _| taYHcH fAYLCL | t 3-572 AFN.01472Dintel 8284A/8284A-1 WAVEFORMS (Continued) READY SIGNALS (FOR SYNCHRONOUS DEVICES) me a PY i i j oe K tconi pt taivc.>} >| tRive. je ae RDY1,2 j r taraw >] tcraix AENT2Z E oe 7 tayve, = jee sm} toa as ASYNC t X | tclayx READY r a tryLcL | [~e LOAD a CLK (SEE NOTE 1) 24 MHz LJ X2 FIC R, Rez CSYNC = + = Ry = Rg = 5100. Clock High and Low Time (Using X1, X2) * PULSE = LOAD GENERATOR EFI CLK (SEE NOTE 1) Voc FIC [| CSYNC Clock High and Low Time (Using EFI) 3-573 AFNO14720intel 8284A/8284A-1 Vcc | KEN LOAD 1 LK (SEE NOTE 1) x1 = a LOAD 2amez Co READY (SEE NOTE 2) X2 PULSE GENERATOR RDY2 OSC Ay Re TRIGGER FIG A AEN? CSYNC i = = = R, = Rp = 510. Ready to Clock (Using X1, X2) PULSE LOAD GENERATOA EFI CLK (SEE NOTE 1) Vcc | FIC TRIGGER AEN PULSE RDY2 GENERATOR RENE LOAD CSYNC READY (SEE NOTE 2) NOTES: Ready to Clock (Using EFI) 1. Gy = 100 pF 2 CL = 30pF 3-574 " AENO14720