LM118QML
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SNOSAJ3A –JULY 2005–REVISED MARCH 2013
LM118QML Operational Amplifier
Check for Samples: LM118QML
1FEATURES DESCRIPTION
The LM118 is a precision high speed operational
2• 15 MHz Small Signal Bandwidth amplifier designed for applications requiring wide
• Ensured 50V/μs Slew Rate bandwidth and high slew rate. It features a factor of
• Maximum Bias Current of 250 nA ten increase in speed over general purpose devices
without sacrificing DC performance.
• Operates from Supplies of ±5V to ±20V
• Internal Frequency Compensation The LM118 has internal unity gain frequency
compensation. This considerably simplifies its
• Input and Output Overload Protected application since no external components are
• Pin Compatible with General Purpose Op necessary for operation. However, unlike most
Amps internally compensated amplifiers, external frequency
compensation may be added for optimum
performance. For inverting applications, feed forward
compensation will boost the slew rate to over
150V/μs and almost double the bandwidth.
Overcompensation can be used with the amplifier for
greater stability when maximum bandwidth is not
needed. Further, a single capacitor can be added to
reduce the 0.1% settling time to under 1 μs.
The high speed and fast settling time of this op amp
makes it useful in A/D converters, oscillators, active
filters, sample and hold circuits, or general purpose
amplifiers. This device is easy to apply and offers an
order of magnitude better AC performance than
industry standards such as the LM709.
Fast Voltage Follower
Do not hard-wire as voltage follower (R1 ≥5 kΩ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
N/C
Bal/Comp1
-IN
+IN
N/C
Comp2
V+
OUT
110
29
38
47
V- Bal/Comp3
56
LM118QML
SNOSAJ3A –JULY 2005–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Connection Diagram
Figure 1. CDIP Package Figure 2. TO-99
Top View Top View
See Package Number J0014A See Package Number LMC
Pin connections shown on schematic diagram and typical
applications are for TO package.
Figure 3. CDIP Package Figure 4. CLGA Package
Top View Top View
See Package Number NAB0008A See NS Package Number NAC0010A
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Absolute Maximum Ratings(1)
Supply Voltage ±20V
8 LD TO-99 750mW
8LD CDIP 1000mW
Power Dissipation(2) 14LD CDIP 1250mW
10LD CLGA 600mW
Differential Input Current(3) ±10 mA
Input Voltage(4) ±15V
Output Short-Circuit Duration Continuous
Operating Temperature Range −55°C ≤TA≤+125°C
Thermal Resistance 8 LD TO-99 (Still Air @ 0.5W) 160°C/W
8 LD TO-99 (500LF / Min Air flow @ 0.5W) 86°C/W
8LD CDIP (Still Air @ 0.5W) 120°C/W
8LD CDIP (500LF / Min Air flow @ 0.5W) 66°C/W
θJA 14LD CDIP (Still Air @ 0.5W) 87°C/W
14LD CDIP (500LF / Min Air flow @ 0.5W) 51°C/W
10LD CLGA (Still Air @ 0.5W) 198°C/W
10LD CLGA (500LF / Min Air flow @ 0.5W) 124°C/W
8 LD TO-99 48°C/W
8LD CDIP 17°C/W
θJC 14LD CDIP 17°C/W
10LD CLGA 22°C/W
Storage Temperature Range −65°C ≤TA≤+150°C
Lead Temperature (Soldering, 10 seconds) 300°C
ESD Tolerance(5) 2000V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For specifications and test conditions, see the Electrical
Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the
device is not operated under the listed test conditions.
(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
(3) The inputs are shunted with back-to-back diodes for over voltage protection. Therefore, excessive current will flow if a differential input
voltage in excess of 1V is applied between the inputs unless some limiting resistance is used.
(4) For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
(5) Human body model, 1.5 kΩin series with 100 pF.
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Quality Conformance Inspection
Mil-Std-883, Method 5005; Group A
Subgroup Description Temp°C
1 Static tests at 25
2 Static tests at 125
3 Static tests at -55
4 Dynamic tests at 25
5 Dynamic tests at 125
6 Dynamic tests at -55
7 Functional tests at 25
8A Functional tests at 125
8B Functional tests at -55
9 Switching tests at 25
10 Switching tests at 125
11 Switching tests at -55
12 Settling time at 25
13 Settling time at 125
14 Settling time at -55
LM118/883 Electrical Characteristics DC Parameters
The following conditions apply, unless otherwise specified.
DC VCC = ±15V, VCM = 0V Sub-
Symbol Parameter Conditions Notes Min Max Unit groups
VIO Input Offset Voltage VCM = ± 11.5V, RS= 50Ω-4.0 +4.0 mV 1
-6.0 +6.0 mV 2, 3
VCC = ± 20V, RS= 50Ω-4.0 +4.0 mV 1
-6.0 +6.0 mV 2, 3
VCC = ± 20V, VCM = ± 15V, -4.0 +4.0 mV 1
RS= 50Ω-6.0 +6.0 mV 2, 3
VCC = ± 5V, RS= 50Ω-4.0 +4.0 mV 1
-6.0 +6.0 mV 2, 3
IIO Input Offset Current VCM = ± 11.5V, RS= 10KΩ-50 +50 nA 1
-100 +100 nA 2, 3
VCC = ± 20V, RS= 10KΩ-50 +50 nA 1
-100 +100 nA 2, 3
VCC = ± 5V, RS= 10KΩ-50 +50 nA 1
-100 +100 nA 2, 3
IIB Input Bias Current VCM = ± 11.5V, RS= 10KΩ1.0 250 nA 1
1.0 500 nA 2, 3
VCC = ± 20V, RS= 10KΩ1.0 250 nA 1
1.0 500 nA 2, 3
VCC = ± 5V, RS= 10KΩ1.0 250 nA 1
1.0 500 nA 2, 3
PSRR Power Supply Rejection Ratio +VCC = 20V to 5V, RS= 50Ω70 dB 1, 2, 3
-VCC = -20V to -5V, RS= 50Ω70 dB 1, 2, 3
CMRR Common Mode Rejection Ratio VCC = ± 15V, VCM = ± 11.5V, RS=80 dB 1, 2, 3
50Ω
+IOS Short Circuit Current t < 25mS -65 -5.0 mA 1, 2, 3
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LM118/883 Electrical Characteristics DC Parameters (continued)
The following conditions apply, unless otherwise specified.
DC VCC = ±15V, VCM = 0V Sub-
Symbol Parameter Conditions Notes Min Max Unit groups
-IOS Short Circuit Current t < 25mS 5.0 65 mA 1, 2
5.0 80 mA 3
ICC Power Supply Current VCC = ± 20V 8.0 mA 1
7.0 mA 2
11 mA 3
VIO adj. Input Offset Voltage Adjust VCC = ± 20V 4.0 -4.0 mV 1
RIInput Resistance See(1) 1.0 MΩ1
VIInput Voltage Range VCC = ± 15V +11.
See(2) -11.5 V 1, 2, 3
5
AVS Large Signal Voltage Gain RL= 2KΩ, VO= 0 to -10V See(3) 50 V/mV 4
See(3) 25 V/mV 5, 6
RL= 2KΩ, VO= 0 to +10V See(3) 50 V/mV 4
See(3) 25 V/mV 5, 6
VOOutput Voltage Swing RL= 2KΩ+12 -12 V 4, 5, 6
(1) Specified by design not tested
(2) Specified by CMRR
(3) Datalog in K = V/mV
LM118/883 Electrical Characteristics AC Parameters
The following conditions apply parameters, unless otherwise specified.
AC VCC = ±15V, VCM = 0V, RS= 0Ω, RL= 2KΩ,, CL= 33pF Sub-
Symbol Parameter Conditions Notes Min Max Unit groups
SRSlew Rate VCC = ± 20V, VI= -5V to +5V, AV=1 50 V/µS 7
VCC = ± 20V, VI= +5V to -5V, AV=1 50 V/µS 7
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Typical Performance Characteristics
Input Current Voltage Gain
Figure 5. Figure 6.
Power Supply Rejection Input Noise Voltage
Figure 7. Figure 8.
Common Mode Rejection Supply Current
Figure 9. Figure 10.
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Typical Performance Characteristics (continued)
Closed Loop Output Impedance Current Limiting
Figure 11. Figure 12.
Input Current Unity Gain Bandwidth
Figure 13. Figure 14.
Voltage Follower Slew Rate Inverter Settling Time
Figure 15. Figure 16.
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Typical Performance Characteristics (continued)
Large Signal Frequency Response Open Loop Frequency Response
Figure 17. Figure 18.
Voltage Follower Pulse Response Large Signal Frequency Response
Figure 19. Figure 20.
Open Loop Frequency Response Inverter Pulse Response
Figure 21. Figure 22.
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AUXILIARY CIRCUITS
Feedforward Compensation
for Greater Inverting Slew Rate Compensation for Minimum Settling Time
Slew and settling time to 0.1% for a 10V step change is 800 ns.
Slew rate typically 150V/μs.
Offset Balancing Isolating Large Capacitive Loads
Overcompensation
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Typical Applications
Fast Voltage Follower
Do not hard-wire as voltage follower (R1 ≥5 kΩ)
Integrator or Slow Inverter
CF= Large (CF≥50 pF)
*Do not hard-wire as integrator or slow inverter; insert a 10k-5 pF network in series with the input, to prevent
oscillation. Fast Summing Amplifier Differential Amplifier
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Four Quadrant Multiplier
ΔOutput zero.
*“Y” zero
+“X” zero
‡Full scale adjust.
D/A Converter Using Binary Weighted Network
*Optional—Reduces settling time.
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SNOSAJ3A –JULY 2005–REVISED MARCH 2013
REVISION HISTORY SECTION
Date Released Revision Section Originator Changes
07/12/05 A New Release, Corporate format L. Lytle 1 MDS data sheet, MNLM118–X Rev 0A0 was
converted into the Corp. datasheet format.
MDS datasheet will be archived.
03/20/2013 A All Sections Changed Layout of National Data Sheet to TI
format
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM118H/883 ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM118H/883 Q ACO
LM118H/883 Q >T
LM118J-8/883 ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM118J-8
/883 Q ACO
/883 Q >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
NAB0008A
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J08A (Rev M)
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