XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 1 of 16
Product Features
• Supports Pentium
and Pentium
Pro and Mobil
Pentium
Processor designs.
• 4 CPU clocks up to 8 loads.
• Up to 8 SDRAM clocks for 2 DIMMs.
• Supports Power Management.
• 7 PCI synchronous clocks.
• Optional common or mixed supply mode:
• (Vdd = Vddq3 = Vddq2 = 3.3V) or
• (Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V)
• < 250ps skew CPU and SDRAM clocks.
• < 250ps skew among PCI clocks.
• I
2C 2-Wire serial interface
• Programmable registers featuring:
• enable/disable each output pin
• mode as tri-state, test, or normal
• 24/48 MHz selections
• 1 IOAPIC clock for multiprocessor support.
• 48-pin SSOP and TSSOP package
• Spread Spectrum Technology for up to 13dB of
EMI reduction
Block Diagram
REF
OSC
Xin
Xout
3
Buffers REF0,1,2
IOAPIC0
Vddq2
PLL1SEL
4CPUCLK0~3
Vddq2
Buffer
Buffers
Buffers
8SDRAM0~7
Vddq3
dly Buffers
6PCICLK0~5
PLL2
Buffer
Buffer
48/24MHZ
48/24MHZ
Buffer PCICLK_F
SDATA
SDCLK
PCI_STOP#
CPU_STOP#
PWR_DWN#
MODE
Frequency Table
SEL CPU PCI
0 60.0 30.0
1 66.6* 33.3*
*Spread Spectrum mode capable
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
REF1
REF0
Vss
Xin
Xout
MODE
Vddq3
PCICLK_F
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
Vss
Vss
Vddq3
SEL
SDATA
Vddq3
48/24MHZ
48/24MHZ
Vss Vdd
SDRAM7/PCI_STOP#
SDRAM6/CPU_STOP#
Vddq3
SDRAM5
Vss
SDRAM4
SDRAM2
SDRAM1
SDRAM0
CPUCLK3
CPUCLK2
CPUCLK1
CPUCLK0
SDRAM3
Vddq3
Vss
Vddq2
Vss
PWR_DWN#
IOAPIC0
Vddq2
REF2
Vdd
SDCLK
IMIXG571
Purchas e of I
2
C com ponents of I nternational Microcirc uits, Inc. or one
of its subl icens ed As s ociat ed Com panies conveys a lic ense under the
Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification
as defined by Philips.
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 2 of 16
Pin Description
Xin, Xout - These pins form an on-chip reference
oscillator when connected to terminals of an external
parallel resonant crystal (nominally 14.318 MHz). Xin
may also serve as input for an externally generated
reference signal.
SEL - Standard frequency select input. It has internal
pull-up.
CPUCLK(0:3) - Low skew (<250 pS) clock outputs for
host frequencies such as CPU, Chipset, Cache. Vddq2
is the supply voltage for these outputs.
SDRAM(0:5) - Synchronous DRAM DIMs clocks. They
are powered by Vddq3.
SDRAM6/CPU_STOP# - If MODE=1, this pin is a
Synchronous DRAM DIMs clock output powered by
Vddq3. If MODE=0, this pin is a CPU_STOP# input
signal, where a low level stops the CPU however, the
SDRAM clocks will stay active. It has an internal pull-
up.
SDRAM7/PCI_STOP# - If MODE=1, this pin is a
Synchronous DRAM DIMs clock output powered by
Vddq3. If MODE=0, this pin is a PCI_STOP# input
signal, where a low level stops the PCI c locks . It has an
internal pull-up.
MODE - A low level on this pin causes pins 26, and 27
to be power management inputs PCI_STOP#, and
CPU_STO P# respec tly. A high level on this pin causes
pins 26, and 27 to be clock output signals SDRAM7,
and SDRAM6 respectively. It has an internal pull-up
resistor.
PCICLK(0:5) - Low skew (<250pS) clock outputs for
PCI frequencies. These buffers voltage level is
controlled by Vddq3
PCICLK_F - A PCI clock output that does not stop until
in power down mode. It is synchronous with other PCI
clocks.
REF(0:2) - Buffered outputs of on-chip reference.
IOAPIC0 - Buffered output of 14.3MHZ for
multiprocessor support. It is powered by Vddq2.
PWR_DWN# - Power down pin. When this pin is
asserted low, the IC is in shutdown mode where all
circuitry is turned off including VCO, crystal buffer and
PCICLK_F. It has an internal pull-up. The I2C interface
is disabled with the PWR_DWN# pin is low.
48/24MHz(0:1) - Programmable 48 MHZ or 24 MHZ
clock outputs.
SDATA - serial data of I2C 2-wire control interface. Has
internal pull-up resistor.
SDCLK - serial clock of I2C 2-wire control interface.
Has internal pull-up resistor.
Vss - Ground pins for the chip.
Vdd - 3.3 Volt power supply pins for analog circuit and
core logic.
Vddq3 - Power supply pins for 3.3V IO pins.
Vddq2 - Power supply pins for 2.5V/3.3V IO pins.
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 3 of 16
Pow er Management Functions
All clock s c an be individually enabled or stopped via the 2-wire control interf ace. All clock s ar e st opped in the low s tate.
All clocks maintain a valid high period on transitions f rom r unning to stopped and on transitions from stopped to running
when the chip was not powered down. On power up, the VCOs will stabilize to the c orrec t pulse widths within about 0.2
mS. The CPU, SDRAM, and PCI clocks transition between running and stopped by waiting for one positive edge on
PCICLK_F followed by a negative edge on the clock of interest, af ter which high levels of the output are either enabled
or disabled.
When MODE=0, pins 26 and 27 are inputs PCI_ST OP# and CPU_ST OP# res pectively (when MODE=1, these functions
are not available). A particular output is enabled only when both the serial interf ac e and these pins indic ate that it s hould
be enabled. The IMIXG571 clocks may be disabled according to the following table in order to reduce power
consum ption. All c lock s are s topped in the low state. All clock s m aintain a valid high per iod on transitions f rom running
to stopped. On low to high transitions of PW R_DW N#, external circuitry should allow 0.2 mS for the VCOs to stabilize
prior to assuming the clock periods are correct. The CPU and PCI clocks transition between running and stopped by
waiting for one positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels
of the output are either enabled or disabled.
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK PCICLK OTHER CLKs XTAL & VCOs
X X 0 LOW LOW LOW OFF
0 0 1 LOW LOW RUNNING RUNNING
0 1 1 LOW 33/30 MHZ RUNNING RUNNING
1 0 1 66/60 MHZ LOW RUNNING RUNNING
1 1 1 66/60 MHZ 33/30 MHZ RUNNING RUNNING
Pow e r Management Timing
PCICLK_F
PCI_STOP#
PCICLK(0:5)
CPU_STOP#
CPUCLK(0:3)
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 4 of 16
2-Wire I2C Control Interface
The 2-wire control interface implements a write only slave interface. The IMIXG571 cannot be read back. Sub-
addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-
wire control interface allows each clock output to be individually enabled or disabled. It also allows 24/48 MHZ frequency
selection and test mode enable.
During normal data transf er, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK
is high. T here ar e two exc eptions to this . A high to low trans ition on SDAT A while SDCLK is high is us ed to indic ate the
start of a data transfer cycle. A low to high transition on SDAT A while SDCLK is high indicates the end of a data tr ans f er
cycle. Data is always sent as complete 8-bit bytes, after which an ac knowledge is generated. T he f irs t byte of a transf er
cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The devic e will respond to writes to 10 bytes (m ax ) of data to addr es s D2 by generating the acknowledge (low) signal on
the SDATA wire f ollowing reception of each byte. The device will not respond to any other c ontrol interf ace conditions .
The I2C interface is disabled when the PWR_DWN# pin is low. Previously set control registers are retained.
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
Byte 0: Function Select Regi st er
Bit @Pup Pin# Description
70 *Reserved
60 *Reserved
50 *Reserved
40 *Reserved
3 1 23 48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz)
2 1 22 48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz)
1
00
0Bit1 Bit0
1 1 Tri-State
1 0
Spread Spectrum operating mode
0 1 Test Mode
0 0 Normal operating mode
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 5 of 16
Serial Control Registers (Cont.)
Function Table
Function Outputs
Description CPU PCI SDRAM Ref IOAPIC 24MHZ 48MHZ
Tri-State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Test Mode Tclk/2 Tclk/4 Tclk/2 Tclk Tclk Tclk/4 Tclk/2
Normal SEL=1 66 CPU/2 CPU 14.318 14.318 24 48
Normal SEL=0 60 CPU/2 CPU 14.318 14.318 24 48
Notes:
1. Tclk is a test clock over driven on the Xin input during test mode.
2. The frequency ratio Fout/Fin for the USB output is 3.35294.
Byte 1: CPU, 48/24 MHz Clock Regi st er (1 = enable, 0 = Stopped)
Bit @Pup Pin# Description
7 1 23 48/24 MHz enable/Stopped
6 1 22 48/24 MHz enable/Stopped
5 x - Reserved
4 x - Reserved
3 1 38 CPUCLK3 enable/Stopped
2 1 39 CPUCLK2 enable/Stopped
1 1 41 CPUCLK1 enable/Stopped
0 1 42 CPUCLK0 enable/Stopped
Byte 2: PCI Clock Register ( 1 = enable, 0 = St opped)
Bit @Pup Pin# Description
7x-Reserved
6 1 8 PCICLK_F enable/Stopped
5 1 16 PCICLK5 enable/Stopped
4 1 14 PCICLK4 enable/Stopped
3 1 13 PCICLK3 enable/Stopped
2 1 12 PCICLK2 enable/Stopped
1 1 11 PCICLK1 enable/Stopped
0 1 9 PCICLK0 enable/Stopped
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 6 of 16
Serial Control Registers (Cont.)
Byte 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped)
Bit @Pup Pin# Description
7 1 26 SDRAM7 enable/Stopped
6 1 27 SDRAM6 enable/Stopped
5 1 29 SDRAM5 enable/Stopped
4 1 30 SDRAM4 enable/Stopped
3 1 32 SDRAM3 enable/Stopped
2 1 33 SDRAM2 enable/Stopped
1 1 35 SDRAM1 enable/Stopped
0 1 36 SDRAM0 enable/Stopped
Byte 4: Additional SDRAM Clock Register ( 1 = enable, 0 = Stopped)
Bit @Pup Pin# Description
7x-Reserved
6x-Reserved
5x-Reserved
4x-Reserved
3x-Reserved
2x-Reserved
1x-Reserved
0x-Reserved
Byte 5: Peripheral Control (1 = enable, 0 = St opped)
Bit @Pup Pin# Description
7x-Reserved
6x-Reserved
5 1 - Reserved
4 1 45 IOAPIC0 enable/Stopped
3x-Reserved
2 1 47 REF2 enable/Stopped
1 1 1 REF1 enable/Stopped
0 1 2 REF0 enable/Stopped
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 7 of 16
Serial Control Registers (Cont.)
Byte 6: Reserved Register
Bit @Pup Pin# Description
7x-Reserved
6x-Reserved
5x-Reserved
4x-Reserved
3x-Reserved
2x-Reserved
1x-Reserved
0x-Reserved
Byte 7: Frequency Control
Bit @Pup Description
7xReserved
6xReserved
5xReserved
4xReserved
3xReserved
21Reserved
1xReserved
0xReserved
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 8 of 16
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
spreading the sam e am ount of energy over a spectrum . T his technique is ac hieved by m odulating the clock down f rom
its resting f requency by a certain percentage (which als o determines the energy distr ibution bandwidth). In this product,
the modulation is 1.0% down from the resting frequency.
Amplitude
(dB)
Frequency(MHz)
Modulated Center
Frequency
Without S pectrum Spread
W ith Spectrum Spread
Spectrum Analysis
Rested Center
frequency
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 9 of 16
Maximum Ratings
Voltage Relative to VSS: -0.3V
Voltage Relative to VDD: 0.3V
Storage Temperature: -65ºC to + 150ºC
Operating Temperature: 0ºC to +70ºC
Maximum Power Supply: 7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Electrical Characteristics
Characteristic Symbol Min Typ Max Units Conditions
Input Low Voltage VIL - - 0.8 Vdc -
Input High Voltage VIH 2.0 - - Vdc -
Input Low Current IIL -66 µA
Input High Current IIH 5 µA
Output Low Voltage
IOL = 4mA VOL - - 0.4 Vdc All Outputs (see buffer spec)
Output High Voltage
IOH = 4mA VOH 2.4 - - Vdc All Outputs Usin
g
3.3V Power
(see buffer spec)
Tri-State leakage Current Ioz - - 10 µA
Dynamic Supply Current Idd - - 100 mA CPU = 66.6 MHz, PCI = 33.3 MHz
Static Supply Current Isdd - - 1 mA Powered Down = Active
Short Circuit Current ISC 25 - - mA 1 output at a time - 30 seconds
VDD = VDDQ3 =3.3V
±5
%, VDDQ2 = 2.5V
±5
% , TA = 0ºC to +70ºC
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 10 of 16
Switching Characteristics
Characteristic Symbol Min Typ Max Units Conditions
Output Duty Cycle - 45 50 55 % Measured at 1.5V
CPU to PCI Offset tOFF 1 - 4 ns 15 pf Load Measured at 1.5V
Buffer out Skew All CPU
and PCI Buffer Outputs tSKEW - - 250 ps 15 pf Load Measured at 1.5V
∆Period Adjacent Cycles ∆P- - +250 ps -
Jitter Spectrum 20 dB
Bandwidth from Center BWJ500 KHz
Overshoot/Undershoot
Beyond Power Rails Vover - - 1.5 V 22 ohms @ source of 8 inch PCB run
to 15 pf load
Ring Back Exclusion VRBE 0.7 2.1 V Note1
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
Note 1: Ring Back must not enter this range.
Buffer Characteristics for CPUCLK(0:3), IOAPIC
Characteristic Symbol Min Typ Max Units Conditions
Pull-Up Current IOH 22 - 31 mA Vout = VDD - .5V
Pull-Up Current IOH 37 - 56 mA Vout = 1.25V
Pull-Down Current IOL 30 - 41 mA Vout = 0.4V
Pull-Down Current IOL 75 - 102 mA Vout = 1.2V
Rise/Fall Time Min
Between 0.4 V and 2.0 V TRFmin 0.4 - - nS 10 pF Load
Rise/Fall Time Max
Between 0.4 V and 2.0 V TRFmax - - 2.0 nS 20 pF Load
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 11 of 16
Buffer Characteristics for REF(1:2) and 48/24 MHz
Characteristic Symbol Min Typ Max Units Conditions
Pull-Up Current IOH 13 - 17 mA Vout = VDD - .5V
Pull-Up Current IOH 30 - 44 mA Vout = 1.5V
Pull-Down Current IOL 13 - 19 mA Vout = 0.4V
Pull-Down Current IOL 32 - 44 mA Vout = 1.5V
Rise/Fall Time Min Between 0.4 V and 2.4 V TRFmin 1.0 - - nS 10 pF Load
Rise/Fall Time Max Between 0.4 V and 2.4 V TRFmax - - 2.0 nS 20 pF Load
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
Buffer Characteristics for REF0 and SDRAM(0:7)
Characteristic Symbol Min Typ Max Units Conditions
Pull-Up Current IOH 30 - 39 mA Vout = VDD - .5V
Pull-Up Current IOH 75 - 109 mA Vout = 1.5V
Pull-Down Current IOL 30 - 40 mA Vout = 0.4V
Pull-Down Current IOL 75 - 103 mA Vout = 1.2V
Rise/Fall Time Min Between 0.4 V and 2.4 V TRFmin 0.5 - - nS 20 pF Load
Rise/Fall Time Max Between 0.4 V and 2.4 V TRFmax - - 2.0 nS 30 pF Load
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
Buffer Characteristics for PCICLK(0:5,F)
Characteristic Symbol Min Typ Max Units Conditions
Pull-Up Current IOH 18 - 23 mA Vout = VDD - .5V
Pull-Up Current IOH 44 - 64 mA Vout = 1.5V
Pull-Down Current IOL 18 - 25 mA Vout = 0.4V
Pull-Down Current IOL 50 - 70 mA Vout = 1.5V
Rise/Fall Time Min Between 0.4 V and 2.4 V TRFmin 0.5 - - nS 15 pF Load
Rise/Fall Time Max Between 0.4 V and 2.4 V TRFmax - - 2.0 nS 30 pF Load
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 12 of 16
Crystal and Reference Oscillator Parameters
Characteristic Symbol Min Typ Max Units Conditions
Frequency Fo12.00 14.31818 16.00 MHz
Tolerence TC - - +/-100 PPM Calibration note 1
TS - - +/- 100 PPM Stability (Ta -10 to +60C) note 1
TA - - 5 PPM Aging (first year @ 25C) note 1
Mode OM - - - Parallell Resonant
Pin Capacitance CP 6 pF Capacitance of XIN and Xout pins to
ground (each)
DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V
Startup time Ts - - 30 µS
Load Capacitance CL - 20 - pF The crystal’s rated load. Note 1
Effective Series
resonant
resistance
R1 - - 40 Ohms
Power Dissipation DL - - 0.10 mW Note 1
Shunt Capacitance CO - -- 8 pF Crystal’s internal package
capacitance (total)
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore 2.0 pF
Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore 3.0 pF
External crystal loading capacitors (connect to ground) 15.0 pF
the total parasitic capacitance would therefore be = 20.0.0 pF.
Note 1: It is recommended but not mandatory that a crystal meets these specifications.
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 13 of 16
PCB Layout Suggestion
This is only a layout recommendation for best performance and lower EMI. The designer may choose a
different approach but C4, C5, C6, C7, C8, C9, C10, C11and C12 (all are 0.1µf) should always be used and
placed close to their VDD pins.
IMIXG571
Via to VDD Island
Via to GND plane
VCC
3
.
3V
1
2
3
4
5
6
C4 7
8
10
9
11
12
13
14
C5 15
17
16
18
19
20
C6 21
23
22
24
47
39
38
37
36
35 C9
34
32
33
31
30
29 C8
28
26
27
C12
48
C11
46
45
44
43
42
41
C7
25
C10
40
C3 22µF
FB1
VCC
2
.
5V
C14
22µF
FB2
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 14 of 16
Package Drawing and Dimensions
48 Pin SSOP Outline Dimensions
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A 0.095 0.102 0.110 2.41 2.59 2.79
A10.008 0.012 0.016 0.20 0.31 0.41
A2 0.088 0.090 0.092 2.24 2.29 2.34
B 0.008 0.010 0.0135 0.203 0.254 0.343
C 0.005 - 0.010 0.127 - 0.254
D 0.620 0.625 0.630 15.75 15.88 16.00
E 0.292 0.296 0.299 7.42 7.52 7.59
e 0.025 BS C 0.635 BSC
H 0.400 0.406 0.410 10.16 10.31 10.41
a 0.10 0.013 0.016 0.25 0.33 0.41
L 0.024 0.032 0.040 0.61 0.81 1.02
a0º5º8º0º5º8º
X 0.085 0.093 0.100 2.16 2.36 2.54
Be
A
A1
A2
E
H
a
L
C
D
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 15 of 16
Package Drawing and Dimensions (Cont.)
BO
SURFACES ROUGH NESS: 6+ 27n(RZ)
D
-B-
385
E1
L20
R0.1
B
e
-C- C
0.07
RD
4
[10° TYP
R1.30
1.0
0.10~0.15 0.00 ~ 0.05
SECTION V- V
0.05 MAX .
0.05 MAX .
1.0
1.0
E
R0.15
A
A1
0.25
A2
R
L
A
8°
b
cc1
b1
DETAIL B
.08 CB A
DETAIL A
14° TYP
48 Pin TSSOP Dimensions
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A - - 0.0433 - - 1.10
A1 0.002 0.004 0.006 0.05 0.10 0.15
A2 0.033 0.035 0.037 0.85 0.90 0.95
L 0.019 0.023 0.029 0.50 0.60 0.75
R 0.043 - - 0.10 - -
b 0.006 - 0.010 0.170 - 0.27
b1 0.006 0.008 0.009 0.170 0.20 0.225
c 0.004 - 0.007 0.105 - 0.175
c1 0.004 0.005 0.006 0.105 0.125 0.145
θ0°-8°
e 0.020 BS C 0.50 BSC
D 0.488 0.492 0.496 12.40 12.50 12.60
E 0.313 0.319 0.325 7.95 8.1 8.25
E1 0.236 0.240 0.244 6.00 6.1 6.20
XG571C
I2C Frequency Clock Generator w/ EM I Reduction Spread Spectr um Technol ogy
for Pentium Processor Based Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.8 10/22/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 16 of 16
Ordering Information
Part Number Package Type Production Flow
IMIXG571CYB 48 PIN SSOP Commercial, 0ºC to +70ºC
IMIXG571CTB 48 PIN TSSOP Commercial, 0ºC to +70ºC
Note: The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI
XG571CYB
Date Code, Lot #
IMIXG571CYB Flow
B = Commercial, 0ºC to + 70ºC
Package
Y = SSOP
T = TSSOP
Revision
IMI Device Number
