DS18B20 - Dallas Semiconductor

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FEATURES

• Unique 1-wire interface requires only one

port pin for communication

• Each device has a unique 64-bit serial code

stored in an on-board ROM

• Multi-drop capability simplifies distributed

temperature sensing applications

• Requires no external components

• Can be powered from data line. Power supply

range is 3.0V to 5.5V

• Measures temperatures from –55°C to

+125°C (–67°F to +257°F)

• ±0.5°C accuracy from –10°C to +85°C

• Thermometer resolution is user-selectable

from 9 to 12 bits

• Converts temperature to 12-bit digital word in

750 ms (max.)

• User-definable nonvolatile alarm settings

• Alarm search command identifies and

addresses devices whose temperature is

outside of programmed limits (temperature

alarm condition)

• Software compatible with the DS1822

• Applications include thermostatic controls,

industrial systems, consumer products,

thermometers, or any thermally sensitive

system

PIN ASSIGNMENT

PIN DESCRIPTION

GND - Ground

DQ - Data In/Out

VDD - Power Supply Voltage

NC - No Connect

DESCRIPTION

The DS18B20 Digital Thermometer provides 9 to 12–bit centigrade temperature measurements and has

an alarm function with nonvolatile user-programmable upper and lower trigger points. The DS18B20

communicates over a 1-wire bus that by definition requires only one data line (and ground) for

communication with a central micropro cessor. It has an op eratin g tempera ture ran g e of –55°C to + 125°C

and is accurate to ±0.5°C over the range of –10°C to +85°C. In addition, the DS18B20 can derive power

directly from the data line (“parasite power”), eliminating the need for an external power supply.

Each DS18B20 has a unique 64-bit serial code, which allows multiple DS18B20s to function on the same

1–wire bus; thus, it is simple to use one microprocessor to control many DS18B20s distributed over a

large area. Applications that can benefit from this feature include HVAC environmental controls,

temperature monitoring systems inside buildings, equipment or machinery, and process monitoring and

control systems.

DS18B20

Programmable Resol utio n

1-Wire® Digital Ther momete

www.dalsemi.com

8-pin 150-mil SOIC

(DS18B20Z)

TO-92

(

DS18B20

)

(

BOTTO M VIEW

)

2 3

DALLAS

18B20

GND

VDD

2 3 N

GND

VDD

DALLAS

18B20

DS18B20

2 of 20

DETAILED PIN DESCRIPTIONS Table 1

8-PIN SOIC* TO-92 SYMBOL DESCRIPTION

5 1 GND

Ground.

4 2 DQ Data Input/Output pin. Open-drain 1-wire interface pin. Also

provides power to the device when used in parasite power mode

(see “Parasite Power” section.)

3 3 VDD Optional VDD pin. VDD must be grounded for operation in

parasite power mode.

*All pins not specified in this table are “No Connect” pins.

OVERVIEW

Figure 1 shows a block diagram of the DS18B20, and pin descriptions are given in Table 1. The 64-bit

ROM stores the device’s unique serial code. The scratchpad memory contains the 2-byte temperature

access to the 1-byte upper and lower alarm trigger registers (TH and TL), and the 1-byte configuration

conversion to 9, 10, 11, or 12 bits. The TH, TL and configuration re gisters are nonvolatile (EEPROM), so

they will retain data when the device is powered down.

The DS18B20 uses Dallas’ exclusive 1-wire bus protocol that implements bus communication using one

control signal. The control line requires a weak pullup resistor since all devices are linked to the bus via a

3-state or open-drain port (the DQ pin in the case of the DS18B20). In this bus system, the

microprocessor (the master device) identifies and addresses devices on the bus using each device’s unique

64-bit code. Because ea ch device has a unique code, the number of devices that can be addressed on one

bus is virtually unlimited. The 1-wire bus protocol, including detailed explanations of the commands and

“time slots,” is covered in the 1-WIRE BUS SYSTEM section of this datasheet.

Another feature of the DS18B20 is the ability to operate without an external power supply. Power is

instead supplied through the 1-wire pullup resistor via the DQ pin when the bus is high. The high bus

signal also charges an internal capacitor (CPP), which then supplies power to the device when the bus is

low. This method of deriving power from the 1-wire bus is referred to as “parasite power.” As an

alternative, the DS18B20 may also be powered by an external supply on VDD.

DS18B20 BLOCK DIAGRAM Figure 1

VPU

4.7K

POWER

SUPPLY

SENSE

64-BIT R OM

AND

1-wire PORT

INTERNAL VDD

CPP

PARASITE POWER

CIRCUIT MEMORY CONTROL

LOGIC

SCRATCHPAD

8-BIT CRC GENERATOR

TEMPERATURE SENSOR

ALARM HIGH TRIGGER (TH)

ALARM LOW TRIGGER (TL)

CONFIGURATION REGISTER

(EEPROM)

GND

DS18B20

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O PER ATION – MEASURING TEMPERAT UR E

The core functionality of the DS18B20 is its direct-to-digital temperature sensor. The resolution of the

temperature sensor is user-configurable to 9, 10, 11, or 12 bits, corresponding to increments of 0.5°C,

0.25°C, 0.125°C, and 0.0625°C, respectively. The default resolution at power-up is 12 bit. The

DS18B20 powers-up in a low-power idle state; to initiate a temperature measurement and A-to-D

conversion, the master must issue a Convert T [44h] command. Following the conversion, the resulting

thermal data is stored in the 2-byte temperature register in the scratchpad memory and the DS18B20

returns to its idle state. If the DS18B20 is powered by an external supply, the master can issue “read

time slots” (see the 1-WIRE BUS SYSTEM section) after the Convert T command and the DS18B20 will

respond by transmitting 0 while the temperature conversion is in progress and 1 when the conversion is

done. If the DS18B20 is powered with parasite power, this notification technique cannot be used since

the bus must be pulled high by a strong pullup during the entire temperature conversion. The bus

requirements for par asite power are explained in detail in the POWER ING THE DS18B20 sectio n of this

datasheet.

The DS18B20 output temperature data is calibrated in degrees centigrade; for Fahrenheit applications, a

lookup table or conversion routine must be used. The temperature data is stored as a 16-bit sign-extended

two’s complement number in the temperature register (see Figure 2). The sign bits (S) indicate if the

temperature is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. If the

DS18B20 is configured for 12-bit resolution, all bits in the temperature register will contain valid data.

For 11-bit resolution, bit 0 is undefined. For 10-bit resolution, bits 1 and 0 are undefined, and for 9-bit

resolution bits 2, 1 and 0 are undefined. Table 2 gives examples of digital output data and the

corresponding temperature reading for 12-bit resolution conversions.

TEMPERATURE REGISTER FORM AT Figure 2

bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 b it 1 bit 0

LS Byte 23 2

2 2

1 2

0 2

-1 2

-2 2

-3 2

-4

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8

MS Byte S S S S S 26 2

5 2

TEMPERATURE/DATA RELATI ONSHI P Table 2

TEMPERATURE DIGITAL OUTPUT

(Binary) DIGITAL OUTPUT

(Hex)

+125°C 0000 0111 1101 0000 07D0h

+85°C* 0000 0101 0101 0000 0550h

+25.0625°C 0000 0001 1001 0001 0191h

+10.125°C 0000 0000 1010 0010 00A2h

+0.5°C 0000 0000 0000 1000 0008h

0°C 0000 0000 0000 0000 0000h

-0.5°C 1111 1111 1111 1000 FFF8h

-10.125°C 1111 1111 0101 1110 FF5Eh

-25.0625°C 1111 1110 0110 1111 FE6Fh

-55°C 1111 1100 1001 0000 FC90h

*The power-on reset value of the temp erature regis ter is +85°C

DS18B20

4 of 20

O PER ATION – ALARM SIGNALIN G

After the DS18B20 performs a temperature conversion, the temperature value is compared to the user-

defined two’s complement alarm trigger values stored in the 1-byte TH and TL registers (see Figure 3).

The sign bit (S) indicates if the value is positive or negative: for positive numbers S = 0 and for negative

numbers S = 1. The TH and TL registers are nonvolatile (EEPROM) so they will retain data when the

device is powered down. TH and T L can be access ed throu gh b ytes 2 and 3 of the scrat chpad as ex plained

in the MEMORY section of this datasheet.

TH AN D T L REGISTER FORMAT Figure 3

bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 b it 1 bit 0

S 26 2

5 2

2 2

1 2

Only bits 11 through 4 of the temperat ure register are used in the TH and TL comparison since TH and TL

are 8-bit registers. If the result of a temperature measurement is higher than TH or lower than TL, an

alarm condition exists and an alarm flag is set inside the DS18B20. This flag is updated after every

temperature measurement; therefore, if the alarm condition goes aw a y, the flag will be turned off after the

next temperature conversion.

The master device can check the alarm flag status of all DS18B20s on the bus by issuing an Alarm Search

[ECh] command. Any DS18B20s with a set alarm flag will respond to the command, so the master can

determine exactly which DS18B20s have experienced an alarm condition. If an alarm condition exists

and the TH or TL settings have changed, another temperature conversion should be done to validate the

alarm condition.

POWERING THE DS18B20

The DS18B20 can be po wered by an external sup p l y on the VDD pin, or it can ope rate in “par asite p ower”

mode, which allows the DS18B20 to function without a local external supply. Parasite power is very

useful for applications that require remote temperature sensin g or that are very sp ace constrained. Figure

1 shows the DS18B20’s parasite-power control circuitry, which “steals” power from the 1-wire bus via

the DQ pin when the bus is high. The stolen charge powers the DS18B20 while the bus is high, and some

of the charge is stored on the parasite power capacitor (CPP) to provide power when the bus is low.

When the DS18B20 is used in parasite power mode, the VDD pin must be connected to ground.

In parasite power mode, the 1-wire bus and CPP can provide sufficient current to the DS18B20 for most

operations as long as the specified timing and voltage requirements are met (refer to the DC

ELECTRICAL CHARACTERISTICS and the AC ELECTRICAL CHARACTERISTICS sections of this

data sheet). However, when the DS18B20 is performing temperature conversions or copying data from

the scratchpad memory to EEPROM, the operating current can be as high as 1.5 mA. This current can

cause an unacceptable voltage drop across the weak 1-wire pullup resistor and is more current than can be

supplied by CPP. To assure that the DS18B20 has sufficient supply current, it is necessary to provide a

strong pullup on the 1-wire bus whenever temperature conversions are taking place or data is being

copied from the scrat chpad to EEPROM. This can be accompli shed by using a MOSFET to pull the bus

directly to the rail as shown in Fi gure 4. The 1-wire bus must be switched to the strong pullup within 10

µs (max) after a Convert T [44h] or Copy Scratchpad [48h] command is issued, and the bus must be held

high by the pullup for the duration of the conversion (tconv) or data transfer (twr = 10 ms). No other

activity can take place on the 1-wire bus while the pullup is enabled.

The DS18B20 can also be powered by the conventional method of connecting an external power supply

to the VDD pin, as shown in Figure 5. The advantage of this method is that the MOSFET pullup is not

required, and the 1–wire bus is free to carry other traffic during the temperature conversion time.

DS18B20

5 of 20

The use of parasite power is not recommended for temperatures above 100°C since the DS18B20 may not

be able to sustain com munications due to th e higher leaka ge currents that can ex ist at t hese temperatures.

For applications in which such temperatures are likely, it is strongly recommended that the DS18B20 be

In some situations the bus master may not know whether the DS18B20s on the bus are parasite powered

or powered by external supplies. The master needs this information to determine if the strong bus pullup

should be used during temperature conversions. To get this information, the master can issue a Skip

ROM [CCh] command followed by a Read Power Supply [B4h] command followed by a “read time

slot”. During the read time slot, parasite powered DS18B20s will pull the bus low, and externally

powered DS18B20s will let the bus remain high. If the bus is pulled low, the master knows that it must

supply the strong pullup on the 1-wire bus during temperature conversions.

SUPPLYING THE PARASITE-POWERED DS18B20 DURING TEMPERATURE

CONVERSIONS Figure 4

POWERING THE DS18B20 WITH AN EXTERNAL SUPPLY Figure 5

64-BIT LASERED ROM CODE

Each DS18B20 contains a unique 64–bit code (se e Fi gure 6) stored in ROM. The least significant 8 bits

of the ROM code contain the DS18B20’s 1–wire family code: 28h. The next 48 bits contain a unique

serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is

calculated from the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in

the CRC GENERATION section. The 64–bit ROM code and associated ROM function control logic

allow the DS18B20 to operate as a 1–wire device using the protocol detailed in the 1-WIRE BUS

SYSTEM section of this datasheet.

64-BIT LASERED ROM CODE Figure 6

8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (28h)

MSB MSB LSB LSB LSBMSB

VDD (External Supply)

DS18B20

GND VDD DQ

VPU

4.7K To Other

1-Wire Devices

1-Wire Bus

Micro-

processor

VPU

4.7K

1-Wire Bus

Micro-

processor

DS18B20

GND VDD DQ

To Other

1-Wire Devices

DS18B20

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MEMORY

The DS18B20’s memory is organized as shown in Figure 7. The memory consists of an SRAM

scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (TH and TL)

and configuration register. Note that if the DS18B20 alarm function is not used, the TH and TL registers

can serve as general-purpose memory. All memory commands are described in detail in the DS18B20

FUNCTION COMMANDS section.

Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,

respectively. These bytes are read-only. Bytes 2 and 3 provide access to TH and TL registers. Byte 4

contains the configuration register data, which is explained in detail in the CONFIGURATION

cannot be overwritten; these bytes will return all 1s when read.

Byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (CRC) code for bytes 0

through 7 of the scratchpad. The DS18B20 generates this CRC using the method described in the CRC

GENERATION section.

Data is written to bytes 2 , 3, and 4 of the scratchpad using the Write Scratchpad [4Eh] command; the data

must be transmitted to the DS18B20 starting with the least significant bit of byte 2. To verify data

integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is

written. When reading the scratchpad, data is transferred over the 1-wire bus starting with the least

significant bit of b yte 0. To transfer the TH, TL and configuration data fro m the scratchpad to EEPROM,

the master must issue the Copy Scratchpad [48h] command.

Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM

data is reloaded into the corresponding scratchpad locations. Data can al so be reloaded from EEPROM

to the scratchpad at any time using the Recall E2 [B8h] command. The master can issue read time slots

following the Recall E2 command and the DS18B20 will indicate the statu s of the r ecall by transmitting 0

while the recall is in progress and 1 when the recall is done.

DS18B20 MEMORY MAP cáÖìêÉ=T

SCRATCHPAD (Power-up State)

byte 0 Temperature LSB (50h)

byte 1 Temperature MSB (05h) EEPROM

byte 2 TH Register or User Byte 1* TH Register or User Byte 1

byte 3 TL Register or User Byte 2* TL Re gister or User Byte 2

byte 4 Configuration Register* Configuration Register

byte 5 Reserved (FFh)

byte 6 Reserved (0Ch)

byte 7 Reserved (10h)

byte 8 CRC*

*Power-up state depends on value(s) stored

in EEPROM

(85°C)

DS18B20

7 of 20

CONFIGURATION REGISTER

Byte 4 of the scratchpad memory contains the configuration register, which is organized as illustrated in

Figure 8. The user can set the conversion resolution of the DS18B20 using the R0 and R1 bits in this

Note that there is a direct tradeoff between resolution and conversion time. Bit 7 and bits 0-4 in the

configuration register are reserved fo r internal use b y the device and cannot be overwritten; these bits will

return 1s when read.

CONFIGURATION REGISTER Figure 8

bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 b it 0

0 R1 R0 1 1 1 1 1

THERMOM ETER RESOLUTION CONFIG UR ATION Table 3

R1 R0 Resolution Max Conversion Time

0 0 9-bit 93.75 ms (tCONV/8)

0 1 10-bit 187.5 ms (tCONV/4)

1 0 11-bit 375 ms (tCONV/2)

1 1 12-bit 750 ms (tCONV)

CRC GENERATION

CRC bytes are provided as part of the DS18B20’s 64-bit ROM code and in the 9th byte of the scrat chpad

memory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is contained in

the most significant byte of the ROM. The scratchpad CRC is calculated from the data stored in the

scratchpad, and therefore it changes when the data in the scratchpad ch anges. The CRCs provide the bus

master with a method of data validation when data is read from the DS18B20. To verify that data has

been read correctly, the bus master must re-calculate the CRC from the received data and then compare

this value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for scratchpad reads).

If the calculated CRC matches the read CRC, the data has been received error free. The comparison of

CRC values and the decision to continue with an operation are determined entirely by the bus master.

There is no circuitry inside the DS18B20 that prevents a command sequence from proceeding if the

DS18B20 CRC (ROM or scratchpad) does not match the value generated by the bus master.

The equivalent polynomial function of the CRC (ROM or scratchpad) is:

CRC = X8 + X5 + X4 + 1

The bus master can re-calculate the CRC and compare it to the CRC values from the DS18B20 using th e

polynomial generator shown in Figure 9. This circuit consists of a shift register and XOR gates, and the

shift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the least

significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. After

shifting in the 56th bit from the ROM or the most significant bit of byte 7 from the scratchpad, the

polynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC

from the DS18B20 must be shifted into the circuit. At this point, if the re-calculated CRC was correct,

the shift register will contain all 0s. Additional information about the Dallas 1-wire cyclic redundancy

DS18B20

8 of 20

check is available in Application Note 27 entitled “Understanding and Using Cyclic Redundancy Checks

with Dallas Semiconductor Touch Memory Products.”

CRC GENERATOR Figure 9

1-WIRE BUS SYSTEM

The 1-wire bus system uses a single bus master to control one or more slave devices. The DS18B20 is

always a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”

system; the system is “multi-drop” if there are multiple slaves on the bus.

All data and commands are transmitted least significant bit first over the 1-wire bus.

The following discussion of the 1-wire bus system is broken down into three topics: hardware

configuration, transaction sequence, and 1-wire signaling (signal types and timing).

HARDWARE CONFIGURATIO N

The 1-wire bus has by definition only a single data line. Each device (master or slave) interfaces to the

data line via an open drain or 3–state port. This allows each device to “release” the data line when the

device is not transmitting data so the bus is available for use by another device. The 1-wire port of the

DS18B20 (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 10.

The 1-wire bus requires an external pullup resistor of approximately 5 kΩ; thus, the idle state for the 1-

wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle

state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-wire

bus is in the inactive (high) state du rin g the recover y period. If the bus is held low fo r more than 480 µs,

all components on the bus will be reset.

HARDWARE CONFIGURATIO N Figure=NM=

(MSB) (LSB)

XOR XOR XOR

INPUT

VPU

4.7K

5 µA

Typ.

DS18B20 1-WIRE PORT

100 Ω

ΩΩ

Ω

FET

RX = RECEI V E

TX = TRANSMIT

1-wire Bus

DS18B20

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TRANSACTION SEQUENCE

The transaction sequence for accessing the DS18B20 is as follows:

Step 1. Initialization

Step 2. ROM Command (followed by any required data exchange)

Step 3. DS18B20 Function Command (followed by any required data exchange)

It is very important to follow this sequence every time the DS18B20 is accessed, as the DS18B20 will not

respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search

ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM commands, the

master must return to Step 1 in the sequence.

INITIALIZATION

All transactions on the 1-wire bus begin with an initialization sequence. The initialization sequence

consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the

slave(s). The presence pulse lets the bus master know that slave devices (such as the DS18B20) are on

the bus and are ready to operate. Timing for the reset and presence pulses is detailed in the

1-WIRE SIGNALING section.

ROM COMMANDS

After the bus master has detected a presence pulse, it can issue a ROM command. These commands

operate on the unique 64–bit ROM codes of each slave device and allow the master to single out a

specific device if many are present on the 1-wire bus. These commands also allow the master to

determine how man y and what types of devices are present on the bus or if an y device has experien c ed an

alarm condition. There are five ROM commands, and each command is 8 bits long. The master device

must issue an appropriate ROM command before issuing a DS18B20 function command. A flowchart for

operation of the ROM commands is shown in Figure 11.

SEARCH ROM [F0h]

When a system is initially powered up, the master must identify the ROM codes of all slave devices on

the bus, which allows the master to determine the number of slaves and their device types. The master

learns the ROM codes through a process of elimination that requires the master to perform a Search ROM

cycle (i.e., Search ROM command followed by data exchan ge) as many times as necessary to identify all

of the slave devices. If there is onl y on e slave on the bus, the sim pler Read ROM command (see below)

can be used in place of the Search ROM process. For a detailed explanation of the Search ROM

procedure, refer to the i B utton Book of Standards at www.ibutton.com/ibuttons/standard.pdf. Aft er every

Search ROM cycle, the bus master must return to Step 1 (Initialization) in the transaction sequence.

READ ROM [33h]

This command can onl y be used when there is one slave on the bus. It allows the bus master to read the

slave’s 64-bit ROM code without using the Sea rch ROM procedure. If this command is used wh en there

is more than one slave present on the bus, a data collision will occur when all the slaves attempt to

respond at the same time.

MATCH ROM [55h]

The match ROM command followed b y a 64–bit ROM code sequence allows the bus master to address a

specific slave device on a multi-drop or single-drop bus. Only the slave that exactly matches the 64–bit

ROM code sequence will respond to the function command issued by the master; all other slaves on the

bus will wait for a reset pulse.

DS18B20

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SKIP ROM [CCh]

The master can use this command to address all devices on the bus simultaneously without sending out

any ROM code information. For example, the master can make all DS18B20s on the bus perform

simultaneous temperature conversions by issuing a Skip ROM command followed by a Convert T [44h]

command. Note, however, that the Skip ROM command can only be followed by the Read Scratchpad

[BEh] command when th ere is one slave on the bus. This sequence saves time by allowing the master to

read from the device without sending its 64–bit ROM code. This sequence will cause a data collision on

the bus if there is more than one slave since multiple devices will attempt to transmit data simultaneously.

ALARM SEARCH [ECh]

The operation of this command is identical to the operation of the Search ROM command except that

only slaves with a set alarm flag will respond. This command allows the master device to determine if

any DS18B20s experienced an alarm condition during the most recent temperature conversion. After

every Alarm S earch c ycle (i .e., Alarm S earch co mmand followed by data exchange), the bus m aster must

return to Step 1 (Initialization) in the transaction sequence. Refer to the OPERATION – ALARM

SIGNALING section for an explanation of alarm flag operation.

DS18B20 FUNCTION COM MANDS

After the bus master has used a ROM command to address the DS18B20 with which it wishes to

communicate, the m aster can issue one of th e DS18B20 funct ion comman ds. These commands al low the

master to write to and read from the DS18B20’s scratchpad memory, initiate temperature conversions and

determine the power supply mode. The DS18B20 function commands, which are described below, are

summarized in Table 4 and illustrated by the flowchart in Figure 12.

CONVERT T [44h]

This command initiates a single temperature conversion. Following the conversion, the resulting thermal

data is stored in the 2-byte temperature register in the scratchpad memory and the DS18B20 returns to its

low-power idle state. If the device is being used in parasite power mode, within 10 µs (max) after this

command is issued the master must enable a strong pullup on the 1-wire bus for the duration of the

conversion (tconv) as described in the POWERING THE DS18B20 section. If the DS18B20 is powered

by an external supply, the master can issue read time slots after the Convert T command and the

DS18B20 will respond by transmitting 0 while the temperature conversion is in progress and 1 when the

conversion is done. In parasite power mode this notification technique cannot be used since the bus is

pulled high by the strong pullup during the conversion.

WRITE SCRATCHPAD [4Eh]

This command allows the master to write 3 bytes of data to the DS18B20’s scratchpad. The first data

byte is written into the TH register (byte 2 of the scratchpad), the second byte is written into the TL

transmitted least significant bit first. All three bytes MUST be written before the master issues a reset, or

the data may be corrupted.

READ SCRATCHPAD [BEh]

This command allows the master to read the contents of the scratchpad. The data transfer starts with the

least significant bit of byte 0 and continues through the scratchpad until the 9th byte (byte 8 – CRC) is

read. The master may issue a reset to terminate reading at any time if only part of the scratchp ad data is

needed.

COPY SCRATCHPAD [48h]

This command copies the contents of the scratchpad TH, TL and confi guration registers (bytes 2, 3 and 4)

to EEPROM. If the device is b eing used in parasite power mode, within 10 µs (max) aft er thi s com mand

DS18B20

11 of 20

is issued the master must enable a strong pullup on the 1-wire bus for at least 10 ms as described in the

POWERING THE DS18B20 section.

RECALL E2 [B8h]

This command recalls the alarm trigger values (TH and TL) and configuration data from EEPROM and

places the data i n bytes 2, 3, and 4, respectivel y, in the scratchpad memor y. The master device can issue

read time slots following the Recall E2 command and the DS18B20 will indicate the status of the recall by

transmitting 0 while the recall is in progress and 1 when the recall is done. The recall operation happens

automatically at power-up, so valid data is available in the scratchpad as soon as power is applied to the

device.

READ POWER SUPPLY [B4h]

The master device issues this command followed by a read time slot to determine if any DS18B20s on the

bus are using parasite power. During the read time slot, parasite powered DS18B20s will pull the bus

low, and externally powered DS18B20s will let the bus remain high. Refer to the POWERING THE

DS18B20 section for usage information for this command.

DS18B20 FUNCTION COMMAN D SET Table 4

Command Description Protocol 1-Wire Bus Activity

After Command is Issued

Notes

TEMPERATURE CONVERSION COMMANDS

Convert T Initiates temperature

conversion. 44h DS18B20 transmits conversion

status to master (not applicable

for parasite-powered

DS18B20s).

MEMORY COMMANDS

Read Scratchpad Reads the entire scratchpad

including the CRC byte. BEh DS18B20 transmits up to 9 data

bytes to master. 2

Write Scratchpad Writes data into scratchpad

bytes 2, 3, and 4 (TH, TL,

and configuration registers).

4Eh Master transmits 3 data bytes to

DS18B20. 3

Copy Scratchpad Copies TH, TL, and

configuration register data

from the scratchpad to

EEPROM.

48h None 1

Recall E2 Recalls TH, TL, and

configuration register data

from EEPROM to the

scratchpad.

B8h DS18B20 transmits recall status

to master.

Read Power

Supply Signals DS18B20 power

supply mode to the master. B4h DS18B20 transmits supply status

to master.

NOTES:

1. For parasite-powered DS18B20s, the master must enable a strong pullup on the 1-wire bus during

temperature conversions and copies from the scr atchpad to EEPROM. No other bus activity may take

place during this time.

2. The master can interrupt the transmission of data at any time by issuing a reset.

3. All three bytes must be written before a reset is issued.

DS18B20

12 of 20

ROM COMMANDS FLOW CHART Figure 11

CCh

SKIP ROM

COMMAND

MASTER T X

RESET PULS E

DS18B20 TX

PRESENCE

PULSE

MASTER T X ROM

COMMAND

33h

READ ROM

COMMAND

55h

MATCH ROM

COMMAND

F0h

SEARCH ROM

COMMAND

ECh

LARM SEARCH

COMMAND

MASTER T X

BIT 0

DS18B20 T

BIT 0

DS18B20 T

BIT 0

MASTER T X BIT 0

BIT 0

MATCH?

MASTER T X

BIT 1

MATCH?

BIT 63

MATCH?

MASTER T X

BIT 63

Y Y Y Y

N N NN

DS18B20 T

BIT 1

DS18B20 T

BIT 1

MASTER T X BIT 1

DS18B20 TX BIT 63

DS18B20 T

BIT 63

MASTER T

BIT 63

BIT 0

MATCH?

BIT 1

MATCH?

BIT 63

MATCH?

DS18B20 TX

FAMILY CODE

1 BYTE

DS18B20 TX

SERIAL NUMBER

6 BYTES

DS18B20 TX

CRC BYTE

DS18B20 T

BIT 0

DS18B20 T

BIT 0

MASTER T X BIT 0

DEVICE(S)

W IT H ALARM

FLAG SET?

Initialization

Sequence

MASTER T X

FUNCTION

COMMAND

(FIGURE 12)

DS18B20

13 of 20

DS18B20 FUNCTION COM MANDS FLOW CHART Figure 12

MASTER T X

FUNCTION

COMMAND

44h

CONVERT

TEMPERATURE

PARASITE

POWER

N Y

DS18B20 BEGINS

CONVERSION

DEVICE

CONVERTING

TEMPERATURE

MASTER

RX “0s”

MASTER

RX “1s”

MASTER ENABLES

STRONG PULL U P ON DQ

DS18B20 CONVERTS

TEMPERATURE

MASTER DISABLES

STRONG PULLUP

48h

COPY

SCRATCHPAD

PARASITE

POWER

MASTER ENABLES

STRONG PULL -UP ON DQ

DATA COPIED FROM

SCRATCHPAD TO EEPROM

MASTER DISABLES

STRONG PULLUP

MASTER

“0s”

COPY IN

PROGRESS

MASTER

RX “1s”

RETURN TO INITIALIZATION

SEQUENCE (F IGURE 11) FOR

NEXT TRANSACTION

B4h

READ

POWER SUPPLY

PARASITE

POWERED

MASTER

RX “1s”

MASTER

RX “0s”

MASTER T X TH BYTE

TO SCRATCHPAD

N 4Eh

WRITE

SCRATCHPAD

MASTER T X TL BYTE

TO SCRATCHPAD

MASTER T X CONFIG. BYTE

TO SCRATCHPAD

BEh

READ

SCRATCHPAD

HAVE 8 BYTES

BEEN READ

MASTER

TX RESET

MASTER RX DATA BYTE

FROM SCRATCHPAD

MASTER RX SCRATCH PAD

CRC BYTE

MASTER

RX “1s”

N B8h

RECALL E2

MASTER BEGINS DAT A

RECALL FROM E2 PROM

DEVICE

BUSY RECALLING

DATA

MASTER

RX “0s”

DS18B20

14 of 20

1-WIRE SIGNALING

The DS18B20 uses a strict 1-wire communication protocol to insure data integrity. Several signal types

are defined b y this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All of these

signals, with the exception of the presence pulse, are initiated by the bus master.

INITIALIZATION PROCEDURE: RESET AND PRESEN CE PULSES

All communication with the DS18B20 begins with an initialization sequence that consists of a reset pulse

from the master followed b y a presen ce pulse from the DS18B20. This is illustrated in Figure 13. When

the DS18B20 sends the presence pulse in response to the reset, it is indicating to the master that it is on

the bus and ready to operate.

During the initialization sequence the bus master transmits (TX) the reset pulse by pulling the 1-wire bus

low for a minimum of 480 µs. The bus master then releases the bus and goes into receive mode (RX).

When the bus is released, the 5k pullup resistor pulls the 1-wire bus high. When the DS18B20 detects

this rising edge, it waits 15–60 µs and then transmits a presence pulse by pulling the 1-wire bus low for

60–240 µs.

INITIALI ZATION TIMING Figure 13

READ/WRITE TIME SLOTS

The bus master writes data to the DS18B20 during write time slots and reads data from the DS18B20

during read time slots. One bit of data is transmitted over the 1-wire bus per time slot.

WRITE TIME SLOTS

There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master

uses a Write 1 time slot to write a logic 1 to the DS18B20 and a Write 0 time slot to write a logic 0 to the

DS18B20. All write time slots must be a minimum of 60 µs in duration with a minimum of a 1 µs

recovery time between individual write slots. Both types of write time slots are initiated by the master

pulling the 1-wire bus low (see Figure 14).

To generate a Write 1 time slot, after pulling the 1-wire bus low, the bus master must release the 1-wire

bus within 15 µs. When the bus is released, the 5k pullup resistor will pull the bus high. To generate a

Write 0 time slot, after pulling the 1-wire bus low, the bus master must continue to hold the bus low for

the duration of the time slot (at least 60 µs).

LINE TYPE LEG END

Bus master pulling low

DS18B20 pulling low

Resistor

ullu

VPU

GND

1-WIRE BUS

480

µµ

µs minimum 480

µµ

µs minimum

DS18B20 TX

presence pulse

60-240 µ

µµ

µs

MASTER TX RESET PULSE MASTER

DS18B20

waits 15-60 µ

µµ

µs

DS18B20

15 of 20

The DS18B20 samples the 1-wire bus during a window that lasts from 15 µs to 60 µs after the master

initiates the write time slot. If the bus is high during the sampling window, a 1 is written to the

DS18B20. If the line is low, a 0 is written to the DS18B20.

READ/WRITE TIM E SLOT TIMING DIAGRAM Figure 14

READ TIME SLOTS

The DS18B20 can only transmit data to the master when the master issues read time slots. Therefore, the

master must generate read time slots immediately after issuing a Read Scratchpad [BEh] or Read Power

Supply [B4h] command, so that the DS18B20 can provide the requested data. In addition, the master can

generate read time slots after issuing Convert T [44h] or Recall E2 [B8h] commands to find out the status

of the operation as explained in the DS18B20 FUNCTION COMMAND section.

All read time slots must be a minimum of 60 µs in duration with a minimum of a 1 µs recovery time

between slots. A read time slot is initiated by the master device pulling the 1-wire bus low for a

minimum of 1 µs and then releasing the bus (see Figure 14). After the master initiates the read time slot,

the DS18B20 will begin transmitting a 1 or 0 on bus. The DS18B20 transmits a 1 by leaving the bus high

and transmits a 0 by pulling the bus low. When transmitting a 0, the DS18B20 will release the bus by the

end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output

data from the DS18B20 is valid for 15 µs after the falling edge that initiated the read time slot.

µµ

µs

µµ

µs

VPU

GND

1-WIRE BUS

µµ

µs < TX “0” < 120 1 µ

µµ

µs < TREC < ∞

DS18B20 Samples

MIN TYP MA

µµ

µs30

µµ

µs

> 1

µµ

µs

MASTER WRITE “0” SL O T MASTER WRITE “1” SLO T

VPU

GND

1-WIRE BUS

µµ

µs

MASTER READ “0” SLOT MASTER READ “1” SLOT

Master samples Master samples

START

OF SLOT

START

OF SLOT

> 1

µµ

µs

1 µ

µµ

µs < TREC < ∞

µµ

µs15

µµ

µs30

µµ

µs

µµ

µs

DS18B20 Samples

MIN TYP MA

LINE TYPE LEG END

Bus master pulling low DS18B20 pulling low

Resistor pullup

> 1

µµ

µs

DS18B20

16 of 20

Therefore, the mast er m ust rel ease the bus and t hen sampl e the bus stat e wit hin 15 µs from the start of the

slot.

Figure 15 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15 µs for a read time slot.

Figure 16 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible

and by locating the master sample time during read time slots towards the end of the 15 µs period.

DETAILED MASTER RE AD 1 TIMING Figure 15

RECOMME NDED MASTER READ 1 TIMING Figure 16

RELATED APP LICATION NOTES

The following Application Notes can be applied to the DS18B20. These notes can be obtained from the

Dallas Semiconductor “Application Note Book,” via the Dallas website at http://www.dalsemi.com/, or

through our faxback service at (214) 450–0441.

Application Note 27: “Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor

Touch Memory Product”

Application Note 55: “Extending the Contact Range of Touch Memories”

Application Note 74: “Reading and Writing Touch Memories via Serial Interfaces”

Application Note 104: “Minimalist Temperature Control Demo”

Application Note 106: “Complex MicroLANs”

Application Note 108: “MicroLAN – In the Long Run”

Sample 1-wire subroutines that can be used in conjunction with AN74 can be downloaded from the

Dallas website or anonymous FTP Site.

VPU

GND

1-WIRE BUS

µµ

µs

IH of Master

TRC

TINT > 1

µµ

µs Master samples

LINE TYPE LEG END

Bus master pulling l o w

Resistor pullup

VPU

GND

1-WIRE BUS

µµ

µs

IH of Master

TRC =

small

TINT =

small

Master samples

DS18B20

17 of 20

DS18B20 OPERATION EXAMPLE 1

In this example there are multiple DS18B20s on the bus and they are using parasite power. The bus

master initiates a temperature conversion in a specific DS18B20 and then reads its scratchpad and

recalculates the CRC to verify the data.

MASTER MODE DATA (LSB FIRST) COMMENTS

TX Reset Master issues reset pulse.

RX Presence DS18B20s respond with presence pulse.

TX 55h Master issues Match ROM command.

TX 64-bit ROM code Master sends DS18B20 ROM code.

TX 44h Master issues Convert T command.

TX DQ line held high by

strong pullup Master applies strong pullup to DQ for the duration of the

conversion (tconv).

TX Reset Master issues reset pulse.

RX Presence DS18B20s respond with presence pulse.

TX 55h Master issues Match ROM command.

TX 64-bit ROM code Master sends DS18B20 ROM code.

TX BEh Master issues Read Scratchpad command.

RX 9 data bytes Master reads entire scratchpad including CRC. The master

then recalculates the CRC of the first eight data bytes from the

scratchpad and compares the calculated CRC with the read

CRC (byte 9). If they match, the master continues; if not, the

read operation is repeat ed.

DS18B20 OPERATION EXAMPLE 2

In this example there is only one DS18B20 on the bus and it is using parasite power. The master writes

to the TH, TL, and configuration registers in the DS18B20 scratchpad and then reads the scratchpad and

recalculates the CRC to verify the data. The master then copies the scratchpad contents to EEPROM.

MASTER MODE DATA (LSB FIRST) COMMENTS

TX Reset Master issues reset pulse.

RX Presence DS18B20 responds with presence pulse.

TX CCh Master issues Skip ROM command.

TX 4Eh Master issues Write Scratchpad command.

TX 3 data bytes Master sends three data bytes to scratchpad (TH, TL, and config).

TX Reset Master issues reset pulse.

RX Presence DS18B20 responds with presence pulse.

TX CCh Master issues Skip ROM command.

TX BEh Master issues Read Scratchpad command.

RX 9 data bytes Master reads entire scratchpad including CRC. The master then

recalculates the CRC of the first eight data bytes from the

scratchpad and compares the calculated CRC with the read CRC

(byte 9). If they match, the master continues; if not, the read

operation is repeated.

TX Reset Master issues reset pulse.

RX Presence DS18B20 responds with presence pulse.

TX CCh Master issues Skip ROM command.

TX 48h Master issues Copy Scratchpad command.

TX DQ line held high by

strong pullup Master applies strong pullup to DQ for at least 10 ms while copy

operation is in progress.

DS18B20

18 of 20

AB SOLUTE MAXIMU M RATINGS*

Voltage on any pin relative to ground –0.5V to +6.0V

Operating temperature –55°C to +125°C

Storage temperature –55°C to +125°C

Soldering temperature See J-STD-020A Specification

*These are stress ratings only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS (-55°C to +125°C; VDD=3.0V to 5.5V)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES

Supply Voltage VDD Local Power +3.0 +5.5 V 1

Parasite Power +3.0 +5.5 Pullup Supply

Voltage VPU Local Power +3.0 VDD V 1,2

-10°C to

+85°C ±0.5

°C

3 Thermometer Error tERR

-55°C to

+125°C ±2

Input Logic Low VIL -0.3 +0.8 V 1,4,5

Local Power

+2.2 Input Logic High VIH

Parasite Power +3.0

The lower of

5.5

VDD + 0.3

V 1, 6

Sink Current IL V

I/O=0.4V 4.0 mA 1

Standby Current IDDS 750 1000 nA 7,8

Active Current IDD V

DD=5V 1 1.5 mA 9

DQ Input Current IDQ 5 µA 10

Drift ±0.2 °C 11

NOTES:

1. All voltages are referenced to ground.

2. The Pullup Supply Voltage specification assumes that the pullup device is ideal, and therefore the

high level of the pullup is equal to VPU. In order to meet the VIH spec of the DS18B20, the actual

supply rail for the strong pullup transistor must include margin for the voltage drop across the

transistor when it is turned on; thus: VPU_ACTUAL = VPU_IDEAL + VTRANSISTOR.

3. See typical performance curve in Figure 17

4. Logic low voltages are specified at a sink current of 4 mA.

5. To guarantee a presence pulse under low voltage parasite power conditions, VILMAX may have to be

reduced to as low as 0.5V.

6. Logic high voltages are specified at a source current of 1 mA.

7. Standby current specified up to 70°C. Standby current typically is 3 µA at 125°C.

8. To minimize IDDS, DQ should be within the following ranges: GND ≤ DQ ≤ GND + 0.3V or VDD –

0.3V ≤ DQ ≤ VDD.

9. Active current refers to supply current during active temperature conversions or EEPROM writes.

10. DQ line is high (“hi-Z” state).

11. Drift data is based on a 1000 hour stress test at 125°C with VDD = 5.5V.

DS18B20

19 of 20

AC ELECTRICAL CHAR ACTERISTICS: NV MEMORY

(-55°C to +100°C; VDD=3.0V to 5.5V)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

NV Write Cycle Time twr 2 10 ms

EEPROM Writes NEEWR -55°C to +55°C 50k writes

EEPROM Data Retention tEEDR -55°C to +55°C 10 years

AC ELECTRICAL CHARACTERISTICS (-55°C to +125°C; VDD=3.0V to 5.5V)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES

Temperature Conversion tCONV 9-bit resolution 93.75 ms 1

Time 10-bit resolution 187.5 ms 1

11-bit resolution 375 ms 1

12-bit resolution 750 ms 1

Time to Strong Pullup On tSPON Start Convert T

Command Issued 10 µs

Time Slot tSLOT 60 120 µs 1

Recovery Time tREC 1 µs 1

Write 0 Low Time rLOW0 60 120 µs 1

Write 1 Low Time tLOW1 1 15 µs 1

Read Data Valid tRDV 15 µs 1

Reset Time High tRSTH 480 µs 1

Reset Time Low tRSTL 480 µs 1,2

Presence Detect High tPDHIGH 15 60 µs 1

Presence Detect Low tPDLOW 60 240 µs 1

Capacitance CIN/OUT 25 pF

NOTES:

1. Refer to timing diagrams in Figure 18.

2. Under parasite power, if tRSTL > 960 µs, a power on reset may occur.

TYPICAL PERFORMANCE CURVE Figure 17

DS18B20 Typic al Error Curve

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0 10203040506070

Reference Temp (°C)

Thermomet er Error (°C)

Mean Error

+3s Error

-3s Error

DS18B20

20 of 20

TIMING DI AGR AMS Figure 18