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FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Replaces 32k x 8 volatile static RAM,
EEPROM or Flash memory
Unlimited write cycles
Low-power CMOS
Read and write access times as fast as 70 ns
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Full ±10% VCC operating range (DS1230Y)
Optional ±5% VCC operating range
(DS1230AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
JEDEC standard 28-pin DIP package
New PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standardized pinout for all nonvolatile
SRAM products
- Detachment feature on PowerCap allows
easy removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A14 - Address Inputs
DQ0 - DQ7 - Data In/Data Out
CE - Chip Enable
WE - Write Enable
OE - Output Enable
VCC - Power (+5V)
GND - Ground
NC - No Connect
DS1230Y/AB
256k Nonvolatile SRAM
www.dalsemi.com
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28-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ7
DQ5
DQ6
28
26
25
24
23
22
21
20
19
18
17
15
16
A12
A6
DQ2
GND DQ4
DQ3
1
NC 2
3
NC
NC
NC
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
A
14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
34 NC
GND VBAT
34-Pin POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
DS1230Y/AB
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DESCRIPTION
The DS1230 256k Nonvolatile SRAMs are 262,144-bit, fully static, nonvolatile SRAMs organized as
32,768 words by 8 bits. Each NV SRAM has a self-contained lithium ener gy source and control circuitry
which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1230 devices can be used in place of existing 32k x 8 static
RAMs directly conforming to the popular b ytewide 28-pin DIP standard. The DIP devices also match the
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230 devices
in the Low Profile Module package are sp ecifically designed for surfa ce-mount applications. There is no
limit on the number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
READ MODE
The DS1230 devices ex ecute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs
(A0 - A14) defines which of the 32,768 b ytes of data is to be a ccessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1230 devices execute a write cycle whenever the WE and CE signals are active (low) after
address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabl ed (CE and OE acti ve) t h en
WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1230AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1230Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without an y additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resum e after VCC exceeds 4.75 volts for the DS1230AB and 4.5 volts for the
DS1230Y.
FRESHNESS SEAL
Each DS1230 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full ener gy capacit y. When VCC is first applied at a level greater than 4.25 volts, the lithium
energy source is enabled for battery back-up operation.
DS1230Y/AB
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PACKAGES
The DS1230 devices are available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM).
The 28-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a
single package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates
SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the
DS9034PC PowerCap. The PowerCap Module package design allows a DS1230 PCM device to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1230 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the
PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1230 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped
in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1230AB Power Supply Voltage VCC 4.75 5.0 5.25 V
DS1230Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 0.8 V
DC ELECTRICAL (VCC=5V ±=5% for DS1230AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ±=10% for DS1230Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current IIL -1.0 +1.0 µA
I/O Leakage Current CE ≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
Standby Current CE =2.2V ICCS1 5.0 10.0 mA
Standby Current CE =VCC-0.5V ICCS2 3.0 5.0 mA
Operating Current ICCO1 85 mA
Write Protection Voltage (DS1230AB) VTP 4.50 4.62 4.75 V
Write Protection Voltage (DS1230Y) VTP 4.25 4.37 4.5 V
DS1230Y/AB
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CAPACITANCE (tA=25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 510pF
Input/Output Capacitance CI/O 510pF
AC ELECTRICAL (VCC=5V ±=5% for DS1230AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ±=10% for DS1230Y)
DS1230AB-70
DS1230Y-70 DS1230AB-85
DS1230Y-85 DS1230AB-100
DS1230Y-100
PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
Read Cycle
Time tRC 70 85 100 ns
Access Time tACC 70 85 100 ns
OE to Output
Valid tOE 35 45 50 ns
CE to Output
Valid tCO 70 85 100 ns
OE or CE to
Output Active tCOE 555 ns5
Output High Z
from
Deselection
tOD 25 30 35 ns 5
Output Hold
from Address
Change
tOH 555 ns
Write Cycle
Time tWC 70 85 100 ns
Write Pulse
Width tWP 55 65 75 ns 3
Address Setup
Time tAW 000 ns
Write Recovery
Time tWR1
tWR2
5
15 5
15 5
15 ns 12
13
Output High Z
from WE tODW 25 30 35 ns 5
Output Active
from WE tOEW 555 ns5
Data Setup
Time tDS 30 35 40 ns 4
Data Hold
Time tDH1
tDH2
0
10 0
10 0
10 ns 12
13
DS1230Y/AB
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AC ELEC TRICAL CHARACTERISTICS (cont'd)
DS1230AB-120
DS1230Y-120 DS1230AB-150
DS1230Y-150 DS1230AB-200
DS1230Y-200
PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
Read Cycle
Time tRC 120 150 200 ns
Access Time tACC 120 150 200 ns
OE to Output
Valid tOE 60 70 100 ns
CE to Output
Valid tCO 120 150 200 ns
OE or CE to
Output Active tCOE 555 ns5
Output High Z
from
Deselection
tOD 35 35 35 ns 5
Output Hold
from Address
Change
tOH 555 ns
Write Cycle
Time tWC 120 150 200 ns
Write Pulse
Width tWP 90 100 100 ns 3
Address Setup
Time tAW 000 ns
Write Recovery
Time tWR1
tWR2
5
15 5
15 5
15 ns 12
13
Output High Z
from WE tODW 35 35 35 ns 5
Output Active
from WE tOEW 555 ns5
Data Setup
Time tDS 50 60 80 ns 4
Data Hold Time tDH1
tDH2
0
10 0
10 0
10 ns 12
13
DS1230Y/AB
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
DS1230Y/AB
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WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION
DS1230Y/AB
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POWER-DOWN/POWER-UP TIMING (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE, at VIH before Power-Down tPD 0µs11
VCC slew from VTP to 0V (CE at VIH)tF300 µs
VCC slew from 0V to VTP (CE at VIH)tR300 µs
CE at VIH after Power-Up tREC 2 125 ms
(tA=25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDH, tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1230Y has a built-in switch that disconnects the lithium source until VCC is first applied by
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
time power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial produ cts, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from WE going high.
13. tWR2 and tDH2 are measured from CE going high.
14. DS1230 DIP modules are recognized by Underwriters Laboratory (U.L.) under file E99151.
DS1230 PowerCap modules are pending U.L. review. Contact the factory for status.
DS1230Y/AB
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DC TEST CONDITIONS AC TEST CONDITIONS
Outputs Open Output Load: 100 pF + 1TTL Gate
Cycle = 200 ns for operating current Input Pulse Levels: 0 - 3.0V
All voltages are referenced to ground Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
DS1230 TTP - SSS - III Operating Temperature Range
blank: 0° to 70°
IND: -40° to +85°C
Access Speed
70: 70 ns
85: 85 ns
100: 100 ns
120: 120 ns
150: 150 ns
200: 200 ns
Package Type
blank: 28-pin 600-mil DIP
P: 34-pin PowerCap Module
VCC Tolerance
AB: ±5%
Y: ±10%
DS1230Y/AB NONVOLATILE SRAM, 28-PIN 740-MIL EXTENDED DIP
MODULE PKG 28-PIN
DIM MIN MAX
A IN.
MM 1.480
37.60 1.500
38.10
B IN.
MM 0.720
18.29 0.740
18.80
C IN.
MM 0.355
9.02 0.375
9.52
D IN.
MM 0.080
2.03 0.110
2.79
E IN.
MM 0.015
0.38 0.025
0.63
F IN.
MM 0.120
3.05 0.160
4.06
G IN.
MM 0.090
2.29 0.110
2.79
H IN.
MM 0.590
14.99 0.630
16.00
J IN.
MM 0.008
0.20 0.012
0.30
K IN.
MM 0.015
0.38 0.021
0.53
DS1230Y/AB
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DS1230Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE
INCHES
PKG
DIM MIN NOM MAX
A0.920 0.925 0.930
B0.980 0.985 0.990
C- - 0.080
D0.052 0.055 0.058
E0.048 0.050 0.052
F0.015 0.020 0.025
G0.020 0.025 0.030
DS1230Y/AB
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DS1230Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH
POWERCAP
INCHES
PKG
DIM MIN NOM MAX
A0.920 0.925 0.930
B0.955 0.960 0.965
C0.240 0.245 0.250
D0.052 0.055 0.058
E0.048 0.050 0.052
F0.015 0.020 0.025
G0.020 0.025 0.030
ASSEM BLY AND USE
Reflow soldering
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented label-side up (live-bug).
Hand soldering and touch-up
Do not touch soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the
lead frame pad and apply solder. To remove part, apply flux, heat pad until solder reflows, and use a
solder wick.
LPM replacement in a socket
To replace a Low Profile Module in a 68-pin PLCC socket, attach a DS9034PC PowerCap to a module
base then insert the complete module into the socket one row of leads at a time, pushing only on the
corners of the cap. Never apply force to the center of the device. To remove from a socket, use a PLCC
extraction tool and ensure that it does not hit or damage any of the module IC components. Do not use
any other tool for extraction.
DS1230Y/AB
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RECOMME NDED POWERC AP MODULE L AND PATTERN
INCHES
PKG
DIM MIN NOM MAX
A- 1.050 -
B- 0.826 -
C- 0.050 -
D- 0.030 -
E- 0.112 -
RECOMME NDED POWERC AP MODULE SOLDER STENCI L
INCHES
PKG
DIM MIN NOM MAX
A- 1.050 -
B- 0.890 -
C- 0.050 -
D- 0.030 -
E- 0.080 -
