SPICE Device Model SUD40N04-10A
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71751 www.vishay.com
19-Oct-01 1
N-Channel 40-V (D-S) 175°C MOSFET
CHARACTERISTICS
• N- and P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical
electrical characteristics of the n-channel vertical
DMOS. The subcircuit model is extracted and
optimized over the −55 to 125°C temperature ranges
under the pulsed 0-to10V gate drive. The saturated
output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is
used to model the gate charge characteristics while
avoiding convergence difficulties of the switched C
g
d
model. All model parameter values are optimized to
provide a best fit to the measured electrical data and
are not intended as an exact physical interpretation of
the device.
SUBCIRCUIT MODEL SCHEMATIC
SPICE Device Model SUD40N04-10A
Vishay Siliconix
www.vishay.com Document Number: 71751
219-Oct-01
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Simulated
Data
Measured
Data Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA2.1 V
VDS = 5 V, VGS = 10 V 568
VGS = 10 V, ID = 40A 0.0072 0.0075
VGS = 10 V, ID = 40 A, TJ = 125°C 0.011 0.012
On-State Drain CurrentaID(on)
VGS = 10 V, ID = 40 A, TJ = 175°C 0.013 0.015
A
VGS = 4.5 V, ID = 10 A 0.011 0.011
VGS = 4.5 V, ID = 10 A, TJ = 125°C 0.016 0.018Drain-Source On-State ResistancearDS(on)
VGS = 4.5 V, ID = 10 A, TJ = 175°C 0.018 0.022
Ω
Forward Transconductanceagfs VDS = 15 V, ID = 40 A 55 40 S
Forward Voltage a VSD IS = 40 A, VGS = 0 V 0.91 1 V
Dynamic b
Input Capacitance Ciss 1771 1700
Output Capacitance Coss 382 370
Reverse Transfer Capacitance Crss
VGS = 0 V, VDS = 25 V, f = 1 MHz
139 145
pF
Total Gate ChargecQg32 35
Gate-Source ChargecQgs 66
Gate-Drain ChargecQgd
VDS = 20 V, VGS = 10 V, ID = 40A
88
nC
Turn-On Delay Time c td(on) 10 14
Rise Time c tr14 7.5
Turn-Off Delay Time c td(off) 19 30
Fall Time c tf
VDD = 20 V, RL = 0.50 Ω
ID ≅ 40 A, VGEN = 10 V, RG = 2. Ω
25 14
Reverse Recovery Time trr IF = 40 A, di/dt = 100 A/µs21 30
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%
b. Guaranteed by design, not subject to production testing
c. Independent of operating temperature.
SPICE Device Model SUD40N04-10A
Vishay Siliconix
Document Number: 71751 www.vishay.com
19-Oct-01 3
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
